Method for manufacturing photonic devices with reduced losses

Abstract

The invention relates to a method for manufacturing a photonic device (D1) comprising the following steps: providing an optical guidance structure (WG) disposed on a first thermal SiO2 layer; the first layer (C1) being disposed on a first face of a substrate (SUB) made of a semiconductor material; etching the second face opposite the first face of the substrate below at least a portion of the optical guidance structure down to the first thermal SiO2 layer (C1) so as to obtain a membrane (M1) formed by a portion of the first layer suspended above a cavity (CV) delimited by two pillars (PL1, PL2); the optical guidance structure being disposed on said membrane; depositing a second SiO2 layer (C2) on the first layer (C1) on the cavity (CV) side so as to increase the thickness of the membrane (M1). Abstract figure: Fig. 4

Description

Title of the invention: Method for manufacturing a photonic device with reduced losses

[0001] Scope

[0002] The invention relates to a photonic wave-guiding device mounted on a membrane suspended on a semiconductor substrate and its manufacturing process.

[0003] Problem raised

[0004] Several fabrication techniques have been developed to create microstructures and nanostructures on semiconductor substrates, enabling the fabrication of integrated circuits and systems. These systems cover a multitude of uses such as transistor-based microelectronic circuits, MEMS (Micro-Electro-Mechanical Systems) or NEMS (Nano-Electro-Mechanical Systems) type microsystems, integrated sensors (pressure sensors, accelerometers, chemical sensors, etc.), or photonic and optoelectronic systems integrated on a semiconductor substrate.

[0005] More specifically, it is possible to fabricate photonic circuits with laser emitters associated with beam processing layers (guiding, multiplexing / demultiplexing, amplification, etc.), the processing layer(s) being deposited on a silicon substrate ("Photonic on Silicon"). The emitting lasers can be integrated into the photonic circuit chip or external to the photonic circuit chip.

[0006] By way of illustrative and non-limiting example, [Fig. 1] shows a perspective view of a photonic device according to the state of the art. The coupler D0 comprises an optical guidance structure WG0 made of a first dielectric material disposed on a SiO2 layer C0, which is itself disposed on a bulk silicon substrate. The layers are stacked along a Z direction normal to a plane (X,Y). The optical guidance structure WG0 extends along a Y direction orthogonal to the stacking direction Z. The optical guidance structure WG0 is designed to confine an electromagnetic wave propagating along its Y extension direction.

[0007] Several problems have been clearly identified in photonic circuits according to the state of the art. Indeed, in certain parts of the circuit, such as input couplers or RF modulators, the propagated light beam widens and confinement is not ideal, especially in the transitions from one part to another of the photonic circuit. Light tends to flow towards the material with the highest refractive index. In state-of-the-art solutions, the SiO2 layer separating the structure from The substrate guidance system typically has a thickness less than Ipm and at best between 2 and 3 pm. This induces an overlap between the light and the semiconductor substrate located beneath the guidance structure. This overlap results in optical leakage and therefore losses. These losses lead to a decrease in the output power obtained for classical photonic circuits and, in the context of quantum photonics, a considerable degradation of the signal, rendering it unusable for performing quantum operations. In this context, eliminating the coupling of the propagated wave with the semiconductor substrate becomes crucial.

[0008] In the context of the invention, "thermal SiO2" refers to a layer of silicon dioxide formed by the thermal oxidation of silicon wafers. This process involves heating the silicon wafers in an oxygen-rich environment, resulting in the formation of a thin layer of SiO2 on the surface. Thermal SiO2 is commonly used in the manufacture of semiconductor components due to its excellent electrical insulation properties.

[0009] In the context of the invention, "non-thermal SiO2" or "deposited SiO2" refers to a silicon dioxide layer formed by deposition techniques such as plasma-enhanced chemical vapor deposition, sputtering, or other deposition methods. This terminology is commonly used to distinguish SiO2 layers formed by deposition processes from those formed by the thermal oxidation of silicon.

[0010] From a structural point of view, it is possible to distinguish a thermal SiO2 layer from a non-thermal SiO2 layer via the following parameters: - Material density: Thermal SiO2 has a higher density than deposited SiO2. This is because the silicon and oxygen atoms are generally more tightly bonded and more densely packed due to the oxidation process of crystalline silicon that occurs during thermal formation. - presence of free hydrogen bonds: thermal SiO2 does not have free hydrogen bonds, which is not the case in deposited SiO2. - density: Thermal SiO2 has a higher density than non-thermal SiO2.

[0011] Analytical techniques such as X-ray reflection, Raman spectroscopy, Fourier transform infrared (FTIR) spectroscopy, ellipsometry and electron microscopy can be used to characterize the structure and composition of SiO2 films and thus differentiate a thermal SiO2 layer from a non-thermal deposited SiO2 layer.

[0012] Prior art / Prior art restrictions

[0013] Among the state-of-the-art solutions considered, increasing the distance between the optical guidance structure and the semiconductor substrate by increasing the thickness of the thermal SiO2 layer is noteworthy. However, current manufacturing methods lack reproducibility, produce fragile structures, or are expensive, making their industrialization difficult. Indeed, increasing the thickness of said layer to sufficient thicknesses to eliminate coupling requires a thermal oxidation time on the order of a few days, which is very costly in terms of time and energy. Alternatively, in the case of using SOI (Silicon-on-Insulator) wafers, the thickness of the SiO2 layer is predetermined by the supplier.

[0014] Furthermore, obtaining a thermal SiO2 layer with a thickness greater than 5 µm requires several thermal annealing cycles at temperatures above 800°C. This induces an increase in internal mechanical stresses within the layers forming the photonic circuit, which weakens it.

[0015] Alternatively, depositing an additional layer of non-thermal SiO2 on the thermal SiO2 layer degrades the interface seen by the optical guidance structure due to the presence of free hydrogen bonds. These bonds absorb a portion of the propagated electromagnetic wave for the target wavelengths and thus reduce the performance of the photonic circuit.

[0016] Response to the problem and provision of a solution

[0017] To overcome the limitations of existing solutions with regard to implementation, the invention proposes a manufacturing process for obtaining an optical guidance structure based on a membrane formed by a stack comprising at least one thermal SiO2 layer and one non-thermal SiO2 layer. The membrane separates the guidance structure from the semiconductor substrate and thus eliminates optical losses due to the overlap of the propagated wave with the semiconductor.

[0018] Furthermore, the process according to the invention makes it possible to produce a membrane with sufficient thickness to improve confinement within the guiding structure without resorting to multiple thermal annealing processes. This avoids the drawbacks of thermal annealing described above, namely the thermal budget and the introduction of mechanical brittleness.

[0019] Furthermore, the method according to the invention makes it possible to maintain an interface between the guiding structure and the thermal SiO2 and thus not to degrade the optical performance of the photonic circuit by absorption.

[0020] A guiding structure with reduced optical losses is then obtained by the process according to the invention without degrading the mechanical robustness of the device or the propagated optical power.

[0021] Summary / Claims

[0022] The invention relates to a method for manufacturing a photonic device comprising the following steps: - provide an optical guidance structure disposed on a first layer of thermal SiO2; the first layer being disposed on a first face of a substrate made of a semiconductor material; - etch the second face opposite the first face of the substrate below at least part of the optical guidance structure up to the first thermal SiO2 layer so as to obtain a membrane formed by part of the first layer suspended above a cavity delimited by two pillars; the optical guidance structure being disposed on said membrane; - deposit a second layer of SiO2 on the first layer on the cavity side in order to increase the thickness of the membrane.

[0023] According to a particular aspect of the invention, the step (iii) of depositing the second layer is carried out by high-density plasma-assisted chemical vapor deposition or by atomic layer deposition or by pulsed laser deposition or by low-pressure chemical vapor deposition.

[0024] According to a particular aspect of the invention, step (i) includes a sub-process for manufacturing the optical guidance structure on the first thermal SiO2 layer.

[0025] According to a particular aspect of the invention, the sub-process for manufacturing the optical guidance structure (WG) comprises the following sub-steps: - provide a substrate (SOI) comprising a silicon film positioned on a buried thermal SiO2 layer positioned on a bulk silicon support; - etch the substrate in such a way as to create a ribbon forming an optical guidance structure from the silicon film on the buried thermal SiO2 layer.

[0026] According to a particular aspect of the invention, the sub-process for manufacturing the optical guidance structure comprises the following sub-steps: - to provide the bulk substrate in a semiconductor material. - deposit the first layer of thermal SiO2 onto the substrate by thermal oxidation; - deposit an intermediate layer of a dielectric material on the first layer; - etch the intermediate layer to structure the optical guidance structure.

[0027] According to a particular aspect of the invention, the process further comprises the following step: depositing a third layer of SiO2 on the second layer on the cavity side; step (iv) being carried out by plasma-assisted chemical vapor deposition or by sputtering or by liquid spinning deposition.

[0028] According to a particular aspect of the invention, the method further comprises the following step: polishing the two pillars on the cavity side so as to expose at least part of the substrate in a semiconductor material.

[0029] According to a particular aspect of the invention, the method further comprises the following step: encapsulating at least a part of the guiding structure in a dielectric encapsulation layer.

[0030] According to a particular aspect of the invention, the method further comprises the following step: Filling the cavity with an adhesive liquid having an optical index within the range [nopt -10%, nopt+10%], nopt being the refractive index of the membrane.

[0031] The invention also relates to a photonic device comprising an optical guidance structure disposed on a membrane suspended between two pillars; said membrane being formed by a stack of layers comprising a first layer of thermal SiO2 and at least one second layer of non-thermal SiO2; the first layer being confined between the optical guidance structure and the second layer.

[0032] According to a particular aspect of the invention, the membrane has a thickness greater than 3 pm.

[0033] According to a particular aspect of the invention, the first layer has a higher density than the second layer. Detailed description

[0034] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0035] Figure 1 illustrates a perspective view of a photonic device according to the state of the art. This figure has already been described.

[0036] Figure [Fig.2] illustrates the flowchart of a manufacturing process according to the invention.

[0037] Figure 3a illustrates the structure obtained at the end of the first step of the process of manufacture according to the invention.

[0038] Fig. 3b illustrates the structure obtained at the end of the second step of the manufacturing process according to the invention.

[0039] Fig. 3c illustrates the structure obtained at the end of the third step of the manufacturing process according to the invention.

[0040] Fig. 3d illustrates the structure obtained at the end of the fourth step of the manufacturing process according to the invention.

[0041] Fig. 3e illustrates the structure obtained at the end of the fifth step of the manufacturing process according to the invention.

[0042] Figure 4 illustrates a photonic device according to the invention.

[0043] Figure 2 illustrates the flowchart of the PI process for manufacturing a photonic DI device according to the invention. Figures 3a to 3e illustrate the steps of the PI process according to the invention.

[0044] The first step (i) consists of providing an optical guidance structure WG disposed on a first thermal SiO2 layer Cl. The intermediate structure obtained at the end of the first step (i) is illustrated in [Fig. 3a]. The first Cl layer is disposed on a first upper face of a SUB substrate made of a semiconductor material, more particularly silicon. The optical guidance structure WG extends along a Y direction orthogonal to the stacking direction Z. The optical guidance structure WG is intended to confine an electromagnetic wave propagating along its Y extension direction. The first Cl layer is obtained by thermal oxidation of the silicon substrate. The first Cl layer has a thickness of between 2 pm and 3 pm. The SUB substrate has a thickness greater than 100 pm.The guide structure is a ribbon made of a dielectric or semiconductor material having an optical index at least 20% higher than that of SiO2, for example, silicon or silicon nitride (SiN). Advantageously, the stack provided in step (i) further includes an ENC encapsulation layer of SiO2 in which at least part of the guide structure is embedded. The ENC encapsulation layer protects the WG guide structure when it is inverted in subsequent steps of the PL manufacturing process.

[0045] The first step (i) may be limited to providing the structure described in [Fig. 3a] previously fabricated. Alternatively, the first step (i) comprises a sub-process for fabricating the optical guidance structure WG on the first thermal SiO2 Cl layer. The sub-process for fabricating the optical guidance structure WG depends on the use of a bulk silicon SUB substrate or a SOI (Silicon on Insulator) type SUB substrate.

[0046] According to a first embodiment, the sub-process for manufacturing the guiding structure comprises the following sub-steps: supplying the bulk silicon SUB substrate and then forming the first Cl layer in thermal SiO2 on the substrate by oxidation thermal; then deposit an intermediate layer of a dielectric or semiconducting material, for example SiN, on the first Cl layer and finally etch the intermediate layer to obtain the ribbon forming the optical guidance structure WG.

[0047] By way of example, the deposition of the intermediate layer in SiN is carried out by Low-Pressure Chemical Vapor Deposition (LPCVD).

[0048] According to a second embodiment, the sub-process for manufacturing the guidance structure comprises the following sub-steps: providing an SOI substrate comprising a silicon film positioned on a buried thermal SiO2 layer positioned on a bulk silicon SUB substrate; then etching the silicon film so as to obtain the ribbon forming the optical guidance structure WG and to uncover the buried thermal SiO2 layer around the optical guidance structure WG.

[0049] Optionally, the PI process includes a step of encapsulating the optical guidance structure WG by depositing an ENC encapsulation layer made of a dielectric, for example, SiO2. For example, the ENC encapsulation layer is deposited by high-density plasma chemical vapor deposition (HDPCVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), or low-pressure chemical vapor deposition (LPCVD). All of these techniques offer a good compromise between the quality of the resulting material and the ease of integration and implementation within a microtechnology manufacturing process. This provides physical protection for the guidance structure without degrading the optical performance of the device.

[0050] The second step (ii) consists of etching the second lower face of the substrate SUB opposite the first face. The intermediate structure obtained at the end of the second step (ii) is illustrated in [Fig. 3b]. The structure provided in step (i) is inverted to perform back etching. The second face opposite the first face of the substrate is etched below at least a portion of the optical guidance structure WG down to the first thermal SiO2 layer Cl. The back etching allows the formation of a membrane consisting of a portion of the first Cl layer suspended above a CV cavity delimited by two pillars PLI, PL2. The optical guidance structure WG is disposed on this membrane ML. The membrane ML, in its current state, has a thickness between 2 µm and 3 µm. The membrane is made of thermal SiO2 with maximized density, an absence of free hydrogen bonds, and a regular interface (without defects in roughness). The volume of semiconductor material of the SUB substrate previously located below the guide structure is removed. The CV cavity has a width 11 greater than the width of the WG guide structure. The width 11 of the CV cavity is between 1 Opm and 200 µm. The back-etching is performed using a dry and / or wet etching technique. Partial removal of the substrate below the WG guide structure eliminates optical losses resulting from the overlap between the light and the semiconductor substrate.

[0051] The third step (iii) consists of depositing a second C2 layer of SiO2 onto the first Cl layer on the CV cavity side so as to increase the thickness of the ML membrane. The intermediate structure obtained at the end of the third step (iii) is illustrated in [Fig. 3c]. The deposition of the second layer is carried out by high-density plasma chemical vapor deposition (HDPCVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), or low-pressure chemical vapor deposition (LPCVD). The second C2 layer has a lower quality than the first thermal SiO2 layer but is sufficient to obtain better optical performance with reduced losses compared to known solutions.On the other hand, implementing this step is simpler and less energy-intensive than thermal oxidation. The techniques listed above allow for a compromise between the quality of the resulting material and the ease of integration and implementation within a microtechnology manufacturing process. Adding the second lower layer C2 allows the thickness hl of the Ml membrane to be increased to values ​​greater than 3 µm without resorting to thermal annealing. Increasing the thickness of the Ml membrane simultaneously eliminates optical losses due to overlap and mechanically reinforces the fabricated photonic device. Furthermore, the Ml membrane maintains a contact interface between the WG guiding structure and the first thermal SiO2 layer Cl.It is worth noting that thermal SiO2 has a better density and an absence of free hydrogen bonds, thus minimizing losses through absorption of propagated light.

[0052] The fourth step (iv) consists of depositing a third SiO2 layer C3 onto the second layer C2 on the CV cavity side. The intermediate structure obtained at the end of the fourth step (iv) is illustrated in [Fig. 3d]. Step (iv) is carried out by plasma-enhanced chemical vapor deposition (PECVD), sputtering, or liquid spinning. The third C3 layer mechanically reinforces the structure, and more specifically the membrane. The deposition techniques used allow for the rapid and inexpensive production of a C3 reinforcing layer. The optical quality of the SiO2 in the third C3 layer is inferior to that of the first Cl layer or the second C2 layer, but this does not compromise the confinement of the propagated light. This is because the third C3 layer is sufficiently far from the WG guiding structure. The distance separating the third C3 layer from the WG guiding structure is greater than 3 pm.

[0053] Advantageously, and optionally, the PI process includes a polishing step (v) of the two PLI, PL2 pillars on the CV cavity side. This removes the SiO2 deposited on the lower surface of the PLI, PL2 pillars, exposing at least a portion of the SUB substrate to a semiconductor material. This creates electrostatic contact zones (ZC) between the SUB substrate and the manufacturing machines. These electrostatic contact zones prevent the accumulation of electrical charges at the interface between the SUB substrate and the manufacturing machines during the various stages of the chip manufacturing process. The intermediate structure obtained after the polishing step is illustrated in [Fig. 3d].

[0054] Advantageously, and optionally, the PI process includes a step of filling the cavity by CV an adhesive liquid having an optical index within the range [nopt -10%, nopt+10%], nopt being the refractive index of the ML membrane. This improves the confinement of the light propagated in the WG guiding structure.

[0055] Figure 4 illustrates the DI photonic device according to the invention. The DI photonic device comprises an optical guidance structure WG placed on a membrane M1 suspended between two PLI pillars, PL2. This membrane M1 is formed by a stack of layers, comprising a first layer Cl of thermal SiO2 and at least one second layer C2 of non-thermal or deposited SiO2. The first layer Cl is confined between the optical guidance structure WG and the second layer C2. The membrane M1 has a thickness greater than 3 µm. This suspended structure eliminates optical losses due to overlap with the substrate and provides improved mechanical robustness. The first layer Cl of thermal SiO2 provides a regular and dense interface with the guidance structure, thus improving the optical performance of the system.The first thermal SiO2 Cl layer does not have free hydrogen bonds, which limits losses due to absorption of light propagated by the ML membrane. Optionally, the ML membrane includes a third non-thermal SiO2 C3 layer to mechanically reinforce the floating structure. Optionally, the WG guide structure is encapsulated in a dielectric encapsulation layer for mechanical protection.

[0056] The photonic DI device can be a directional coupler, a radio frequency modulator, or a ring source. A directional coupler in photonics is an optical device that allows light from different optical paths to be split or combined in a controlled manner. A photonic RF (Radio Frequency) modulator is an optoelectronic device used to modulate an optical signal in response to a high-frequency (RF) electrical signal. It allows control of various characteristics of the light, such as its amplitude, frequency, or phase. A ring source in photonics is an optical device that uses a ring-shaped structure to generate photons. The light injected into the ring undergoes multiple internal reflections, which can increase the efficiency of photon generation at certain wavelengths.These sources are used in various photonics applications for their ability to produce high-quality light and precisely control the emitted wavelength.

Claims

Demands

1. A method (PI) for manufacturing a photonic device (Dl) comprising the following steps: i. providing an optical guidance structure (WG) disposed on a first thermal SiO2 layer; the first layer (Cl) being disposed on a first face of a substrate (SUB) made of a semiconductor material; ii. etching the second face opposite the first face of the substrate (Sub) below at least a portion of the optical guidance structure (WG) down to the first thermal SiO2 layer (Cl) so as to obtain a membrane (Ml) formed by a portion of the first layer suspended above a cavity (CV) delimited by two pillars (PL1, PL2); the optical guidance structure (WG) being disposed on said membrane (Ml); iii. depositing a second SiO2 layer (C2) on the first layer (Cl) on the cavity (CV) side so as to increase the thickness of the membrane (Ml);

2. A method (PI) for manufacturing a photonic device (Dl) according to claim 1 wherein the step (iii) of deposition of the second layer (C2) is carried out by high-density plasma-assisted chemical vapor deposition (HDPCVD) or by atomic layer deposition (ALD) or by pulsed laser deposition (PLD) or by low-pressure chemical vapor deposition (LPCVD).

3. Method (PI) of manufacturing a photonic device (Dl) according to any one of claims 1 or 2 wherein step (i) comprises a sub-method of manufacturing the optical guidance structure (WG) on the first layer (Cl) in thermal SiO2.

4. A method (PI) for manufacturing a photonic device (Dl) according to claim 3, wherein the sub-method for manufacturing the optical guidance structure (WG) comprises the following sub-steps: provide a substrate (SOI) comprising a silicon film positioned on a buried thermal SiO2 layer positioned on a bulk silicon support; - etch the substrate in such a way as to create a ribbon forming an optical guidance structure from the silicon film on the buried thermal SiO2 layer.

5. A method (PI) for manufacturing a photonic device (Dl) according to claim 3, wherein the sub-method for manufacturing the optical guidance structure (WG) comprises the following sub-steps: - providing the bulk substrate (SUB) of a semiconductor material; - depositing the first layer (Cl) of thermal SiO2 onto the substrate by thermal oxidation; - depositing an intermediate layer of a dielectric material onto the first layer (Cl); - etching the intermediate layer to structure the optical guidance structure (WG).

6. A method (PI) for manufacturing a photonic device (Dl) according to any one of claims 1 to 5 further comprising the following step: (iv) depositing a third layer (C3) of SiO2 on the second layer (C2) on the cavity (CV) side; step (iv) being carried out by plasma-enhanced chemical vapor deposition (PECVD) or by sputtering or by liquid spinning deposition.

7. A method (PI) for manufacturing a photonic device (Dl) according to any one of claims 1 to 6 further comprising the following step: (v) polishing the two pillars (PLI, PL2) on the cavity (CV) side so as to expose at least a portion of the substrate (SUB) in a semiconductor material.

8. Method (PI) of manufacturing a photonic device (Dl) according to any one of claims 1 to 7 further comprising the following step: encapsulating at least a part of the guiding structure (WG) in a dielectric encapsulation layer (ENC).

9. A method (PI) for manufacturing a photonic device (Dl) according to any one of claims 1 to 8, further comprising the following step:

10.

11.

12.

13. Fill the cavity (CV) with an adhesive liquid having an optical index within the range [nopt -10%, nopt+10%], nopt being the refractive index of the membrane (Ml). Photonic device (Dl) comprising an optical guidance structure (WG) disposed on a membrane (Ml) suspended between two pillars (PL1, PL2); said membrane (Ml) being formed by a stack of layers comprising a first layer (Cl) in thermal SiO2 and at least a second layer (C2) in non-thermal SiO2; the first layer (Cl) being confined between the optical guidance structure (WG) and the second layer (C2). Photonic device (Dl) according to claim 10 in which the membrane has a thickness greater than 3 pm. Photonic device (Dl) according to any one of claims 10 or 11 wherein the first layer (Cl) is devoid of free hydrogen bonds. Photonic device (Dl) according to any one of claims 10 to 12 in which the first layer (Cl) has a higher density than the second layer (C2).

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