Wafer-level chip packaging structure and electronic equipment

Abstract

The embodiment of the invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to improve the transmission performance between chips. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are arranged in a stacked mode, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel. The wafer level chip is arranged on the adapter plate. The wafer level chip includes a plurality of device regions, each device region including at least one chip. Along a first direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, and the chips in the two device regions at the two ends are connected through an optical interconnection channel. Along a second direction parallel to the adapter plate, the chips in the two adjacent device regions are connected through an electric interconnection channel, the chips in the two device regions at the two ends are connected through an optical interconnection channel, and the first direction and the second direction are crossed.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and particularly relates to a wafer-level chip packaging structure and an electronic device. BACKGROUND

[0002] With the rapid development of artificial intelligence, the hardware system continues to evolve, but there are bottlenecks at the system level. The AI computing power platform is limited to support large-scale model training, the high-bandwidth domain supports limited parallel computing scale, the communication delay rises with the expansion of nodes, and the existing architecture is difficult to support the continuous expansion of dense models. Moreover, in terms of cluster networking, the expansion of high-bandwidth domain encounters the "scale wall", which is restricted by physical distance, overhead, link utilization, etc. Wafer-level packaging is considered as the direction of hardware evolution, but it faces challenges such as long transmission distance between chips.

[0003] Therefore, how to improve the transmission performance between chips has become a problem to be solved in the field. SUMMARY

[0004] The present application provides a wafer-level chip packaging structure and an electronic device, which aims to improve the transmission performance between chips.

[0005] In one aspect, the present application provides a wafer-level chip packaging structure, which includes a conversion board and a wafer-level chip. The conversion board includes a first heavy wiring layer and a second heavy wiring layer stacked. The first heavy wiring layer includes an optical interconnection channel, and the second heavy wiring layer includes an electrical interconnection channel. The wafer-level chip is arranged on the conversion board. The wafer-level chip includes a plurality of device regions, each device region including at least one chip. In the first direction parallel to the conversion board, the chips in the adjacent two device regions are connected through the electrical interconnection channel, and the chips at the two ends of the two device regions are connected through the optical interconnection channel. In the second direction parallel to the conversion board, the chips in the adjacent two device regions are connected through the electrical interconnection channel, and the chips at the two ends of the two device regions are connected through the optical interconnection channel, and the first direction intersects with the second direction.

[0006] In the embodiments of the present application, the wafer-level chip packaging structure includes a conversion board and a wafer-level chip. The wafer-level chip is arranged on the conversion board. The conversion board includes a first heavy wiring layer and a second heavy wiring layer stacked. The optical interconnection channel is arranged in the first heavy wiring layer, and the electrical interconnection channel is arranged in the second heavy wiring layer. The wafer-level chip includes a plurality of device regions, each device region including at least one chip.

[0007] It can be understood that the chips in the device regions can be connected through the optical interconnection channels in the first redistribution layer and through the electrical interconnection channels in the second redistribution layer, so as to realize the optical-electrical collaborative interconnection communication between different chips. Moreover, the optical interconnection channels and the electrical interconnection channels are located in different redistribution layers, so that the optical interconnection channels and the electrical interconnection channels are decoupled from each other, and the signals transmitted by the two are independent of each other, thereby facilitating the improvement of the anti-interference performance of signal transmission and ensuring the feasibility and flexibility in hardware design.

[0008] Moreover, along a first direction parallel to the adapter plate, the chips in two adjacent device regions are connected through the electrical interconnection channels, and the chips in the two device regions at the two ends are connected through the optical interconnection channels. Along a second direction parallel to the adapter plate, the chips in two adjacent device regions are connected through the electrical interconnection channels, and the chips in the two device regions at the two ends are connected through the optical interconnection channels. The first direction intersects the second direction.

[0009] It can be understood that the plurality of device regions in the wafer-level chip are arranged and connected in a 2D-Torus (two-dimensional torus) manner. One device region is one node. The distance between adjacent device regions is relatively short, and the two are connected through the electrical interconnection channels. The distance between the device regions at the two ends of the torus is relatively far, and the two are connected through the optical interconnection channels, so as to realize the collaborative communication of optical interconnection and electrical interconnection.

[0010] Moreover, the electrical interconnection has the advantages of high speed, low power consumption, and high density, and the optical interconnection has the advantages of end delay and high bandwidth density. Through the arrangement of the present application, efficient data transmission can be realized between any two device regions on the wafer-level chip packaging structure, so as to achieve a high level of inter-chip communication efficiency and overall computing performance, thereby improving the transmission performance between chips.

[0011] In some embodiments, the wafer-level chip is arranged on the side of the second redistribution layer away from the first redistribution layer.

[0012] In some embodiments, the wafer-level chip is arranged on the side of the first redistribution layer away from the second redistribution layer.

[0013] In some embodiments, the optical interconnection channel includes a laser source, a modulator, and a photodetector. The plurality of device regions include at least a first device region and a second device region, the first device region includes a first chip, and the second device region includes a second chip. The chip includes a sending circuit and a receiving circuit, the sending circuit of the first chip is electrically connected to the modulator, and the receiving circuit of the second chip is electrically connected to the photodetector. The modulator is configured to convert the laser from the laser source into an optical signal according to an electrical signal from the sending circuit of the first chip, and transmit the optical signal to the photodetector. The photodetector is configured to convert the optical signal into a current signal, and transmit the current signal to the receiving circuit of the second chip.

[0014] In some embodiments, the transmitting circuit includes a first data buffer, a serial converter and a driving amplifier which are electrically connected in sequence. The first data buffer is configured to receive the first electrical signal and transmit the first electrical signal to the serial converter. The serial converter is configured to convert the first electrical signal into a serial signal and transmit the serial signal to the driving amplifier. The driving amplifier is configured to amplify the serial signal to form the electrical signal and transmit the electrical signal to the modulator.

[0015] In some embodiments, the receiving circuit includes a cross-group amplifier, a comparator and a second data buffer which are electrically connected in sequence. The cross-group amplifier is configured to convert the current signal into a level signal and transmit the level signal to the comparator. The comparator is configured to output the second electrical signal to the second data buffer according to the level signal.

[0016] In some embodiments, the wafer-level chip further includes a plurality of thermal management modules, and the thermal management modules are arranged in the transmitting circuit and the receiving circuit.

[0017] In some embodiments, the second rewiring layer further includes a vertical interconnection structure, one end of the vertical interconnection structure is electrically connected with the optical interconnection channel, and the other end of the vertical interconnection structure is electrically connected with the chip in the device region located at the other end.

[0018] In another aspect, the present application also provides an electronic device, which includes the wafer-level chip packaging structure in any of the above embodiments and a circuit board. The wafer-level chip packaging structure is electrically connected with the circuit board.

[0019] The electronic device has the same beneficial technical effects as the wafer-level chip packaging structure, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and not the actual size of the product involved in the embodiments of the present application, the actual flow of the method.

[0021] Figure 1 A side view of the wafer-level chip packaging structure provided by the embodiments of the present application; Figure 2 A top view of the wafer-level chip packaging structure provided by the embodiments of the present application; Figure 3 A schematic diagram of the internal structure of the wafer-level chip packaging structure provided by the embodiments of the present application; Figure 4 A structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0023] Unless otherwise required by context, the term “comprises” in the specification and claims is to be construed as an open, inclusive meaning, i.e., “comprising, but not limited to”.

[0024] Hereinafter, the terms “first” and “second” are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of “a plurality of” is two or more.

[0025] In describing some embodiments, the term “connected” and its conjugations can be used. The term “connected” should be interpreted broadly, for example, “connected” can be fixedly connected, or detachably connected, or integrated. It can be directly connected, or indirectly connected through an intermediate medium. For example, in describing some embodiments, the term “connected” can be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0026] In addition, the use of “based on” means open and inclusive, because the process, step, calculation or other action “based on” one or more conditions or values can be based on additional conditions or values in practice.

[0027] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0028] With the rapid development of artificial intelligence technology, hardware systems continue to evolve to meet the urgent needs of AI models for high computing power and high bandwidth. However, there are still many bottlenecks at the system level. Current AI computing platforms face significant constraints in supporting larger-scale model training, deviating significantly from the expansion laws revealed by the Scaling Law. Specifically, the high-bandwidth domain (HBD) can usually only support a limited number of high-computing nodes in parallel computing. As the node scale expands, the limited interconnection bandwidth (such as 200 GB / s) leads to a sharp rise in communication delay. For example, when the parallel scale expands from 4 nodes to 32 nodes, the system delay increases by about 3.3 times. In addition, the existing hardware architecture is difficult to effectively support the continuous expansion of dense models with larger parameter scales (such as Qwen2.5-14B, etc.), resulting in the current mainstream dense model parameter scale being limited to less than 8 billion, thereby limiting the further breakthrough of the capability boundary of large models.

[0029] In terms of cluster networking, the expansion of the high-bandwidth domain also encounters the constraints of the "scale wall". On the one hand, the high-bandwidth domain is limited by the physical transmission distance. For example, although the Scale-up architecture based on NVLink can achieve a domain bandwidth of 900 GB / s, its effective coverage range is usually no more than 50 meters, making it difficult to achieve large-scale deployment across cabinets. On the other hand, high-bandwidth networking has significant overheads at multiple levels: at the transaction transmission level, the delay introduced by the multi-layer switching network can be up to 3 times that of a single-layer network, and MB (megabyte) to hundreds of MB of cache need to be configured to ensure throughput performance; at the physical connection level, cross-cabinet optical interconnection has problems such as signal attenuation, insufficient reliability, high power consumption, and optical-electrical conversion delay (about 400 ns); at the link utilization level, due to the strong sequentiality requirement of memory transactions, existing protocols are difficult to achieve efficient load balancing, thereby restricting the communication efficiency and scalability of large-scale clusters.

[0030] In this context, wafer-level packaging is considered an important direction for the evolution of future hardware systems. This technology integrates different functional modules on a single wafer, integrates communication units using an interposer, and builds logic, storage, and other functional chips (dies) on it. However, wafer-level packaging currently still faces technical challenges such as long chip-to-chip transmission distances.

[0031] Wafer-level system interconnects are expected to break through the limitations of traditional chip-to-chip interconnects, such as the "scaling wall". Currently, a complete process flow has been developed to realize interconnection between multiple dies, but the communication medium of the existing scheme still generally uses traditional electrical signals. When the physical distance between nodes is far, electrical signals have problems such as low bandwidth density, poor signal integrity, and large transmission delay. For wafer size, the distance between remote chips has exceeded the effective range of reliable transmission of electrical signals. If a relay node is added in the communication path to extend the transmission distance, additional delay and power consumption will be introduced.

[0032] In the face of the above bottlenecks of electrical interconnection, optical interconnection has become an important technical path to replace electrical transmission in long-distance node communication, with its advantages of high bandwidth density, low transmission delay, and low power consumption. In recent years, some progress has been made in introducing optical interconnection into wafer-level chips, but there are still many challenges in realizing all-optical interconnection. The conversion of electrical signals to optical signals requires the introduction of additional hardware resources, resulting in the overall performance and energy efficiency of optical interconnection still being inferior to electrical interconnection in short-distance communication scenarios. Therefore, when the communication distance is short (generally considered to be within about 2 centimeters), electrical interconnection is still a better choice. The diameter of a 12-inch wafer can be up to about 30 centimeters, which is much longer than the critical distance. At present, there is still a lack of a wafer-level chip system design scheme that can efficiently cooperate optical and electrical interconnections to realize the complementary advantages of performance and power consumption.

[0033] Therefore, in one aspect, the embodiments of the present application provide a wafer-level chip packaging structure, Figure 1 a side view of the wafer-level chip packaging structure provided by the embodiments of the present application; Figure 2 a top view of the wafer-level chip packaging structure provided by the embodiments of the present application.

[0034] Referring to Figure 1 The wafer-level chip packaging structure 10 includes a conversion board 1 and a wafer-level chip 2.

[0035] Referring to Figure 1 and Figure 2 The conversion board 1 includes a first re-distribution layer (RDL) 11 and a second RDL 12 stacked, the first RDL 11 includes an optical interconnection channel 3, and the second RDL 12 includes an electrical interconnection channel 4. The wafer-level chip 2 is arranged on the conversion board 1.

[0036] For example, the conversion board 1 and the wafer-level chip 2 can be welded by a micro bump 100 to realize electrical connection between the two. The conversion board 1 can also be called a hybrid interposer.

[0037] It can be understood that, no matter the optical interconnection channel 3 or the electrical interconnection channel 4, signal transmission is performed through the adapter board 1, and the RDL of the optical interconnection channel 3 and the RDL of the electrical interconnection channel 4 are respectively located on different layers of the adapter board 1, i.e., the first redistribution layer 11 and the second redistribution layer 12.

[0038] The wafer-level chip 2 includes a plurality of device regions N, each of which includes at least one chip 5.

[0039] Exemplarily, the chip 5 can be a silicon optical device. For example, the chip 5 can be an optical communication switch chiplet, or the chip 5 can also be other computing power chips. Embodiments of the present application do not limit the type of chip 5.

[0040] Referring to Figure 2 , along a first direction X parallel to the adapter board 1, the chips 5 in two adjacent device regions N are connected through the electrical interconnection channel 4, and the chips 5 at both ends of the two device regions N are connected through the optical interconnection channel 3. Along a second direction Y parallel to the adapter board 1, the chips 5 in two adjacent device regions N are connected through the electrical interconnection channel 4, and the chips 5 at both ends of the two device regions N are connected through the optical interconnection channel 3. The first direction X and the second direction Y intersect, and embodiments of the present application take the case where the first direction X and the second direction Y are perpendicular as an example.

[0041] It can be understood that the plurality of device regions N are arranged and connected in a 2D-Torus (two-dimensional torus) manner. One device region N is one node. That is, a two-dimensional ring grid topology is formed in which the device regions N at the head and tail of each row and each column are connected. The nodes at the above-mentioned grid boundary are connected to the opposite side through a "wrap-around edge", so as to shorten the longest transmission path of the device region N and increase the equivalent bandwidth.

[0042] In addition, in the case where there is a communication demand between different device regions N, the distance between the chips 5 in two adjacent device regions N is close, and the two are connected through the electrical interconnection channel 4, i.e., electrical interconnection is used to send information from the source end to the destination end. The distance between the chips 5 in two device regions N at both ends is far, and the two are connected through the optical interconnection channel 3, i.e., optical interconnection is used to send information from the source end to the destination end.

[0043] Exemplarily, continuing to refer to Figure 2Embodiments of the present application take a 4*4 array of device regions N as an example. The wafer-level chip 2 includes four rows and four columns, along a first direction X, the first row includes device region N11, device region N12, device region N13 and device region N14, the second row includes device region N21, device region N22, device region N23 and device region N24, the third row includes device region N31, device region N32, device region N33 and device region N34, and the fourth row includes device region N41, device region N42, device region N43 and device region N44.

[0044] For example, taking device region N11 as an example, device region N12 and device region N21 are connected with device region N11 through electrical interconnection channel 4, and device region N14 and device region N41 are connected with device region N11 through optical interconnection channel 3.

[0045] For example, Figure 1 Device region N11, device region N12 and device region N14 are shown in FIG. 1. Device region N11 is arranged adjacent to device region N12, and the two are connected through electrical interconnection channel 4. Along the first direction X, device region N11 and device region N14 are located at the two ends respectively, and the two are connected through optical interconnection channel 3.

[0046] In embodiments of the present application, the wafer-level chip packaging structure 10 includes a conversion board 1 and a wafer-level chip 2. The wafer-level chip 2 is arranged on the conversion board 1. The conversion board 1 includes a first redistribution layer 11 and a second redistribution layer 12 arranged in layers, the first redistribution layer 11 is arranged with optical interconnection channel 3, and the second redistribution layer 12 is arranged with electrical interconnection channel 4. The wafer-level chip 2 includes a plurality of device regions N, and each device region N includes at least one chip 5.

[0047] It can be understood that the chip 5 in the device region N can be connected through the optical interconnection channel 3 of the first redistribution layer 11, or through the electrical interconnection channel 4 in the second redistribution layer 12, so as to realize photoelectric collaborative interconnection communication between different chips 5. The optical interconnection channel 3 and the electrical interconnection channel 4 are located in different redistribution layers, so that the optical interconnection channel 3 and the electrical interconnection channel 4 are decoupled, and the signals transmitted by the two are independent of each other, thereby facilitating the improvement of the anti-interference performance of signal transmission, and ensuring the feasibility and flexibility in hardware design.

[0048] Furthermore, along the first direction X parallel to the conversion board 1, the chips 5 in the two adjacent device regions N are connected through the electrical interconnection channel 4, and the chips 5 in the two device regions N at the two ends are connected through the optical interconnection channel 3. Along the second direction Y parallel to the conversion board 1, the chips 5 in the two adjacent device regions N are connected through the electrical interconnection channel 4, and the chips 5 in the two device regions N at the two ends are connected through the optical interconnection channel 3, and the first direction X and the second direction Y intersect.

[0049] It can be understood that the plurality of device regions N in the wafer-level chip 2 are arranged and connected in a 2D-Torus (two-dimensional ring network) manner. One device region N is a node. Adjacent device regions N are close to each other and are connected through the electrical interconnection channel 4. Device regions N at two ends of the ring network are far away from each other and are connected through the optical interconnection channel 3, so as to realize cooperative communication of optical interconnection and electrical interconnection.

[0050] In addition, the electrical interconnection has the advantages of high speed, low power consumption, and high density. The optical interconnection has the advantages of end delay and high bandwidth density. Through the arrangement of the present application, efficient data transmission can be realized between any two device regions N on the wafer-level chip packaging structure 10, so as to achieve a high level of inter-chip communication efficiency and overall computing performance, thereby improving the transmission performance between the chips 5.

[0051] In some embodiments, referring to Figure 1 , the wafer-level chip 2 is arranged on the side of the second redistribution layer 12 away from the first redistribution layer 11. It can be understood that, along the direction Z, the second redistribution layer 12 is located above the first redistribution layer 11, and the wafer-level chip 2 is in direct contact with the second redistribution layer 12.

[0052] By arranging the second redistribution layer 12 closer to the wafer-level chip 2, the length of the electrical interconnection channel 4 can be shortened, thereby shortening the distance between the chips 5 in adjacent device regions N connected through the electrical interconnection channel 4, which is conducive to reducing the electrical interconnection channel delay, so as to further improve the transmission performance between the chips 5.

[0053] In some embodiments, referring to Figure 1 , the second redistribution layer 12 further comprises a vertical interconnection structure 7. For example, the vertical interconnection structure 7 can be a through-silicon via (TSV). One end of the vertical interconnection structure 7 is electrically connected with the optical interconnection channel 3, and the other end is electrically connected with the chip 5 in the device region N at the two ends.

[0054] It can be understood that, along the direction Z, the first redistribution layer 11 provided with the optical interconnection channel 3 is located at the lowermost position, and the optical interconnection channel 3 is electrically connected with the chip 5 in the device region N through the TSV penetrating through the second redistribution layer 12.

[0055] In some embodiments, the wafer-level chip 2 is arranged on the side of the first redistribution layer 11 away from the second redistribution layer 12. It can be understood that, along the direction Z, the second redistribution layer 12 can also be located below the first redistribution layer 11, and the wafer-level chip 2 is in direct contact with the first redistribution layer 11, which is conducive to realizing long-distance interconnection of the device regions N through the optical interconnection channel 3.

[0056] The electrical interconnection channel 4 and the optical interconnection channel 3 are located in different redistribution layers, and signals transmitted by the two are independent of each other, thereby improving the anti-interference of signal transmission and improving the accuracy of signals.

[0057] Figure 3 An internal structure diagram of a wafer-level chip package structure provided by an embodiment of the present application.

[0058] In some embodiments, referring to Figure 3 , the optical interconnection channel 3 includes a laser source 31, a modulator 32, and a photodetector 33. The photodetector 33 may, for example, be a photodiode detector (PD).

[0059] The plurality of device regions N includes at least a first device region N1 and a second device region N2, the first device region N1 including a first chip 51, and the second device region N2 including a second chip 52. The first device region N1 and the second device region N2 may, for example, be device regions N located at the edges of a 2D-Torus, and the two are connected by the optical interconnection channel 3.

[0060] The chip 5 includes a sending circuit 61 and a receiving circuit 62, the sending circuit 61 of the first chip 51 being electrically connected to the modulator 32, and the receiving circuit 62 of the second chip 52 being electrically connected to the photodetector 33.

[0061] The first chip 51 may, for example, include two sending circuits 61 and two receiving circuits 62. The sending circuit 61 of the first chip 51 may, for example, be electrically connected to the modulator 32 through a micro bump 100. The internal structure of the second chip 52 may be the same as or different from that of the first chip 51. In the present application, the internal structure of the second chip 52 is taken as an example of being the same as that of the first chip 51, and the internal structure of the second chip 52 is simplified in Figure 3 , for example. The receiving circuit 62 of the second chip 52 may, for example, be electrically connected to the photodetector 33 through a micro bump 100.

[0062] Continuing to refer to Figure 3 , the modulator 32 is configured to convert laser light from the laser source 31 into an optical signal according to an electrical signal from the sending circuit 61 of the first chip 51, and transmit the optical signal to the photodetector 33. The photodetector 33 is configured to convert the optical signal into a current signal, and transmit the current signal to the receiving circuit 62 of the second chip 52.

[0063] It can be understood that the transmitting circuit 61 of the first chip 51 transmits the electrical signal to the modulator 32, and the laser source 31 transmits the laser to the modulator 32, the modulator 32 modulates the laser according to the electrical signal, converts the laser into an optical signal, and the optical signal carries the information of the first chip 51. Then the modulated optical signal is transmitted to the photodetector 33 connected to the second chip 52, the photodetector 33 converts the optical signal into a weak current signal and transmits it to the receiving circuit 62 of the second chip 52, thereby realizing the signal transmission between the first chip 51 and the second chip 52.

[0064] In some embodiments, referring to Figure 3 , the transmitting circuit 61 comprises a first data buffer 611, a serializer 612 and a driver 613 connected in sequence.

[0065] The first data buffer 611 is used to receive the first electrical signal and transmit the first electrical signal to the serializer 612. The serializer 612 is used to convert the first electrical signal into a serial signal and transmit the serial signal to the driver 613. The driver 613 is used to amplify the serial signal to form an electrical signal and transmit the electrical signal to the modulator 32.

[0066] It can be understood that the first electrical signal enters the first chip 51 through the first data buffer 611, and after the first electrical signal is converted into a serial signal by the serializer 612, the serial signal is amplified by the driver 613 to form an electrical signal transmitted to the modulator 32. After modulation by each component in the transmitting circuit 61, the signal quality of the electrical signal finally transmitted by the transmitting circuit 61 is better, which is conducive to improving the signal transmission quality between the chips 5.

[0067] In some embodiments, referring to Figure 3 , the receiving circuit 62 comprises a trans-impedance amplifier (TIA) 621, a comparator 622 and a second data buffer 623 connected in sequence. The comparator 622 can distinguish whether the input analog signal is "0" or "1".

[0068] The trans-impedance amplifier 621 is used to convert the current signal into a level signal and transmit the level signal to the comparator 622. The comparator 622 is used to output a second electrical signal to the second data buffer 623 according to the level signal.

[0069] For example, after the photoelectric detector 33 transmits the current signal to the receiving circuit 62, the current signal enters the cross-group amplifier 621, which converts the weak current signal into a level signal, and then the comparator 622 performs bit identification on the level signal, and outputs the standard 0 bit or 1 bit information (i.e. the second electric signal) to the second data buffer 623.

[0070] For example, after the second data buffer 623 receives the second electric signal, the second data buffer 623 can input the second electric signal to the internal computing core of the device area N, so as to complete information transmission.

[0071] In some embodiments, referring to Figure 3 , the wafer-level chip 2 further comprises a plurality of thermal management modules 63, and the sending circuit 61 and the receiving circuit 62 are both provided with the thermal management module 63. For example, the thermal management module 63 comprises a thermal stabilizer (Thermal). In the case that the temperature of the chip 5 changes, the thermal management module 63 can reduce the changes of the power, frequency, material size, mechanical stress, etc. of the chip 5, so as to improve the performance, service life and reliability of the chip 5.

[0072] For example, referring to Figure 2 and Figure 3 , the first device area N1 shown in the figure comprises two optical interconnection channels 3 and two electrical interconnection channels 4, so the first device area N1 can be a node in the 2D-Torus which requires two optical interconnections and two electrical interconnections, such as N11, N14, N41 and N44.

[0073] In addition, the device areas N in other positions can be connected with different numbers of optical interconnection channels 3 and electrical interconnection channels 4 according to the interconnection requirements in the topology structure. For example, N12, N13, N21, N31, N24 and N34 have one optical interconnection channel 3 and three electrical interconnection channels 4. For example, N22, N23, N32 and N33 have four electrical interconnection channels 4. The device areas N connected with the optical interconnection channel 3 can share the same laser source (Laser) 31.

[0074] On the other hand, the embodiments of the present application also provide an electronic device, Figure 4 which is a structural schematic diagram of the electronic device provided by the embodiments of the present application.

[0075] Referring to Figure 4 , the electronic device 20 comprises a wafer-level chip packaging structure 10 and a circuit board 8. The wafer-level chip packaging structure 10 is electrically connected with the circuit board 8.

[0076] For example, the wafer-level chip packaging structure 10 can be welded with the circuit board 8 through the soldering points 81. For example, the soldering points 81 can be C4 bumps.

[0077] Since the wafer level chip package structure 10 improves the transmission performance between chips, the transmission performance inside the electronic device 20 including the wafer level chip package structure 10 is also improved.

[0078] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can think of the changes or replacements within the technical scope disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A wafer level chip scale package structure, comprising: Comprising: a transition plate comprising a first heavy wiring layer and a second heavy wiring layer stacked, the first heavy wiring layer comprising optical interconnection channels, the second heavy wiring layer comprising electrical interconnection channels; a wafer-level chip disposed on the transition plate; the wafer-level chip comprising a plurality of device regions, each device region comprising at least one chip; in a first direction parallel to the transition plate, the chips in adjacent two device regions are connected through the electrical interconnection channels, and the chips in the two end device regions are connected through the optical interconnection channels; in a second direction parallel to the transition plate, the chips in adjacent two device regions are connected through the electrical interconnection channels, and the chips in the two end device regions are connected through the optical interconnection channels, the first direction intersecting the second direction.

2. The wafer level chip package structure of claim 1, wherein, The wafer-level chip is disposed on the side of the second heavy wiring layer away from the first heavy wiring layer.

3. The wafer level chip package structure of claim 1, wherein, The wafer-level chip is disposed on the side of the first heavy wiring layer away from the second heavy wiring layer.

4. The wafer level chip package structure of claim 1, wherein, The optical interconnection channel comprises a laser source, a modulator and a photodetector; the plurality of device regions comprises at least a first device region and a second device region, the first device region comprising a first chip, and the second device region comprising a second chip; The chip comprises a transmitting circuit and a receiving circuit, the transmitting circuit of the first chip is electrically connected with the modulator, and the receiving circuit of the second chip is electrically connected with the photodetector; The modulator is configured to convert laser from the laser source into an optical signal according to an electrical signal from the transmitting circuit of the first chip, and transmit the optical signal to the photodetector; The photodetector is configured to convert the optical signal into a current signal, and transmit the current signal to the receiving circuit of the second chip.

5. The wafer level chip package structure of claim 4, wherein, The transmitting circuit comprises a first data buffer, a serial converter and a driving amplifier connected in sequence; The first data buffer is configured to receive a first electrical signal and transmit the first electrical signal to the serial converter; the serial converter is configured to convert the first electrical signal into a serial signal and transmit the serial signal to the driving amplifier; The driving amplifier is configured to amplify the serial signal to form the electrical signal and transmit the electrical signal to the modulator.

6. The wafer level chip package structure of claim 4, wherein, The receiving circuit comprises a cross-group amplifier, a comparator and a second data buffer connected in sequence; The cross-group amplifier is configured to convert the current signal into a level signal and transmit the level signal to the comparator; the comparator is configured to output a second electrical signal to the second data buffer according to the level signal.

7. The wafer level chip package structure of claim 4, wherein, The wafer-level chip further comprises a plurality of thermal management modules, and the thermal management modules are disposed in the transmitting circuit and the receiving circuit.

8. The wafer level chip package structure of claim 2, wherein, The second heavy wiring layer further comprises a vertical interconnection structure, one end of the vertical interconnection structure is electrically connected with the optical interconnection channel, and the other end is electrically connected with the chip in the two end device regions.

9. An electronic device, comprising: Comprising: The wafer-level chip packaging structure according to any one of claims 1-8; A circuit board, the wafer-level chip packaging structure is electrically connected with the circuit board.

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