Current-driven magnetic RAM electronic circuit

Abstract

A random access memory electronic circuit comprising an array (100) of memory cells (10), each including at least one magnetic pillar and a spin-interacting Hall effect line forming a tripole, each cell (10) further comprising a means for selecting the connection to the terminals of said tripole, a terminal (WL(k)) of each cell being connected in the circuit for selecting memory cells of the array according to a first dimension of the array using the means for selecting the memory cells, and a pair of terminals (BL(i), BLB(i)) of each cell being connected in the circuit to allow a common application, to memory cells of the array selected according to a second dimension of the array, of electrical energy for reading or writing magnetic information in the pillar.The said electrical energy being applied by circulating a current controlled by a current control circuit (111). Abbreviated figure: 7C.

Description

Title of the invention: Current-driven magnetic RAM electronic circuit Technical context

[0001] The invention relates to the field of random access memory (RAM), specifically magnetic memory or MRAM, which uses the magnetic orientation of the electron to store information over the long term. These are known as non-volatile RAM. The cells consist of two ferromagnetic layers, for example, cobalt-iron boride alloy (CoFeB), separated by an insulating layer such as magnesium oxide (MgO). Each cell is organized as a pillar of the three layers. The pillar is called a nanopillar due to the nanometric dimensions of the structures used. The first ferromagnetic layer is a magnet with a fixed polarity; the second has a polarity that can be changed, thus enabling data storage. This configuration uses the phenomenon of magnetoresistance tunneling to store a bit and protect it from external influences.The information can be read by measuring the electrical resistance of the cell.

[0002] The first MRAMs developed were of the STT-MRAM type, STT standing for spin transfer torque, referring to a phenomenon occurring when a spin-polarized current flows through a magnetic material and acts on the magnetization. In STT-MRAM, the current, for the purpose of writing, flows through the magnetotunnel junction (MTJ) from one ferromagnetic layer to the other, which is commonly summarized by the statement that reading and writing occur along the same path.

[0003] More recently, SOT-MRAM type MRAMs have been developed, SOT standing for spin orbit torque or spin orbit transfer. Writing is performed by injecting a current into a track or line placed in a plane perpendicular to the pillars, which can be made of a heavy metal such as tungsten. It is based on the spin Hall effect. Since the write current in SOT-MRAM passes parallel to the layers, the write current does not generate wear on the MTJ pillar. The amplitude of the write current can therefore be increased to improve the write speed. SOT technology thus makes it possible to consider shorter write times than for STT cells, without compromising the lifespan of the devices.Reading, however, is always done by measuring the electrical resistance of the cell, and we therefore say that there is decoupling of the read and write paths, unlike the operation of STT-MRAM. For a review of SOT-MRAM technology memories, see Krizakova et al., “Spin-orbit torque switching of magnetic tunnel junctions for memory applications,” Journal of Magnetism and Magnetic Materials, 562:169692, 2022, or S. Lee et al., “Emerging Three-Terminal Magnetic Memory Devices,” in Proceedings of the IEEE, 104(10):1831–1843, 2016. For a review addressing reading, which can be done in the same way on an STT-MRAM or an SOT-MRAM, see T. Na et al., “STT-MRAM Sensing: A Review,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 68(1):12–18, 2021.

[0004] The invention described below is presented in particular, but not limited to, SOT-MRAM type MRAMs.

[0005] [Fig. 1] With reference to [Fig. 1], a SOT-MRAM memory cell, responsible for storing a single bit, includes a pillar called a magnetic pillar MTJ comprising a magnetic tunneling junction. The magnetic pillar MTJ is made up of the stacking, along the pillar direction, of laterally delimited blocks formed in layers of materials according to the following succession, from bottom to top in [Fig. 1] - a ferromagnetic layer with fixed magnetization RL made up, from bottom to top on the [Fig.l], - of a synthetic antiferromagnetic SAF sublayer (the [Fig.1] shows opposite magnetizations in equivalent proportion in this layer: the total magnetization is zero) -and a ferromagnetic layer called the reference layer RL0 with fixed magnetization (Fig. 1 shows uniform magnetization in the layer and identical in the left and right views), these two sublayers SAF and RL0 being in contact with each other, the whole being considered as the reference layer itself, hence the notation RL for the whole of SAF and RL0, -an oxide layer forming the tunnel barrier TB in contact with the reference layer RL0, and a few nanometers thick, -a ferromagnetic layer with variable magnetization or free layer FL (the [Fig.l] shows a uniform magnetization in the layer and opposite in the left view compared to the right view), in contact with the oxide layer.

[0006] The oxide layer constitutes a thin material barrier between the two ferromagnetic layers.

[0007] The lateral delimitation (circular or polygonal in shape, for example) of the blocks of materials defines an AMTJ area, transverse to the direction of the magnetic pillar MTJ.

[0008] The variable magnetization layer FL stores binary data (one bit) in the form of a 0 or parallel state (P) offering a low electrical resistance RP, on the left part of [Fig.l], or of an anti-parallel state 1 (AP) offering a high electrical resistance Rap, on the right part of [Fig.l].

[0009] The electrical parameters of the MTJ junction or pillar include the resistance-area product RAMTJ denoted RA and the relative resistance deviation TMR.

[0010] The resistance-area product RA, which is on the order of 5 to 5000 Q.pm2, is controllable by the thickness of the barrier layer TB, and it directly impacts the low resistance value associated with the state P, which is proportional to it according to the relation: Rp — RA / A^j.

[0011] The relative resistance difference TMR is related to the resistance difference between state P and state AP by the relation _ R^Rp. This difference is generally between 0.8 and 2, that is to say between 80 and 200%.

[0012] For a relative resistance difference (TMR) of 100% and a circular MTJ pillar with a diameter of 40 nm, if RA = 5 Q / pm², the resistances in both states are RP = 4 kQ and Rap = 8 kQ. If RA = 20 Q / pm², the resistance values ​​are RP = 16 kQ and Rap = 32 kQ. If RA = 1000 Q / pm², the resistance values ​​are RP = 800 kQ and Rap = 1.6 MQ. A low TMR makes reading operations difficult.

[0013] [Fig.2] In [Fig.2], the MTJ pillar is represented by not distinguishing RL0 and S AF within RL, and by placing RL at the top of [Fig.2], and FL at the bottom of [Fig.2].

[0014] The MTJ pillar is placed on an LSOT track (also called a line, or SOT line) of a heavy metal such as tungsten W, platinum Pt, or tantalum Ta, or of a topological insulator, or mixtures or alloys of these materials. The LSOT track is in contact with the free layer FL, which is therefore placed between the tunnel barrier TB and the LSOT track.

[0015] However, solutions are also known in which the SOT track is placed above the MTJ pillar, and the RL and FL layers are then reversed to keep the FL layer in contact with the SOT track.

[0016] The reversal of the magnetization of the free layer FL occurs through the conversion of a writing current, which is a displacement of electric charges between two terminals BEI and BE2 of the LSOT, into a spin current. The circulation of the writing current through the SOT line produces a spin current (not shown) perpendicular to the writing, propagating in the LSOT line towards the interface between the SOT line and the free layer FL, which results in the reversal of the magnetization of the free layer FL. This is an interaction between the magnetic pillar and the SOT line via spin-orbit coupling. The SOT line is called a spin Hall effect line.

[0017] As mentioned, SOT-MRAM memories have the advantage of decoupling the write path from the read path: during a write operation, the current As already mentioned, writing data only travels through the SOT line, without passing through the MTJ pillar. Therefore, the writing speed can be increased without negatively impacting the memory's long-term endurance.

[0018] On the other hand, during a read operation, the read current flows through the MTJ pillar, between the BEI terminal (and / or BE2) of the LSOT line and a TE terminal of the RL reference layer.

[0019] It is noted that the magnetic pillar MTJ and the runway LSOT form a tripole (BEI, BE2, TE)

[0020] It is also noted that the value of the resistance-area product RA has no impact on the writing operations.

[0021] During a write operation in an SOT cell, the direction of the writing current depends on the data to be written (it was shown in Figure 2 in the direction from BEI to BE2, but it can also be oriented from BE2 to BEI, but then the written data is the opposite data). The amplitude of the writing current also depends on several parameters: the surface area of ​​the MTJ pillar AMTJ, the nature of the material of the LSOT line and its dimensions, the material and dimensions of the free layer FL, and the desired writing speed, among others.

[0022] For a tungsten W LSOT line, a CoFeB free layer, and a circular MTJ pillar with a diameter of 40 nm, the write current is estimated at 260 pA for a 1 ns write, or 200 pA for a 10 ns write. The write currents of an SOT-MRAM memory are on the order of a few hundred pA.

[0023] SOT lines are generally thin, on the order of a few nm, which gives them a high resistivity. For a tungsten W SOT line (with a resistivity Pw = 160 pH.cm), with a thickness of 5 nm and a width of 40 nm: the resistance Rsotw is on the order of 300 Ω for a length of approximately 50 nm and Rsot.w is on the order of 1 kΩ for a length of approximately 120 nm.

[0024] Typically, as a convention, for a write of the value '0', it is considered that the write current, the write, flows from BEI to BE2 and that the MTJ pillar, at the level of its free layer, goes from the anti-parallel state AP to parallel P, and for a write of the value '1', the write current, the write, flows from BE2 to BEI, and the pillar goes from the parallel state P to the anti-parallel state AP.

[0025] Reading the binary information stored in the MTJ pillar can be performed at a constant voltage. A constant read voltage, Viecture, is applied between the BEI and TE terminals of the MTJ pillar. Viecture is limited by the breakdown voltage of the MTJ pillar, on the order of 1 to 2 V, depending in particular on the value of RA. Applying this voltage causes a read current, Iecture, to flow through the MTJ pillar. The read value depends on the magnetization state, P or AP, of the MTJ pillar. The value of the current reading in state P, Reading,o, must be greater than that in state AP, Reading,i- Reading.o and Reading,i are typically at least 10 pA with a difference Reading of at least 5 pA.

[0026] Reading the binary information stored in the MTJ pillar can also be performed at constant current. A constant read current is passed through the MTJ pillar; the read current must not disturb the magnetization state of the MTJ pillar by parasitic writing (Iread < 60 pA). The current flow generates a voltage drop, Vread, between the BEI and TE terminals of the MTJ pillar. The value of Vread depends on the magnetization state, P or AP, of the MTJ pillar. The value of Vread in the P state, Vread, must be less than that in the AP state, Vread. Typically, the voltage difference Vread between Vread and Vread is at least 100 mV.

[0027] It is noted that the writing only circulates in the SOT line, and that the writing operation is independent of the RA value of the MTJ pillar.

[0028] It is also noted that it is necessary to precisely control the value of the writing for writing operations, and that the writing has high values ​​with current materials.

[0029] For a matrix implementation, selector components, typically NMOS transistors, are used. This was discussed, for example, in M. Gupta et al., "High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node," IEEE IEDM, pp. 24.5.1–24.5.4, 2020. Since SOT-MRAM has three terminals (BEI, BE2, and TE), it requires two selector components (e.g., two NMOS transistors) per SOT-MRAM memory cell (bitcell). This configuration is known as 2T1R, for two transistors and one resistor. The resistor is the magnetic pillar and part of the SOT line. The cell is called a 2T1R SOT-MRAM memory cell.

[0030] There are two possible implementations: (i) 1 NMOS transistor connected to BEI (or BE2) and 1 NMOS transistor connected to TE, (ii) or 1 NMOS transistor connected to BEI and 1 NMOS transistor connected to BE2.

[0031] Generally, SOT-MRAM memories are driven with constant voltage sources, as in US2018 / 0061467A1. The voltage sources can be placed outside the memory array. A constant voltage generated by the voltage sources, Vwrite, is applied between two access lines (the sign of Vwrite depends on the data to be written, '0' or '1'), which generates a write current flowing in the SOT line. Due to parasitic routing resistances of the access lines, as well as leakage currents in unselected memory cells, the voltage actually applied across the terminals of a selected memory cell decreases with increasing distance from the drive circuits. This results in a decrease in the write current with increasing distance from the drive circuits: the cell The memory cell furthest from the driver circuits consequently has the lowest write current; the memory cell closest to the driver circuits has the highest write current. The amplitude of the write current can differ depending on whether a '0' or a '1' is written due to the asymmetry of the structures: the write current for '1', i, is generally higher than the write current for '0', o, and it is difficult to control the values ​​of these two currents independently of each other.

[0032] By default, for the same voltage Vwrite applied in write mode '0' or '1' (the polarity of Vwrite depending on the data to be written), the currents lwrite,0 and lwrite,i generally have different values ​​due to the asymmetry of the structures. This is a problem if equal amplitudes of lwrite,0 and lwrite,i are desired. However, in some cases, it may also be desired for lwrite,0 and lwrite,i to have different amplitudes. Two different voltage values ​​could then be used for writing '0' (Vwrite,0) and '1' (Vwrite,i). However, in both cases (equal amplitudes or different amplitudes), it is difficult to precisely and independently control the value of the two currents when driven by voltage, i.e., it is difficult to find appropriate values ​​of Vwrite,0 in write mode '0' and Vwrite,i in write mode '1' to obtain the desired write currents.The solution described below solves this problem and allows easy control of the values ​​of the writing,o ​​and the writing,i- .

[0033] During a write operation, a leakage current, IMTJ, may flow through the MTJ pillar of the selected memory cell because it is difficult to control the voltage across the MTJ pillar. Furthermore, IMTJ increases for low RA values ​​of the MTJ pillar and depends on the magnetization state of the MTJ pillar.

[0034] The problems mentioned above complicate the sizing and use of the memory circuit. For example, it is necessary to have precise knowledge of the values ​​of parasitic routing resistances, leakage currents, and variations in the manufacturing process, and the access transistors must be sized to control the write speed circulating in a selected memory cell. The invention and its advantages

[0035] To resolve the difficulties thus identified, an electronic RAM circuit is proposed comprising a matrix of memory cells, each including at least one magnetic pillar and a spin Hall effect line interacting by spin-orbit coupling and forming a three-pole, each cell further comprising a means for selecting the connection to the terminals of said three-pole, - a terminal of each cell being connected in the circuit for selecting memory cells of the matrix according to a first dimension of the matrix - typically word lines - using the means for selecting the memory cells, -and a pair of terminals of each cell being connected in the circuit to allow a common application, to memory cells of the matrix selected according to a second dimension of the matrix - typically bit lines - of electrical energy for reading or writing magnetic information in the pillar,

[0036] Remarkably, said electrical energy is applied by passing a current controlled by a current-driving circuit.

[0037] Instead of driving the memory matrix by voltage, the memory matrix is ​​driven entirely by current.

[0038] The invention uses a current-driven system comprising at least one current generator capable of circulating a constant current through the bit lines. The invention also uses a biasing circuit comprising a voltage supply that biases the bit lines at voltages suitable for current-driven operation.

[0039] During a write operation, the driver circuit generates a reference write current, Iref,write, which flows through the SOT line of the selected memory cell. During a read operation, the driver circuit generates a constant reference read current, Iref,read, which flows through the MTJ pillar of the selected memory cell.

[0040] The write current flowing through the selected memory cell, the write, is thus constant, regardless of its position in the memory array (the write ~Iref,write). Furthermore, the value of the write current, the write, is more robust against parasitic routing resistances of the access lines and leakage currents through unselected memory cells. The write value depends primarily on the reference write current, Iref,write, and the sizing of the NMOS access transistors of the memory cells.The sizing and use of the memory circuit are simpler when current control is implemented: without having precise knowledge of the parasitic routing resistances, leakage currents, variations induced by the manufacturing process, we nevertheless control the write value by controlling only the value of Iref,write (knowing that Iwrite ~ Iref,write)- The NMOS access transistors are sized beforehand to be large enough to allow the write to flow in the memory cell.

[0041] The values ​​of the '0' and '1' writing currents can be obtained identically, even if the structure is asymmetric. However, if necessary, different current values ​​can also be obtained by choosing different values ​​of Iref,writing for '0' and '1' writing.

[0042] The leakage current through the MTJ pillar, IMTJ, is almost zero. This solution is compatible with low supply voltages (<1V). Optionally and advantageously,

[0043] electrical energy can be applied by current mirror copy branches each associated with a line of cells in the second dimension, a transistor of said current mirrors being shared to form a common reference branch of said current mirrors. - electrical energy can be applied by a common copy branch to several rows of cells according to the second dimension of the matrix, a circuit controller selecting a row of cells to connect selectively to said common copy branch. - the electrical energy for writing can be applied by connecting to the same terminal of the spin Hall effect line a first current source with associated current mirror PMOS for writing the first binary value, and a second current source with associated current mirror NMOS for writing the second binary value. - Electrical energy for writing can be applied by connecting a current source to a first terminal of the spin Hall effect line for writing the first binary value and to a second terminal of the spin Hall effect line for writing the second binary value, a circuit controller biasing the terminal of the Hall effect line opposite to the current source according to the binary value to be written. -Electrical energy for reading can be applied by connecting a current source according to the principles described below in relation to the figures. In particular, electrical energy for reading can be applied by connecting a current source to one end of a magnetic pillar opposite the spin Hall effect line, the spin Hall effect line being polarized for the reading operation. -Electrical energy for reading can be applied in the magnetic pile in a first direction or an opposite direction depending on a value written during a simultaneous writing operation. - the current control circuit can also circulate an assist current through the magnetic pillar to facilitate or oppose writing, for example by STT or VCMA (voltage-controlled magnetic anisotropy) effects. -The magnetic RAM electronic circuit may include a biasing circuit placed relative to the matrix in opposition to the current driving circuit. -the selection means may include two field-effect transistors each connected by a source or a drain to a respective terminal of the assembly formed by the magnetic pillar and the spin Hall effect line. -the cells can be SWL1 or SWL2 cells. -Memory cells can be single-pillar, double-pillar, or triple-pillar cells

[0044] The multi-pillar structures used for the invention may have many magnetic pillars arranged on an SOT line and include an additional selection element each time a pillar is added, typically an NMOS transistor on top of each added magnetic pillar.

[0045] Multi-pillar structures to which the invention applies may include only a few magnetic pillars, and in particular 4 pillars, to have a 2-bit equivalent or another number of magnetic pillars less than 20, or possibly greater.

[0046] The invention, described with the SWL1 cell, is transferable to the SWL2 structure and also to the SOT-5T structure, all of whose terminals are independent. The main embodiments are compatible with the SOT-SBL structure.

[0047] List of figures

[0048] Fig. 1, already commented on, represents the structure of a magnetic pile used in the invention, in the two magnetization states.

[0049] Fig. 2, already discussed, presents the principle of SOT memories.

[0050] Figure [Fig. 3] shows an SOT-5T MRAM cell.

[0051] Fig. 4 shows a cell called SOT-SWL1 (4T).

[0052] Figure 5 presents a memory circuit according to one embodiment of the invention.

[0053] Figure 6 presents the memory matrix according to the embodiment.

[0054] Fig. 7A presents the control circuit according to the embodiment.

[0055] Figures 7B and 7C show examples of implementation of the circuit of [Fig.7A],

[0056] Figure 8A presents a detail of the implementation, in one embodiment.

[0057] Figure 8B explains the operation.

[0058] Figures 9 and 10 show other SOT MRAM cells to which the invention applies.

[0059] Fig. 11, compared to Fig. 8A, presents another embodiment of the invention, with addressing of only one memory line at a time.

[0060] Fig. 12 presents another embodiment, with remote location of one of the two current sources, using PMOS current mirrors for current injection.

[0061] Fig. 13 presents another embodiment, with remote location of one of the two current sources, using NMOS current mirrors for current absorption.

[0062] Fig. 14 presents another embodiment, with simultaneous reading and writing.

[0063] Figures 15 to 18 present the principles of STT current writing assistance.

[0064] Figures 19 to 24 present an embodiment with writing assistance by STT current.

[0065] Figures 25 and 26 present the principles of VCMA voltage writing assistance.

[0066] Figures 27 to 32 present an embodiment with writing assistance by VCMA voltage. Description of examples related to the figures

[0067] [Fig.3]. With reference to [Fig.3], we are discussing the configuration in which the cell includes an NMOS transistor connected to BEI, here this transistor is denoted NI, and an NMOS transistor connected to TE, here this transistor is denoted N2. The memory cell 10 can have up to five independent terminals - and these terminals are denoted -RWL, WWL (terminals of the gates of the two NMOS transistors, WL meaning wordline and R and W meaning read and write), these terminals are connected either to ground (0V) or to the supply voltage VDD> and these terminals are connected, - for the first RWL to a conductor common to all the cells of a given column of index k in the matrix, denoted RWL(k) dedicated to the selection for the purpose of reading the cells of column k, -and for the second WWL to a common driver for all cells in column k of the matrix, denoted WWL(k) and dedicated to selection for the purpose of writing cells in column k -and BL, BLB, and RBL (the three other terminals, BL and BLB being on the LSOT line, and RBL being at the TE terminal, two of these three connections being made via one of the NMOS transistors, BL also meaning bitline or bit line, BLB meaning bitline bar and especially opposite potential, the BLB terminal being intended for writing, and R in RBL meaning read), these terminals are connected, - for the first BL with a conductor common to all cells of a given row of index i in the matrix, denoted BL(i) and dedicated to writing and reading the cells of row i, -and for the second BLB, a conductor common to all cells of row i in the matrix, denoted BLB(i) and dedicated to writing and reading cells of row i, -for the third RBL to a conductor common to all the cells of the row of index i in the matrix, noted RBL(i) and dedicated to reading, and possibly writing, the cells of row i.

[0068] [Fig.4] It is possible to share certain terminals to facilitate the routing of access lines and reduce the area of ​​the memory cell, and this is represented in [Fig.4],

[0069] If the WWL and RWL terminals are shared, and one of the two NMOS transistors is connected to the TE terminal, the cell is called the SOT-SWL1 cell (SOT shared wordline 1 – referring to the concept of a shared wordline). This is the one shown in [Fig. 4]. In this case, there are 4 terminals, labeled WL (which includes WWL and RWL), BL, BLB, and RBL.

[0070] If there is sharing of the BL and RBL terminals, the cell is called SOT-SBL (SOT shared bitline) and has 4 terminals noted WWL, RWL, BL (which includes RBL), and BLB.

[0071] If the two NMOS transistors are at terminals BEI and BE2, the cell is called the SOT-SWL2 cell (SWL again meaning shared wordline). There are 4 terminals, denoted WL (which again includes WWL and RWL), BL, BLB, and RBL.

[0072] If the terminals are not shared (this is what is represented in [Fig.3]), the cell is called SOT-5T (SOT 5 terminal).

[0073] A 2048-cell memory line SWL1 (with shared BL, BLB, and RBL) was simulated online, with a circuit supply voltage VDD = 0.9 V, channel lengths of the two transistors NI and N2 LNi = LN2 = 20 nm, channel widths of the two transistors NI and N2 WN[ = 1 pm, WN2 = 80 nm, a resistance-area product RA = 20 Q.pm2, and a line resistance LSOT Rsot ~ 300 Q. The drive is voltage-controlled. The topology is BL, BLB, RBL perpendicular to WL. The results obtained on a 2048-cell memory line are applicable to a 4 Mbit matrix with 2048 rows and 2048 columns.

[0074] The write current of the furthest memory cell (No. 2048) is approximately 2 times lower than that of the nearest memory cell (No. 1) due to the parasitic resistances of the access lines BL and BLB for a parasitic resistance value RBL,par = RBLB,par = 0.3 Q / cell and the leakage currents taken into account in the simulation. The write current '0' is approximately 1.5 times lower than that of write '1'.

[0075] Furthermore, for a pillar resistance-area product RA = 20 Q.pm2 and a relative resistance difference TMR = 100% (RP = 16 kQ and Rap = 32 kQ), the leakage currents in the MTJ pillar, IMTJ, can reach approximately 7 pA, and up to 17 pA for RA = 5 Q.pm2. The higher the value of the parasitic resistances, the higher the leakage currents in the MTJ pillar.

[0076] Thus, due to voltage control, because of the non-uniformity of the write current between the nearest and furthest memory cells, and between writes '0' and '1', it is often chosen to size the memory circuit according to the The "worst-case" scenario involves ensuring that the write current '0' of the furthest memory cell is sufficiently high. However, this implies oversizing the other memory cells, meaning their write current is too high, up to four times higher. This results in unnecessary energy consumption and risks of degradation of the SOT lines, which are typically very thin, on the order of 3 to 5 nm. Furthermore, memory circuit design is complex because the write current amplitude depends on several parameters, such as the values ​​of the routing parasitic resistances, the size of the memory array, the selection and sizing of the memory cell selection elements, and variations related to the manufacturing process. The design becomes even more complicated when the write currents involved exceed 200 pA.Finally, it is difficult to limit leakage currents through the MTJ pillar during a write operation: this degrades the endurance of the memory array.

[0077] [Fig. 5] For a 100-word SOT-MRAM type memory matrix of n bits, such as that shown in [Fig. 5], the current-drive circuit is composed - of an addressing device 110 which includes a current source 111 generating the currents Iref, write and Iref, read, and which connects the current source 111 to the selected memory lines (i.e. the bit lines RBL, BL, and BLB selected between bit 1 and bit n), - a biasing circuit 120 which includes a voltage supply 121 and biases the bit lines from 1 to n at appropriate voltages, - and finally a 130 word line addressing circuit that selects a memory column between word 1 and word m.

[0078] The current Iref,write can flow from BL to BLB, or from BLB to BL depending on whether the data to be written is '0' or '1', respectively.

[0079] The current Iref,iecture can flow from RBL to BLB, or from RLB to BL, or from BLB to RBL or from BL to RBL.

[0080] [Fig. 6] In [Fig. 6], a 100-cell memory matrix of 10 cells is shown. The embodiment presented uses the 2T1R SWL1 memory cell, which, as previously explained, has 4 independent terminals (RWL and WWL are shared and denoted WL). The invention is applicable, in its principal embodiments, to other memory cell structures (e.g., SOT-5T, SOT-SBL, and SOT-SWL2). The memory matrix is ​​addressed by the terminals RBL, BL, and BLB in the same direction, and by the terminal WL in the direction perpendicular to the former.

[0081] [Fig.7A] In [Fig.7A], the implementation of the control circuit follows the following principles, for the memory matrix 100 of type SOT-MRAM of m words of each n bits.

[0082] The writing of the data '0' is done by injecting the current Iref.émllire.o, generated by a current source 111-0 into the selected BL line (of index i from bit 1 to bit n), and this current flows from the selected BL line to the selected BLB line (of the same index i) through the selected memory cell.

[0083] The writing of the data '1' is done by extracting the current Iref,writing,i generated by a current source 111-1, from the selected BL line (of index i from bit 1 to bit n), the current flowing from the selected BLB line to the selected BL line (of the same index i) through the selected memory cell.

[0084] The figure shows that the current sources 111-0 and 111-1 have a common terminal, and their other terminals are respectively connected to the supply voltage VDD and to ground GND. This is, however, a simplified view since the circuit may be configured differently.

[0085] Constant current reading is performed by injecting a reading current Iref, generated by a current source 111-9, into the selected RBL line (index i from bit 1 to bit n), the current flowing through the MT J pillar of the selected memory cell. The data is read by measuring the potential of the selected RBL line at the input or output of the line.

[0086] The current source 111-9 has one terminal at the supply potential VDD. The selection or addressing of a cell with indices i between 1 and n and k between 1 and m is done - by switching a SW switching element of index i of the addressing device 110 and the biasing circuit 120 from ON for a selected memory line to OFF for an unselected line and vice versa - this switching element connects the BL terminal of index i to the current sources 111-0 and 111-1 and the BLB terminal of index i to the VBlb potential created by a voltage source 121-0, and the RBL terminal of index i to the current source 111-9, - and the application by the addressing circuit 130 to the WL terminal of index k of a potential VWl=VDd, the supply potential for a selected memory column of index k. If the column is not selected, the potential of the WL terminal VWL is less than or equal to 0 V.

[0087] In this embodiment, the voltage source 121-0 is the sole or main voltage source of the voltage supply 121 of the biasing circuit 120 defined in relation to [Fig. 5]. It provides a defined potential VBlb with respect to ground GND.

[0088] These principles can be transposed to the SOT-SBL structure, taking into account the following comments:

[0089] The selection or addressing of a cell with indices i between 1 and n and k between 1 and m is done - by switching a SW switching element with index i of the addressing device 110 and the biasing circuit 120 from ON for a selected memory line to OFF for an unselected line and vice versa - this switching element connects the BL terminal with index i to the current sources 111-0 and 111-1 and the BLB terminal with index i to the potential VBlb created by a voltage source 121-0, and the RBL terminal with index i to the current source 111-9, - and the application by the addressing circuit 130 to the WL terminal with index k of a potential VWl=VDd the supply potential for a selected memory column with index k. If the column is not selected, the potential of the WL VWL terminal is less than or equal to 0 V.

[0090] [Fig.7B] If only reading is intended, the BL terminal (or possibly the BLB terminal) may not be used and, for example, left floating (BL is therefore not shown on [Fig.7B]), and as shown in [Fig.7B], there is a terminal (WL(k)) of each cell connected in the circuit for selecting cells of the matrix according to a first dimension of the matrix using the transistor, or transistors, of the cell serving as connection selection means, and a pair of terminals (BLB(i), RBL(i)) of each cell connected in the circuit to allow a common application, to cells of the matrix selected according to a second dimension of the matrix, of electrical energy for reading binary information in the cell.

[0091] [Fig.7C] If only writing is intended, the RBL terminal may not be used, and as shown in [Fig.7C], there is a terminal (WL(k)) of each cell connected in the circuit for selecting matrix cells according to a first dimension of the matrix using the transistor, or transistors, of the cell serving as connection selection means, and a pair of terminals (BL(i), BLB(i)) of each cell connected in the circuit to allow a common application, to matrix cells selected according to a second dimension of the matrix, of electrical energy for writing binary information into the cell.

[0092] [Fig.8A] The current control circuit can be implemented as follows, represented, for non-exhaustive purposes, in [Fig. 8A]. The following is implemented for writing: -PMOS current mirrors based on a single PMOS transistor P0E0 and n transistors PlEo,i to PlEo,n all mirrored with P0E0 to inject current (Writing the value '0') into the BL line, - and NMOS current mirrors based on a single NMOS transistor N0Ei and n transistors N1Ei,i to N1Ei>n all mirrored with N0Ei to draw current (Writing the value '1') from the BL line. For all i between 1 and n the free terminals of the transistors PlE0,i and NlEi,i (the copy branches) are connected together and connected, by the SW switch; to the BL(i) terminal of the cell with index i.

[0093] The current source 111-0 is placed between the supply potential VDd and the ground potential (GND), the PMOS transistor POEO being interposed by its source and its drain between the supply VDd and the current source 111-0. When the current source 111-0 is activated, the BLB(i) line is brought to the potential 0V (GND), which allows current to flow from BL(i) to BLB(i).

[0094] The current source 111-1 is placed between the supply potential VDD and the ground potential (GND), with the NMOS transistor N0Ei interposed by its drain and source between the current source 111-1 and ground. When the current source 111-1 is activated, the BLB(i) line is brought to the potential VDD, which allows current to flow from BLB(i) to BL(i).

[0095] For reading: - PMOS current mirrors based on a single PMOS transistor P0L and n transistors PlL,i to PlL,n all mirrored with P0L to inject current into the RBL line (read).

[0096] For any i between 1 and n the free terminal of the transistor P1L,; (the copy branch) is connected by the switch SW; to the terminal RBL(i) of the cell of index i.

[0097] The current source 111-9 is placed between the supply potential VDd and the ground potential (GND), the PMOS transistor P0L being interposed by its source and its drain between the supply VDd and the current source 111-9. When the current source 111-9 is activated, the BLB(i) line is brought to 0V potential, which allows current to flow from RBL(i) to BLB(i).

[0098] The operation of the control circuit is then based on the fact that a memory cell is selected when it is at the intersection between a selected memory row and a selected memory column.

[0099] A memory column is selected if the voltage of the corresponding WL terminal, VWL,t for a k column, is greater than the threshold voltage of the NMOS transistors NI, for writing, and / or N2, for reading, of the 2T1R memory cells: typically, but it is also possible to use different v WL, s ëtectsBHa&e ~VnDt tensions.

[0100] A memory column is unselected if the corresponding WL voltage, VWl, for a column k, is less than the threshold voltage of the NMOS transistors N1 and N2 of the 2T1R memory cells: typically, v., . . _n.v, but it is possible Using different voltages, such as negative voltages for unselected columns, is advantageous for limiting leakage currents. Other voltages, this time positive but not too high, can be used for the unselected columns.

[0101] A memory line at index i is unselected if the SW; switch is OFF -it is assigned the value 0 if Iref.émlure.o >0A and VBlb = 0 V or possibly a negative voltage - it is written with the value 1 if Iref.écrnure.i >0A and VBlb = VDD - it is read if Iref,taure >0A and VBLb = 0 V or possibly a negative voltage.

[0102] The write current in a selected memory cell is characterized by the following observations, based on simulations with lœf.écriture^OOiLiA, RA=20 U.pm2, RSOt “ 300 Q: during a write operation '0' or '1', the write current, I write, flowing in the selected memory cell is constant and independent of its position (-Ld.émunJ- the write only flows in the SOT line and the MTJ leakage currents are negligible (<0.5 pA). the write is not affected by parasitic routing resistances (as long as they are less than, at least, 0.5 Q / cell - this parasitic routing resistance value of 0.5 Q / cell corresponds to the parasitic resistance on the BL and BLB lines - assumed to be equal in the simulations. The parasitic routing resistance of the RBL line has no impact, given that the write current flows only through BL and BLB.It is fixed at 3.5 Q / cell in all simulations, which corresponds to a worst-case scenario with a minimum-width RBL routing line and leakage currents in unselected memory cells. There is no MTJ pillar degradation (VMtj~0V). There is no asymmetry between write '0' and write '1'. However, it is also possible to circulate write '0' and '1' currents of different amplitudes in the selected memory cell, using different values ​​of Iref,write,0 and keLemiure.i.

[0103] The read voltage during a read operation is also characterized by the following observations, based on simulations with identical parameters and Iref,reading = 10gA: during a constant current read operation, the current-drive circuit injects a small, constant read current, Iref,reading, through the memory cell to be read. The selected RBL line charges to a voltage Viecture,o / i that depends on the data being read ('0' or '1', respectively). For Iref,reading = 10 pA, Viecture,o ~ 175 mV if the data being read is '0', and Viecture,i ~ 325 mV if the data being read is '1'. The read is therefore functional since the difference AViecture is approximately 150 mV, which is sufficient to distinguish the data. Viecture,o / i is constant regardless of the position of the memory cell being read. The value of Viecture,o / i is very insensitive to parasitic routing resistances RRBL,Par>3.5 Q / cell because Iref,lecture is low, and there is no degradation of the MTJ pillar because VMtj<0.4 V, nor any parasitic writing by STT since IMTj~Iref,reading - The parasitic resistance of the RBL access line is always fixed at 3.5 Q / cell in this simulation and has little impact on the read operation because the read current is low. The parasitic resistances of the BL and BLB lines also have little impact on the read (they can go up to more than 1 Q / cell without impacting the read voltages).

[0104] It should be noted at this point that the invention also applies to other SOT-MRAM memory cell structures involving at least two selector components per memory cell, connected to two different terminals. The invention applies to the SOT-SBL structure because current does not flow simultaneously in the SOT line and the MTJ pillar: writing and reading are separated. The current source of RBL is connected to BL.

[0105] [Fig.8B] Thus, for a writing of the data '0', it is represented in [Fig.8B], the injection of a current Iref, writing from BL to BLB with biasing of the terminal BLB at 0V.

[0106] This is done by selecting one memory cell on the memory row (memory cell k, the WL terminal receives a potential equal to the supply voltage VWL=VDD) and deselected the other memory cells (VWL=0V, the WL terminal receives the potential from ground). The write operation then flows primarily through the selected memory cell, taking into account leakage currents.

[0107] The potentials at terminals BL and BLB of the selected memory cell, VBl, and VBlb, are adjusted to ensure the flow of the Iref,write current through the selected memory cell. Memory line(s) i selected Memory lines not selected Write '0' Write '1' Read Write / Read SW, ON OFF Iref, write, 0 Iref,write>0 A 0A 0A / T _ . ^ret, write. 1 0A Iref,write>0 A. 0A / Iref,read 0A 0A Iref,read>0 A / Vblb 0 V Vdd ov /

[0108] To deselect a memory line at index i, switch SW; to OFF (open). To select a memory line at index i, switch SW; to ON (closed).

[0109] For writing the data '0', the current source 111-0 is activated with a non-zero positive current Iref,write.o >0A, and the current sources 111-1 and 111-9 are cut off: Iref,write,! = Iref,read = 0A. The potential Vrir of the BLB terminal is connected to ground (0V).

[0110] To disable the write current mirror '1' (corresponding to the case Iref,write, i = 0 A), a switch is used on the connection between the current source 111-1 and the gate of transistor N0,Ei-. When the write current mirror '1' is used, this switch allows the connection between the current source and the gate of the transistor (as in [Fig. 8A]). When the write current mirror '1' is disabled (i.e., bef,write,i = 0 A), the switch disconnects the current source 111-1 and the gate of transistor N0,Ei, and connects this gate to GND.

[0111] For PMOS type current mirrors, a similar principle is applied, the deactivation being done by connecting the gates to the VDD supply, to block the PMOS transistors.

[0112] For writing the data '1', the current source 111-1 is activated with a non-zero positive current Iref,ccriturc.i >0A, and the current sources 111-0 and 111-9 are cut off: Iref,écriture,o = Iref,lecture = 0A. The VBLB potential of the BLB terminal is connected to the supply (VDD).

[0113] The currents supplied by the sources 111-0 and 111-1 for writing the data '0' and the data '1' can be substantially of the same intensity, or substantially different in intensity.

[0114] For reading the data, the current source 111-9 is activated with a non-zero positive current Irefjecture >0A, and the current sources 111-0 and 111-1 are cut off: Iref, write, 0 = Iref.write,! = 0A. The VBLB potential of the BLB terminal is connected to ground (0V).

[0115] The selected memory cells are identified as the intersections between the selected memory rows (there may be one or more simultaneously) and the selected memory columns (there is only one, in the embodiment shown in figures 6 and 8B, but possibly with certain adjustments there may be several simultaneously).

[0116] The selected memory columns are defined by the fact that the potential of the corresponding WL terminal, VWL> (for a column k) is greater than the threshold voltage of the NMOS transistors NI (for writing) and / or N2 (for reading) of the 2T1R memory cells: typically, V wL,nonséiecüonnée = V DD (but it is possible to use different potentials).

[0117] Unselected memory columns are identified by the fact that the potential of the corresponding WL terminal, VWL> (for a column k), is less than the threshold potential of the NMOS transistors NI and N2 of the 2T1R memory cells. Typically, V wL,nonselectnée =0 V (it is possible to use different voltages, for example negative).

[0118] [Fig.9] It is also planned to use the SOT-SBL (4T) cell shown in [Fig.9]. In an embodiment with writing and reading implemented separately, and not simultaneously, the invention is applicable to the SOT-SBL structure. The read current source 111-9 is connected to the same common terminal as the write current sources 111-0 and 111-1.

[0119] [Fig. 10] It is also planned to use the SOT-SWL2 (4T) cell shown in [Fig. 10]. Similarly, the SOT-5T cell of [Fig. 3] is compatible with the invention.

[0120] It is also planned, in variants, to use other matrix organizations, with at least two cross lines two by two.

[0121] In one embodiment, it is envisaged that body-bias (application of a non-zero potential to a box of the circuit) and / or different WL word line voltages will be used for addressing the memory columns.

[0122] In one embodiment, it is also provided that the positions of the current control circuit and the biasing circuit are reversed, the two circuits being in opposition with respect to the memory matrix, at the two ends of the bit lines BL, RBL and BLB.

[0123] In one embodiment, it is also envisaged to maintain a voltage source on the RBL line. In this embodiment, the writing is similar. However, for reading, a constant voltage reading is performed (i.e., the reading current flowing through the MT pillar J varies according to the data read).

[0124] [Fig. 11] Variants relating to the current control circuit are also planned.

[0125] In the [Fig. 11] configuration, an alternative to that of [Fig. 8A], only one memory line is addressed at a time (and not potentially several at the same time), which offers the possibility of using a single copy branch per Current mirroring for the entire matrix (instead of a copy branch per memory line) simplifies the driver circuit. The selection of a single line to be addressed is controlled by the controller 115 of the addressing device 110 (see [Fig. 5]). If multiple lines need to be addressed, the controller 115 chooses to process them sequentially (whereas with the circuit in [Fig. 8A] this could be done simultaneously).

[0126] Thus, there is a single current mirror copying branch connected to n switches (BL(1), ..., BL(n); RBL(1), ..., RBL(n)), which offers a simplification of the circuit compared to the circuit in [Fig.8A]: we go from n current mirror copying branches to a single branch.

[0127] There is therefore the implementation of - a PMOS current mirror based on a single PMOS transistor P0E0 and a single P1EO transistor mirrored with P0E0 to inject current (Writing the value '0'), - and an NMOS current mirror based on a single NMOS transistor N0E[ and a single N1Ei transistor mirrored with N0Ei to draw current (Writing the value '1').

[0128] The free terminals of transistors P1EO and N1Ei (the copy branches) are connected together, and for any i between 1 and n are connected, by the SW switch; to the BL(i) terminal of the selected cell of the row of index i.

[0129] PMOS current mirrors are implemented, based on a single PMOS transistor P0L and a single transistor P1L mirrored with P0L to inject current (read). For any i between 1 and n, the free terminal of transistor P1L (the copy branch) is connected via the SW switch to the RBL(i) terminal of the selected cell on the row with index i.

[0130] The current sources 111-0, 111-1 and 111-9 are placed in the same way as in the embodiment of [Fig.8A].

[0131] To conclude these comments related to [Fig.1 1], it is specified that the assembly of this figure is compatible with the SOT-SBL structure, but in this case the current mirror with 111-9 is connected to the BL terminal instead of the RBL terminal.

[0132] [Fig.12] In [Fig.12], a variant is shown in which one is disconnected On the other hand, the two current sources connected to the BL terminals in the embodiment of [Fig. 6], namely source 111-0 and source 111-1, are connected. Furthermore, the two poles of current source 111-1 are reversed. Finally, this source is connected to the BLB terminals.

[0133] This involves adding, alongside the 121-0 voltage source, a 121-1 voltage source providing a VBL potential on the BL terminals at the end of the matrix for biasing. This VBL potential is applied via an optional SWBL global switch. and the specific switches SW; with i from 1 to n simultaneously controlling the application of the potential VBlb to the line BLB(i) and the potential VBl to the line BL(i), as well as the application of the current source 111-0 to the terminal BL(i), the current source 111-1 to the terminal BLB(i), and the current source 111-9 to the terminal RBL(i). The potentials VBL and VBLB are applied under the control of a controller 116 of the addressing circuit 110.

[0134] This setup allows the use of only one type of current mirror, in this case PMOS mirrors in the setup of [Fig. 12]. The same reference branch is used for all current mirrors in the entire array. The copy branches are sized according to the target values ​​of Iref,writing,0, Iref,writing,i, pf T J-ref, reading*

[0135] In this embodiment, the voltage sources 121-0 and 121-1 are the voltage sources of the voltage supply 121 of the biasing circuit 120 mentioned in relation to [Fig. 5]. They provide the potentials VBLB and VBL defined with respect to ground GND.

[0136] To conclude these comments related to [Fig.12], it is specified that the assembly of this figure is compatible with the SOT-SBL structure, but in this case the current source 111-9 is connected to the BL terminal instead of the RBL terminal.

[0137] [Fig. 13] In [Fig. 13], a variant is shown in which the two poles of the current source 111-0 are reversed, as well as the two poles of the current source 111-1 and also the two poles of the current source 111-9, compared to the embodiment of [Fig. 12].

[0138] This assembly allows the use of only one type of current mirror, but of the NMOS type.

[0139] To conclude these comments related to [Fig. 13], it is specified that the assembly of this figure is compatible with the SOT-SBL structure, but in this case the current source 111-9 is connected to the BL terminal instead of the RBL terminal.

[0140] The variants presented below are applicable to SOT-5T, SOT-SWL1 and SOT-SWL2 cells.

[0141] [Fig.14] In [Fig.14], a variant is shown, in which, starting from the embodiment of [Fig.7A], a second current source is added to the RBL terminal.

[0142] The current source 111-8 placed, for the purposes of the figure, between ground and the pole opposite to the supply of the current source 111-9, draws a current from the terminal RBL(i), when the switch SW; is closed.

[0143] This makes it possible to perform a read and write operation simultaneously on a selected memory cell, which is useful for performing "write-verify" in a single clock cycle, that is to say, check that the memory cell has switched with the write operation, otherwise the writing of the data is attempted again, or check in real time the switching moment, or for certain applications of calculations in memory (operations called "in-memory computing").

[0144] During a '0' write operation, current source 111-0 is activated to perform the conventional write operation, and current source 111-9 is also activated (as for a conventional read operation). Terminal BLB(i) is biased at the end of the line to 0V. The write current generated by current source 111-0 flows only in the SOT LSOT line of the selected memory cell (from Bl(i) to BLB(i)), and the read current generated by current source 111-9 flows only in the MT J pillar of the selected memory cell (from RBL(i) to BLB(i)).

[0145] At the output of the LSOT line (terminal BLB(i)), the two currents (write '0' and read) are added together. However, since the read current is low compared to the write current (e.g., 30 times lower in the simulations for Iref,write,0 = 300pA and read = 10 pA), this has no impact on the write operation (i.e., a '0' write is performed as described previously).

[0146] Simultaneously, the reading current flow in the MTJ pillar biases the RBL(i) line to a reading voltage that depends on the magnetization state of the MTJ pillar (similar to a conventional reading).

[0147] During a '1' write operation, the principle is identical to that of a '0' write operation: current source 111-1 is activated to draw current from the BL(i) line (as in a conventional '1' write operation), and current source 111-8 (which draws current from RBL(i)) is activated simultaneously instead of current source 111-9 (which injects current into RBL(i)). Since the BLB(i) line is biased at VDD at the end of the line during a '1' write operation, it is preferable to use current source 111-8 rather than current source 111-9 because of the voltage levels: for reading purposes, it is simpler to draw current from BLB(i) to RBL(i) than to inject it due to the VDD bias at the end of the BLB(i) line.

[0148] The variants in figures 12 and 13 also allow writing and reading to be carried out simultaneously.

[0149] For example, in the circuit of [Fig. 12], identically to that implemented in the circuit of [Fig. 14], for a write '0', the write current source 111-0 is activated, and simultaneously the read current source 111-9 is activated. Similarly, for a write '1', the write current source 111-1 is activated, and simultaneously the read current source 111-9. In the case of [Fig. 12], the line is always biased to GND (if in write '0' mode, BLB(i) is biased to 0V at the end of the line; if in write '1' mode, BL(i) is biased to the end of the line). line to OV). Unlike the case of [Fig. 14], since the voltage level at the end of the line is always OV, there is no longer a need to add a second current source to RBL: in both writing cases, current is always injected into RBL. For the comparator of the reading circuit, it may be necessary to have two different reference voltage levels for writing '0' and writing '1' (and this is also true for the embodiment of [Fig. 14]).

[0150] For the circuit in [Fig. 13], the same operating principle is implemented as for [Fig. 12] (however, the line is biased at VDD instead of GND), and the same comments apply. Only sources that draw current from the lines are used.

[0151] Furthermore, as will be explained below, by implementing two current sources per access line (BL, BLB, and RBL), it is possible to assist write operations with spin-transfer torque (STT) current (for MT J pillars with low RA values, i.e., low resistance values). This also allows simultaneous writing and reading. The implementation of two current sources per access line primarily enables writing with STT current. Moreover, this implementation also offers the possibility of performing simultaneous writing and reading, possibly using multiple reference voltages.

[0152] [Fig. 15] Figures 15 and 16 explain the operating principle of writing with the assistance of an STT current. This subject is addressed in the article E. Grimaldi et al., “Single-shot dynamics of spin-orbit torque and spin transfer torque switching in three-terminal magnetic tunnel junctions”, in Nature Nanotechnology, 15(2):111-117, 2020, and also in EP3671749A1.

[0153] For the data '0' write operation, in addition to the classic write current flowing through the SOT line, Iwrite,soT.o, an STT write current, Iwrite,sTT,o, also flows through the MTJ pillar, on the [Fig. 15] from terminal TE to the SOT line, during a '0' write operation. This is shown in [Fig. 15].

[0154] [Fig. 16] And for the data '1' write operation, in addition to the classic write current flowing through the SOT line, Ieaiture,soT,i, an STT write current Iécriture,STT,i also flows through the MTJ pillar, on the figure from the SOT line to the TE terminal, during a '1' write operation. This is represented in [Fig.16].

[0155] Writing by STT is bipolar, the direction of flow of the STT current depends in fact on the data to be written.

[0156] [Fig. 17] The STT current facilitates the writing of '0' by flowing in one direction (for example from top to bottom of the MTJ pillar as in [Fig. 15] and in the left part of [Fig.17]).

[0157] [Fig. 18] The STT current facilitates the writing of '1' by flowing in the opposite direction (for example from the bottom to the top of the MTJ pillar, as in [Fig. 16] and in the right part of [Fig.18]).

[0158] But it is also possible to use the STT current to oppose writing, the STT current flowing in the opposite direction to facilitation depending on the data to be written, for example to select a pillar in a multi-pillar structure.

[0159] The STT current opposes the writing '0' by circulating in the opposite direction, namely from the bottom to the top of the MTJ pillar in the right part of [Fig. 17].

[0160] The STT current opposes the writing '1' by circulating in the opposite direction, namely from top to bottom of the MTJ pillar in the left part of [Fig.18].

[0161] Writing with STT assistance requires that the value of the resistance-area product RA of the MTJ pillar be low, typically less than 20 ^.pm2.

[0162] The STT writing current, IécntureSTTO / 1' Allows the writing current by SOT, Iécriture,SOT.0 / l' required to be reduced when there is facilitation, or, conversely, to increase the writing current by SOT required when there is opposition.

[0163] To implement this functionality, it is necessary to control the flow directions of the SOT and STT write currents independently.

[0164] Some SOT-MRAM memory circuits using STT current-assisted writing are driven with constant voltage sources to generate the SOT write current, Lwrite.soT, and the STT write current, Iwrite,sTT:

[0165] The SOT and STT write currents are often non-uniform within the memory matrix, with a decrease in currents as one moves away from the driver circuits, and an asymmetry between the '0' and '1' write.

[0166] Moreover, it is difficult to control precisely and independently the circulation paths of the SOT and STT writing currents: in order to be able to facilitate or oppose writing independently of the data to be written ('0' or '1'), the writing,siT must be able to circulate through the MTJ pillar in both directions (from top to bottom, or from bottom to top) independently of the direction of circulation of hmune.soï (in the SOT line, from BL to BLB or BLB to BL).

[0167] The presented embodiment therefore provides that instead of driving the memory matrix by voltage, the memory matrix is ​​driven entirely by current:

[0168] The driver circuit generates a reference SOT write current, Iref,write,sot, which flows through the SOT line of the selected memory cell

[0169] The driver circuit generates a reference STT write current, Iref,write,stt, which flows through the MTJ pillar of the selected memory cell.

[0170] The currents Iref,écriture,sot and Iref,écriture,stt are controlled independently of each other.

[0171] The driver circuit used to generate the STT write current also allows read operations to be performed.

[0172] The proposed solution resolves the problems encountered:

[0173] The write currents SOT and STT flowing through the selected memory cell, Umure.soT and Lmune.sïï- respectively, are constant regardless of the position of the selected memory cell and the data to be written ('0' or '1') (Lécriture.soT « Iref,écriture,SOT and Lécriture,sTT^bef,écriture,stt)* These two currents are not dependent on the position and the data to be written, but depend only on Iref,écriture,sot and Lef,écriture,stt, respectively

[0174] The circulation paths of Iécriture,sot and Iécriture,stt are bidirectional and independent of each other.

[0175] The proposed solution is to implement within the current source 111 (see [Fig.5]) STT current sources in addition to the SOT current sources already mentioned.

[0176] The current control circuit then includes a current source that generates Iref,write,SOT, Iref,write,stt, and Iref,read, the component of the current source generating Lef,read also generating Lef,write,STT*

[0177] Iref,reading and Iref,writing,stt are generally of about the same amplitude (Iref,reading -10-20 pA and Lef,write,stt ~20-30 pA in our case). In particular, Lef,write,stt alone cannot write data to the MTJ pillar (writing is done by the joint action of Lef,write,sot and Lef,write,stt)* Thus, it is possible to use the structure of [Fig. 19] (discussed below) to do the writing but also at another time the reading (i.e. for reading, one can use one of the two current sources Lef,write,stt,p or Lef,write,stt,n at choice, by deactivating all the write current sources SOT, and a classic read is performed without risk of parasitic writing).

[0178] If Lef,writing,stt and Lef,reading have significantly different amplitudes, we predict an additional current source on RBL that is specific to playback (a current source that either injects or pulls current from RBL, either one at will).

[0179] To perform simultaneous reading and writing, the same operating principle is used as before, recognizing that the read current and the write current STT are the same current in the embodiment of [Fig. 19] (discussed below). The read circuit requires several reference voltages depending on the activated current source RBL.

[0180] The current control circuit also includes an addressing device which connects the current source to the selected memory lines (i.e., selected RBL, BL, and BLB).

[0181] A biasing circuit is still used, biasing the bit lines at appropriate voltages, as before, as well as a word line addressing circuit that selects a memory column.

[0182] The architecture is the same as that shown in figures 5 and 6.

[0183] [Fig.19] In [Fig.19], the implementation of the STT assisted control circuit meets the following principles, for the 100 memory matrix of type SOT-MRAM of m words of each n bits.

[0184] It is based on an addressing device 110, comprising a greater number of current sources than before. These are detailed below.

[0185] The data is written by -the injection of the current Iref, écriture, sot, bl, p, generated by a current source l 11-0 into the selected BL line (of index i from bit 1 to bit n), and this current flows from the selected BL line to the selected BLB line (of the same index i) through the selected memory cell, -the extraction of the current Iref,writing,sot,BL,N generated by a current source l 11-1, from the selected BL line (of index i from bit 1 to bit n), the current flowing from the selected BLB line to the selected BL line (of the same index i) through the selected memory cell, -the injection of the current Iref,writing,sot,blb,p, generated by a current source l 11-2 into the selected BLB line (of index i from bit 1 to bit n), and this current flows from the selected BLB line to the selected BL line (of the same index i) through the selected memory cell, -the extraction of the current Iref,writing,sot,BLB,N generated by a current source l 11-3, from the selected BLB line (of index i from bit 1 to bit n), the current flowing from the selected BL line to the selected BLB line (of the same index i) through the selected memory cell.

[0186] The current sources 111-0 and 111-1 have, for the purposes of [Fig.19], a common terminal, and their second terminals are respectively connected to the supply voltage VDD and to ground GND.

[0187] The current sources 111-2 and 111-3 have, for the purposes of [Fig. 19], a common terminal, and their second terminals are respectively connected to the supply voltage VDD and to ground GND.

[0188] STT writing assistance is provided by - the injection of the current Iref,écriture,stt,p, generated by a current source l 11-9 into the selected RBL line (index i from bit 1 to bit n) - and by extracting the current Iref,writing,srr,N generated by a current source l 11-8, from the selected RBL line (index i from bit 1 to bit n).

[0189] The current sources 111-9 and 111-8 have, for the purposes of [Fig. 19], a common terminal, and their second terminals are respectively connected to the supply voltage VDD and to ground GND.

[0190] The word line addressing circuit 130 that selects a memory column between word 1 and word m is configured and operates as before.

[0191] [Fig.20] The current control circuit includes, as before, a biasing circuit 120 which includes a voltage supply biasing the bit lines from 1 to n at appropriate voltages.

[0192] In this embodiment, the voltage sources 121-0 and 121-1 are the voltage sources of the voltage supply 121 of the biasing circuit 120. They provide the potentials VBlb and VBl defined with respect to ground GND, for the terminals BLB and BL, respectively. This is shown in [Fig. 20].

[0193] [Fig.21] The current control circuit can be implemented as follows. There is a setup, and this is represented in [Fig.21], -PMOS current mirrors based on a single PMOS transistor P0BL and n transistors PlBL,i to PlBL>n, all mirrored with P0BL to inject current into the BL lines -and NMOS current mirrors based on a single NMOS transistor N0BL and n transistors N1BLji to N1BL>n all mirrored with N0BL to draw current from BL lines.

[0194] For any i between 1 and n the free terminals of the transistors PlBL,i and NlBL,i (the copy branches) are connected together and connected, by the switch SW;, to the terminal BL(i) of the cell of index i.

[0195] As before, the current source 111-0 is placed between the supply potential VDd and the ground potential (GND), the PMOS transistor P0BL being interposed by its source and its drain between the supply VDD and the current source 111-0.

[0196] And the current source 111-1 is placed between the supply potential VDD and the ground potential (GND), the NMOS transistor NOBL being interposed by its drain and its source between the current source 111-1 and ground.

[0197] There is also implementation

[0198] of PMOS current mirrors based on a single PMOS transistor P0BLB and n transistors PlBLB,i to PlBLB,n all mirrored with P0BLB to inject current into the BLB lines,

[0199] and NMOS current mirrors based on a single NMOS transistor N0BLB and n transistors N1BLBji to N1BLB>n all mirrored with N0BLB to draw current from the BLB lines.

[0200] For any i between 1 and n the free terminals of the transistors PIblbj and NIblbj (the copy branches) are connected together and connected, by the SW switch; to the terminal BLB(i) of the cell of index i.

[0201] The current source 111-2 is placed between the supply potential VDD and the ground potential (GND), the PMOS transistor P0BLB being interposed by its source and its drain between the supply VDD and the current source 111-2.

[0202] The current source 111-3 is placed between the supply potential VDD and the ground potential (GND), the NMOS transistor N0BLB being interposed by its drain and its source between the current source 111-1 and ground.

[0203] The PMOS and NMOS current mirrors mentioned above are used for SOT writing.

[0204] [Fig.22] There is also setup, and this is represented in [Fig.22] which extends the [Fig.21]

[0205] For any i between 1 and n the free terminals of the transistors PlSiT,i and N lSTr>i (the copy branches) are connected together and connected, by the SW switch; to the RBL(i) terminal of the cell of index i.

[0206] The current source 111-9 is placed between the supply potential VDD and the ground potential (GND), the PMOS transistor POsn being interposed by its source and its drain between the supply VDd and the current source 111-9.

[0207] The current source 111-8 is placed between the supply potential VDD and the ground potential (GND), the NMOS transistor NOsi being interposed by its drain and its source between the current source 111-8 and ground.

[0208] The injection or withdrawal of current in the RBL lines, by the PMOS and NMOS mirrors of [Fig.22], serves to assist STT in writing.

[0209] The injection via the PMOS mirrors of [Fig. 22] is also used, as needed, for reading. Alternatively, it is also possible to use the NMOS mirrors.

[0210] [Fig.23] To select the memory column with index k, the potential is applied VDD to VWLjk. To deselected it, a zero potential is applied to it.

[0211] To deselect a memory line with index i, switch SW; to OFF (open). Conversely, to select a memory line with index i, switch SW; to ON (closed).

[0212] Once a cell is selected, there are 4 writing operating cases, corresponding to the fact that there are two data that may need to be written ("0" and "1") and that during a given write operation, the STT write current can flow through the MTJ pillar from top to bottom or from bottom to top.

[0213] Fig. 23 therefore shows two cases for the writing of a first piece of data, here noted as "0".

[0214] Writing '0' Writing '1' Case 0A Case 0B Case IA Case 1B SWj ON Iref.writing,SOT3LJ' Iref,writing,SOT>0 A 0A 0A 0A Iref,writing,SOT3L,N 0A 0A 0A Iref,writing,SOT >0 A Iref,writing,SOT,BLB,P 0A 0A Iref,writing,SOT>0 A 0A Iref.writing,SOT,BLB,N 0A Iref.writing,SOT>0 A 0A 0A Iref.writing.STT.P Iref,writing,STT>0 A 0A Iref,writing,STT>0 A 0A Iref,writing,STT,N 0A Iref,writing,STT^O A. 0A Iref,writing,STT >0 A swBL OFF ON ON OFF ^BL - ^dd ov - SWBLB ON OFF OFF ON Vblb 0 V - - Vdd

[0215]

[0216]

[0217]

[0218]

[0219] On the left side of Figure 23, the case is labeled OA. Current source 111-0 is activated with a non-zero positive current W.write,soT,BL.p>0A, and current sources 111-1, 111-2, and 111-3 are cut off: Iref,write,SOTBL,N = Iref,write,SOTBLRP = Iref,write,SOT3LBN = 0A. To cut off the current sources, alternatively, a switch can be used that connects or disconnects the connection between the current sources and the gates of the associated transistors, in which case the gates are connected to GND for NMOS transistors, or VDD for PMOS transistors. Current source 111-9 is activated with a non-zero positive current Lcf,&riturc,STTj'>0A, and current source 111-8 is cut off: Ircf,ccriturc.STT,N = 0A. The SWBL switch is toggled to OFF (open), the SWBLB switch to ON (closed), and the VBLB potential is connected to ground (0V). On the right of figure 23, the case is noted 0B. The current source 111-3 is activated with a non-zero positive current Ircf,ccriturL,soTB^ and the current sources 111-0, 111-1, and 111-2 are cut off: Ircf,ccriturc,SOT,BL,P = IrcWcriturc,S0T3LN = Iref,écriture,SOTBLBJ1 = 0A. Current source 111-8 is activated with a non-zero positive current Lcf,&riturc,STT3T>0A, and current source 111-9 is cut off: ïrcf,ccritiue,STT,p = 0A.

[0220] The SWBL switch is toggled to ON (closed), the SWBLB switch to OFF (open), and the VBL potential is connected to the supply voltage (VDD).

[0221] [Fig.24] Fig.24 shows the two other cases, for the writing of the second data, here noted "1".

[0222] On the left of figure 24, the case is noted IA. The current source 111-2 is activated with a non-zero positive current IrefA;riture,soT,BLBjp>0A, and the current sources 111-0, 111-1, and 111-3 are cut off: Iref / écritureJS0T3LP = Iref.écriture.SOT.BUN = Iref,écriture,SOT,BLB,N = 0A.

[0223] Current source 111-9 is activated with a non-zero positive current Iref,writing,STT,P>0A, and current source 111-8 is cut off: Irefwriting.STT.N = 0A.

[0224] The SWBL switch is toggled to ON (closed), the SWBLB switch to OFF (open), and the VBL potential is connected to ground (0V).

[0225] To the right of Figure 24, the case is noted IB. The current source 111-1 is activated with a non-zero positive current IrefA;riture,soT,BL.N>0A, and the current sources 111-0, 111-2, and 111-3 are cut off: Iref,écriture,SOT,BL,P = Iref,écriture,SOT,BLB,P = Iref écriture,SOT,BLB,N = 0A.

[0226] The current source 111-8 is activated with a non-zero positive current Iref,writing,STT,N>0A, and the current SOUTCe 111-9 is cut off: Irefwriting,STT.P = 0A.

[0227] The SWBL switch is toggled to OFF (open), the SWBLB switch to ON (closed), and the VBLB potential is connected to the supply voltage (VDd)-

[0228] The reading operation is as follows: SW Reading; ON Iref.writing,SOT,BL,P 0A ^re-writing,SOT,BL,N 0A Iref,writing,SOT3LB.P 0A Iref,writing,SOT,BLB.N 0A Iref,writing,STT.P Jref3reading>0 A. Iref,writing,SnT,N 0A swBL OFF Vbl - swBLB ON Vblb ov

[0229] Current sources 111-0, 111-1, 111-2, and 111-3 are cut off: lref,éaiiure,soT,BL,p= ^ref,écriture,SOT,BL,N = U£écriture,SOT,BLB,P = VeEécriture,SOT,BLB,N = OA.

[0230] One of the current sources 111-9 (in the variant of the table) or alternatively 111-8 is activated with a non-zero positive current lref,ieciure>0A, and the second of these two sources is cut off (OA).

[0231] In the variant of the table, the SWBL switch is toggled to OFF (open), the SWBLB switch to ON (closed), and the VBLB potential is connected to ground (0V). Alternatively, VBlb is at VDD if source 111-8 is used for reading.

[0232] The method is advantageous because the amplitudes of the SOT and STT write currents are constant and controlled regardless of the position of the selected memory cell between the line terminals. There is no degradation of the MTJ pillar (the voltage across the pillar remains limited).

[0233] Lécrit.sTT can be approximately 20 pA and Lécrit.soT approximately 60 to 200 pA, or lower, or higher. By reducing the value of lécrit,sot, the circuit is more efficient (i.e., it is simpler to size the circuit and / or to use higher values ​​of lécrit,stt).

[0234] Alternatively, we use Iref,écriture,stt,n = Vlecture (and Iref,écriture,stt,p = 0A), in which case, Vblb is brought to VDD.

[0235] The invention applies to single pillar structures, but the principle remains the same for multi-pillar structures.

[0236] The proposed implementation covers all possible cases. If the paths of the write operations, sot and stt, within the circuit are known in advance, it is possible to simplify the circuit by removing unnecessary current sources. Thus, if the circuit is only used for write assistance, two of the six current sources in the circuit can be eliminated.

[0237] The embodiments presented use current mirrors to implement the current sources, but it is possible to use other implementations for the current sources.

[0238] [Fig.25] By implementing two current sources per access line (BL, BLB, and RBL), it is possible to assist writing operations with a VCMA voltage (for MTJ pillars with a high resistance-area product value RA, i.e., high resistance values).

[0239] In one embodiment, writing is performed with VCMA (voltage-controlled magnetic anisotropy) assistance, a technique discussed, for example, in Y. Wu et al., "Voltage-Gate-Assisted Spin-Orbit-Torque Magnetic Random-Access Memory for High-Density and Low-Power Embedded Applications," Physical Review Applied, 15(6):064015, 2021, or also in US2016 / 0232959A1. In addition to the writing current In a conventional operation, a voltage is applied across the SOT line, Iwrite,soT,o or Iwrite,soT.i, during a '0' or '1' write operation, respectively. VCMA-assisted writing is unipolar: the VCMA voltage, VMTJ, lowers the potential energy barrier between the parallel (P) and antiparallel (AP) magnetic states to facilitate writing.

[0240] The polarity direction of the VMtj voltage does not depend on the data to be written: VMtj facilitates the writing of '0' when it is, for example, positive between the top and bottom of the MTJ pillar, as is the case in the left part of [Fig. 25]. It is then also possible, as is the case in the right part of [Fig. 25], to use the VCMA voltage to oppose the writing of the data '0' by applying a negative VMTJ (opposite to the voltage used in the facilitation case) between the top and bottom of the MTJ pillar.

[0241] [Fig.26] VMTJ also facilitates the writing of '1' when it is positive between the top and bottom of the MTJ pillar, as is the case in the left part of [Fig.26], and as was the case to facilitate the writing of the data '0' in [Fig.25]. It is also possible to use the VCMA voltage to oppose the writing of the data '1' by applying a negative Vmtj (opposite to the voltage used in the facilitation case) between the top and bottom of the MTJ pillar, as is the case in the right part of [Fig.26].

[0242] It is necessary to control the polarity direction of the VCMA voltage, VMTJ, independently of the direction of flow of the SOT write current. VCMA assisted writing requires high resistance-area products RA of the MTJ pillar, for example, greater than 20 μm.pm2. The VCMA voltage, Vmtj, allows the required SOT write current, IeWriting,soT,o or Iwrite,soT,i, to be reduced when there is facilitation, or, conversely, the required SOT write current to be increased when there is opposition, for example, to implement selectivity in a multi-pillar structure.

[0243] SOT-MRAM memory circuits using VCMA voltage-assisted writing are sometimes driven with constant voltage sources to generate the SOT write current, Fmune.soT, and the VCMA voltage, VMtj:

[0244] The problems previously described are encountered: the SOT write current, as well as the VCMA voltage, are not uniform within the memory array. There is a decrease in the SOT current and the amplitude of the VCMA voltage as one moves away from the driver circuits, and an asymmetry between writing '0' and '1'. Furthermore, it is difficult to precisely and independently control the direction of flow of the SOT write current and the direction of bias of the VCMA voltage. To facilitate or impede writing independently of the data to be written ('0' or '1'), Vmtj must be able to be applied to the terminals of the MTJ pillar in both directions (positive from above). downwards, or positive from bottom to top) regardless of the direction of writing flow.soT - in the SOT line, from BL to BLB or from BLB to BL.

[0245] The amplitude of the VCMA voltage (in addition to that of the SOT current) is not uniform: it depends on the position of the selected memory cell (from 1 to n) and the data to be written. Furthermore, it is difficult to control the direction of the VCMA voltage.

[0246] [Fig. 27] Instead of driving the memory array with voltage, the memory array is again driven entirely with current. The driver circuit generates a reference SOT write current, Iref,write,sot, which flows through the SOT line of the selected memory cell. The driver circuit generates a reference VCMA write current, Iref,write,vcma, which biases the MT J pillar of the selected memory cell to the desired VCMA voltage, Vmtj*. The SOT write current and the VCMA voltage are controlled independently of each other. The driver circuit used to generate the VCMA voltage also performs the read operations. The currents used to generate the VCMA voltage (between 1 and 5 pA) are generally substantially the same as the currents used for reading (between 1 and 10 pA, depending on the RA value of the pillar).Furthermore, the current used to generate the VCMA voltage is insufficient on its own to write data to the MTJ pillar. Therefore, the same current source can be used for both VCMA assistance and reading (either current source 111-8 or current source 111-9). If the current for the VCMA voltage and the current for the reading are significantly different, another current source is added to the RBL line, used solely for reading.

[0247] The proposed solution resolves the problems mentioned above: the write current SOT and the voltage VCMA of the selected memory cell, lécriture.soT and VMTJ, respectively, are constant regardless of the position of the selected memory cell and the data to be written ('0' or '1') (Iécriture,soT~Iref,écriture,sot and Vmtj depend directly on Iref,écriture, vcma), i.e. this current and this voltage are not dependent on the position and the data to be written, but depend only on Iref,écriture,SOT and Iref,écriture,VCMA, respectively.

[0248] The direction of circulation of Iécriture,soT and the orientation of Vmtj are bidirectional and independent of each other.

[0249] The current-driven circuit includes a current source that generates Iref,write,SOT, Iref,write,VCMA, and Iref,read* Iref,read & 0c preferenCC the 11161116 SOUTCC qUC Iref,write,VCMA*

[0250] The system includes, as before, an addressing device which connects the current sources to the selected memory lines (i.e., selected RBL, BL, and BLB).

[0251] The bit lines are biased by a dedicated circuit. There is also a word line addressing circuit which selects a memory column, as before.

[0252] Figure 27 shows the current sources 111-0, 111-1, 111-2, 111-3, 111-8, and 111-9 positioned like their counterparts in Figure 19. Sources 111-0 and 111-1 generate currents Iref,write,sot,bl,p and Iref,write,sot,bl,n*. Sources 111-2 and 111-3 generate currents Iref,write,sot,blb,p and Iref,write,sot,blb,n*. Sources 111-9 and 111-8 generate currents Iref,write,vcma,p and Iref,write,vcma,n*.

[0253] [Fig.28] Fig.28 shows the biasing of the bit lines of the circuit, which is similar to that implemented in the embodiment of figures 19 and 20.

[0254] [Fig.29] Fig.29 shows an example of implementation of the principles of the figure previous with PMOS and NMOS current mirrors.

[0255] [Fig.30] Fig.30, which extends Fig.29, shows the operation of the sources of current 111-8 and 111-9.

[0256] Current sources 111-0, 111-1, 111-2 and 111-3 operate in the same way as the current sources shown in [Fig.21].

[0257] Thus, there is implementation,

[0258] of PMOS current mirrors based on a single PMOS transistor POvcma and n transistors P1Vcma,i to P1Vcma,u all mirrored with P0Vcma to inject current into the RBL lines,

[0259] and NMOS current mirrors based on a single NMOS transistor N0Vcma and n transistors N1Vcma,i to N1VcMA,n all mirrored with N0vcma to draw current from RBL lines.

[0260] For any i between 1 and n the free terminals of the transistors PIvcmaj and NIvcmaj (the copy branches) are connected together and connected, by the switch SWi, to the RBL(i) terminals of the cells of the row of index i.

[0261] The injection or pull of current into the RBL lines, by the PMOS and NMOS mirrors of [Fig.30], serves to assist VCMA in writing.

[0262] The injection via the PMOS mirrors of [Fig. 30] is also used, as needed, for reading. Alternatively, the NMOS current mirrors can also be used.

[0263] [Fig.31] To select the memory column with index k, the potential is applied VDD to VWLjk. To deselected it, a zero potential is applied to it.

[0264] To deselect a memory line at index i, switch SW; to OFF (open). Conversely, to select a memory line at index i, switch SW; to ON (closed).

[0265] Once a cell is selected, there are 4 writing operating cases, corresponding to the fact that two different data may have to be written ("0" and "1") and that during a given write, the VCMA voltage at the ends of the MTJ pillar may be oriented in one direction or the other.

[0266] Fig. 31 therefore shows two cases for the writing of a first piece of data, here noted as "0". Writing '0' Writing '1' Case 0A Case 0B Case IA Case IB SW; ON Lrf.writing,SOT,BL,P ^re^writing.SOT^OA 0A 0A 0A Lxf,writing,SOT,BL,N 0A 0A 0A tref,writing, SOT >0 A tref,writing,SOT,BLBæ 0A 0A Iref,writing,SOT >0 A 0A hef.writing,SOT,BLB,\: 0A tref,writing,SOT> 0 A 0A 0A ^ref,writing.VCMJ\,P trefA'riture,VCMA> 0 A 0A tre^writing,VCMA>0 A 0A ^ref, writing, VCMA.N 0A Ccf,writing,VCMA>0 A 0A ïrcf,writing,VCm>0 A swBL OFF ON ON OFF VBL - Vdd 0 V - SWBLB ON OFF OFF ON Vblb 0 V - - Vdd

[0268] On the left of Figure 31, the case is noted 0A. The current source 111-0 is activated with a non-zero positive current W.écriture,soT,BL.P>0A, and the current sources 111-1, 111-2, and 111-3 are cut off: Iref,écriture,SOTBL,N = Iref,écriture,SOT^LRP = læf,écriture,SOT.BLBN = 0A.

[0269] Current source 111-9 is activated with a non-zero positive current Iref,écrjture,vcMAj?>0A, and current source 111-8 is cut off: Iref,écriuœ,vcMA^ = 0A.

[0270] The SWBL switch is toggled to OFF (open), the SWBLB switch to ON (closed), and the VBLB potential is connected to ground (0V).

[0271] To the right of figure 31, the case is noted 0B. The current source 111-3 is activated with a non-zero positive current lrerécriture,soT,BLB,N>OA, and the current sources 111-0, 111-1, and 111-2 are cut off: lref,eciilure,S0T3LP = ^ref,écriliue,SOT,BL,N = lref,écrilure.SOT.BLB,P = OA.

[0272] Current source 111-8 is activated with a non-zero positive current iref,écriiure,vcMAM>OA, and current source 111-9 is cut off: lref,écriiure,vcmap = OA.

[0273] The SWBL switch is toggled to ON (closed), the SWBLB switch to OFF (open), and the VBL potential is connected to the supply voltage (VDD).

[0274] [Fig.32] Fig.32 shows the two other cases, for the writing of the second data, here noted "1".

[0275] On the left of figure 32, the case is noted IA. The current source 111-2 is activated with a non-zero positive current IrefAriture,soT^LHP>0A, and the current sources 111-0, 111-1, and 111-3 are cut off: Iref,écriture,SOT,BL,P = Iref^ritui^30T,BLJN = Wécriture.SOT.BLB,N = 0A.

[0276] Current source 111-9 is activated with a non-zero positive current lref,writing,VCMA,P>0A, and current source 111-8 is cut off: Iref,writing,VCMAJV = 0A.

[0277] The SWBL switch is toggled to ON (closed), the SWBLB switch to OFF (open), and the VBL potential is that of ground (0V).

[0278] To the right of Figure 32, the case is noted IB. The current source 111-1 is activated with a non-zero positive current IrefAriture,soT^LjQ>0A, and the current sources 111-0, 111-2, and 111-3 are cut off: Iref,écriture,SOT,BL,P = lref,écriture,SOT,BLB.P = lref,écriture,SOT,BLB,N = 0A.

[0279]

[0280]

[0281]

[0282] The current source 111-8 is activated with a non-zero positive current lref,écriture,vctma,n>0A, and the current source 111-9 is cut off: Iref,écriture,vcma,p = 0A. The SWBL switch is toggled to OFF (open), the SWBLB switch to ON (closed), and the VBLB potential is that of the supply voltage (VDd)- The reading operation is as follows (it is identical to that mentioned in connection with figures 23 and 24): SW reading, ON ^ref,writing, SOT 0A lref,writing, SOT,BL,N 0A Lof,writing,SOT,BLB,P 0A tref,writing,SOT.BLB,N 0A lref.writing,VCMAæ Iref,reading>0 A tref.writing,VCMA,N 0A SWBL OFF VBL - swBLB ON VBlb OV

[0283] Current sources 111-0, 111-1, 111-2, and 111-3 are cut off: Iref,écriture,soT.BL,p = Cef.écriture,SOT,BL.N = hd.écriture.SOT.BLB.P = Cei;écriture,SOT,BLB,N = OA.

[0284] One of the current sources 111-9 in the variant shown in the table or alternatively 111-8 is activated with a non-zero positive current lref,taure>0A, and the second of these two sources is cut off (OA).

[0285] The SWBL switch is toggled to OFF (open), the SWBLB switch to ON (closed), and the VBLB potential is connected to ground (0V).

[0286] The amplitudes of the SOT write current and the VCMA voltage are essentially constant from the first to the last cell and controlled regardless of the position of the selected memory cell.

[0287] During writing, the VCMA voltage through the MTJ pillar can be oriented from top down or from bottom up.

[0288] There is no degradation of the MTJ pillar (VMTJ<1 V).

[0289] A VCMA voltage, VMtj, of approximately 250 mV could, according to simulations, reduce the required SOT current, hmune.soï, by 30%. Simulations show that it is possible to obtain VMtj at 250 mV with an Écriture, soT = 200 pA. By reducing the value of Écriture.sor, the circuit is simpler to dimension and to use with higher values ​​of VMTJ.

[0290] Alternatively, we use Lef .write, vcma,n — Lef,read and Lef,write,vcma,p — 0A, in which case, VblB = Vdd.

[0291] The invention has been presented with single pillar structures, but is also applied in other embodiments to multi-pillar structures.

[0292] In general, unnecessary current sources are removed. If the circuit is only used for write assistance, 3 of the 6 current sources in the circuit are removed.

Claims

Demands

1. Electronic RAM circuit comprising an array (100) of memory cells (10) each including at least one magnetic pillar and a spin Hall effect line interacting by spin-orbit coupling and forming a tripole (BEI, BE2, TE), each cell (10) further comprising a means for selecting (NI, N2) the connection to the terminals of said tripole (BEI, BE2, TE), • a terminal (WL(k)) of each cell being connected in the circuit for selecting memory cells of the array according to a first dimension of the array using the means for selecting (NI, N2) the memory cells, • and a pair of terminals (BLB(i), RBL(i);BL(i), BLB(i)) of each cell being connected in the circuit to allow a common application, to memory cells of the matrix selected according to a second dimension of the matrix, of electrical energy for reading or writing magnetic information in the pillar, said electronic RAM circuit being characterized in that said electrical energy is applied by circulating a current controlled by a current-driving circuit (111).;

2. A RAM electronic circuit according to claim 1, characterized in that electrical energy is applied by current mirror copy branches (PlEo.i, P1e o,n ;N1E i 4, N1Ei >n ;PlL.i, PlE,n) each associated with a cell line along the second dimension, a transistor of said current mirrors being shared to form a common reference branch of said current mirrors.

3. A RAM electronic circuit according to claim 1 or claim 2, characterized in that electrical energy is applied by a copy branch (P1EO; N1E i; P 11) common to several cell lines along the second dimension of the matrix, a controller (115) of the circuit selecting a cell line to selectively connect it to said common copy branch.

4. A random access memory electronic circuit according to any one of claims 1 to 3, characterized in that the electrical energy for writing is applied by connecting to the same terminal of the spin Hall effect line a first current source with associated current mirror PMOS (PlEOji,PlE o,n ; PlEo) for writing the first binary value, and a second current source with associated current mirror NMOS (N1E i ,i, N1Ei >n ;N1E i) for writing the second binary value.

5. A RAM electronic circuit according to any one of claims 1 to 4, characterized in that the electrical energy for writing is applied by connecting a current source (111-0, 111-1) to a first terminal (BL, BLB) of the spin Hall effect line for writing the first binary value and to a second terminal (BL, BLB) of the spin Hall effect line for writing the second binary value, a controller (116) of the circuit biasing the terminal (BL, BLB) of the Hall effect line opposite to the current source as a function of the binary value to be written.

6. RAM electronic circuit according to any one of claims 1 to 5, characterized in that the electrical energy for reading is applied by connecting a current source (111-9) to one end of the magnetic pillar opposite the spin Hall effect line, the spin Hall effect line being polarized for the read operation.

7. A RAM electronic circuit according to any one of claims 1 to 6, characterized in that the electrical energy for reading is applied in the magnetic pile in a first direction or an opposite direction depending on a value written during a simultaneous write operation.

8. Electronic RAM circuit according to any one of claims 1 to 7, characterized in that the current-drive circuit (110) further circulates an assist current (Lnune.sïï; lécnture, vcma) through the magnetic pillar to facilitate or prevent writing.

9. Electronic RAM circuit according to any one of claims 1 to 8, characterized in that the magnetic RAM electronic circuit comprises a biasing circuit (120) placed with respect to the matrix (100) in opposition to the current-driving circuit (110).

10. A RAM electronic circuit according to any one of claims 1 to 9, characterized in that the selection means comprises two field-effect transistors (NI, N2) each connected by a source or a drain at a respective terminal of the assembly formed by the magnetic pillar and the spin Hall effect line.

11. RAM electronic circuit according to any one of claims 1 to 10, characterized in that the cells are SOT-5T, SWL1 or SWL2 cells.

12. A RAM electronic circuit according to any one of claims 1 to 11, characterized in that the memory cells (10) are single-pillar magnetic cells, or four-pillar magnetic cells, or cells with another number of magnetic pillars less than 20.

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