53 results about "Magnetic ram" patented technology

A magnetic memory fabricated on a semiconductor substrate is disclosed. The method and system include a plurality of magnetic tunneling junctions and a plurality of shields for magnetically shielding the plurality of magnetic tunneling junctions. Each of the plurality of magnetic tunneling junctions includes a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. At least a portion of the plurality of shields have a high moment and a high permeability and are conductive. The plurality of shields are electrically isolated from the plurality of magnetic tunneling junctions. The plurality of magnetic tunneling junctions are between the plurality of shields.

A spin Hall effect magnetoresistive memory comprises apparatus of a three terminal magnetoresistive memory cell having an MTJ stack, a functional magnetic layer having a magnetization anti-parallel or parallel coupled with a recording layer magnetization in the MTJ stack, and a SHE-metal base layer. The control circuitry coupled through the bit line and the two select transistors to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two bottom electrodes and to supply a bi-directional spin Hall effect recording current, and accordingly to directly switch the magnetization of the functional magnetic coupling layer and indirectly switching the magnetization of the recording layer through the coupling between the functional magnetic coupling layer and the recording layer.

A fast and low-power sense amplifier and writing circuit for high-speed Magnetic RAM (MRAM) which provides the long retention times and endurance of magnetic tunnel junction (MTJ) cells, while providing faster access speeds, verified writes, and an increased sensing margin. A high-speed and low-power pre-read and write sense amplifier (PWSA) provide VCMA effect precessional switching of MTJ cells which include pre-read and comparison steps which reduce power consumption. An embodiment of the PWSA circuit is described with write and pre-charge circuit, S and D latches, comparison circuit, and a differential amplifier and control circuit.

A new magnetic RAM cell device is achieved. The device comprises a plurality MTJ cells each comprising a free layer and a pinned layer separated by a dielectric layer. A common conductive layer couples together all of the pinned layers of the MJT cell. A first end of the common conductive layer is switchably coupled to a programming line. A second end of the common conductive layer is switchably coupled to a ground. A pluraity of diodes is used. Each diode is coupled between one of the MJT cells and one of a plurality of bit lines.

A magnetic RAM (MRAM) using a thermo-magnetic spontaneous Hall effect includes a MOS transistor formed on a substrate; a heating layer formed above the MOS transistor and connected to a source region of the MOS transistor; a memory layer having a data write area to which data is written, the data write area being formed on the heating means; a bit line formed on the data write area; an upper insulating film formed on the bit line and the memory layer; and a write line formed on the upper insulating film so that a magnetic field necessary for writing data is generated in at least the data write area of the memory layer. The MRAM writes or reads data using the fact that a spontaneous Hall voltage greatly differs according to the magnetization state of a memory layer, thereby providing the device a high data sensing margin.

A new magnetic RAM cell device is achieved. The device comprisese, first, a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A reading switch is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.

A memory device and a fabrication method therefor. In order to improve an operation property of a magnetic RAM (abbreviated as "MRAM') having a higher speed than an SRAM, integration as high as a DRAM, and a property of a nonvolatile memory such as a flash memory, an oxide film is thinly formed on a second word line which is a write line, and an MTJ cell is formed according to a succeeding process. The MRAM is formed by reducing a distance between the write line and the MTJ cell. It is thus possible to perform a write operation with a small current.

Reference cells are provided in a memory cell array. When the data is read, the data in the reference cells are inverted, thereby preventing the data in the selected cell from changing. This makes it possible to decrease the number of write operations and realize a high-speed read operation and lower power consumption.

The present disclosure generally relates to the fabrication of metal-oxide-semiconductor (MOS) select transistors in a vertical orientation such that the transistor pair fits within the footprint of a 4F² memory cell. The present disclosure further relates to the simultaneous fabrication of a vertical stack of transistors in which each transistor is distinct, as opposed to being serially connected in a NAND-like string. An initial stack of materials is built to include silicon layers to act as source and drain regions as well as to serve as epitaxial growth seed points. As such, the transistor disclosed may be utilized in conjunction with memory elements such as Phase Change, Resistive, or Magnetic RAM memory within array designs, among others.

The present invention discloses a kind of magnetic RAM (MRAM). The MRAM unit has bit line BL and word write line WWL in the same side of magnetic film memory unit, and the magnetic film memory unit is connected to the drain of the transistor ART via the contact hole. MRAM unit has ground line GND and the word write line WWL configured in the identical metal wiring layer. This structure has the advantages of reduced metal wire layers and contact holes, simplified technological process, lowered manufacture cost and raised MRAM integration level.

A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first magnetic portion and a portion of the first insulating layer around the first magnetic portion, the non-magnetic portion being interposed between the first and second magnetic portions.

The invention relates to a semiconductor memory device which is programmed by dualism of carrying characteristic of current passed through an adjacent memory cell. The semiconductor memory device includes a programmable memory cell and at least two current carrying structures. Wherein, at least one of the current carrying structures has a segmented current carrying structure comprising a plurality of first segments positioned on a first plane, the plurality of first segments is coupled with a plurality of second segments positioned on a second plane, and widths of the second segments are larger than the widths of the first segments. The semiconductor memory device of the invention improve a high current interconnection structure, eliminates an electron shift effect due to a high current density so as to enhance reliability.