Magnetic RAM and its data reading method

Abstract

A magnetic random access memory having a memory cell array in which one block is formed from a plurality of magnetoresistive elements using a magnetoresistive effect, and a plurality of blocks are arranged in row and column directions, includes a plurality of first magnetoresistive elements arranged in a first block, a plurality of first word lines each of which is independently connected to one terminal of a corresponding one of the first magnetoresistive elements and runs in the row direction, a first read sub bit line commonly connected to the other terminal of each of the first magnetoresistive elements, a first block select switch whose first current path has one end connected to one end of the first read sub bit line, and a first read main bit line which is connected to the other end of the first current path and runs in the column direction.

Description

[0001] Cross References to Related Patent Applications [0002] This application is based on and claims priority from prior Japanese Patent Application No. 2002-374716 filed on December 25, 2002, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to a magnetic random access memory (MRAM) for storing "1" and "0" data by using a magnetoresistive effect. Background technique [0004] In recent years, many memories utilizing new principles for storing data have been proposed. One of them is a magnetic random access memory (MRAM) utilizing a tunneling magnetoresistance (hereinafter referred to as TMR) effect. As a proposal on a magnetic random access memory, for example, the following non-patent reference 1 is known: Roy Scheuerlein et al., "A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell", 2000 ISSCC Digest of Technical Papers (U.S.A.), February 2...

AI Technical Summary

Problems solved by technology

[0043] However, if the number of cell arrays is simply increased while reducing the number of cells connected to the bit line BL due to constraints on the maximum number of cells connectable to the bit line BL, the chip size increases and it is impossible to sufficiently increase the Integration density

Therefore, it is almost impossible to take the above measures for mass storage

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