Error detection and correction

Abstract

Error Detection and Correction This description relates to a method (200) for detecting and correcting an error in at least two bits of binary data stored in memory, comprising the following successive steps: (a) modifying (205) the value of one bit of said binary data; (b) implementing (206) a mechanism for correcting an error in one bit of said modified binary data; (c) if a fault is still detected, repeating step (a) (205) by modifying the value of another bit of said binary data. Figure for the abstract: Fig. 2

Description

Title of the invention: Error detection and correction technical field

[0001] This description relates generally to electronic systems and devices, and to data management by such electronic systems and devices. This description relates more particularly to data verification, and more specifically to the detection and correction of errors in binary data. Prior art

[0002] Data management during the operation of a system or electronic circuit generally requires the use of one or more memories. Operating data is, for example, written to and / or read from these memories before or after they have been used.

[0003] It is important to be able to verify the reliability of data stored in memory, for example before use or after storage. Techniques exist to detect when a bit of binary data is erroneous.

[0004] It would be desirable to be able to improve, at least in part, certain aspects of the methods for detecting data errors in memory. Summary of the invention

[0005] There is a need for methods of verifying data stored in memory.

[0006] There is a need for methods of detecting and correcting errors in data stored in memory.

[0007] There is a need for methods of detecting and correcting errors of at least two bits in data stored in a memory.

[0008] There is a need for electronic devices adapted to implement such error detection and correction processes.

[0009] An embodiment overcomes all or part of the drawbacks of known error detection and correction methods.

[0010] One embodiment provides an error detection and correction method adapted to detect and correct an error of at least two bits in data stored in a memory.

[0011] One embodiment provides a method for detecting and correcting errors using: - a bit-by-bit search for a second error on a bit of this data; and - a method for detecting and correcting a first error on a bit of a data.

[0012] One embodiment provides a device adapted to implement such error detection and correction processes.

[0013] One embodiment provides a method for detecting and correcting an error on at least two bits of binary data stored in a memory, comprising the following successive steps: (a) modify the value of a bit of said binary data; (b) implement a mechanism for correcting an error on a bit of said modified binary data; (c) if a fault is still detected, repeat the step by changing the value of another bit of said binary data.

[0014] Another embodiment provides a device for detecting and correcting an error on at least two bits of binary data stored in a memory, adapted to implement a method comprising the following successive steps: (a) modify the value of one bit of said binary data; (b) implement a mechanism for correcting an error on a bit of said modified binary data; (c) if a fault is still detected, repeat the step by changing the value of another bit of said binary data.

[0015] According to one embodiment, the method further comprises, after step (b), a step (d) during which if no fault is detected, the value of said binary data is made equal to the value of said modified binary data, and is considered corrected.

[0016] According to one embodiment, the method further comprises, before step (a), a step (e) of implementing said error correction mechanism on a bit of said binary data.

[0017] According to one embodiment, the method further comprises, after step (e), a step (f) during which if no fault is detected, the value of said binary data is made equal to the value of said binary data obtained in step (e), and is considered corrected.

[0018] According to one embodiment, the method further comprises, after step (c), a step (g) during which if all the bit values ​​of said binary data have been changed at least once and a fault is still detected, then said binary data is considered uncorrectable.

[0019] According to one embodiment, said one-bit error correction mechanism uses a Hamming code.

[0020] According to one embodiment, said binary data comprises bits representing an error detection and correction code and bits representing a value of said binary data.

[0021] According to one embodiment, said one-bit error correction mechanism includes a calculation step of a comparison data of said detection and correction code and a recalculated code from said value of said binary data.

[0022] According to one embodiment, said correction mechanism includes a means for automatically calculating a corrected error detection and correction code. Brief description of the drawings

[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0024] [Fig.1] represents, very schematically and in block form, an embodiment of an electronic device adapted to implement an error detection and correction process;

[0025] [Fig.2] represents a flowchart illustrating a method of implementing an error detection and correction process;

[0026] [Fig. 3] represents a block diagram illustrating an example of practical implementation of the process of [Fig. 2]; and

[0027] [Fig.4] represents a block diagram illustrating another example of practical implementation of the process of [Fig.2]. Description of the implementation methods

[0028] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0033] The embodiments described below relate to the detection and correction of errors in data stored in memory. These embodiments relate more particularly to the detection and correction of an error of at least two bits in data stored in memory. An error of at least two bits is defined here as an error that modifies at least two bits of data. The embodiments described below search bit by bit for the first bit of error until a method for correcting one bit of error is capable of correcting the second erroneous bit. Two variants of such a method and a practical example of their implementation are described with reference to Figures 2 to 4. A device adapted to implement these embodiments is described with reference to [Fig. 1].

[0034] Furthermore, the embodiments described above are particularly suitable for use in any type of industrial market where error detection and correction in data are required. More specifically, such an error detection method can be used to: - the automotive industry, for example in the field of automotive electrification or in the field of advanced driver assistance systems (ADAS); - the industrial industry, for example in the field of green energy, in the field of infrastructure electrification, the Internet of Things (IoT) and Smart Homes, where electricity and energy consumption and data exchange are key elements; - the personal electronics industry, for example in the field of mobile telephony and the Internet of Things (IoT), as well as in the field of broadband interfaces; and - the communications equipment, computer and peripherals industry, for example in the field of infrastructure and data centers, and in the field of low Earth Orbit (LEO) satellites.

[0035] Fig. 1 is a block diagram representing, very schematically, an architecture of an example of an electronic device 100 adapted to implement an error detection and correction process according to an embodiment.

[0036] The electronic device 100 includes a processor 101 (CPU) adapted to implement various processing of data stored in memories and / or provided by other circuits of the device 100. According to one embodiment, the processor 101 is adapted to implement an error detection and correction process according to one embodiment.

[0037] The electronic device 100 further comprises various types of memory 102 (MEM), including, for example, non-volatile memory, memory volatile, and / or read-only memory. Each memory 102 is adapted to store different types of data. In one embodiment, the detection and correction methods described in relation to Figures 2 to 4 are particularly suited to processing data stored in non-volatile memories, such as flash memories, phase-change memory (PCM), magnetic RAM, resistive RAM, etc. In one embodiment, one or more of the memories 102 include a circuit dedicated to implementing error detection and correction methods.

[0038] The electronic device 100 further includes, for example, a secure element 103 (SE) adapted to process sensitive and / or secret data. The secure element 103 may include its own processor(s), its own memory(ies), etc. In one embodiment, the secure element 103 is adapted to implement an error detection and correction process, and, more particularly, in one example, the secure element 103 includes a memory comprising a circuit dedicated to implementing error detection and correction processes.

[0039] The electronic device 100 may further include interface circuits 104 (IN / OUT) adapted to send and / or receive data from outside the device 100, such as from external memory. The interface circuits 104 may also be adapted to implement a data display, for example, a display screen. According to one example, the interface circuits are adapted to implement an error detection and correction method according to one embodiment.

[0040] The electronic device 100 further comprises various circuits 105 (FCT1) and 106 (FCT2) adapted to perform different functions. By way of example, the circuits 105 and 106 may include measurement circuits, data conversion circuits, etc. In one embodiment, the circuits 105 and 106 may include a circuit adapted to implement an error detection and correction method.

[0041] The electronic device 100 further includes one or more data buses 107 adapted to transfer data between its different components.

[0042] The [Fig.2] is a block diagram illustrating an implementation method of a method 200 for detecting and correcting an error on at least two bits of binary data stored in a memory.

[0043] Herein, Data200 refers to binary data programmed on several data bits, for example, on N data bits, where N is a strictly positive integer. Each bit of the binary data is denoted Data200Bit[i], where i is an integer between 0 and Nl representing the position of the bit in the binary data Data200.

[0044] Furthermore, according to one example, the binary data Data200 is composed of a first group of bits representing the value of the binary data Data200, and a second group of bits representing an error detection and correction code (ECC, Error Correction Code) for the binary data Data200. According to one example, the first group of bits comprises P bits, P being a strictly positive integer less than or equal to N, and the second group of bits comprises Q bits, Q being a positive integer less than N. According to one example, the sum of the integers P and Q is equal to the integer N.

[0045] Furthermore, a one-bit error is defined here as an error in binary data in which only one bit of the binary data is erroneous. There are mechanisms for finding and correcting such errors that use the error detection and correction code of the binary data to directly correct the data. Such mechanisms are described below.

[0046] Similarly, an error on at least two bits is here called an error in binary data in which at least two bits of the binary data are erroneous.

[0047] The purpose of method 200 is to verify the conformity of binary data stored in memory, and more particularly to detect a fault in binary data and to correct this fault to the extent possible. A fault is defined here as an error in binary data where the number of bits it affects is not determined. A fault is, for example, detected using the error detection and correction code for binary data. Method 200 is, more particularly, adapted to detect and correct one-bit and two-bit errors in binary data. According to one embodiment, method 200 can be used in a method for detecting and correcting errors on at least three bits of binary data.

[0048] At an initial step 201 (Read data), the binary data Data200 is read from a memory.

[0049] In a step 202 (Detect fault?), following step 201, a fault detection operation is applied to the binary data Data 100. Such an operation uses, for example, error detection and correction code to detect a fault. The implementations of fault detection operations are within the grasp of a person skilled in the art and are not described in detail here. If no fault is detected (output N of step 202), the next step is step 203 (Correct Data); otherwise (output Y of step 202), the next step is step 204 (1-error correction).

[0050] At step 203, following step 202, no fault was detected in the binary data Data200, therefore the binary data Data200 can be considered correct.

[0051] At step 204, a fault was detected in the binary data Data200. As previously stated, the number of erroneous bits in the binary data Data200 is not determined. A one-bit error correction operation is applied to the binary data Data200. As an example, such an operation can be based on calculating a Hamming code, also called a Hamming error-correcting code. Implementations of one-bit error correction operations are within the scope of a person skilled in the art and are not described in detail here.

[0052] If the 1-bit correction attempt succeeds (output Y of step 204), the data is now corrected, the next step is step 203, otherwise (output N of step 204) the next step is a step 204 (1-error correction).

[0053] According to one variant, steps 202 and 204 can be combined. According to another variant, step 202 may not take place.

[0054] In step 203, following step 204, the binary data Data200 has been corrected in step 204, the binary data Data200 is made equal to the corrected binary data Data200, and the binary data Data200 can therefore be considered as correctly corrected and therefore as correct.

[0055] At a step 205 (Invert bit i of data), successive to step 204, a fault is always detected at the level of the binary data Data200. The modified binary data obtained at step 204 is no longer considered, the initial binary data Data200 is used.

[0056] In step 205, the value of a bit Data200Bit[i] of rank i of the binary data Data200 is modified to obtain a modified binary data Data200Modif[i]. According to an example, for the first implementation of step 205, the integer i is equal to zero.

[0057] In a step 206 (1-error correction), subsequent to step 205, a 1-bit error correction attempt operation is applied to the modified binary data Data200Modif[i]. This 1-bit error correction operation is of the same type as that of step 204.

[0058] Furthermore, in step 206, after the attempted correction operation, a fault detection operation, of the type of the operation in step 202, is implemented on the corrected modified binary data Data200Modif[i]. If no fault is detected (output N of step 206), this indicates that the attempted correction was successful and the next step is step 203; otherwise (output Y of step 206), the next step is step 207 (Next i).

[0059] At step 203, following step 206, no fault was detected in the modified binary data Data200Modif[i] corrected in step 206, the binary data Data200 is made equal to the modified binary data Data200Modif[i] corrected, and the binary data Data200 can therefore be considered as correctly corrected and therefore as correct.

[0060] At step 207, a fault is still detected in the binary data Data200. This means that the bit modified in step 205 had a correct initial value. Therefore, it is necessary to try modifying the value of another bit in the binary data Data200. for this a new integer i is chosen, for example by incrementing the previously chosen value of i by one unit.

[0061] At step 207, it is also verified that all values ​​of the integer have been tested. For example, if the integer i is incremented at step 207, then it is verified that the integer i does not exceed the number Nl, which is the position of the last bit of the binary data Data200. If all values ​​of the integer i have been tested (output Y of step 207), the next step is step 208; otherwise (output N of step 207), the next step is step 205.

[0062] In step 205, which follows step 207, the value of a bit Data200Bit[i] of rank i, i having been modified in step 207, of the binary data Data200 is modified to obtain a modified binary data Data200Modif[i]. The correction operation of step 206 is then implemented.

[0063] In step 208, all bits of the binary data Data200 were modified at least once, and the correction operation implemented in step 206 could not provide corrected binary data. This means that the fault detected in the binary data in step 202 affects more data bits. The binary data Data200 is therefore considered uncorrectable by using method 200 alone.

[0064] One advantage of the error detection and correction method embodiment 200 is that it allows for the reliable correction of a two-bit error in binary data. Other advantages are described with reference to Figures 3 and 4.

[0065] Furthermore, it should be noted that a method of the type of method 200 can be used in a method for detecting and correcting an error on at least three bits.

[0066] Fig. 3 represents, schematically and partially in block form, a practical example of a device 300 for implementing the process 200 described in relation to Fig. 2.

[0067] According to one example, the device 300 is adapted to receive a Data300 and its error detection and correction code ECC300, both stored in a memory 350. According to one example, in the memory 350, the binary Data300 and its error detection and correction code ECC300 are stored as two parts of the same data word.

[0068] According to one example, the device 300 includes a first register Reg301 (Data reg) adapted to store the Data300, and a second register Reg302 (ECC reg) adapted to store the ECC300 code.

[0069] According to one example, the device 300 further comprises two circuits, InvBit301 (Inverse Selected Bit) and InvBit302 (Inverse Selected Bit), adapted to invert a bit of a data word. The InvBit301 circuit is adapted to invert a bit of the data Data300 stored in the Reg301 register, the position of the bit to be inverted being selected by a SelDataBit300 control signal. The InvBit302 circuit is adapted to invert a bit of the code ECC300 is stored in the Reg302 register, the position of the bit to be inverted being selected by a SelECCBit300 control signal.

[0070] According to one example, the device 300 further comprises two multiplexers, Mux301 and Mux302, each comprising two input terminals, one control terminal, and one output terminal. According to one example, the multiplexer Mux301 receives, on a first input terminal, the binary data Data300, and, on a second input terminal, data provided by the InvBit301 circuit. A control terminal of the multiplexer Mux301 receives a SelMux300 control signal. According to another example, the multiplexer Mux302 receives, on a first input terminal, the ECC300 code, and, on a second input terminal, data provided by the InvBit302 circuit. A control terminal of the multiplexer Mux302 receives a SelMux300 control signal. The Mux301 and Mux302 multiplexers allow you to define whether a 1-bit error correction operation is implemented on the Data300 data and the ECC300 code or on a modified version of the Data300 data and the ECC300 code.

[0071] According to one example, the device 300 further comprises a control circuit FSM300 (FSM). The FSM300 circuit is, for example, adapted to provide the SelDataBit 300, SelECCBit300, and SelMux300 control signals. The FSM300 circuit can, moreover, be adapted to provide a WaitSt300 signal indicating that the device 300 is in a wait state, and a SeqSt300 signal indicating that a 2-bit error search is in progress. According to one example, the FSM300 control circuit is a state machine.

[0072] According to one example, the device 300 further includes an l-errorCorr300 stage for detecting and correcting a 1-bit error.

[0073] According to one example, the l-errorCorr300 stage includes a Calc301 circuit adapted to calculate a NewECC300 error detection and correction code from the data supplied at the output of the Mux301 multiplexer. As a reminder, this data is either equal to the binary data Data300, or equal to a modified version of binary data Data300 in which one bit has been inverted.

[0074] According to one example, the l-errorCorr300 stage further includes an XOR (Exclusive OR) logic gate XOR301 used to compare the ECC300 code and the NewECC300 code. In other words, the XOR301 gate has two input terminals, one receiving the ECC300 code and the other the NewECC300 code. The XOR301 gate provides, as output, a comparison data Synd300, also called Synd300 syndrome, which is the result of applying the bitwise XOR logic gate to the two inputs.

[0075] According to one example, the l-errorCorr300 stage further comprises Q comparators CmpECC300[0] to CmpECC300[Q1] and Q XOR (Exclusive OR) logic gates XOR302[0] to XOR302[Q-1], Each comparator CmpECC300[0], ..., CmpECC300[Q1] compares the Synd300 data to a constant reference value. The result of this comparison is then used by the XOR302[0], ..., XOR302[Q-1] gate to the corresponding bit of the data output from the Mux302 multiplexer, in order to potentially invert and thus correct the corresponding bit of the data. As a reminder, this data is either the ECC300 code or a modified version of the ECC300 code in which one bit has been inverted. In other words, each XOR302[0], ..., XOR302[Q-1] gate has two input terminals: one receiving a bit of the output data from the Mux302 multiplexer, and the other receiving a bit resulting from the comparison between the Synd300 data and the constant reference value.

[0076] According to one example, the l-errorCorr300 stage further comprises P comparators CmpData300[0] to CmpData300[P1] and P XOR logic gates XOR303[0] to XOR303[P1]. Each comparator CmpData300[0], ..., CmpData300[P1] compares the Synd300 data to a constant reference value. The result of this comparison is then used by the XOR303[0], ..., XOR303[P-1] gate, along with the bit of the same position from the data supplied as output from the Mux301 multiplexer, in order to possibly invert and thus correct the corresponding bit of the data. As a reminder, this data is either equal to the binary data Data300 or to a modified version of the Data300 data in which one bit has been inverted. In other words, each XOR303[0], ..., XOR303[P-1] gate includes two input terminals, one receiving the output data from the Mux301 multiplexer and the other a bit resulting from the comparison between the Synd300 data and the constant reference value.

[0077] According to one example, the l-errorCorr300 stage further includes an OR type logic gate OR300 comprising P+Q inputs each connected to one of the comparators CmpECC300[0], ..., CmpECC300[Ql], CmpData300[0], ..., CmpData300[Pl]. The OR300 gate further includes an output terminal providing an OBC300 signal allowing verification of whether a data bit has been inverted and thus corrected.

[0078] According to one example, the l-errorCorr300 stage further includes a Verif300 verification circuit which takes as input the OBC300 signal and the Q-bit output signal of the XOR301 gate. If the OBC300 signal is equal to zero and if the output signal of the XOR gate is not zero then the data supplied at the output of the multiplexers Mux301 and Mux302 is erroneous data.

[0079] The operation of device 300 is as follows.

[0080] When steps 202 and 204 are implemented, the multiplexers Mux301 and Mux302 directly provide the data received from memory 350, i.e., the Data300 data and the ECC300 code. The Calc301 calculation circuit calculates the NewECC300 code from the Data300 data, and the XOR301 gate uses it to obtain the comparison data Synd300. This comparison data Synd300 It only includes 1 bits at positions where the ECC300 code and the NewECC300 code are different. The XOR302[0] to XOR302[Q-1] and XOR303[0] to XOR303[P-1] gates are then used to modify the value of a bit in the ECC300 code or the Data300 data. The bits provided as outputs from XOR302[0] to XOR302[Q-1] and XOR303[0] to XOR303[P-1] allow for the formation of a corrected code and data.

[0081] When steps 205 to 207 are implemented, the multiplexers Mux301 and Mux302 provide a modified one-bit version of the ECC300 code or the data300. The Calc301 calculation circuit calculates the NewECC300 code from the data300, or its modified version as appropriate, and the XOR301 gate uses it to obtain the comparison data Synd300. This comparison data Synd300 includes 1 bits only at the positions where the ECC300 code, or its modified version as appropriate, and the NewECC300 code are different. The gates XOR302[0] to XOR302[Q-1] and XOR303[0] to XOR303[P-1] are then used to modify the value of one bit of the ECC300 code or the data300. The bits supplied as output from XOR302[0] to XOR302[Q-1] and XOR303[0] to XOR303[P-1] allow a code and corrected data to be formed.

[0082] One advantage of such an implementation is that it allows limiting the number of additional bits stored in memory, the number of logic gates added.

[0083] Fig. 4 represents, schematically and partially in block form, another practical example of a device 400 for implementing the process 200 described in relation to Fig. 2.

[0084] Device 400 is very similar to Device 300 described in relation to [Fig. 4]. The features common to Devices 300 and 400 are not described again in detail here. Only the differences between Devices 300 and 400 are highlighted.

[0085] Like device 300, device 400 comprises: - the Reg301 (Data reg) and Reg302 (ECC reg) registers; - the InvBit301 (Inverse Selected Bit) and InvData302 (Inverse Selected Bit) circuits; - the Mux301 and Mux 302 multiplexers; and - the FSM300 (FSM) control circuit.

[0086] According to one example, the difference between devices 300 and 400 lies in the stage for detecting and correcting a 1-bit error. Device 400 includes a 1-bit error detection and correction stage l-errorCorr400 which further includes a means for automatically calculating a corrected error detection and correction code.

[0087] According to an example, like the l-errorCorr300 stage, the l-errorCorr400 stage further comprises: - the Calc301 calculation circuit; - the P+Q comparators CmpECC300[0] to CmpECC300[Ql] and CmpData300[0] to CmpData300[Pl]; - the P+Q logic gates of type XOR XOR302[0] to XOR303[Q-1], and XOR303[0] to XOR303[Pl]; - the OR300 type OU door; and -the Verif300 verification circuit.

[0088] According to one example, the automatic calculation means comprises a Reg401 register, two multiplexers Mux401 and Mux402, and an XOR (exclusive OR) logic gate XOR401. The Reg401 register is adapted to store the expected value of the ECC300 code, this value being provided by the Calc301 calculation circuit. The Mux401 multiplexer comprises two input terminals and one output terminal. The first input terminal is adapted to receive the NewECC300 code, and the second input is adapted to receive the data stored in the Reg401 register. The output of the Mux401 multiplexer is connected, preferably connected, to an input of the XOR401 gate.

[0089] The second multiplexer, Mux402, is adapted to receive as input various comparison data of the type of comparison data Synd300, each of these data representing the comparison data obtained when a bit of the ECC300 code is modified or when a bit of the Data300 data is modified. The correct value is chosen by a DeltaECCSE1400 signal provided by the FSM300 control circuit. This value is chosen according to the bit that is modified by the InvBit301 or InvBit302 circuits.

[0090] This embodiment makes it possible to avoid a step of calculating the comparison data Synd300.

[0091] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0092] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method (200) for detecting and correcting an error in at least two bits of binary data (Data200; Data300) stored in a memory (102; 350), comprising the following successive steps: (a) modifying (205) the value of one bit of said binary data (Data200; Data300); (b) implementing (206) a mechanism for correcting an error in one bit of said modified binary data (Data200Modif[i]; Data300Modif[i]); (c) if a fault is still detected, repeating step (a) (205) by modifying the value of another bit of said binary data (Data200; Data300).

2. A method according to claim 1, wherein the method (200) further comprises, after step (b), a step (d) (203) during which, if no fault is detected, the value of said binary data (Data200; Data300) is made equal to the value of said modified binary data (Data200Modif[i]; Data300Modif[i]), and is considered corrected.

3. A method according to claim 1 or 2, wherein the method further comprises, prior to step (a), a step (e) (204) of implementing said one-bit error correction mechanism of said binary data (Data200; Data300).

4. A method according to claim 3, wherein the method further comprises, after step (e), a step (f) (203) during which, if no fault is detected, the value of said binary data (Data200; Data300) is made equal to the value of said binary data obtained in step (e), and is considered corrected.

5. A method according to any one of claims 1 to 4, wherein the method further comprises, after step (c), a step (g) (208) during which if all bit values ​​of said binary data (Data200; Data300) have been changed at least once and a fault is still detected, then said binary data (Data200; Data300) is considered uncorrectable.

6. A method according to any one of claims 1 to 5, wherein said one-bit error correction mechanism uses a Hamming code.

7. A method according to any one of claims 1 to 6, wherein said binary data comprises bits representing an error detection and correction code (ECC300) and bits representing a value of said binary data (Data200; Data300).

8. Method according to claims 6 and 7, wherein said one-bit error correction mechanism comprises a calculation step of a comparison data (Synd300) of said detection and correction code and a recalculated code (NewECC300) from said value of said binary data (Data200; Data300).

9. A method according to claims 6 and 7 or claim 8, wherein said correction mechanism comprises a means for automatically calculating a corrected error detection and correction code.

10. Device for detecting and correcting an error on at least two bits of a binary data (Data200; Data300) stored in a memory (102; 350), adapted to implement a method (200) comprising the following successive steps: (a) modify (205) the value of one bit of said binary data (Data200; Data300); (b) implement (206) a mechanism for correcting an error on one bit of said modified binary data (Data200Modif[i]; Data300Modif[i]); (c) if a fault is still detected, repeat step (a) (205) by modifying the value of another bit of said binary data (Data200; Data300).

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