Injection-locked digital oscillator

Abstract

Injection-Locked Digital Oscillator This description relates to an injection-locked digital oscillator (2). An adder (100) adds the first and second digital words (OP2, OP1) and provides a third digital word (RES) as a result, the words being N bits long, with N an integer strictly greater than 1. A register (102) updates the second word from the third word (RES) at each period of a clock signal (clk). A first circuit (200) receives a reference signal (REF) at a natural frequency of one output bit (OUT), and a reference increment, inc_ref. The first circuit calculates a first value (valref) that is selectively equal to and less than the reference increment inc_ref, depending on at least one state of the reference signal.The first circuit provides the first word at least in part by summing the first value and a positive control number, P, the output bit being a bit from the second word. Figure for the abbreviation: Fig. 2.

Description

Title of the invention: Digital oscillator with injection locking. Technical field

[0001] The present description relates generally to electronic circuits. Previous technique

[0002] More and more applications are using neural computing.

[0003] Digital circuits based on Von-Neummann architectures implementing neural computing are known. However, the number of computations per unit of time that these known circuits can perform is limited by memory access requirements, which are also energy-intensive.

[0004] To overcome the limitations of these known digital circuits, known analog or mixed-signal circuits implement neural computing in the time domain. Unlike known analog circuits, which use the amplitude of an analog quantity (voltage or current) as the information vector, in the time domain, the information vector is a time-domain quantity (delay, frequency, phase, duty cycle). This provides greater robustness to noise compared to an analog or mixed-signal circuit using an amplitude as the information vector. Furthermore, known analog or mixed-signal circuits in the time domain can operate with lower supply voltages than known analog or mixed-signal circuits using an amplitude as the information vector, thereby reducing power consumption.

[0005] Several approaches are known for implementing neural circuits composing a neural network for the implementation of neural computing in the time domain.

[0006] A first approach is based on pulse density modulation. In this first approach, the information, for example the result of the neural computation performed by a neuron, is encoded by the density of a pulse train, that is, by the number of pulses per unit of time in the pulse train. An example of such an approach is, for example, described in the paper by A. Valentian et al., entitled "Fully Integrated Spiking Neural Network with Analog Neurons and RRAM Synapses" and presented in 2019 at the IEEE International Electron Devices Meeting (IEDM), San Francisco. However, known analog neural circuits based on pulse density modulation for computation in the time domain are sensitive to PVT (Process, Voltage, Temperature) variations.

[0007] A second approach is based on pulse width modulation (PWM). In this second approach, data is encoded by the width, or duration, of a pulse which serves as a command to an integrator circuit accumulating a quantity encoding the weight associated with this data.

[0008] Known analog neural circuits based on pulse-width modulation for time-domain computing use a capacitor to implement the accumulation function. The voltage across the capacitor is then converted into a pulse whose width is proportional to the capacitor voltage. An example of such an analog neural circuit is described, for instance, in the article by M. Yamaguchi, G. Iwamoto, Y. Nishimura, H. Tamukoh, and T. Morie, entitled "An Energy-Efficient Time-Domain Analog CMOS Binary Connect Neural Network Processor Based on a Pulse-Width Modulation Approach," published in IEEE Access, vol. 9, pp. 2644–2654, 2021. However, these known analog neural circuits are limited to implementations of binary neural networks, which restricts the accuracy of the computations.Furthermore, the implementation of a neural network based on such analog neuron circuits is sensitive to PVT variations, which lead to mismatches between the neuron circuits.

[0009] Digital neural circuits based on pulse-width modulation for time-domain computing are also known. Examples of such neural circuits are, for example, described in the article by A. Sayal, SST Nibhanupudi, S. Fathima and JP Kulkami, entitled "A 12.08-TOPS / W Ail-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing" and published in IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 60-75, Jan. 2020, and in the article by M. Mohey, M. Kosunen, J. Ryynânen and M. Andraud, entitled "Toward All-Digital Time-Domain Neural Network Accelerators for In-Sensor Processing Applications" and published in 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), Aalborg, Denmark, 2023, pp. 1-6.One drawback of pulse-width modulation-based digital neural circuits for time-domain computation is that, when calculating a weighted sum of input data where each input is multiplied by its associated weight, the multiplications are performed sequentially, thus limiting the computational speed. Furthermore, these known digital neural circuits are limited to implementations of binary neural networks, which restricts the accuracy of the calculations.

[0010] A third approach is based on phases.

[0011] For example, known phase-based neural circuits for time-domain computation use an oscillator whose oscillations are switched on or off by input data from a MAC (Multiply And) operation Accumulate (multiplication and accumulation), and thus the frequency is controlled by the weight applied to the data. The oscillator output drives a counter that acts as a phase accumulator. However, in such neural circuit examples, besides the need for a digital-to-time converter to convert the input data into an oscillator oscillation duration, the weight-data pairs used to calculate the weighted sum of the input data are applied sequentially, which limits the computation speed. The article by Y. Toyama, K. Yoshioka, K. Ban, S. Maya, A. Sai, and K. Onizuka, titled "An 8-Bit 12.4 TOPS / W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators" and published in the IEEE Journal of Solid-State Circuits, vol. 54, no. 10, pp. 2730–2742, Oct. 2019, describes an example of a such a neural circuit.

[0012] As another example, known phase-based neural circuits for time-domain computation use an analog injection-locked oscillator (ILO) to implement a weighted sum of several phase shifts, as is the case, for example, in patent EP 4002698 AL. However, the analog implementation of these oscillators leads to matching errors when implementing a neural network. Furthermore, these analog injection-locked oscillators are sensitive to noise from active components, which limits the signal-to-noise ratio. Summary of the invention

[0013] There is a need to overcome all or part of the drawbacks of known neural circuits for computation in the time domain.

[0014] One embodiment overcomes all or part of the drawbacks of known neural circuits for computation in the time domain.

[0015] For example, an embodiment overcomes all or part of the disadvantages of known analog injection-locked oscillators and provides for a digital injection-locked oscillator.

[0016] For example, one embodiment provides a phase shifter based on the proposed digital injection-locked oscillator. Such a digital phase shifter can, for example, be used to convert digital data into a phase shift, for example, as input to a phase-based neural network.

[0017] For example, one embodiment provides a phase adder based on the proposed digital injection-locked oscillator. Such a phase adder allows the implementation of a phase-weighted sum of input signals to the adder.

[0018] For example, one embodiment provides a neural circuit based on the proposed digitally injected latching oscillator. For example, in such In a neural circuit, the digital injection latched oscillator allows the implementation of a phase-weighted sum of input signals from the neuron.

[0019] For example, one embodiment provides a neural network where the neural circuits of the network are each based on the proposed digital injection locking oscillator.

[0020] One embodiment provides a digital injection-locked oscillator comprising: an adder configured to add a first N-bit digital word with a second N-bit digital word and to provide a result of the addition in the form of a third N-bit digital word, with N an integer strictly greater than 1; a register configured to update the second digital word from the third digital word at each period of a clock signal; a first circuit configured for: - receive a reference signal at a reference frequency equal to a natural frequency of one output bit of the oscillator, and a reference increment, inc_ref, - calculate a first value selectively equal to the reference increment inc_ref and minus the reference increment inc_ref as a function of at least one binary state of the reference signal, and - provide the first digital word determined at least in part by summing the first value and a positive control number, P, of the oscillator, the output bit being a bit of the second word.

[0021] According to one embodiment, the output bit is the most significant bit of the second numeric word.

[0022] According to one embodiment, the first circuit is configured to receive the output bit from the oscillator, and so that the first value is equal to the reference increment inc_ref if a result of an XOR between the output bit and the reference signal is in a first binary state and less the increment inc_ref if the result of the XOR is in a second binary state.

[0023] One embodiment provides a digital phase shifter comprising the oscillator as defined above, in which the number P belongs to a range of values ​​centered on a number PO and of width equal to twice the absolute value of the reference increment incref, PO being equal to 2L.(Fref / Fclk), with L an index of the output bit in the second digital word, Fref the reference frequency and Fclk the frequency of the clock signal, the index L having a value in a range from 1 to N.

[0024] According to one embodiment, the control number P determines a value of a phase shift of the output bit relative to the reference signal.

[0025] According to one embodiment, the first digital word is equal to the sum of the first value and the control number P of the oscillator.

[0026] According to one embodiment, the output bit is phase-shifted by q> relative to the reference signal, with: PP f tp = y + if inc_ref is of a first polarity' and pp <p= - 7 + ir2^-- si inc_ref est d’une deuxième polarité opposée à la première polarité-

[0027] One embodiment provides a digital phase adder comprising: the oscillator as defined above, in which: The first circuit comprises K second Lock_i circuits, with i an integer index from 1 to K and K an integer greater than or equal to 1, each second Lock_i circuit being configured to: - receive the output bit, an increment inc_i and an injection signal S_i at a frequency equal to the reference frequency with a phase shift <p_i par rapport au signal de référence, et - provide a second value out_i equal to the increment inc_i if the result of an XOR between the output bit and the injection signal S_i is in a first binary state, and minus the increment inc_i otherwise; and the first circuit is configured to provide the first digital word equal to the sum of the order number P, the first value and the K second values ​​val_i.

[0028] According to one embodiment, the command number P is equal to 2L.(Fref / Fclk), with L an index of the output bit in the second digital word, Fref the reference frequency and Fclk the frequency of the clock signal, the index L having a value in a range from 1 to N.

[0029] According to one embodiment, the output bit is phase-shifted by q> relative to the reference signal, with: a • £ v'=K- A = inc ref + <p - f si A est dune première polarité, fl- V-'K, 5 *' ZZK 1 «VI • Z = - 7 + S1A has a second polarity opposite to the first polarity

[0030] One embodiment provides a neural circuit comprising a first digital phase adder as defined above, in which K is equal to Kl in the first adder, the Kl phase shifts <p_i du premier additionneur correspondent à Kl valeurs d'entrée du circuit de neurone, Kl poids w_i du circuit de neurone déterminent les Kl incréments inc_i du premier additionneur et de l'incrément de référence inc_ref du premier additionneur, et Kl est supérieur ou égal à 2.

[0031] According to one embodiment, the Kl increments inc_i of the first adder and the reference increment inc_ref of the first adder satisfy: y^i=KI .. ​​. .. -mc_i+ w_janc_t = -w_jinc_ref, with j an integer index ranging from 1 to Kl, r ri r -i | mc_ref I + , I mc_t | < And pp with II the absolute value operator, and PI the value of number P of the first adder.

[0032] According to one embodiment, the neural circuit further comprises a second digital phase adder as defined above, in which K is equal to K2 in the second adder and the output bit of the first adder corresponds to one of the K2 injection signals of the second adder.

[0033] According to one embodiment, the reference signal of the second adder has the same frequency as the reference signal of the first adder, and a phase shift between the reference signal of the first adder and the reference signal of the second adder is determined by a sign of the sum of the increments inc_i and inc_ref of the first adder, preferably so as to compensate for a phase shift introduced by the first adder.

[0034] One embodiment provides for a neural network comprising M successive layers of 600h neurons, with M an integer strictly greater than 1, and h an integer index from 1 to M and increasing from inputs to outputs of the network, in which: Each neuron is implemented by a neural circuit as defined above, where the output bit of the first adder of the neural circuit is the output bit of the neuron; The neurons in layers 600h with odd indices h all receive the same reference signal; and Each of the neurons in the 600h layers with even indices h receives a reference signal at the same frequency as the reference signal of the neurons in the 600h layers with odd indices h, but with a phase shift between these two reference signals determined by a sign of the sum of the increments inc_i and inc_ref of each of the first adders of the neurons in the layers with odd indices h.

[0035] One embodiment provides for a neural network comprising several layers of neurons, in which: Each neuron is implemented by a neural circuit as defined above; the first adders of the neurons in the network all receive the same reference signal.

[0036] One embodiment provides a neural network comprising several neurons, each implemented by a neural circuit as defined above. In each neural circuit, each of the Kl injection signals from the first adder is an output bit of another neural circuit in the network.

[0037] One embodiment provides a ring oscillator comprising Q digital oscillators, with Q an integer strictly greater than 1, preferably greater than 2, in which: one of the Q digital oscillators is an injection-locked digital oscillator as defined above in which the first value is equal to the reference increment inc_ref of that injection-locked digital oscillator when the reference signal of that injection-locked digital oscillator is in a first binary state, and less the reference increment inc_ref otherwise; Each of the other Ql digital oscillators is: - either an injection-locked digital oscillator as defined above in which the first value is equal to the reference increment inc_ref of this injection-locked digital oscillator when the reference signal of this injection-locked digital oscillator is in a first binary state, and less the reference increment inc_ref otherwise, - either a free-oscillating digital oscillator comprising: * an adder configured to add a first N-bit digital word with a second N-bit digital word and to provide a result of the addition in the form of a third N-bit digital word; * A register configured to update the second digital word from the third digital word at each period of the clock signal, an output bit of this free-oscillating oscillator being a bit of the third word and the first digital word being a control word of this free-oscillating oscillator, wherein the Q digital oscillators are connected in a ring one after the other, the register of each digital oscillator being configured to be reset by a state of the output bit of the preceding digital oscillator in the ring. Brief description of the drawings

[0038] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0039] [Fig.1] represents an example of an embodiment of a digital oscillator;

[0040] [Fig. 2] represents an example of an embodiment of an oscillator with digital injection locking, based on the digital oscillator of [Fig.l];

[0041] [Fig.3] represents an example of an embodiment of a phase adder based on the oscillator of [Fig.2];

[0042] [Fig.4] represents an example of an embodiment of a neural circuit based on the phase adder of [Fig.3];

[0043] [Fig.5] represents an example of an embodiment of a neural network;

[0044] [Fig.6] represents another example of an embodiment of a neural network;

[0045] Figure 7 represents another example of a neural circuit; and

[0046] [Fig.8] represents a ring oscillator based on the oscillator of [Fig.2]. Description of the implementation methods

[0047] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0048] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, although the digital injection-locked oscillator proposed in this description is suitable and advantageous for implementation in a neural circuit or a phase-based neural network for time-domain computation, the proposed digital injection-locked oscillator can be used in applications other than neural computing, providing the same advantages, for example, when it implements a phase adder or a phase shifter. As further examples of applications, the proposed digital injection-locked oscillator can be used to implement a digital-to-time converter, a bandpass filter, or a phase-to-digital converter.

[0049] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0050] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0051] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0052] In this description, unless otherwise indicated, the expression "going from a first value to a second value" means going from the first inclusive value to the second inclusive value.

[0053] [Fig. 1] represents an example of an embodiment of a digital oscillator 1. As will be explained in more detail in relation to [Fig. 2], this oscillator 1 enables the implementation of a digital injection locking oscillator.

[0054] The digital oscillator 1 includes a digital circuit 100 configured to calculate the sum of an N-bit digital signal OP1 and an N-bit digital signal OP2, and to provide an N-bit digital signal RES corresponding to the result of this sum. The signals OP1, OP2, and RES are therefore N-bit digital words, each encoding a value. N is an integer strictly greater than 1, for example, greater than 10. The circuit 100 is, for example, called an N-bit adder.

[0055] The oscillator 1 further includes an N-bit register 102. The register 102 is controlled by a clock signal clk at a frequency Fclk. The register 102 is configured to update the OP1 signal from the RES signal at each period of the clk signal, for example, at the beginning of each period of the clk signal corresponding, for example, to a rising edge of the clk signal. Between two successive updates, the register 102 stores the OP1 signal, or, in other words, maintains the OP1 signal at its current value.

[0056] For example, register 102 includes a data input D configured to receive the output word RES from adder 100, a synchronization input CK configured to receive the signal clk, and an output Q configured to provide the signal OP1. As an example, register 102 includes N D-type flip-flops, each flip-flop receiving one bit of the RES signal and providing a corresponding bit of the OP1 signal.

[0057] The combination of adder 100 and register 102 forms a phase accumulator.

[0058] Oscillator 1 provides an output bit OUT. This OUT bit corresponds to a bit of the OP1 signal. For example, calling the bits of the OP1 signal OPln, with n an integer index from 1 to N increasing towards the most significant bits of the OP1 signal, the OUT signal is the OPln bit with index n equal to L, with L an integer belonging to the range from 1 to N. Thus, in [Fig. 1], by way of illustration, the OUT bit of the OP1 signal is represented as provided by register 102.

[0059] Preferably, L is equal to N, or, in other words, the output OUT bit corresponds to the most significant bit of the word OP1.

[0060] The oscillator 1 also receives a control number P. The number P is preferably positive, so that the number P is added, by the adder 100, to the number OP1. As another example, the number P is negative and the adder 100 performs a subtraction of the number P from the number OP1, or, in other words, the number P is positive and the operation performed by the adder 100 is a subtraction. In this description, an adder is a circuit configured to add or subtract two operands it receives. The number P is supplied to oscillator 1 as a digital signal, or digital word, of N bits. The word OP2 is determined at least in part by the number P. More specifically, in the example in [Fig. 1], the word OP2 is equal to the number P. For example, in [Fig. 1], the word OP2 encodes the number P.

[0061] It can be shown that the FO frequency of the OUT bit is defined by the following equation:

[0062] [Math.l] F0 = ÿpclk

[0063] Preferably, P and L are chosen so that F0 is less than Fclk / 2, from which it follows that, preferably, P is chosen less than 2L*.

[0064] When the index L of the OUT bit in the word OP1 is equal to N, that is to say when the OUT bit is the most significant bit of the word OP1, the frequency FO of the OUT bit is therefore defined by the following equation:

[0065] [Math.2] F0 = ÿfclk

[0066] Thus, choosing the value P allows the value of the frequency F0 of the OUT bit to be modified. The frequency F0 is, for example, called the natural frequency of oscillator 1.

[0067] Since oscillator 1 is not, in [Fig.1], locked in injection, this oscillator 1 is, for example, called a free-oscillating digital oscillator.

[0068] [Fig.2] represents an example of an embodiment of a digital injection locking oscillator 2, based on the digital oscillator 1 of [Fig.1].

[0069] Oscillator 2 includes oscillator 1. However, compared to the example in [Fig.1] where the word OP2 receives the number P, i.e. the N-bit digital word encoding the number P, in the injection-locked oscillator 2, the word OP2 is provided by a circuit 200, from the number P. In [Fig.2], the circuit 200 is delimited by dashed lines.

[0070] Circuit 200 allows oscillator 2 to be locked by injection.

[0071] Circuit 200 enables injection locking by providing the OP2 signal so that it corresponds to the number P to which a reference increment inc_ref is selectively added or subtracted on the basis at least of the binary state of a reference signal REF at a reference frequency Fref.

[0072] In the circuit 200 of the example in [Fig. 2], the reference increment inc_ref is selectively added to or subtracted from a reference frequency Fref of a reference signal REF at a rate determined by the binary state of the OUT bit. In other words, in the circuit 200 of the example in [Fig. 2], to obtain the word OP2, the reference increment inc_ref is selectively added to or subtracted from the number P based on The binary state of a signal is determined by the reference signal REF and the OUT bit. Thus, in the example in [Fig.2], the word OP2 is determined by the control number P, the reference frequency Fref, the reference increment inc_ref and the OUT bit output of oscillator 2.

[0073] For example, circuit 200 in [Fig. 2] is configured to receive the OUT bit, the REF signal at frequency Fref, and the reference increment inc_ref. Circuit 200 then calculates, or determines, a value valref. The value valref is equal to the increment inc_ref if the result OREF of a Boolean XOR operation between the REF signal and the OUT bit is in a first binary state, and the value valref is equal to minus the increment inc_ref (-inc_ref in [Fig. 2]) otherwise, that is, when the result OREF of this XOR operation is in a second binary state. Circuit 200 then provides the OP2 signal, determined at least in part by a sum between the number P and the value valref. In the example in [Fig. 2], the word OP2 is equal to the sum of the number P and the value valref.Preferably, the increment inc_ref and the value valref are multi-bit digital signals, for example N bits, i.e., digital words encoding the value of the increment inc_ref and the value valref. As an example, the reference increment valref is positive, although in other examples, the increment valref may be negative.

[0074] By way of example, in circuit 200 of [Fig.2], to generate the value valref, circuit 200 includes a logic gate 202 implementing an XOR operation, a selection circuit 204 and a digital adder 206.

[0075] Gate 202 receives the REF signal and the OUT bit, and provides the OREF binary signal resulting from the XOR between the REF and OUT signals.

[0076] The selection circuit 204 provides the value valref equal to the increment inc_ref when the OREF signal is in a first binary state, for example a first binary state corresponding to logic T, and equal to minus the increment inc_ref when the OREF signal is in a second binary state, for example a second binary state corresponding to logic '0'. By way of example, the circuit 204 is a multiplexer receiving the increment inc_ref and minus the increment inc_ref ("-inc_ref" in [Fig. 2]), and providing the value valref, the multiplexer 204 being controlled by the OREF signal.

[0077] The adder 206 is configured to receive the value valref, to add it to the number P, and to provide the signal OP2 resulting from this addition.

[0078] In oscillator 2, after several periods of the REF signal, oscillator 2 locks. The frequency of the OUT bit becomes equal to the reference frequency Fref, but the OUT signal is out of phase with the REF signal. The value of this phase shift depends on the value of the reference increment inc_ref, and on the difference between the frequency Fref and the natural frequency F0 of oscillator 2.

[0079] This locking behavior is observed when the frequency Fref has a value belonging to a locking range of the oscillator 2. This locking range has a width (or extent) AF defined by the following equation:

[0080] [Math.3] a r-1 Af r- .11 Ar — JtCIK

[0081] In equation [Math. 3] above, L is equal to N when the OUT bit corresponds to the most significant bit of the word OP1.

[0082] The locking range is centered on the natural frequency F0 of the oscillator.

[0083] In the particular case where the number P is equal to a value PO such that the frequency If the natural frequency F0 of oscillator 2 is equal to the injection frequency Fref, once oscillator 2 is locked, the phase shift between the OUT signal and the REF signal has an absolute value of n / 2 and a sign that depends on the sign of the reference increment inc_ref. For example, taking the example from [Fig. 2] where the value valref is equal to the reference increment inc_ref if the OREF bit is at T', this phase shift is equal to n / 2 when the increment inc_ref is positive, and to -11 / 2 when the increment inc_ref is negative. For the natural frequency F0 and the reference frequency Fref to be equal, the number P is equal to the value PO defined by the following equation:

[0084] [Math.4] pn _ Def qL Fdk~

[0085] When the index L of the OUT bit in the word OP1 is equal to N, that is to say when the OUT bit is the most significant bit of the signal OP1, the value PO is therefore defined by the following equation:

[0086] [Math.5] pn _ nN rv “ Fclk

[0087] Once the oscillator 2 is locked to the frequency Fref, the phase shift between the bit OUT and the signal REF can be modified by changing the natural frequency F0 of the oscillator 2, that is to say by changing the value of the number P relative to the value PO for which the natural frequency F0 of the oscillator 2 is equal to the reference frequency Fref.

[0088] Thus, the oscillator 2 can be used as a digital phase shifter controlled by the digital word P. In other words, the oscillator 2 can be used as a digital-phase-shift converter configured to convert the digital word P into a corresponding phase shift between the OUT signal and the reference signal REF.

[0089] By way of example, such a digital-to-phase-shift converter can be used as the input to a phase-based neural network to implement neural computing, so as to convert a digital input data of the network into a corresponding phase shift. The data to be converted determines the command word P and is converted into a corresponding phase shift of the OUT signal relative to the Fref signal.

[0090] For example, the phase shift q> of the OUT signal with respect to the REF signal is defined by the following relations:

[0091] [Math.6] PP tp = f + if inc_ref > 0

[0092] [Math.7] . p-po ■ • rn tp = - 2 + 7T2*iïïcf"[ S1 mc_ref < 0

[0093] Equations [Math. 6] and [Math. 7] given above apply to the example in [Fig. 2] where gate 202 is an exclusive OR gate, valref receives inc_ref when the output of gate 202 is active (at '1'), and valref receives -inc_ref when the output of gate 202 is inactive (at '0'). However, a person skilled in the art can generalize equations [Math. 6] and [Math. 7] above to other examples. For example, in the case where gate 202 is an exclusive OR gate, valref receives -inc_ref when the output of gate 202 is active (at '1'), and valref receives inc_ref when the output of gate 202 is inactive (at '0'), for example because an inverter is placed between the output of gate 202 and the control input of circuit 204, then the sign of the fixed phase shift of value TI / 2 is positive when inc_ref is negative, and negative when inc_ref is positive. Thus, more generally, the equation [Math.6] is valid when inc_ref is of a first polarity and equation [Math. 7] is valid when inc_ref is of a second polarity opposite to the first, this validity depending further on how the circuit 204 is controlled by the output of gate 202. .

[0094] For example, it follows from the two relations above that the range of variation of the value of the number P which allows obtaining a range of variation of the phase shift q> of width TI is centered on PO and has an extent AP defined by the following relation:

[0095] [Math. 8] AP - 2,|inc_ref L with 11 the absolute value function

[0096] For example, to obtain a phase shift q> having a value within a range from 0 to II when the increment inc_ref is positive and a value within a range from -Il to 0 when the increment inc_ref is negative, the number P has a value within a range from a value Pmin to a value Pmax defined by the following relations:

[0097] [Math.9] Pmin = PO- |inc_ref|

[0098] [Math. 10] Pmax = PO + |inc_ref|

[0099] The gain G of the phase shifter 2, which corresponds to the slope of variation of the phase shift q> as a function of the number P, is defined by the following relation:

[0100] [Math. 11] c — n 2jnc_tef

[0101] Fig. 3 represents an example of an embodiment of a 3-phase adder.

[0102] The phase adder 3 includes many elements in common with the injection-locked oscillator 2, and only the differences between these two devices 2 and 3 are highlighted here.

[0103] The phase adder 3 includes the oscillator 1 and a circuit 200 providing the digital word OP2 at least in part on the basis of the sum of the value valref and the number P, the value valref being selectively equal to the increment inc_ref and to less the increment inc_ref depending at least on the reference signal REF.

[0104] In [Fig.3], as in [Fig.2], the value valref is equal to the increment inc_ref if the result OREF of an exclusive OR between the bit OUT and the signal REF is in a first binary state and less the increment inc_ref otherwise.

[0105] In [Fig.2] the circuit 200 is configured so that the word OP2 is the result of the sum of the value valref and the number P, and the signal OP2 is then determined by the sum of the value valref and the number P. In contrast, in the circuit 200 of the phase adder 3, the signal OP2 is not determined by the sum of the value valref and the number P.

[0106] Indeed, in the adder 3, not only is the circuit 200 configured, as in the oscillator 2, to calculate the value valref and add it to the number P, but, in addition, for an integer index i from 1 to K, with K an integer greater than or equal to 1, for: - receive K injection signals S_i (S_l and S_K in [Fig.3]), each signal S_i being at the reference frequency Fref and exhibiting a phase shift <p_i par rapport au signal REF. De préférence, chaque déphasage <p_i appartient à la plage de valeur allant de -Il àn ; - receive K increments inc_i (inc_l and inc_K in [Fig.3]), each increment inc_i being, preferably, received in the form of a numeric word, for example on N bits; - provide K values ​​val_i (val_l and val_K in [Fig.3]), each value val_i being, in the example of [Fig.3], equal to the increment inc_i if the result O_i (O_l and O_K in [Fig.3]) of a Boolean XOR operation between the signal S_i and the OUT bit is in a first binary state and minus the increment inc_i, that is to say -inc_i (-inc_l and -inc_K in [Fig.3]), if the result of the Boolean XOR operation between The signal S_i and the OUT bit are in a second binary state. Preferably, each value val_i is provided as a digital word, for example of N bits; - add the values ​​val_i to the number P to obtain the word OP2.

[0107] Thus, the phase adder 3 circuit 200 is configured to provide the word OP2 equal to the sum of the number P, the value valref and the K values ​​val_i.

[0108] When the reference frequency F0 of the oscillator 1 is equal to the frequency Fref, that is to say when P is equal to the value PO, it is possible to demonstrate that the phase shift q> between the bit OUT and the signal REF is defined by the following relations in the example of [Fig.3]:

[0109] [Math. 12] . . ... v^i=K. A - me ref + , me i

[0110] [Math. 13] ri inc_üp_i . <P= 2 + L1=(......A...... SI A> 0 [YES] [Math. 14] " 2 +^i=i A If A<0

[0112] Thus, the adder 3 provides the OUT bit with a phase shift q> relative to the reference signal REF which is determined by the weighted sum of the phase shifts <p_i, chaque déphasage <p_i étant pondéré par la valeur de l'incrément inc_i correspondant divisée par le nombre (ou somme) A. Par exemple, le déphasage q> The OUT bit relative to the reference signal REF is equal to this weighted sum plus a phase offset having, for example, a fixed absolute value equal to n / 2 and a sign determined by the sign of the number A.

[0113] However, in the same way as described for formulas [Math.6] and [Math.7], the use of formulas [Math.13] and [Math.14] depends more generally on the polarity of A. Indeed, formula [Math.13] is valid for a first polarity of A and formula [Math.14] is valid for a second polarity of A. Whether the first polarity is the positive or negative polarity depends in particular on the polarity of each of the increments inc_ref and inc_i and / or on how the circuits 204 and 204_i are controlled by the respective gates 204 and 204_i.

[0114] It should be noted that, in the above description, the phase shift q> corresponds to the phase shift of the OUT bit relative to the REF signal. However, a person skilled in the art will be able, knowing the value of the phase shift <pref du signal REF par rapport à un autre signal de référence qui ne sert pas de signal d'injection dans le circuit 200 mais qui est à la fréquence Fref, de déterminer, à partir des relations ci-dessus, le déphasage du signal OUT par rapport à cet autre signal de référence.

[0115] Moreover, although this is not detailed here, in the same way as in circuit 2 of [Fig.2], in circuit 3 of [Fig.3], it is possible to vary the value of the phase shift q> by changing the value of the number P relative to the value PO.

[0116] By way of example, in [Fig. 3], circuit 200 comprises K Lock_i circuits (Lock_l and Lock_K in [Fig. 3]). Each Lock_i circuit is configured to receive the OUT bit, the signal S_i at frequency Fref, and the increment inc_i. Each Lock_i circuit then calculates, or determines, a value val_i equal to the increment inc_i if the result O_i of a Boolean XOR operation between the signal S_i and the OUT bit is in the first binary state, and minus the increment inc_i (-inc_l and -inc_K in [Fig. 3]) otherwise, that is, when the result O_i of this operation is in the second binary state. Circuit 200 then provides the OP2 signal, which, in the example of [Fig. 3], is equal to the sum of the number P, the value varlref, and the K val_i values. Preferably, each increment inc_i is a multi-bit digital signal, for example N bits, i.e. a digital word encoding the value of the increment inc_i. Each increment inc_i can be positive or negative.Preferably, each value val_i is a digital signal on several bits, for example on N bits, that is to say a digital word encoding the value val_i.

[0117] As an example, to generate the value val_i, each Lock_i circuit includes a logic gate 202_i (202_l and 202_K in [Fig.3]) implementing the XOR operation and a selection circuit 204_i (204_l and 204_K in [Fig.3]).

[0118] Each gate 202_i receives the signal S_i and the OUT bit, and provides the binary signal O_i resulting from the XOR between the signals S_i and OUT.

[0119] Each selection circuit 204_i is configured to provide the value val_i equal to the increment inc_i when the signal O_i is in the first binary state, corresponding to logic T, and to provide the value val_i equal to minus the increment inc_i when the signal O_i is in the second binary state, corresponding to logic '0'. By way of example, each circuit 204_i is a multiplexer receiving the increment inc_i and minus the increment inc_i, and providing the value val_i, the multiplexer 204_i being controlled by the signal O_i.

[0120] The adder 206 is configured to receive the value valref and the values ​​val_i, to add these values ​​val_i and valref to the number P, and to provide the signal OP2 as a result of this addition.

[0121] One advantage of the phase adder 3 is that it can serve as a basis for implementing a neural circuit allowing time-domain computation based on phases.

[0122] Indeed, each phase shift <p_i peut alors correspondre à une donnée d'entrée du neurone, et chacun des incréments inc_i et inc_ref peut être déterminé par les poids w_i appliqués à ces données d'entrée. Par exemple, chacun des incréments inc_i et inc_ref can be determined such that the phase shift q> between the OUT bit and the REF signal is equal to the sum of the products <p_i.w_i et d'un décalage de phase de valeur absolue n / 2 et de signe déterminé par le signe de la somme A. Par exemple, le signe du décalage de phase est le signe + (décalage de phase positif) quand le nombre A est positif, et est le signe - (décalage de phase négatif) quand le nombre A est négatif.

[0123] Figure 4 represents an example of an embodiment of a 4-neuron circuit based on the phase adder 3 of [Fig.3].

[0124] In [Fig.4], the neuron circuit 4 includes the adder 3, in which K = Kl, with Kl an integer greater than or equal to 2.

[0125] In this case, the values ​​of the Kl increments inc_i and the reference increment inc_ref can be determined by solving a system of Kl+1 equations with Kl+1 unknowns, namely the values ​​of the Kl increments inc_i and the value of the increment inc_ref. This system is defined by the following Kl+1 equations:

[0126] [Math. 15] - inc_j + L1 = 1 w_j.inc_i = - w_jjnc_ref, for j an integer index from 1 to Kl

[0127] [Math. 16] v-û-KI, . |mc_ret| +Li=] hnc_i| < PI

[0128] The value of inc_ref is chosen so that equation [Math 16] is verified, the number PI of equation [Math 16] being equal to the control number P of adder 3 of [Fig.4] so that Fref is equal to the natural frequency of oscillator 1 of adder 3, therefore to (Fref / Fclk).2L.

[0129] For the sake of explanation, the equation [Math 15] above corresponds to the following system of equations:

[0130] [Math. 17] |(w_ 1 - l).inc_ 1 + w_ l.inc_2 + ... + w_ l.inc_Kl = - w_ l.inc_ref w„2inc_ l+(w_2- l).inc_2+ ... +w_2.inc_Kl= -w_2inc_ref w_Kl.mc_l + w_KLmc_2 + ... + (w_Kl-l).inc_Kl = - w_Kl.inc_ref

[0131] In [Fig.4], the adder 3 of the neuron circuit 4 is configured to implement the calculation of the weighted sum of the phase shifts <p_i où chaque déphasage est pondéré par un poids w_i correspondant, et pour fournir le signal OUT dont le déphasage q> relative to the REF signal is representative of the result of this weighted sum.

[0132] It may be desirable, in a neural circuit, also called a neuron, that an activation function be applied to the result of the weighted sum operation.

[0133] Thus, according to one embodiment, the neuron circuit 4 further comprises an additional adder 3, referenced as 3b in [Fig. 4]. The adder 3b allows implement an activation function for neuron circuit 4. In alternative embodiments, this adder 3b is omitted, and the OUT bit output of the phase adder 3 constitutes the output bit of neuron 4.

[0134] The additional adder 3b is identical to adder 3 of [Fig. 3], except that the elements 100, 102, 200, OUT, OP1, OP2 and RES of adder 3b are designated by the respective references 100b, 102b, 200b, OUTb, OP1b, OP2b and RESb. In addition, in adder 3b, the number K is equal to K2, with K2 equal to 1 in the example of [Fig. 4].

[0135] The output signal OUT of adder 3 constitutes an input injection signal of adder 3b. In other words, the OUT signal of adder 3 corresponds to one of the K2 signals S_i of adder 3b, and, more particularly, to the S_1 signal of adder 3b in the example of [Fig.4].

[0136] In the 200b circuit of the 3b adder, a "b" is placed at the end of the references REF, S_i, 202, 202_i, 204, 204_i, 206, O_i, val_i, inc_i, -inc_i OREF, valref, inc_ref and -inc_ref.

[0137] The reference signal REFb of the adder 3b has the same frequency as the REF signal of the adder 3, but is, preferably, out of phase with the REF signal.

[0138] By way of example, the phase shift value between the REF signal and the REFb signal is determined so as to compensate for the phase shift n / 2 or -TT / 2 introduced by the phase adder 3 between the OUT signal and the REF signal. By way of example, the phase shift between the REF and REFb signals is then determined by the sign of the sum of the increments inc_i.

[0139] By way of example, the phase shift between the REFb signal and the REF signal is chosen to be equal to the phase shift n / 2 or -n / 2 between the OUT bit and the REF signal, and, furthermore, the inc_ib increments are determined so that the sign of the sum of the inc_i and inc_ref increments is opposite to the sign of the sum of the inc_ib and inc_refb increments so that the fixed phase shift introduced by the adder 3b compensates for that of the adder 3. Since the sign of the phase shift of absolute value equal to n / 2 introduced by the adder 3 between the OUT bit and the REF signal is determined by the sign of the sum of the inc_ref and inc_i increments, the phase shift between the REF and REFb signals is determined by the sign of the sum of the inc_ref and inc_i increments.

[0140] By way of example, it is possible to reverse the polarity of the REFb signal with respect to that of the REF signal, or, in other words, to apply a phase shift of II to the phase shift of the REFb signal with respect to the REF signal, which amounts to reversing the sign of the increment inf_refb associated with the REFb signal.

[0141] More generally, in a given phase adder, for example phase adder 3 or 3b, it is possible to choose the fixed phase shift between the signal and reference frequency Fref supplied to the adder, for example the respective signal REF or REFb, and an overall reference signal of frequency Fref, as well as the sign of the sum of the increments of the adder, for example respectively of the sum of the increments inc_i and inc_ref or of the sum of the increments inc_ib and inc_refb, so as to compensate for a fixed phase shift introduced by the adder between its output bit and the overall reference signal.

[0142] Furthermore, it is understood from the examples above that it is possible to obtain, by choosing the increment values ​​in the adder 3b, all possible combinations of gain values ​​in the adder 3b between the input phase of the adder 3b, i.e. the phase shift of the OUT signal with respect to the REFb signal, and the output phase of the adder 3b, i.e. the phase shift of the OUTb signal with respect to the REFb signal, and that this gain has a value that depends on the input phase of the adder 3b. For example, it is possible to implement, in the adder 3b, a gain following a sigmoid function.

[0143] Figure 5 represents an example of an embodiment of a 5-neuron network.

[0144] In the example in Figure 5, the network receives M input signals Em (E1, E2 and EM in [Fig. 5]), with M an integer strictly greater than 1, and m an integer index from 1 to M. As an example, each signal Em is a signal at the reference frequency Fref, but with a phase shift <pm par rapport à un signal de référence du réseau 5 qui est déterminé une valeur d'entrée 5. a titre d'exemple, chaque em fourni convertisseur numérique-phase, exemple déphaseur 2.

[0145] Network 5 comprises several layers of 500 neurons, that is to say several layers of 500 neuron circuits 4.

[0146] In the example in [Fig.5], each neuron 4 includes a phase 3 adder implementing the weighted sum of its inputs by the associated weights, followed by a phase 3b adder implementing an activation function.

[0147] By way of example, in [Fig. 5] where each neuron 4 comprises two phase adders 3 and 3b, although this is not detailed in the figure, all the neurons 4 in the network 5 receive the same reference signal REF, which is the reference signal of the adders 3 of the neurons 4. In this case, in each neuron 4, the reference signal REFb of the adder 3b is at the same frequency as the REF signal, but preferably with a phase shift relative to the REF signal that is determined by the sign of the sum of the increments in each of the adders 3, so as to compensate, in each neuron 4, for the phase shift of absolute value n / 2 introduced by the adder 3 relative to the reference signal REF of neuron 4. In this way, throughout the entire network 5, the phase shifts are all determined (or referenced) relative to a single reference signal REF of the neurons 4. This reference signal REF is, for example, the reference signal for phase shifts in the network 5. For example, in each neuron 4, the adder 3b of neuron 4 receives a reference signal REFb which is in positive or negative quadrature with respect to the signal REF of neuron 4. For example, the polarity of the quadrature of the signal REFb with respect to the signal REF is determined by the sign of the sum of the increments inc_ref and inc_i of the adder 3 of neuron 4.

[0148] By way of another example, the phase shift of the REFb signal relative to the REF signal in a given neuron 4 may be different from the phase shift of the REFb signal relative to the REF signal in another neuron 4, for example another neuron 4 in the same layer 500.

[0149] By way of yet another example, a signal at frequency Fref is used as the overall reference signal of the network 5, and, in each neuron 4, the phase shift of the signal REF relative to this overall reference signal and the phase shift of the signal REFb relative to this overall reference signal are determined so as to compensate for the fixed phase shift of the output bit of neuron 4 relative to the overall reference signal of the network. In other words, in each neuron 4, the phase shifts of the signals REF and REFb of neuron 4 relative to the overall reference signal are determined to cancel the fixed phase shift introduced by the adder 3 of neuron 4 between the signal REF and the output bit OUT of this adder 3 and the fixed phase shift introduced by the adder 3b of neuron 4 between the signal REFb and the output bit OUTb of this adder 3b.

[0150] In relation to [Fig.5] we have described the case of a network 5 of neurons 4 in which each neuron 4 includes an adder 3 followed by an adder 3b implementing an activation function.

[0151] Alternatively, the activation function can be implemented in a neuron 4, without a phase adder 3b.

[0152] For example, taking up again the example of neuron 4 in [Fig.4], the activation function can be implemented in neuron 4 without the adder 3b which is then omitted, the OUT bit of the adder 3 then constituting the output signal (or bit) of neuron 4. For this, the weights w_i applied to the inputs S_i of neuron 4, via the increments inc_i, are each the result of a multiplication between the gain of the activation function to be applied and a weight w'_i to be applied to the input data encoded by the phase shift of the signal S_i. The increments inc_i and inc_ref are calculated from the weights w_i which already include the gain of the activation function, from which it follows that the activation function has already been applied in the phase shift of the output bit OUT of adder 3 with respect to the REF signal of this adder 3.

[0153] Fig. 6 represents another example of an embodiment of a 6-neuron 4 network.

[0154] In the example in [Fig. 6], the network 6 receives M input signals Em (E1, E2 and EM in [Fig. 6]), with M an integer strictly greater than 1, and m an integer index from 1 to M. By way of example, each signal Em is a signal at the reference frequency Fref, but with a phase shift <pm par rapport à un signal de référence du réseau 6 qui est déterminé une valeur d'entrée 6.

[0155] The network comprises H successive 600h layers of neurons, with H an integer strictly greater than 2, and h an index from 1 to H. The index h of successive 600h layers is increasing from inputs to outputs of the network. In the example in [Fig.6], H is strictly greater than 4, and only the 6001, 6002, 6003, 6004 and 600H layers of the network are represented.

[0156] In the example in [Fig. 6], the output bit OUT of the neuron's adder 3 is the neuron's output bit. In other words, in the example in [Fig. 6], each neuron lacks the adder 3b implementing an activation function.

[0157] In the example in [Fig. 6], each neuron 4 includes a phase 3 adder implementing the weighted sum of these inputs by the associated weights. Each neuron 4 can, furthermore, implement an activation function, without an additional phase 3b adder, by multiplying the weights by the gain of the activation function as previously indicated.

[0158] By way of example, although not detailed in [Fig. 6], the neurons 4 in the odd-index h layers 600h all receive the same reference signal REF. In contrast, the reference signals supplied to the neurons 4 in the even-index h layers 600h are at the same frequency as the REF signal in the odd-index h layers 600h, but have different phase shifts relative to the REF signal in the odd-index h layers 600h. More specifically, each neuron 4 in each even-index h layer 600h receives an REF signal whose phase shift relative to the REF signal in the preceding odd-index h layer 600h is determined by the sign of the sum of the increments inc_i and inc_ref in each of the adders 3 of the neurons 4 in that preceding layer. This phase shift is, for example, determined so as to compensate for the phase shift of absolute value n / 2 introduced by the adders 3 of the neurons 4 of the previous 600h layer.This phase shift is, for example, a phase shift with an absolute value equal to n / 2 and a sign (or polarity) determined by the sign (or polarity) of the sum of the increments inc_i and inc_ref of neuron 4 in the previous layer 600h. In this way, throughout the network 6, the phase shifts of the output bits of neurons 4 are all determined (or referenced) with respect to a single reference signal, for example, the REF signal of the 600h layers with odd indices h. This reference signal REF is, for example, the reference signal for phase shifts in the network 6.

[0159] By way of another example, in each neuron 4, the phase shift of the REF signal received by that neuron 4 relative to an overall reference signal of the network 6 at the frequency Fref and / or the sign of the sum of the increments of the adder of neuron 4 are determined to compensate for the fixed phase shift n / 2 or -n / 2 introduced by this neuron between its output bit and its reference signal REF. In this way, throughout the entire network 6, the phase shifts of the output bits of neurons 4 are all determined (or referenced) with respect to a single reference signal, namely the overall reference signal of network 6.

[0160] Fig. 7 represents another example of a 7-neuron circuit.

[0161] In [Fig.7], compared to the previously described neurons 4, neuron 7 comprises a first layer or stage 700 of several neurons 4, followed by a second layer 702 or stage to one neuron 4. The input signals of neuron 7 are distributed among the neurons 4 of the 700 layer, and the neuron 4 of the 702 layer is configured to provide an output signal of neuron 7 from the output signals of the neurons 4 of the 700 layer.

[0162] Put another way, neuron 7 of [Fig.7] corresponds to a network of neurons 4 with only two layers 700 and 702 of neurons 4, in which the inputs of neuron 7 are distributed over the neurons 4 of layer 700, and the single neuron 4 of layer 702 is configured to provide the output signal of neuron 7 from the output signals of the neurons 4 of layer 700.

[0163] For example, the output signal of neuron 7 has a phase shift relative to a reference signal REF supplied to neurons 4 of layer 700 that is equal to the sum of the phase shifts of the output signals of neurons 4 of layer 700, or, put another way, the weights implemented by neuron 4 of layer 702 are unit weights.

[0164] From the description given above in relation to figures 5 and 6 of the neural networks 4, a person skilled in the art will be able to determine the phase shift values ​​between the reference signals supplied to the adders of neurons 4 of neuron 7.

[0165] For example, in the case where each neuron 4 of the network 7 includes only one adder 3, that is to say that the output signal of this neuron 4 then corresponds to the output signal of its adder 3, all the neurons 4 of the layer 700 receive the same reference signal, and the neuron 4 of the layer 702 receives a reference signal which is out of phase with respect to the reference signal of the neurons 4 of the layer 700, this phase shift being determined by the sign of the sum of the increments inc_i and inc_ref of each of the adders 3 of the neurons 4 of the layer 700, for example so as to compensate for the phase shift introduced by each of these adders 3.

[0166] By way of alternative example, the neurons 4 of layer 700 may be of the type described in relation to [Fig. 4] and each comprise two adders 3 and 3b, whereas neuron 4 of layer 702 comprises only adder 3. By way of other As an alternative example, the neurons 4 in layer 700 each contain only adder 3, and neuron 4 in layer 702 is of the type described in relation to [Fig. 4] and contains two adders, 3 and 3b. As yet another alternative example, all the neurons 4 in neuron (or network 7) are of the type described in relation to [Fig. 4] and each contain two adders, 3 and 3b. A person skilled in the art will be able to determine the phase shifts between the reference signals supplied to adders 3 and 3b of the neurons in these alternative examples from the present description, so as to compensate for phase shifts introduced by adders 3 and 3b relative to a reference signal at frequency Fref.

[0167] Examples of neural networks organized in successive layers have been described above in relation to Figures 5, 6, and 7, in which, in each layer, the neurons of the layer receive as input the output signals from neurons of the preceding layer. However, a person skilled in the art will be able to implement other examples of neural networks organized in layers, and, in particular, examples of networks in which each neuron of a layer can receive as input output signals from neurons of any layer(s) of the network. In other words, a person skilled in the art will be able to foresee a neural network comprising several neurons, each implemented by a neural circuit such as described in relation to [Fig. 3] or with [Fig. 4].4], and in which, in each neural circuit, each of the Kl injection signals S_i of the adder 3 of the neural circuit is an output signal of another neural circuit of the network.

[0168] Above, in relation to Figures 2 to 7, embodiments of a digital injection-locked oscillator 2 and of circuits and networks adapted for neural computing in which the oscillator 2 is used as a phase shifter or as a phase adder 3, 3b have been described.

[0169] Other implementations of digital oscillators can serve as the basis for a phase adder. An example of such a digital oscillator is described below in relation to [Fig.8].

[0170] Fig. 8 represents a digital ring oscillator 8 based on oscillator 2 of Fig. 2.

[0171] More particularly, the ring oscillator 8 comprises an integer number Q strictly greater than 1, preferably greater than 2, of digital oscillators 800q, with q an integer index from 1 to Q. In the example in [Fig.8], Q is equal to 3, and the ring oscillator 8 therefore comprises 3 digital oscillators 8001, 8002 and 8803.

[0172] One of the 800q digital oscillators, namely oscillator 8001 in the example of [Fig.8], is an injection-locked digital oscillator which differs from oscillator 2 of [Fig.2] only in its circuit 200.

[0173] Indeed, in the oscillator 8001, the circuit 200 is configured, as previously described, so that the value valref is selectively equal to the increment inc_ref and to less the increment inc_ref depending at least on the binary state of the reference signal REF.

[0174] However, in [Fig. 8], compared to what has been described in relation to the preceding figures, circuit 200 is more specifically configured so that the value valref is equal to the increment inc_ref when the reference signal REF of oscillator 8001 is in a first binary state, and less than the increment inc_ref otherwise. In other words, compared to circuit 200 illustrated in [Fig. 2], circuit 200 of oscillator 8001 does not include gate 202, and the selection circuit 204 is controlled directly by the REF signal of oscillator 8001.

[0175] Each of the other 800q digital oscillators is: - either a digital injection oscillator identical to the 8001 oscillator, that is to say, which differs from oscillator 2 of [Fig.2] in that its circuit 200 is configured so that the value valref is equal to the increment inc_ref when the reference signal REF of this 800q oscillator is in a first binary state, and less the increment inc_ref otherwise, - either a free-oscillating digital oscillator identical to oscillator 1 of [Fig.1], that is to say a digital oscillator comprising adder 100 and register 102, and in which the digital word OP2 is equal to the value of the control number P.

[0176] In the example in [Fig. 8], the other 800h oscillators (8002 and 8003 in [Fig. 8]) are all free-oscillating digital oscillators. In other examples not shown, the other 800h oscillators (8002 and 8003 in [Fig. 8]) are all injection-locked digital oscillators identical to oscillator 8001. In still other examples not shown, the other 800h oscillators (8002 and 8003 in [Fig. 8]) include both free-oscillating and injection-locked digital oscillators identical to oscillator 8001.

[0177] In the ring oscillator 8, the Q 800q digital oscillators are connected in a ring one after the other. More specifically, the register 102 of each 800q digital oscillator is configured to be reset by a given binary state of the output bit of the digital oscillator preceding it in the ring.

[0178] In oscillator 8, although not detailed in [Fig.8], the control numbers P of the 800q oscillators may have different values ​​between two 800q oscillators.

[0179] In the oscillator 8, the injection locking is achieved via the circuits 200 of the injection-locked oscillator(s) 800q of the oscillator 8. In an oscillator 8 comprising several injection-locked oscillators 800q, the The reference signals REF supplied to the 200 circuits of these 800q oscillators are at the same frequency, but are out of phase with each other. For example, these reference signals REF are out of phase with each other by II / Q.

[0180] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0181] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, a person skilled in the art will be able to compensate for a fixed phase shift between an input signal of a digital injection-locked oscillator and an overall reference signal at the frequency Fref, either by a fixed phase shift between the oscillator's reference signal and the overall reference signal, or by the sign of the sum of the oscillator's increments, or by the sign of the sum of the oscillator's increments and by a fixed phase shift between the oscillator's reference signal and the overall reference signal.< / pm> < / pm>

Claims

Demands

1. Injection-locked digital oscillator (2; 8001) comprising: an adder (100) configured to add a first N-bit digital word (OP2) with a second N-bit digital word (OP1) and to provide a result of the addition in the form of a third N-bit digital word (RES), with N an integer strictly greater than 1; a register (102) configured to update the second digital word (OP1) from the third digital word (RES) at each period of a clock signal (clk);a first circuit (200) configured to: - receive a reference signal (REF) at a reference frequency equal to a natural frequency of an output bit (OUT) of the oscillator, and a reference increment, inc_ref, - calculate a first value (valref) equal selectively to the reference increment inc_ref and minus the reference increment inc_ref as a function of at least one binary state of the reference signal (REF), and - provide the first digital word (OP2) determined at least in part by summing the first value (valref) and a positive control number, P, of the oscillator, the output bit (OUT) being a bit of the second word (OP1).;

2. Oscillator (2; 8001) according to claim 1, wherein the output bit (OUT) is the most significant bit of the second digital word (OP1).

3. Oscillator (2) according to claim 1 or 2, wherein the first circuit (200) is configured to receive the output bit (OUT) of the oscillator, and such that the first value (valref) is equal to the reference increment inc_ref if a result (OREF) of an XOR (202) between the output bit (OUT) and the reference signal (REF) is in a first binary state and less the increment inc_ref if the result (OREF) of the XOR (202) is in a second binary state.

4. A digital phase shifter (2) comprising the oscillator (2) according to claim 3, wherein the number P belongs to a range of values ​​centered on a number PO and of width equal to twice the absolute value of the reference increment incref, PO being equal to 2L.(Fref / Fclk), with L an index of the output bit (OUT) in the second digital word (OP1), Fref the reference frequency and Fclk the frequency of the clock signal (clk), the index L having a value in a range from 1 to N.

5. Digital phase shifter (2) according to claim 4, wherein the control number P determines a value of a phase shift of the output bit (OUT) with respect to the reference signal (REF).

6. Digital phase shifter (2) according to claim 4 or 5, wherein the first digital word (OP2) is equal to the sum of the first value (valref) and the control number P of the oscillator (2).

7. A digital phase shifter (2) according to any one of claims 4 to 6, wherein the output bit (OUT) is phase-shifted by q with respect to the reference signal (REF), with: PP V = I + 2 * inc kf if inc_ref is of a first polarity and p_p <p - - 2 + si inc_ref est d'une deuxième polarité opposée à la première polarité.

8. A digital phase adder (3) comprising: the oscillator (2) according to claim 3, wherein: the first circuit (200) comprises K second Lock_i circuits, with i an integer index from 1 to K and K an integer greater than or equal to 1, each second Lock_i circuit being configured to: - receive the output bit (OUT), an increment inc_i and an injection signal S_i at a frequency equal to the reference frequency with a phase shift <p_i par rapport au signal de référence (REF), et - fournir une deuxième valeur out_i égale à l'incrément inc_i si un résultat d'un OU EXCLUSIF entre le bit de sortie (OUT) et le signal d'injection S_i est dans un premier état binaire et à moins l'incrément inc_i sinon ; et le premier circuit (200) est configuré pour fournir le premier mot numérique (OP2) égal à la somme du nombre de commande P, de la première valeur (valref) et des K deuxièmes valeurs val_i.

9. Digital phase adder (3) according to claim 8, wherein the command number P is equal to 2L.(Fref / Fclk), with L an index of the output bit (OUT) in the second digital word (OP1), Fref the reference frequency and Fclk the frequency of the clock signal (clk), the index L having a value in a range from 1 to N.

10. Digital phase adder (3) according to claim 8 or 9, wherein the output bit (OUT) is phase-shifted by q> with respect to the reference signal, with: A = inc_ref+I^nic_i tp - ? + Li=1 a ” if A is of a first polarity, <p = - 4 +          si a est dune deuxième polarité opposée à la première polarité.

11. A neural circuit (4) comprising a first digital phase adder (3) according to any one of claims 8 to 10, wherein K is equal to Kl in the first adder (3), the Kl phase shifts <p_i du premier additionneur correspondent à kl valeurs d'entrée circuit de neurone, poids w_i neurone déterminent les incréments inc_i et l'incrément référence inc_ref (3), est supérieur ou égal 2.

12. Neural circuit (4) according to claim 11, wherein the Kl increments inc_i of the first adder (3) and the reference increment inc_ref of the first adder (3) satisfy: -inc_i+ L-^ w_jinc_i= -w_jinc_ref, with j an integer index from 1 to Kl, and line ref 1 +^1=Ki|inc il < PI' with " Absolute value operator, and PI the value of the number P of the first adder (3).

13. Neural circuit (4) according to claim 11 or 12, wherein the neural circuit (4) further comprises a second digital phase adder (3b) according to any one of claims 8 to 10, wherein K is equal to K2 in the second adder (3b) and the output bit (OUT) of the first adder (3) corresponds to one of the K2 injection signals of the second adder (3b).

14. Neural circuit (4) according to claim 13, wherein the reference signal (REFb) of the second adder (3b) has the same frequency as the reference signal (REF) of the first adder (3), and a phase shift between the reference signal (REF) of the first adder (3) and the reference signal (REFb) of the second adder (3) is determined by a sign of the sum of the increments inc_i and inc_ref of the first adder (3), preferably so as to compensate for a phase shift introduced by the first adder (3).

15. Neural network (6) comprising M successive 600h layers of neurons (4), with M an integer strictly greater than 1, and h an integer index from 1 to M and increasing from inputs to outputs of the network (6), wherein: each neuron (4) is implemented by a neuron circuit (4) according to claim 11 or 12 wherein the output bit (OUT) of the first adder (3) of the neuron circuit (4) is the output bit of neuron (4); the neurons (4) of the 600h layers with odd indices h all receive the same reference signal; and each of the neurons (4) of the 600h layers of even indices h receives a reference signal at the same frequency as the reference signal of the neurons of the 600h layers of odd indices h, but with a phase shift between these two reference signals determined by a sign of the sum of the increments inc_i and inc_ref of each of the first adder (3) of the neurons (4) of the layers of odd indices h.

16. Neural network (5) comprising several layers (500) of neurons (4), in which: each neuron (4) is implemented by a neuron circuit (4) according to claim 13 or 14, the first adders (3) of the neurons (4) of the network (5) all receive the same reference signal (REF).

17. Neural network comprising several neurons each implemented by a neural circuit according to any one of claims 11 to 14, wherein, in each neural circuit, each of the Kl injection signals of the first adder is an output bit of another neural circuit of the network.

18. Ring oscillator (8) comprising Q digital oscillators (8001, 8002, 8003), with Q an integer strictly greater than 1, preferably greater than 2, wherein: one of the Q digital oscillators (8001) is an injection-locked digital oscillator according to claim 1 or 2 wherein the first value (valref) is equal to the reference increment inc_ref of this injection-locked digital oscillator when the reference signal (REF) of this injection-locked digital oscillator (8001) is in a first binary state, and less the reference increment inc_ref otherwise; Each of the other digital oscillators (8002, 8003) is: - either an injection-locked digital oscillator according to claim 1 or 2 in which the first value (valref) is equal to the reference increment inc_ref of this injection-locked digital oscillator when the reference signal of this injection-locked digital oscillator (8001) is in a first binary state, and less the reference increment inc_ref otherwise, - either a free-oscillating digital oscillator (1) comprising: * an adder (100) configured to add a first N-bit digital word (OP2) with a second N-bit digital word (OP1) and to provide a result of the addition in the form of a third N-bit digital word (RES); * a register (102) configured to update the second digital word (OP1) from the third digital word (RES) at each period of the clock signal (clk), an output bit (OUT) of this free-oscillating oscillator (1) being a bit of the third word (RES) and the first digital word (OP2) being a control word (P) of this free-oscillating oscillator (1), in which the Q digital oscillators (8001, 8002, 8003) are connected in a ring one after the other, the register of each digital oscillator being configured to be reset by a state of the output bit (OUT) of the preceding digital oscillator (8003, 8001, 8002) of the ring (8).