Memory device comprising a bipolar memory cell with optimized active area

Abstract

Memory device comprising an optimized active area memory cell. This description relates to a memory device (100) comprising at least one memory cell having: - a first selector transistor (110) comprising an active area formed in a first semiconductor layer (132); - several interconnection levels (136, 138) superimposed on the first semiconductor layer (132); - a second selector transistor (112) comprising an active area formed in a second semiconductor layer (134) disposed in one of the interconnection levels (136, 138); - a bipolar memory point (102) disposed in another of the interconnection levels located between the first and second semiconductor layers; and wherein a drain electrode (114, 116) of each of the first and second selector transistors is connected to the memory point. Figure for the abstract: Fig. 1

Description

Title of the invention: Memory device comprising a bipolar memory cell with an optimized active surface. Technical field

[0001] This description relates generally to the field of electronic devices with bipolar memory cells, in particular with resistive bipolar memory cells (called RRAM or ReRAM for "Resistive Random-Access Memory") based on oxide (OxRAM for "Oxide-based Random-Access Memory") or metallic electrolyte (CBRAM or "Conductive-Bridging Random-Access Memory"), or with magnetoresistive memory cells (called MRAM for "Magnetoresistive Random-Access Memory"). Prior art

[0002] The main block of a memory is generally formed of an array of memory cells, or "bitcells". Each memory cell includes at least one selection transistor for selecting and electrically accessing the memory cell and at least one memory location where information for the memory cell is stored. The memory cells are electrically coupled to electrical connection elements formed in superimposed interconnection levels of the BEOL ("Back End Of Line") portion of the circuit comprising the memory.

[0003] In an RRAM-type memory cell, each memory point comprises a portion of metallic oxide or electrolyte arranged between two electrodes, generally arranged in a vertical stack. The paper P. Polakowski et al., “Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications”, 2014 IEEE 6th International Memory Workshop (IMW), Taipei, Taiwan, 2014, pp. 1-4, describes such a configuration of an OxRAM-type memory cell.

[0004] Programming a memory location can be achieved using a single transistor coupled to one of the two electrodes of the memory location. Such a transistor forms a unipolar selector for the memory location and can be of the PMOS or NMOS type. Such a 1T1R type memory cell has the advantage of occupying a small semiconductor area (or "footprint") since only one transistor is implemented in the semiconductor layer for this memory cell. However, such a unipolar selector cannot perform operations of different polarities (write and erase operations, involving current flows in different directions) on the memory location in the same way. Due to the asymmetrical electrical properties of a transistor, which depend on its conductivity type, the write and erase operations performed in such a memory cell are highly unbalanced. For example, the selector switch might be well-suited for writing but heavily overpowered during erasing the memory cell.

[0005] The document J.-M. Portai et al., “Design and simulation of a 128 kb embedded nonvolatile memory based on a hybrid RRAM (HfO2) / 28 nm FDSOI CMOS technology,” IEEE Trans. Nanotechnol., vol. 16, no. 4, pp. 677-686, Jul. 2017, describes an example of a 2T1R type memory cell comprising two transistors for programming the memory location, one being of the NMOS type and the other of the PMOS type. Such a memory cell makes it possible to resolve the imbalance problems related to the polarity of the operations to be performed in the memory location, since these operations are implemented with one or the other of the transistors depending on the polarity of the operation. On the other hand, such a memory cell occupies a large semiconductor area (approximately three times larger than that of a 1T1R type memory cell) due to the two transistors that must be manufactured.

[0006] The document A. Levisse et al., “Resistive Switching Memory Architecture Based on Polarity Controllable Selectors,” IEEE Transactions on Nanotechnology, vol. 18, pp. 183–194, 2019, describes the implementation of a 1T1R type memory cell in which the transistor's polarity is controllable according to the operation to be performed. Such a memory cell makes it possible to resolve the imbalance problems related to the polarity of the operations to be performed thanks to the programmability of the transistor's polarity. However, such a memory cell requires a large semiconductor area (approximately twice that required for a 1T1R type memory cell comprising a transistor with non-controllable polarity) due to the area occupied by the controllable-polarity transistor. Summary of the invention

[0007] There is therefore a need to propose a memory device comprising at least one bipolar memory cell which does not present the problems of asymmetry or imbalance of a memory cell with a unipolar selector and which requires a smaller semiconductor surface than those of 2T1R or 1T1R type memory cells with a controllable polarity transistor.

[0008] An embodiment proposes a solution to all or part of the drawbacks of known solutions and proposes a memory device comprising at least one memory cell including:

[0009] - a first selection transistor comprising an active region formed in a first semiconductor layer;

[0010] - several levels of interconnections superimposed on the first semi-layer driver;

[0011] - a second selection transistor comprising an active region formed in a second semiconductor layer arranged in one of the interconnection levels;

[0012] - a bipolar memory point disposed in another of the interconnection levels found between the first and second semiconductor layers;

[0013] and wherein a drain electrode of each of the first and second selection transistors is connected to the memory point.

[0014] According to a particular embodiment, the memory point comprises a resistive portion and the memory cell is of the OxRAM type, or the memory point comprises a solid electrolyte and the memory cell is of the CBRAM type, or the memory point comprises a magnetoresistive stack and the memory cell is of the MRAM type.

[0015] According to a particular embodiment, the active area of ​​the second selection transistor is at least partly arranged directly above the active area of ​​the first selection transistor.

[0016] According to a particular embodiment, one of the first and second selection transistors is of type P and the other of the first and second selection transistors is of type N.

[0017] According to a particular embodiment, the memory device comprises several memory cells arranged in a matrix and addressed by word lines, bit lines and source lines, wherein the word lines are coupled to gates of the first and second selection transistors, and wherein the bit lines and source lines are coupled to source electrodes of the first and second selection transistors and / or to electrodes of the memory points of the memory cells.

[0018] According to a particular embodiment, in each memory cell:

[0019] - a first memory point electrode is coupled to a drain electrode of the first selection transistor;

[0020] - a second memory point electrode is coupled to a drain electrode of the second selection transistor;

[0021] - a source electrode of the first selection transistor is coupled to one of the source lines;

[0022] - a source electrode of the second selection transistor is coupled to one of the bit lines.

[0023] According to a particular embodiment:

[0024] - when the second selection transistor is of type N, the second semi-layer conductive contains semiconducting oxide, or

[0025] - when the second selection transistor is of type P, the second semi-layer conductive contains carbon nanotubes.

[0026] According to a particular embodiment, the second semiconductor layer comprises a crystalline semiconductor material.

[0027] According to a particular embodiment, the memory device is made in the form of an integrated circuit in which the first semiconductor layer is included in the FEOL part of the integrated circuit, and the interconnection levels are included in the BEOL part of the integrated circuit.

[0028] A method for implementing a memory device comprising at least one memory cell, including at least:

[0029] - realization of a first selection transistor comprising an active region formed in a first semiconductor layer;

[0030] - implementation of several levels of interconnections superimposed on the first layer semiconductor, including at least: • realization of a second selection transistor comprising an active region formed in a second semiconductor layer disposed in one of the interconnection levels; • realization of a bipolar memory point in another of the interconnection levels located between the first and second semiconductor layers;

[0031] and wherein a drain electrode of each of the first and second selection transistors is connected to the memory point.

[0032] According to a particular embodiment, the memory device is made in the form of an integrated circuit in which the first semiconductor layer is included in the FEOL part of the integrated circuit and the first selection transistor is made during the realization of the FEOL part of the integrated circuit, and the interconnection levels are included in the BEOL part of the integrated circuit and the memory point and the second selection transistor are made during the realization of the BEOL part of the integrated circuit. Brief description of the drawings

[0033] These features and advantages, as well as others, will be described in detail in the following description of specific examples and embodiments, given by way of non-limiting agreement, in connection with the accompanying figures, among which:

[0034] - Fig. 1 schematically represents an example of a memory device according to a particular embodiment;

[0035] - Figures [Fig. 2] and [Fig. 3] represent steps in an example of a process of creation of a memory device. Description of the implementation methods

[0036] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and detailed. In particular, various elements (read circuit, row decoder, column decoder, etc.) of the memory device are not detailed. A detailed implementation of these elements is within the capabilities of a person skilled in the art using the functional description given below.

[0038] In the different figures, the visible elements are not represented at the same scale relative to each other to facilitate understanding of these figures.

[0039] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intervening elements other than conductors, and when referring to two elements connected or coupled, this means that these two elements can be connected or linked via one or more other elements. Furthermore, the term "coupled" is used to denote electrical coupling between elements.

[0040] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures in a normal operating position of the device.

[0041] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0042] The description below of oxide-based resistive bipolar memory cells (OxRAM) can be similarly applied to other types of resistive bipolar memory cells (RRAM), particularly CBRAM, by replacing the constituent elements of these OxRAM memory cells with their equivalents in CBRAM memory cells, namely, the lower and upper electrodes with a chemically inert and a chemically active electrode, respectively, and the resistive layer with a solid electrolyte. It can also be applied to other types of bipolar memory cells, particularly MRAM, by replacing the resistive layer with a magnetoresistive stack comprising a tunnel oxide layer, for example based on MgO, arranged between two magnetic layers for example based on cobalt.

[0043] An example of a memory device 100 according to a particular embodiment is described below with reference to [Fig. 1]. In this figure, an electrical diagram and a cross-sectional view of a memory cell of the memory device 100 are shown side by side.

[0044] In the example described, the memory device 100 comprises several memory cells arranged side by side in the form of a matrix. In [Fig. 1], only one memory cell is shown.

[0045] Each memory cell of the device 100 comprises a bipolar memory point 102 in which information is intended to be stored. In the example described, the memory point 102 is of the OxRAM type and comprises a resistive portion 104 including an oxide whose resistance varies according to the information stored in the memory cell. For example, the resistive portion 104 may include HfO2 or any other suitable oxide to allow information storage by the formation of conductive filaments within it.

[0046] The resistive portion 104 is disposed between a first electrode 106 and a second electrode 108 of the memory point 102. According to one embodiment, each of the first and second electrodes 106, 108 of the memory point 102 may comprise a first part including, for example, Ti, TiN or TaN and disposed against the resistive portion 104, and at least a second part including, for example, tungsten, TiN, copper or cobalt and serving for the electrical interconnection of the memory point 102. In this example, each of the first and second electrodes 106, 108 has its first part disposed between the resistive portion 104 and its second part. The examples of materials mentioned above for the realization of the first part of the electrodes 106, 108 of the memory point 102 have the advantage of being chemically stable, thus providing electrochemical neutrality to the electrodes 106, 108.

[0047] According to one embodiment, the memory point 102 may optionally include a portion of getter material based on titanium, tantalum, or hafnium, or any other material having an electrochemical affinity for oxygen, when the memory point 102 is of the OxRAM type. Such a portion of getter material may contribute to the creation of one or more electrically conductive filaments in the resistive portion 104.

[0048] Alternatively, the memory location 102 may be of another type, for example CB RAM or MRAM. In this case, the resistive portion 104 may be replaced by another type of portion of material(s) in which information storage is intended to take place.

[0049] The memory cell also includes a first selector transistor 110 and a second selector transistor 112 for controlling the memory location 102 during write, erase, and read operations of the memory location 102. In the example described, transistors 110 and 112 are of the MOS type, but other types of transistors are possible. Furthermore, in the example described, the first transistor 110 is of the P-type and the second transistor 112 is of the N-type. Alternatively, it is possible for the first transistor 110 to be of the N-type and the second transistor 112 to be of the P-type.

[0050] One electrode of each of the first and second transistors 110, 112 is coupled to the memory point 102. In the example described, the first electrode 106 of the memory point 102 is coupled to a drain electrode 114 of the first transistor 110, and the second electrode 108 of the memory point 102 is coupled to a drain electrode 116 of the second transistor 112.

[0051] The memory cells of the device 100 are addressed by word lines, bit lines, and source lines. Each word line and source line is, for example, coupled to the memory cells arranged in the same row of the memory cell matrix of the device 100, and each bit line is, for example, coupled to the memory cells arranged in the same column of the memory cell matrix of the device 100. Other configurations are possible, however, such as having the source lines coupled to the memory cells perpendicular or parallel to the bit lines, having both the source and bit lines coupled to the memory cells perpendicular to the word lines, etc.

[0052] In the example described, the word lines are coupled to the gates of the memory cell selection transistors. In the example of [Fig. 1], a first word line 118.1 is coupled to the gate 120 of the first transistor 110, and a second word line 118.2 intended for the transmission of a signal complementary to that transmitted by the first word line 118.1 (because the first and second transistors 110, 112 are of opposite types in this example) is coupled to the gate 122 of the second transistor 112.

[0053] In the particular embodiment described here, the bit lines and source lines are coupled to source electrodes of the first and second transistors 110, 112 and / or to electrodes of the memory points 102 of the memory cells. In the particular embodiment described in connection with [Fig. 1], one of the bit lines 124 is coupled to a source electrode 126 of the second transistor 112, and one of the source line 128 is coupled to a source electrode 130 of the first transistor 110.

[0054] The first transistor 110 comprises an active region (the region including the channel, source, and drain regions of the transistor) formed in a first semiconductor layer 132. In the embodiment shown in [Fig. 1], the first semiconductor layer 132 is part of a substrate from which the device 100 is fabricated. This substrate may, for example, be a bulk substrate or a SOI substrate (in which case the first semiconductor layer 132 corresponds to the surface semiconductor layer of the SOI substrate). The first transistor 110 may, for example, be of the bulk, FDSOI, or FinFET type.

[0055] In the example described, the device 100 is implemented as an integrated circuit that may include other electronic circuits. The first semiconductor layer 132 is included in the FEOL (Front End-Of-Line) portion of the integrated circuit. Various levels of interconnections are formed above the first semiconductor layer 132, more precisely above the gates and contacts made on the first semiconductor layer 132, and are part of the BEOL (Back End-Of-Line) portion of the integrated circuit. In [Fig. 1], the boundary between the FEOL and BEOL portions of the integrated circuit is symbolized by a dashed line.

[0056] The second transistor 112 includes an active region formed in a second semiconductor layer 134 which is located in one of the interconnection levels superimposed on the first semiconductor layer 132, and therefore in the BEOL portion of the integrated circuit. Similarly, the memory dot 102 is formed in another of these interconnection levels, and therefore also in the BEOL portion of the integrated circuit.

[0057] In the particular embodiment described, the memory point 102 is located in an interconnection level arranged between the first and second semiconductor layers 132, 134. For example, the memory point 102 is arranged in the interconnection level M1 or Metal 1, designated by reference 136 on [Fig.1], located immediately above the BEOL part of the circuit, and the second transistor 112 is arranged in the interconnection level M2 or Metal 2, designated by reference 138 on [Fig.1], of the integrated circuit.

[0058] According to one embodiment, memory point 102 can be realized in the form of a stack of planar layers or in the form of a 3D structure.

[0059] The active area of ​​the second transistor 112 can be at least partly arranged directly above the active area of ​​the first transistor 110. In the embodiment shown in [Fig.1], the active areas of the first and second transistors 110, 112 are aligned one above the other.

[0060] On [Fig. 1], the gate dielectrics of the first and second transistors 110, 112, comprising for example an oxide, are designated respectively by references 140, 142, and the gate spacers, comprising for example a nitride, are designated by references 141 and 143 respectively for the first and second transistors 110, 112.

[0061] As in [Fig. 1], the first semiconductor layer 132 comprises, for example, silicon. A first dielectric layer 144, of the PMD (Pre-Metal Dielectric) type and comprising, for example, a semiconductor oxide such as SiO2, is disposed on the first semiconductor layer 132 and covers, in particular, the gate 120 of the first transistor 110. The electrodes 114, 130 of the first transistor 110 pass through the layer 144 to come into contact with the source and drain regions of the active area of ​​the first transistor 110. For example, the electrodes 114, 130 of the first transistor 110 may comprise tungsten, cobalt, or a Ti / TiN stack.

[0062] Layer 144 and electrodes 114, 130 of the first transistor 110 are coated with a nitride layer 146 comprising, for example, silicon nitride. The interface between the nitride layer 146 and layer 144 can be viewed as forming the separation between the FEOL and BEOL parts of the integrated circuit.

[0063] The interconnection level 136 comprises a second dielectric layer 148, of the IMD type (Inter-Metal Dielectric, and more specifically IMD1 when referring to the interconnection level M1), and comprising, for example, a semiconductor oxide such as SiO2. The layer 148 is disposed on the nitride layer 146.

[0064] The memory point 102 is located in layer 148. In the example of [Fig. 1], the first electrode 106 of the memory point 102 passes through the nitride layer 146 and part of the thickness of layer 148 to come into contact with the drain electrode 114 of the first transistor 110 and with the resistive portion 104. In the example of [Fig. 1], the second electrode 108 of the memory point 102 passes through part of the thickness of layer 148 to come into contact with the second semiconductor layer 134 and with the resistive portion 104. In the example of [Fig. 1], the second electrode 108 of the memory point 102 and the drain electrode 116 of the second transistor 112 are formed by the same portion(s) of material(s).

[0065] The interface between the second semiconductor layer 134 and the layer 148 can be like forming the separation between the interconnection levels 136, 138 of the integrated circuit.

[0066] When the second transistor 112 is of type N, the second semiconductor layer 134 comprises, for example, a semiconductor oxide such as indium tin oxide (ITO), indium(III) oxide (In2O3), IGZO, indium tungsten oxide (IWO), or polysilicon. When the second transistor 112 is of type P, the second semiconductor layer 134 contains, for example, carbon nanotubes (CNTs). Its thickness is, for example, between 1 monolayer and a few nanometers.

[0067] Alternatively, it is possible that the second semiconductor layer 134 corresponds to a layer of crystalline semiconductor material, for example crystalline silicon.

[0068] The gate 122 of the second transistor 112 is disposed on the second semiconductor layer 134. The interconnection level 138 has a third dielectric layer 150, of the IMD type (and more specifically IMD2 when it is the interconnection level M2), and comprising, for example, a semiconductor oxide such as SiO2. The layer 150 is disposed on the second semiconductor layer 134, with a nitride layer 152, comprising, for example, silicon nitride, interposed between them.

[0069] The source electrode 126 of the second transistor 112 passes through the layer 150 and the nitride layer 152 to come into contact with the second semiconductor layer 134, against a source or drain region of the second transistor 112. For example, the source electrode 126 may comprise tungsten, cobalt, a Ti / TiN stack, Ni or Mo.

[0070] Interconnection levels 136, 138 include other metallic interconnection portions not visible in [Fig.1].

[0071] In the embodiment described above, the first and second transistors 110, 112 are single-gate transistors. Alternatively, the gate 122 of the second transistor 112 may be located on the opposite side of the second semiconductor layer 134, i.e., the side of the second semiconductor layer 134 facing the memory point 102. According to another embodiment, the first transistor 110 and / or the second transistor 112 may be double-gate transistors.

[0072] An advantageous configuration of the device 100 corresponds to that in which the first transistor 110 is of type P and has an active area comprising silicon, and in which the second transistor 112 is of type N and has an active area comprising indium oxide.

[0073] In the device 100, the memory cell or each of the memory cells implemented as described above does not present a problem of polarity asymmetry since the memory location 102 of the cell is accessible from each of its electrodes 106, 108 via a transistor coupled to each of its electrodes 106, 108 and whose polarity is adapted to the direction of current flow through the memory location 102. For example, one of the two transistors 110, 112 has a polarity well suited for carrying out a write operation in the memory location 102, and the other of the two transistors 110, 112 has a polarity well suited for implementing an erasure operation in the memory location).

[0074] Furthermore, the footprint, and more specifically the semiconductor surface area occupied by the memory cell or each of the memory cells of the device 100, is limited by the fact that only the first transistor 110 is implemented in the first semiconductor layer 132 of the substrate, and that the memory point 102 and the second transistor 112 are implemented in the interconnection layers 136, 138 superimposed on the first semiconductor layer. This footprint is advantageously optimized when the active areas of the first and second transistors 110, 112 are aligned and positioned directly above each other.

[0075] A method for carrying out the device 100 according to the particular embodiment is described below in relation to figures 2 and 3.

[0076] As shown in [Fig.2], the first transistor 110 is first made from the first semiconductor layer 132. The steps implemented for the realization of this first transistor 110 are not detailed here and correspond to classic steps in the field of integrated circuit realization.

[0077] The first dielectric layer 144 and the electrodes 114, 130 of the first transistor 110 are then formed. For example, the first dielectric layer 144 can first be deposited to the desired thickness. Electrical connections to the various parts of the first transistor 110 can then be made by etching holes through the first dielectric layer 144, thus creating access points to the desired parts. One or more metals can then be deposited in these holes. The metallic portions deposited on the first dielectric layer 144 can then be removed, for example, by chemical-mechanical polishing (CMP). Thus, the metallic portions produced can form, in particular, the electrodes 114, 130 of the first transistor 110, or at least part of the connection between the gate 120 of the first transistor 110 and the first word line 118.1, and at least part of the connection between the source electrode 130 of the first transistor 110 and the source line 128. The structure obtained at this stage of the process is shown in [Fig.2].

[0078] The first nitride layer 146 is then made on the previously made structure, and therefore on the first dielectric layer 144 and the different metallic portions (the electrodes 114, 130 of the first transistor 110 in this example) made in the first dielectric layer 144.

[0079] The memory point 102 and the first level of interconnections 136 are then formed on the first nitride layer 146. The second dielectric layer 148 can in particular be formed by implementing several deposition steps of the desired dielectric material for this layer, with in particular between these steps deposits the implementation of steps forming the different elements of the memory point 102 (realization of the first electrode 106 of the memory point 102 such that it is coupled to the drain electrode 114 of the first transistor 110, realization of the oxide portion 104, realization of the second electrode 108 of the memory point 102). The structure obtained at this stage of the process is represented in [Fig.3].

[0080] The second semiconductor layer 134 is then fabricated on the previously fabricated structure, and therefore on the second dielectric layer 148 and the various metallic portions (the second electrode 108 of the memory point 102 in this example) fabricated in the second dielectric layer 148. The technique(s) used to fabricate the second semiconductor layer 134 depend on the nature of the material(s) of this layer. When the second semiconductor layer 134 comprises a semiconductor oxide, the steps enabling its fabrication can be carried out at temperatures below approximately 400°C. When the second semiconductor layer 134 comprises a crystalline semiconductor material, this layer can be transferred by implementing a low-temperature transfer step, as described, for example, in the document by M. Vinet et al., “3D monolithic integration: Technological challenges and electrical results”, Microelectronic Engineering, Volume 88, Issue 4, 2011, pages 331-335. .

[0081] The second transistor 112 is then made from the second semiconductor layer 134. In the first embodiment, the second transistor 112 is in particular made such that the second electrode 108 of the memory point 102 also forms the drain electrode 116 of the second transistor 112.

[0082] The second level of interconnections 138 is then produced. In particular, the second nitride layer 152, the third dielectric layer 150, and the source electrode 126 of the second transistor 112 are produced. For example, the second nitride layer 152 can be deposited, and then the third dielectric layer 150 can be deposited to the desired thickness. Electrical connections to the various parts of the second transistor 112 can then be made by etching holes through the third dielectric layer 150, thus creating access points to the desired parts. One or more metals can then be deposited in these holes; the metal parts deposited on the third dielectric layer 150 can then be removed, for example, by using a CMP (Cold Molding Process).Thus, the metallic portions produced can form in particular the source electrode 126 of the second transistor 112, at least part of the connection between the gate 122 of the second transistor 112 and the second word line 118.2, and at least part of the connection between the source electrode 130 of the first transistor 110 and the word line. bit 124. The structure obtained is similar to that previously described in connection with [Fig.1].

[0083] In the process described above, only the implementation of the elements of a single memory cell of the device 100 is described. However, when the device 100 is implemented in the form of an integrated circuit, other components and elements are implemented during the fabrication of the FEOL and BEOL portions of the integrated circuit.

[0084] Various embodiments and variants have been described. A person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to a person skilled in the art.

[0085] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. For example, the precise nature of the deposition and engraving steps implemented can be chosen according to, in particular, the material(s) to be deposited or engraved, as well as the thicknesses of the material to be deposited or engraved.

Claims

Demands

1. Memory device (100) comprising at least one memory cell having: - a first selection transistor (110) having an active area formed in a first semiconductor layer (132); - several interconnection levels (136, 138) superimposed on the first semiconductor layer (132); - a second selection transistor (112) having an active area formed in a second semiconductor layer (134) disposed in one of the interconnection levels (136, 138); - a bipolar memory point (102) disposed in another of the interconnection levels (136, 138) located between the first and second semiconductor layers (132, 134); and wherein a drain electrode (114, 116) of each of the first and second selection transistors (110, 112) is connected to the memory point (102).

2. Memory device (100) according to claim 1, wherein the memory point (102) comprises a resistive portion (104) and the memory cell is of the OxRAM type, or wherein the memory point (102) comprises a solid electrolyte and the memory cell is of the CB RAM type, or wherein the memory point (102) comprises a magnetoresistive stack and the memory cell is of the MRAM type.

3. Memory device (100) according to any one of the preceding claims, wherein the active area of ​​the second selection transistor (112) is at least partly disposed directly above the active area of ​​the first selection transistor (110).

4. Memory device (100) according to any one of the preceding claims, wherein one of the first and second selector transistors (110, 112) is of type P and the other of the first and second selector transistors (110, 112) is of type N.

5. Memory device (100) according to any one of the preceding claims, comprising several memory cells arranged in matrix and addressed by word lines (118.1, 118.2), bit lines (124) and source lines (128, 154), wherein the word lines (118.1, 118.2) are coupled to gates (120, 122) of the first and second select transistors (110, 112), and wherein the bit lines (124) and source lines (128, 154) are coupled to source electrodes (126, 130) of the first and second select transistors (110, 112) and / or to electrodes (106, 108) of the memory points (102) of the memory cells.

6. Memory device (100) according to claim 5, wherein, in each memory cell: - a first electrode (106) of the memory point (102) is coupled to a drain electrode (114) of the first selection transistor (110); - a second electrode (108) of the memory point (102) is coupled to a drain electrode (116) of the second selection transistor (112); - a source electrode (130) of the first selection transistor (110) is coupled to one of the source lines (128); - a source electrode (126) of the second selection transistor (112) is coupled to one of the bit lines (124).

7. Memory device (100) according to any one of the preceding claims, wherein: - when the second selector transistor (112) is of type N, the second semiconductor layer (134) comprises semiconductor oxide, or - when the second selector transistor (112) is of type P, the second semiconductor layer (134) comprises carbon nanotubes.

8. Memory device (100) according to any one of claims 1 to 6, wherein the second semiconductor layer (134) comprises a crystalline semiconductor material.

9. Memory device (100) according to any one of the preceding claims, realized in the form of an integrated circuit in which the first semiconductor layer (132) is included in the FEOL part of the integrated circuit, and in which the interconnection levels (136, 138) are included in the BEOL part of the integrated circuit.

10. Method for making a memory device (100) comprising at least one memory cell, comprising at least: - realization of a first selection transistor (110) comprising an active region formed in a first semiconductor layer (132); - implementation of several levels of interconnections (136, 138) superimposed on the first semiconductor layer (132), including at least: • realization of a second selection transistor (112) comprising an active area formed in a second semiconductor layer (134) disposed in one of the interconnection levels (136,138); • realization of a bipolar memory point (102) in another of the interconnection levels (136, 138) located between the first and second semiconductor layers (132, 134); and in which a drain electrode (114, 116) of each of the first and second selector transistors (110, 112) is connected to the memory point (102).

11. A method for making a memory device (100) according to claim 10, wherein the memory device (100) is made in the form of an integrated circuit in which the first semiconductor layer (132) is included in the FEOL part of the integrated circuit and the first selector transistor (110) is made during the realization of the FEOL part of the integrated circuit, and wherein the interconnection levels (136, 138) are included in the BEOL part of the integrated circuit and the memory point (102) and the second selector transistor (112) are made during the realization of the BEOL part of the integrated circuit.

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