SUBSTRATE FOR THE FABRICATION OF A HIGH ELECTRON MOBILITY TRANSISTOR

Abstract

The present invention relates to a substrate for the fabrication of a high electron mobility transistor (HEMT), comprising successively: a support substrate (10) of single-crystal silicon, an intermediate layer (20) of silicon nitride (Si3N4) having a thickness of between 0.5 and 3 µm, and a seed layer (30) of single-crystal GaN, the intermediate layer (20) forming a bonding interface between the support substrate (10) and the seed layer (30). Figure for the abstract: Fig. 2B

Description

Title of the invention: SUBSTRATE FOR THE FABRICATION OF A HIGH ELECTRON MOBILITY TRANSISTOR FIELD OF INVENTION

[0001] The present invention relates to a substrate for the fabrication of a high-electron-mobility transistor, a transistor fabricated from such a substrate, and an integrated monolithic structure based on such a substrate. The invention also relates to a method for the fabrication of a substrate and a high-electron-mobility transistor. PRIOR TECHNOLOGY

[0002] High electron mobility transistors (HEMTs) are power transistors based on a type IILV semiconductor, particularly gallium nitride (GaN). Since bulk gallium nitride substrates do not exist, HEMTs are typically fabricated on a GaN layer deposited by epitaxy on a silicon substrate. A known HEMT transistor is described, for example, in document EP2983195 AL

[0003] Silicon exhibits different structural and mechanical properties than GaN, particularly in terms of its crystal lattice and coefficient of thermal expansion. This results in a significant accumulation of stress in GaN, which increases as the thickness of the GaN layer increases. To compensate for these differences, intermediate layers are added between the silicon substrate and the GaN layers. These intermediate layers typically comprise aluminum nitride (AIN) and gallium aluminum nitride (AlGaN). However, these intermediate layers have low thermal conductivity, which negatively impacts the operation of the HEMT transistor. Furthermore, the thickness and crystal orientation of such a substrate do not allow for monolithic CMOS-type integration of silicon electronic circuits for measuring and controlling HEMT power transistors on a single silicon substrate.

[0004] Figure 1 schematically illustrates a known HEMT. The HEMT comprises, from its base to its surface, a silicon substrate 11 having a plurality of intermediate layers 21, a GaN buffer layer 31, a GaN channel 41, and an AlGaN barrier layer 51. The channel and the barrier layer form a heterojunction allowing the formation of a two-dimensional electron gas confined within the channel. The source electrode 61 and drain electrode 62 are formed on the channel 41. The gate electrode 63 is arranged on the barrier layer 51.

[0005] It is also desirable to fabricate HEMTs on an integrated substrate comprising other components such as driver transistors, CMOS integrated circuits, and any other electronic components intended for use in the same device as the HEMT. Standard silicon substrates are particularly well-suited for carrying electronic components directly on their silicon top surface due to their semiconducting properties, which are well-suited to these applications, and the maturity of silicon microelectronics.

[0006] Furthermore, the switching on and off of HEMT transistors generates electromagnetic fields that can interfere with the operation of neighboring HEMT transistors as well as with electronic measurement and control circuits. This interference, known as "crosstalk," increases with the proximity of the components. It is desirable to reduce the level of interference from electromagnetic fields in order to increase the integration density on the surface of a substrate.

[0007] Monolithic integration solutions for HEMT transistors on GaN and other electronic components on a SOI (Silicon On Insulator) substrate have also been proposed. An SOI substrate typically comprises a silicon support substrate, a buried oxide layer, and a thin silicon layer on which a gallium nitride layer is grown by heteroepitaxy. However, the oxide layer constitutes a thermal barrier, making heat dissipation from the HEMT difficult. Consequently, the transistor can only operate with low electrical currents or must have a large surface area to facilitate heat dissipation. A compromise must therefore be found between performance and integration density. Description of the invention

[0008] An object of the invention is to make available a substrate for the manufacture of a gallium nitride-based HEMT exhibiting improved electrical and thermal performance, allowing in particular the integration of other components on the same substrate while ensuring electrical isolation of the HEMTs from these other components.

[0009] To this end, the invention proposes a substrate for the fabrication of a high electron mobility transistor, comprising successively: • a monocrystalline silicon support substrate, • an intermediate silicon nitride layer with a thickness between 0.5 and 3 pm, and • a seed layer made of single-crystal GaN,

[0010] the intermediate layer forming a bonding interface between the support substrate and the seed layer.

[0011] The intermediate layer simultaneously ensures adhesion of the seed layer to the substrate and provides electrical insulation of the HEMT within the volume, along the thickness of the substrate. This electrical insulation, which can be combined with lateral insulation provided by an electrically insulating wall, prevents interference with the HEMT from electromagnetic fields generated by other components. Consequently, this allows for an increased integration density of components on the same substrate.

[0012] Advantageously, the substrate further comprises a first epitaxial layer of single-crystal GaN on the seed layer, the first epitaxial layer and the seed layer together forming a buffer layer of single-crystal GaN.

[0013] Advantageously, the buffer layer has a thickness between 1 and 10 pm.

[0014] Preferably, the substrate further comprises a second epitaxial layer of unintentionally doped GaN, arranged on the buffer layer.

[0015] Advantageously, the intermediate layer and the buffer layer are in the form of at least one block extending over only a first region of the supporting substrate.

[0016] Particularly advantageously, the intermediate layer and the buffer layer are in the form of a plurality of blocks, each block being adapted for the manufacture of a respective high electron mobility transistor.

[0017] Preferably, the substrate further comprises at least one electronic component arranged on a second region of the support substrate distinct from the first region.

[0018] Advantageously, the substrate further comprises an electrically insulating wall made of a dielectric material in contact with the substrate support portion, said electrically insulating wall being arranged between each pad and an electronic component arranged on the second region of the substrate support.

[0019] In certain embodiments, the support substrate comprises a first portion of monocrystalline silicon having a first electrical resistivity and a second portion of monocrystalline silicon extending over the first portion, said second portion comprising areas having a second electrical resistivity lower than the first electrical resistivity, at least one electronic component arranged on an area having the second electrical resistivity.

[0020] The invention also relates to a high electron mobility transistor, comprising a substrate as described above, a GaN channel arranged on the buffer layer, • a barrier layer forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel, • a source electrode and a drain electrode electrically connected to the channel, • a grid electrode formed on the barrier layer so that the grid electrode is physically isolated from the channel.

[0021] The invention also relates to a method for manufacturing a substrate for a high electron mobility transistor as described above, said method comprising the following steps: • the deposition of at least one intermediate layer of Si3N4 on a monocrystalline silicon support substrate and / or on a monocrystalline GaN donor substrate, the sum of the thicknesses of the respective intermediate layers being between 0.5 and 3 pm; • the formation of a weakening zone by implantation of ionic species in the single-crystal GaN donor substrate so as to delimit a seed layer to be transferred; • the bonding of the donor substrate to the support substrate via the intermediate layer; • the detachment of the donor substrate along the embrittlement zone so as to transfer the seed layer of single-crystal GaN onto the support substrate.

[0022] Preferably, the process further comprises a step of forming a first epitaxial layer of single-crystal GaN on at least a portion of the seed layer, the first epitaxial layer and the seed layer together forming a buffer layer.

[0023] Advantageously, the process further comprises etching a portion of the intermediate layer and the buffer layer so as to expose a region of the supporting substrate.

[0024] Particularly advantageously, the process further comprises the epitaxial deposition of a single-crystal silicon layer on at least a part of the exposed region of the support substrate, the thickness of said silicon layer being equal to the sum of the thicknesses of the intermediate layer and the buffer layer.

[0025] Advantageously, the process further comprises manufacturing at least one electronic component on the region devoid of the intermediate layer and the buffer layer.

[0026] The invention also relates to a method for manufacturing a high electron mobility transistor, comprising: • the manufacture of a substrate by a process such as described above, • the formation, by epitaxy, of a transistor channel on the buffer layer, • the formation by epitaxy of a barrier layer forming a heterojunction with the canal, • the formation of a cover layer on the barrier layer, • the formation of a source electrode and a drain electrode electrically connected to the canal, • the formation of a gate electrode on the covering layer.

[0027] The invention also relates to a method for manufacturing an integrated substrate comprising at least one high electron mobility transistor and at least one electronic component, comprising implementing the method as described above for forming the transistor on a first region of the substrate and implementing the method as described above for forming the electronic component on a second region of the substrate, said method further comprising the formation of an electrically insulating wall between the electronic component and the high electron mobility transistor, said electrically insulating wall being in contact with the substrate support portion. DESCRIPTION OF THE FIGURES

[0028] Fig. 1 is a cross-sectional view of a known high electron mobility transistor.

[0029] Fig. 2A is a cross-sectional view of a high electron mobility transistor according to the invention.

[0030] Fig. 2B is a cross-sectional view of an integrated substrate comprising two high electron mobility transistors according to the invention.

[0031] The [Fig.3] is a substrate for the fabrication of a high electron mobility transistor according to the invention.

[0032] Fig. 4 illustrates a particular embodiment of the support substrate.

[0033] Fig. 5A illustrates a first embodiment of a first step in the formation of a substrate.

[0034] Fig. 5B illustrates a second embodiment of a first step in the formation of a substrate.

[0035] Fig. 6A illustrates a first embodiment of a second manufacturing step of a substrate according to the invention.

[0036] Fig. 6B illustrates a second embodiment of the second manufacturing step of a substrate according to the invention.

[0037] Figure [Fig. 6C] illustrates a third manufacturing step of a substrate according to the invention.

[0038] Figure 6D illustrates a fourth manufacturing step of a substrate according to the invention.

[0039] Fig. 7 illustrates a substrate comprising a GaN buffer layer.

[0040] Figure 8 illustrates a substrate comprising two high-mobility transistors of electrons according to the invention.

[0041] Figure 9 illustrates a substrate comprising two high electron mobility transistors according to the invention and a silicon layer on an exposed portion of the upper face of the support substrate.

[0042] Fig. 10 illustrates a substrate comprising two high electron mobility transistors and a plurality of electronic components.

[0043] Figure 11 illustrates the substrate of Figure 10, which further includes dielectric barriers between the electronic components and the transistors. DETAILED DESCRIPTION OF THE INVENTION

[0044] A HEMT transistor is shown in [Fig. 2A]. The transistor comprises, from its base to its surface, a support substrate 10 made of single-crystal silicon, an intermediate layer 20 made of silicon nitride (Si3N4), a buffer layer 35 made of single-crystal gallium nitride (GaN), a channel 45 made of single-crystal GaN, and a barrier layer 50 typically made of Al₂₅Ga₇₅N over the channel and forming a heterojunction with the channel 40. A cover layer 70, typically a thin layer of gallium nitride or silicon nitride (Si3N4) with a thickness between one monolayer and 100 nm, can be arranged on the barrier layer 50. The cover layer 70 is a passivation layer and also prevents oxidation of the barrier layer 50.

[0045] Source electrodes 61, drain electrode 62 and grid electrode 63 are arranged on the channel 40. The grid electrode 63 is arranged on the cover layer 70 between the source electrode 61 and the drain electrode 62.

[0046] Due to the heterojunction, a two-dimensional electron gas forms at the interface between the channel 45 and the barrier layer 50. This two-dimensional electron gas serves as a conduction channel within the HEMT transistor. The buffer layer 35 has a thickness between 1 and 10 pm and can be doped according to the desired HEMT properties. The buffer layer 35 helps to limit lateral and vertical leakage currents in the transistor and to better confine the two-dimensional electron gas of the heterojunction.

[0047] In certain embodiments, with reference to [Fig. 2B], one or more HEMTs are arranged on an integrated substrate. The integrated substrate has a single common support substrate 10 and may comprise one or more identical or different HEMTs 100A, 100B. Each HEMT comprises an intermediate layer 20a, 20b of respective silicon nitride arranged directly on the support substrate 10, and a buffer layer 35a, 35b of respective buffers arranged on each intermediate layer 20a, 20b. The channel, barrier layer, cover layer (not shown) and electrodes of each HEMT are arranged as described above for an isolated HEMT.

[0048] The integrated substrate further comprises one or more other electronic components 81, 82, 83 that can be arranged directly on the support substrate 10. Such electronic components are, for example, CMOS circuits such as HEMT gate control circuits, known as "drivers," circuits for measuring an electric current or the temperature of the HEMT, or any other electronic component that can be used in combination with or on the same device as the HEMT. Optionally, electrically insulating walls 90 can be arranged between the HEMTs and / or the respective other electronic components. The walls 90 can have a wide variety of geometries in the plane of the substrate, chosen according to the geometry of the components on the support substrate. The height of the walls 90 can also be chosen according to the electromagnetic fields that may be generated during the operation of the components on the integrated substrate.In general, each wall extends from the top face of the support substrate to a height greater than or equal to the height of the intermediate layer 20. Thus, the walls 90 ensure good electrical insulation between the electronic components and further suppress the crosstalk phenomenon between the HEMTs and other components.

[0049] The HEMT transistor or the integrated substrate comprising a HEMT is made from a substrate shown in [Fig.3]. The substrate comprises a support substrate 10, an intermediate layer 20 of silicon nitride (Si3N4), and a seed layer 30 of single-crystal gallium nitride (GaN).

[0050] The support substrate is made of monocrystalline silicon and typically has a thickness between 300 and 1100 |am.

[0051] In a main embodiment, the support substrate has an electrical resistivity between a few ohms and a few million ohms allowing the manufacture of most electronic components and also the manufacture of HEMTs.

[0052] In a particular embodiment, as illustrated in [Fig. 4], the support substrate 10 comprises a first portion 10A made of monocrystalline silicon. The support substrate further comprises a second portion 10B made of monocrystalline silicon having areas 11A having a first high electrical resistivity similar or equal to the electrical resistivity of the first portion, and areas 11B whose electrical resistivity is lower than the first resistivity. Said areas 11B extend over a portion of the upper face of the support substrate on which the electrical components will be fabricated. The areas 11B with low resistivity Electrical components enable the fabrication of certain electronic components requiring an electrically conductive substrate on an integrated substrate. Thanks to the different resistivities in different areas of the substrate, electronic components such as CMOS circuits, for example, HEMT drivers, or circuits enabling the control and / or measurement of parameters such as electric current or HEMT temperature, can be fabricated in monolithic integration with HEMTs on a single substrate.

[0053] The intermediate layer 20 ensures the bonding of the seed layer 30 to the substrate 10. Simultaneously, the intermediate layer 20 provides electrical insulation between the HEMT and other electronic components such as drivers or CMOS circuits that may be fabricated on the same substrate. Furthermore, the dielectric properties of the intermediate layer 20 ensure good HEMT performance, including a high blocking voltage of up to 1200 V, while guaranteeing good thermal conductivity between the HEMT and the substrate. For example, the thermal conductivity of silicon nitride is approximately ten times higher than the thermal conductivity of SiO2, which is used, for instance, in SOI-type substrates.

[0054] The intermediate layer 20 has a thickness between 0.5 and 3 µm. The chosen thickness will depend on the blocking voltage required for the HEMT to be fabricated on the substrate. Typically, a greater thickness of the intermediate layer results in higher blocking voltages for the HEMT. A maximum thickness of 3 µm allows for a blocking voltage of approximately 650 V for a HEMT of known and commonly used dimensions.

[0055] The thickness of the intermediate layer can also be adjusted according to the electrical insulation required in view of the electronic components to be integrated on the same substrate and the intensity of a possible disturbance during the operation of the HEMTs.

[0056] The seed layer 30 is a thin layer of single-crystal GaN, typically with a thickness between 10 nm and 1 pm, for example 300 nm. The seed layer 30 is bonded via the intermediate layer 20 to the upper face of the support substrate 10. The seed layer 30 is used for the deposition of a GaN layer by epitaxial growth in order to form the buffer layer of the HEMT.

[0057] We will now describe the manufacturing steps of such a HEMT transistor.

[0058] We begin by providing a support substrate 10. Typically, the support substrate is a standard single-crystal silicon substrate (100), as widely used in the semiconductor and electronics industries. The notation (100) refers to the crystallographic orientation of the substrate and indicates that the surface of the support substrate is parallel to the crystal plane (100) of the silicon crystal lattice.

[0059] In the case where the substrate includes 1 IB zones exhibiting low electrical resistivity, a portion of the substrate 10A with a first electrical resistivity is deposited, typically by epitaxial growth, a portion 10B onto the portion 10A. During this step, selective doping of silicon is carried out in one or more 1 IB zones in order to obtain low electrical resistivity in the selected zones as illustrated in [Fig.4], and simultaneously deposits the 1 IA zones lacking such doping.

[0060] For the fabrication of the GaN seed layer 30, a donor substrate is provided from which the single-crystal GaN seed layer will be formed. The donor substrate is typically a heterosubstrate, for example, a single-crystal GaN substrate on sapphire or a single-crystal GaN substrate on SiC. Such heterosubstrates are easier to fabricate than bulk substrates, particularly for substrate diameters greater than 4 inches (approximately 100 mm). Alternatively, a bulk single-crystal GaN substrate can be used.

[0061] An intermediate layer of Si3N4 is deposited on the support substrate and / or on the donor substrate. Figure 5A illustrates such an intermediate layer 20 of Si3N4 deposited on the donor substrate 300. Figure 5B illustrates a layer of Si3N420 deposited on the support substrate 10. Typically, the Si3N4 is deposited by chemical vapor deposition (CVD). In some embodiments, a single layer of Si3N4 is deposited either on a main face of the support substrate 10 or on a main face of the donor substrate 300.

[0062] Alternatively, and not shown, a thick layer, with a thickness close to the final thickness of the intermediate layer to be fabricated, is deposited either on the support substrate or on the donor substrate. A thin layer of Si3N4 is also deposited on the other substrate between the support substrate and the donor substrate. After bonding, the thick Si3N4 layer and the thin Si3N4 layer form a single intermediate layer of Si3N4 20. In other embodiments, layers of a certain thickness can be deposited on the support substrate and on the donor substrate. In all embodiments, the sum of the thicknesses of the respective intermediate layers corresponds to the thickness of the intermediate layer 20 and is between 0.5 and 3 µm.

[0063] Depositing Si3N4 on the top surface of the donor substrate has the advantage of encapsulating the GaN top surface of the donor substrate and protecting this surface against silicon migration. This advantage applies to the Si3N4 layers regardless of their thickness.

[0064] Typically, a surface treatment of each substrate comprising a Si3N4 layer is carried out after the deposition of the Si3N4, for example polishing to reduce the roughness of the Si3N4 face.

[0065] In order to prepare the transfer of the GaN seed layer 30 onto the support substrate 10, ionic species, such as hydrogen and / or helium, are implanted to form a weakening zone 31 in the donor substrate 300. In the case where a Si3N4 layer 20 is deposited on the donor substrate 300, as shown in [Fig. 6A], the implantation is carried out on the donor substrate 300 containing the Si3N4 layer, so that the weakening zone 31 is inside the donor substrate 300. When the Si3N4 layer is deposited only on the support substrate 10, the implantation is carried out directly in the donor substrate 300 as illustrated in [Fig. 6B].

[0066] With reference to [Fig.6C], the donor substrate 300, thus weakened, is glued onto the support substrate 10, so that the Si3N4 layer(s) are arranged at the interface between the support substrate 10 and the donor substrate 300, and form an intermediate layer of Si3N4.

[0067] This bonding can be carried out with or without the addition of material, typically under vacuum. Preferably, the bonding is achieved by atomic diffusion bonding (ADB) with the addition of silicon or tungsten. For example, a thin layer of silicon can be deposited on the donor substrate and the support substrate before bonding said substrates.

[0068] With reference to [Fig.6D], the donor substrate 300 is then detached along the embrittlement zone 31, which leads to the transfer of the single-crystal gallium nitride seed layer 30 onto the support substrate 10. The Si3N4 layer(s) form a single intermediate layer 20 at the interface between the support substrate 10 and the seed layer 30.

[0069] The remaining 301 of the donor substrate can be reused for the transfer of one or more other layers of single-crystal GaN onto other substrates.

[0070] Subsequently, with reference to [Fig.7], a first epitaxial layer 40 of GaN is deposited on the seed layer 30. The first epitaxial layer 40 and the seed layer 30 together form a buffer layer 35 of single-crystal GaN.

[0071] For the fabrication of a single HEMT, a channel 45 is formed directly by the epitaxial deposition of a second layer of single-crystal GaN. Generally, this layer is not intentionally doped. A barrier layer 50 is then deposited on the channel 45 as illustrated in [Fig. 2A]. Through this barrier layer 50, which forms a heterojunction with the channel, a two-dimensional gas electrons will be generated at the interface between barrier 50 and channel 45 allowing conduction of electrons within the transistor.

[0072] A cover layer (not shown) can then be deposited on the barrier layer 50. The cover layer is, for example, a p-doped GaN layer for a standard HEMT, or a thin layer of GaN and / or Si3N4 for a HEMT for radio frequency applications.

[0073] In a manner known per se, the source electrodes 61 and drain electrodes 62 are deposited on the barrier layer 50 and the channel 40 or on either side of the barrier layer 50, for example by etching through a mask, and then are subjected to annealing to form an ohmic contact with said barrier layer 50. The grid electrode 63 is typically deposited on the cover layer on the upper face of the barrier layer 50.

[0074] In the case of manufacturing an integrated substrate, selective etching of the substrate is carried out after the deposition of the first epitaxial layer 40. The etching allows, with reference to [Fig.8], to expose a region 102 of the support substrate in order to make one or more electronic components directly in the support substrate 10 in monocrystalline silicon.

[0075] After selective etching, one or more blocks, each composed of an intermediate layer 20A, 20B and a buffer layer 35A, 35B respectively, are stored in a first region 101 of the substrate. Each block can be used to manufacture a HEMT. The geometry of each block in the principal plane of the substrate can be chosen according to the HEMTs and electronic components to be manufactured and can be arbitrary. The geometry of the blocks can therefore be complex and is not limited to rectangular, square, or round shapes. A second region 102 of the substrate lacks the intermediate layer and the buffer layer and can be used for manufacturing electronic components other than HEMTs.

[0076] When the substrate support includes 1 IB zones exhibiting low resistivity as illustrated in [Fig.4], selective etching advantageously exposes at least said 11B zones.

[0077] In order to fabricate silicon electronic components on the upper surface of the integrated substrate, a layer of monocrystalline silicon 80 can optionally be deposited over all or part of the second region 102 of the support substrate 10, which lacks the intermediate and buffer layers. Such a layer of monocrystalline silicon 80 is illustrated in [Fig. 9]. The deposited monocrystalline silicon can have a doping profile adapted to the electronic components to be manufactured. Advantageously, the thickness of the monocrystalline silicon layer is substantially equal to the thickness of each block, i.e., to the sum of the thicknesses of the intermediate layer 20 of Si3N4 and the buffer layer 35. This allows all electronic components of the integrated substrate to have the same surface height, and facilitates substrate integration and electrical isolation between the different components.

[0078] With reference to [Fig.10], electronic components 81, 82, 83 can now be made in the second exposed region 102, preferably in the silicon layer 80 deposited in said region 102. HEMT transistors can be made in one or more blocks according to the steps described above for the fabrication of a single HEMT.

[0079] In a particularly advantageous manner, the procedure is carried out before or after the training HEMTs and other electronic components are protected by the deposition of one or more insulating walls 90 at least up to the height of the intermediate layer 20, as illustrated in [Fig. 1 1]. Preferably, such walls are made by depositing a dielectric material on an exposed region of the substrate, for example, silicon dioxide (SiO2) or silicon nitride (Si3N4). The size and shape of the walls 90 can be adapted to the geometry of the electronic components and, in particular, to the electrical voltages applied to the HEMTs during the operation of the integrated substrate. The insulating walls maximize the protection of the electronic components from disturbances caused by electromagnetic fields generated during HEMT switching. Consequently, the presence of these insulating walls increases the component density on the surface of a substrate. integrated. REFERENCES

[0080] EP2983195 Al

Claims

Demands

1. Substrate for the fabrication of a high electron mobility transistor (HEMT), comprising successively: • a support substrate (10) of single-crystal silicon, • an intermediate layer (20) of silicon nitride (Si3N4) having a thickness of between 0.5 and 3 pm, and • a seed layer (30) of single-crystal GaN, the intermediate layer (20) forming a bonding interface between the support substrate (10) and the seed layer (30).

2. Substrate according to claim 1, further comprising a first epitaxial layer (40) of single-crystal GaN on the seed layer (30), the first epitaxial layer (40) and the seed layer (30) together forming a buffer layer (35, 35a, 35b) of single-crystal GaN.

3. Substrate according to claim 2, wherein the buffer layer (35, 35a, 35b) has a thickness between 1 and 10 pm.

4. Substrate according to claim 2 or claim 3, further comprising a second unintentionally doped GaN epitaxial layer arranged on the buffer layer (35, 35a, 35b).

5. Substrate according to any one of claims 2 to 4, wherein the intermediate layer (20, 20a, 20b) and the buffer layer (35, 35a, 35b) are in the form of at least one block extending over only a first region (101) of the supporting substrate (10).

6. Substrate according to claim 5, wherein the intermediate layer (20, 20a, 20b) and the buffer layer (35, 35a, 35b) are in the form of a plurality of blocks, each block being adapted for the manufacture of a respective high electron mobility transistor.

7. Substrate according to claim 5 or claim 6, further comprising at least one electronic component (81, 82, 83) arranged on a second region (102) of the support substrate distinct from the first region (101).

8. Substrate according to claim 7, further comprising an electrically insulating wall (90) made of a dielectric material in contact with the substrate support portion (102), said electrically insulating wall (90) being arranged between each block (70) and a component electronic (81, 82, 83) arranged on the second region (102) of the support substrate.

9. Substrate according to claim 7 or claim 8, wherein the support substrate (10) comprises a first portion (10A) of monocrystalline silicon having a first electrical resistivity and a second portion (10B) of monocrystalline silicon extending over the first portion, said second portion (10B) comprising areas (11B) having a second electrical resistivity lower than the first electrical resistivity, at least one electronic component (81, 82, 83) arranged on an area (11B) having the second electrical resistivity.

10. High electron mobility transistor, comprising • a substrate according to any one of claims 3 to 9, • a GaN channel (45) arranged on the buffer layer (35), • a barrier layer (50) forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel, • a source electrode (61) and a drain electrode (62) electrically connected to the channel (45), • a gate electrode (63) formed on the barrier layer (50) such that the gate electrode (63) is physically isolated from the channel (45).

11. A method for manufacturing a substrate for a high electron mobility transistor according to any one of claims 1 to 9, said method comprising the following steps: • the deposition of at least one intermediate layer (20) of Si3 N4 on a support substrate (10) of single-crystal silicon and / or on a donor substrate (300) of single-crystal GaN, the sum of the thicknesses of the respective intermediate layers (20) being between 0.5 and 3 pm; • the formation of a weakening zone (31) by implanting ionic species in the donor substrate (300) of single-crystal GaN so as to delimit a seed layer to be transferred; • the bonding of the donor substrate (300) to the support substrate (10) via the intermediate layer (20); • the detachment of the donor substrate (300) along the embrittlement zone (31) so as to transfer the seed layer (30) of single-crystal GaN onto the support substrate.

12. A method for manufacturing a substrate according to claim 11, further comprising a step of forming a first epitaxial layer (40) of single-crystal GaN on at least a portion of the seed layer (20), the first epitaxial layer (40) and the seed layer (30) together forming a buffer layer (35).

13. A method for manufacturing a substrate according to claim 11 or claim 12, further comprising etching a portion of the intermediate layer (20) and the buffer layer (35) so as to expose a region (102) of the support substrate (10).

14. A method for manufacturing a substrate according to claim 13, further comprising the epitaxial deposition of a single-crystal silicon layer (80) on at least a portion of the exposed region (102) of the support substrate (10), the thickness of said silicon layer (80) being equal to the sum of the thicknesses of the intermediate layer (20) and the buffer layer (35).

15. Method of manufacturing a substrate according to claim 13 or claim 14, further comprising manufacturing at least one electronic component (81, 82, 83) on the region (102) devoid of the intermediate layer (20) and the buffer layer (35).

16. A method for manufacturing a high electron mobility transistor, comprising: • manufacturing a substrate by the method according to any one of claims 11 to 15, • forming by epitaxy a channel (45) of the transistor on the buffer layer (35), • forming by epitaxy a barrier layer (50) forming a heterojunction with the channel (45), • forming a cover layer on the barrier layer (70), • forming a source electrode (61) and a drain electrode (62) electrically connected to the channel (45), • forming a gate electrode (63) on the cover layer (70).

17. A method for manufacturing an integrated substrate comprising at least one high electron mobility transistor and at least one electronic component, comprising implementing the method according to claim 16 for forming the transistor on a first region (101) of the substrate and implementing the method according to claim 15 for forming the electronic component on a second region (102) of the substrate, said method further comprising forming an electrically insulating wall (90) between the electronic component (81, 82, 83) and the high electron mobility transistor, said electrically insulating wall (90) being in contact with the substrate support portion (102).

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