Pixel and distance sensor

Abstract

Pixel and Distance Sensor This description concerns a pixel (PIX). A circuit (CIRC1) provides, after each integration period corresponding to one emission period of an FMCW signal, first, second, third, and fourth signals (I, Q, Ic, Qc) representative of photogenerated charges in a photodetector (PD) for first, second, third, and fourth durations respectively, phase-shifted by π / 2 and repeated at an integration frequency (fs). A circuit (CIRC2) provides a fifth signal (IIc) determined by the difference of the first and third signals (I, Ic), and a sixth signal (QQc) determined by the difference of the second and third signals (Q, Qc). A circuit (CIRC3) compares the fifth and sixth signals (IIc, QQc) to a first voltage determined by a positive threshold and to a second voltage determined by a negative threshold. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Pixel and distance sensor technical field

[0001] This description relates generally to electronic circuits. This application relates more particularly to pixels for acquiring a distance to a scene and to sensors comprising such pixels, when the acquisition of distances is based on a frequency modulated continuous wave (FMCW) type measurement. Previous technique

[0002] For a FMCW-type distance measurement, a frequency-modulated continuous wave light signal is emitted by a coherent light source, for example, a laser, for a chirp duration. An optical device transmits part of the light signal, for example, half of the optical power emitted by the source, towards a scene, and the other part of the light signal, for example, the other half of the optical power emitted by the source, towards a pixel. The light signal transmitted towards the scene is reflected by the scene. The resulting reflected light signal is superimposed on, or added to, the light signal that the optical device transmitted directly to the pixel. The superposition of these two light signals results in a periodic light signal at a frequency fR, commonly called the beat frequency.

[0003] For a given duration T of the emission period and an amplitude B of the frequency modulation of the optical frequency FL of the laser, that is to say a slope B / T of frequency modulation of the light signal emitted by the source, the frequency fR is equal to (2.zB) / (cT) for this emission period, with c the speed of light and z the distance between an output of the optical device providing the part of the light signal sent towards the scene and a point of the scene having reflected this light signal in the direction of the pixel, this point being called the point of the scene associated with the pixel.

[0004] Thus, knowing B, T and fR, it is possible to deduce, for example, to calculate the distance z between the pixel and the point of the scene associated with that pixel.

[0005] However, known pixels and sensors implementing distance measurements based on FMCW technology have several drawbacks. Summary of the invention

[0006] There is a need for a pixel and for a sensor comprising a plurality of pixels adapted to the implementation of distance measurements based on FMCW technology which overcome at least some of the disadvantages of known pixels and known sensors implementing such distance measurements.

[0007] For example, it would be desirable to have a pixel and a sensor adapted to the implementation of distance measurements based on FMCW technology which allow a given beat frequency fR to be detected more precisely, less bulkily, less complexly and / or faster than in known pixels and sensors adapted to the implementation of distance measurements based on FMCW technology.

[0008] An embodiment overcomes all or part of the drawbacks of known pixels and sensors configured to implement distance measurements based on FMCW technology.

[0009] One embodiment provides for a pixel (PIX) comprising: at least one photodetector; a first circuit configured to provide, after each integration period corresponding to a period of emission of a frequency-modulated continuous wave light signal, first, second, third and fourth signals representative of a quantity of photogenerated charges in said at least one photodetector during respectively first, second, third and fourth durations of the integration period repeated at an integration frequency, the second durations being phase-shifted by n / 2 with respect to the first durations, the third durations being phase-shifted by II with respect to the first durations, the fourth durations being phase-shifted by 3*n / 2 with respect to the first durations, and the first, second, third, and fourth durations all having the same duration; a second circuit configured to provide a fifth signal determined by the difference between the first and third signals, and a sixth signal determined by the difference between the second and third signals; and a third circuit configured to: - compare each of the fifth and sixth signals to a first voltage determined by a positive threshold and to a second voltage determined by a negative threshold, the positive and negative thresholds having the same absolute value.

[0010] Another embodiment provides for a sensor comprising: one or more pixels (PIX) as defined above; a coherent light source configured to provide, at each emission period, the frequency-modulated continuous wave light signal; an optical device configured, at each emission period, to emit a first part of the frequency-modulated continuous wave signal towards a scene and a second part of the frequency-modulated continuous wave light signal towards each pixel, such that a light signal received by each pixel corresponds to the superposition of the second part of the frequency-modulated continuous wave light signal. frequency and a reflection by a point of the scene associated with the pixel of the first part of the frequency-modulated continuous wave light signal.

[0011] According to one embodiment, the sensor includes a control circuit configured to control several emission periods of the frequency-modulated continuous wave signal and, at each of said several emission periods, to maintain a constant slope of the frequency modulation of the frequency-modulated continuous wave light signal and to modify a value of the integration frequency.

[0012] According to one embodiment, the sensor includes a control circuit configured to control several emission periods of the frequency-modulated continuous wave signal, and, at each of said several emission periods, to maintain a constant value of the integration frequency and modify a slope of the frequency modulation of the frequency-modulated continuous wave light signal.

[0013] According to one embodiment, after each integration period, the third circuit of each pixel is further configured to provide an active detection signal if one and / or the other of the fifth and sixth signals is greater than the first voltage or less than the second voltage.

[0014] According to one embodiment, the first, second and third circuits are configured so that, after each integration period, the detection signal is active: if the difference between the first and third signals is, in absolute value, greater than the absolute value of the positive and negative thresholds; and / or if the difference between the second and fourth signals is, in absolute value, greater than the absolute value of the positive and negative thresholds.

[0015] According to one embodiment: The sensor includes an address event readout circuit; and Each pixel includes an output circuit configured to detect that the detection signal is active and to provide, following detection that the detection signal is active, a pixel address signal to the address event readout circuit, the output circuit and the address event readout circuit being preferably configured to communicate with each other according to a handshake protocol.

[0016] According to one embodiment, the sensor includes a control circuit configured to: maintain the integration frequency constant during an acquisition period; and during the acquisition period, for an increasing integer index i from 0 to N-1, with N a strictly positive integer, and, for each value of the index i, for a decreasing index u from U to 0, with U a strictly positive integer, to control, for each pair of indices i and u, a period of emission of the frequency-modulated continuous wave signal with a frequency modulation excursion equal to B0 / (k'.(2.u+l)), with BO a frequency excursion value determined by an initial value of distance to be detected and k a positive resolution value, preferably only if, for an integer q from 1 to U, logk(2.q+l) is different from ij, with j an integer index from 0 to i-1.

[0017] According to one embodiment, the sensor includes a control circuit configured to maintain a constant frequency modulation slope at each emission period of an acquisition period; and during the acquisition period, for an increasing integer index i from 0 to N-1, with N a strictly positive integer, and, for each value of the index i, for a decreasing index u from U to 0, with U a strictly positive integer, to control, for each pair of indices i and u, an emission period of the frequency-modulated continuous wave signal and a value of the integration frequency equal to k'.fs0 / (2.u + 1) with fs0 an integration frequency value determined by an initial value of the distance to be detected (Z0) and k a positive resolution value, preferably only if, for q an integer from 1 to U, logk(l / (2.q+l)) is different from ij, with j an integer index from 0 to i-1. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1] represents, schematically and in block form, an example of an embodiment of a pixel;

[0020] [Fig.2] illustrates by means of a chronogram the operation of a circuit of the pixel of [Fig.1];

[0021] [Fig.3] illustrates by means of curves the operation of another circuit of the pixel of [Fig.1];

[0022] [Fig.4] represents an example of implementation of the pixel of [Fig.1];

[0023] [Fig.5] illustrates by means of chronograms an operation of the pixel of [Fig.4];

[0024] [Fig. 6] represents another example of the implementation of two pixel circuits of the [Fig.4];

[0025] [Fig.7] represents another example of implementation of a pixel circuit of [Fig.4];

[0026] Fig. 8 represents another example of the implementation of a pixel circuit of Fig. 1;

[0027] [Fig.9] represents another example of implementation of a pixel circuit of [Fig.1];

[0028] [Fig. 10] represents yet another example of the implementation of a pixel circuit of [Fig. 1];

[0029] [Fig.1 1] illustrates by means of chronograms one of operation of an optoelectronic system comprising the pixel of [Fig.1];

[0030] [Fig. 12] illustrates by means of timing diagrams another example of the operation of an optoelectronic system including the pixel of [Fig. 1];

[0031] [Fig. 13] illustrates by means of chronograms yet another example of the operation of an optoelectronic system comprising the pixel of [Fig. 1];

[0032] [Fig. 14] illustrates by means of chronograms yet another example of the operation of an optoelectronic system comprising the pixel of [Fig. 1];

[0033] [Fig. 15] illustrates by means of chronograms yet another example of the operation of an optoelectronic system comprising the pixel of [Fig. 1];

[0034] [Fig. 16] illustrates by means of timing diagrams yet another example of the operation of an optoelectronic system comprising the pixel of [Fig. 1]; and

[0035] [Fig. 17] illustrates an example of implementation of a pixel circuit of [Fig. 1]. Description of the implementation methods

[0036] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0038] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0039] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to a ... in a normal position of use.

[0040] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0041] [Fig. 1] schematically represents, in block form, an example of an embodiment of a PIX pixel. Although not illustrated in [Fig. 1], this PIX pixel can be part of a PIX pixel matrix of a distance sensor.

[0042] The PIX pixel comprises at least one PD photodetector, for example at least one photodiode. In the example of [Fig. 1], the PIX pixel comprises a single PD photodetector.

[0043] Each photodetector PD of the pixel PIX is configured to receive a light signal sigL. The sigL signal corresponds to a superposition of a portion of a frequency-modulated continuous wave light signal and another portion of the frequency-modulated continuous wave light signal that was emitted towards a scene and reflected by a point in the scene associated with the pixel PIX before reaching that pixel PIX. The sigL signal therefore has a beat frequency fR determined at least in part by the distance z between the pixel PIX and the point in the scene associated with the pixel PIX. For example, the beat frequency is determined by the distance z and by the distance traveled by the reference portion of the light signal that is sent directly to the pixel, from the optical device splitting the light signal into two parts, until this reference portion overlaps with the portion of the light signal resulting from a reflection on the scene to be imaged.For example, since the distance traveled by the reference part of the optical signal is very small compared to the distance z, the latter is negligible compared to the distance z and the beat frequency is then considered to be entirely determined by the distance z. c.

[0044] Although not illustrated in [Fig. 1], in practice the PIX pixel is part of an optoelectronic system, for example called a distance sensor, comprising a coherent light source, for example a laser source, configured to provide a first frequency-modulated continuous wave light signal. More specifically, the first signal has its frequency fL varying continuously and linearly (or substantially linearly) over a frequency range of extent B, B also being called the amplitude or excursion of the frequency modulation. This frequency modulation of the first signal occurs continuously and linearly (or substantially linearly) over the entire duration T during which the first signal is emitted by the source, that is to say, over the entire duration T of the emission period (or duration). Thus, the slope of the frequency modulation of the first light signal is equal to B / T.

[0045] Furthermore, although not illustrated in [Fig. 1], the optoelectronic system or sensor comprising the PIX pixel and the coherent light source emitting the first light signal includes an optical device. The optical device is configured to separate the first signal into a second signal and a third signal, to emit the second signal towards a scene, and to provide the third signal, also called the reference signal, at the PIX pixel, that is to say at the photodetector(s) of the PIX pixel. At the level of the PIX pixel, the third signal is superimposed with a signal corresponding to the reflection by the scene of the second signal, for example by means of another optical device, and the sigL signal corresponds to this superposition of two light signals.

[0046] Thus, the frequency fR of the signal sigL is entirely determined by the slope B / T of the frequency modulation for this emission period and by the distance z at which the point of the scene associated with the pixel is located during this emission period.

[0047] The PIX pixel includes a CIRC1 circuit. The CIRC1 circuit is coupled, for example connected, to each PD photodetector of the PIX pixel. By way of example, each PIX pixel photodetector has one electrode, for example its anode, connected to a reference potential, for example ground GND, and another electrode, for example its cathode, coupled, preferably connected, to the CIRC1 circuit, that is to say to a corresponding input of the CIRC1 circuit.

[0048] At each emission period, the PIX pixel, and, more particularly its CIRC1 circuit, are configured to implement a corresponding integration period of the sigL signal, or, more simply put, a corresponding integration of the sigL signal.

[0049] At each integration period of the sigL signal, the CIRC1 circuit is configured to provide, at the end of integration periods (or durations), four signals I, le, Q, and Qc. These signals can be provided simultaneously and / or sequentially to a CIRC2 circuit of the PIX pixel, as will be illustrated later with examples of CIRC1 circuit implementations. By way of example, each integration period (or duration) has a duration equal to the corresponding duration T of emission of the FMCW light signal.

[0050] More specifically, the CIRC1 circuit is configured so that the signal I is representative of, or determined by, a quantity of photogenerated charges in one of the photodetectors of the pixel PIX (in the single photodetector PD in the example of [Fig. 1]) for durations DI of the integration period. The durations DI are periodic and are repeated at a frequency fs called the integration frequency.

[0051] Similarly, the CIRC1 circuit is configured so that the signal Q is representative of, or determined by, a quantity of photogenerated charges in one of the photodetectors of pixel PIX (in the single photodetector PD in the example of [Fig. 1]) for durations D2 of the integration period. The durations D2 are, like the durations Δ1, periodic at the frequency fs. Furthermore, one duration of each duration D2 is equal to one duration of each duration Δ1. In other words, the durations D1 and D2 each have the same duration. The durations D2 are phase-shifted by 1 / 2 with respect to the durations Δ1

[0052] The CIRC1 circuit is further configured so that the signal is representative of, or determined by, a quantity of photogenerated charges in one of the photodetectors of pixel PIX (in the single photodetector PD in the example of [Fig. 1]) for durations D3 of the integration period. The durations D3, like the durations DI and D2, are periodic at the frequency fs. In addition, the durations D1, D2, and D3 each have the same duration. The durations D3 are phase-shifted by II with respect to the durations DL

[0053] Finally, the CIRC1 circuit is configured so that the signal Qc is representative of, or determined by, a quantity of photogenerated charges in one of the photodetectors of pixel PIX (in the single photodetector PD in the example of [Fig. 1]) for durations D4 of the integration period. The durations D4, like the durations D1, D2, and D3, are periodic at the frequency fs. Furthermore, the durations D1, D2, D3, and D4 each have the same duration. The durations D4 are phase-shifted by 3.1 / 2 with respect to the durations D1.

[0054] Thus, the CIRC1 circuit integrates, at the integration frequency fs, the photogenerated charges in the pixel PIX by the signal sigL along four channels, or phases, providing the respective signals I, le, Q and Qc corresponding to the respective durations Dl, D3, D2 and D4. The four channels providing the respective signals I, le, Q and Qc are, for example, called in-phase channel, complementary phase channel, quadrature channel, and complementary quadrature channel.

[0055] The CIRC1 circuit therefore receives control signals of durations D1, D2, D3 and D4, these control signals being timed at the frequency fs.

[0056] [Fig.2] illustrates by means of a timing diagram the operation of the CIRC1 circuit of pixel PIX of [Fig.1],

[0057] In this example, the integration frequency fs is equal to the beat frequency fR of the signal sigL.

[0058] Furthermore, in this example where the PIX pixel includes only one PD photodetector, the durations Dl, D2, D3, and D4 have, for example, a duration equal to Ts / 4, with Ts the repetition period of the durations Dl, D2, D3 and D4 which is equal to 1 / fs.

[0059] As can be seen in [Fig. 2], the signal sigL comprises a DC component sigLDC and an AC component sigLAC (the sigLDC component and the envelope of the signal sigL are schematically represented in [Fig. 2]). The useful part of the signal sigL is its AC component sigLAC.

[0060] Returning to [Fig.1], as previously indicated, the CIRC2 circuit receives the signals I, Q, le and Qc after each integration period of the photogenerated charges by the signal sigL in the pixel PIX.

[0061] The CIRC2 circuit is configured to suppress the influence of the DC component sigLDC in the I, Q, le, and Qc signals. To this end, the CIRC2 circuit is configured to provide Ile and QQc signals. More specifically, the Ile signal is determined by the difference between the I and le signals, while the QQc signal is determined by the difference between the signals Q and Qc. For example, the signal Ile is determined by the difference I-Ic (or Ic-I) and the signal QQc is determined by the difference Q-Qc (or Qc-Q). As an example, the signal Ile is equal to the difference I - I (or Ic-I) plus a fixed VCL offset, the signal QQc being equal to the difference Q - Qc (or Qc - Q) plus the fixed VCL offset.

[0062] According to one embodiment, the CIRC2 circuit comprises a capacitor having a first electrode selectively coupled to a continuous potential VCL. By way of example, the potential VCL can be any fixed potential, and is, for example, a zero potential.

[0063] The CIRC2 circuit is then configured to apply a signal determined by signal I to a second electrode of the capacitor while the first electrode is coupled to the potential VCL and is therefore at a potential at least partially determined by the potential VCL, and then to apply another signal determined by signal Ie to the second electrode of the capacitor while the first electrode is decoupled from the potential VCL, or, in other words, left floating. As a result of these two operations, a voltage across the first floating electrode of the capacitor is determined by the difference Lie and the potential VCL. This voltage then corresponds to signal Ile.

[0064] Similarly, the CIRC2 circuit is configured to apply a signal determined by the Q signal to a second electrode of another capacitance while the first electrode of this other capacitance is coupled to the potential VCL and is therefore at a potential at least partly determined by the potential VCL, and then to apply another signal determined by the Qc signal to the second electrode of this other capacitance while the first electrode of this other capacitance is left floating, so that, as a result of these two operations, a voltage on the first floating electrode of this other capacitance is determined by the difference Q-Qc and by the potential VCL and corresponds to the QQc signal.

[0065] Alternatively, rather than providing another capacitance to generate the QQc signal, this signal can be generated using the same capacitance as that used to generate the Ile signal, the Ile and QQc signals then being produced sequentially by the CIRC2 circuit.

[0066] The Ile and QQc signals are supplied to a CIRC3 circuit of the PIX pixel.

[0067] By way of example, the two signals Ile and QQc are supplied simultaneously to the circuit CIRC3, for example when the CIRC2 circuit includes a capacitor to generate the Ile signal and another capacitor to generate the QQc signal and the two Ile and QQc signals are produced in parallel by the CIRC2 circuit.

[0068] As an alternative example, the two signals are supplied one after the other to the CIRC3 circuit, for example when the CIRC2 circuit includes a single capacitor to generate the Ile signal, then the QQc signal (or vice versa).

[0069] The CIRC3 circuit is configured to compare the difference between the signals I and Qc at two thresholds VTH+ and VTH- having opposite signs but the same absolute value. For example, the threshold VTH+ is positive, and the threshold VTH- is negative. To do this, the CIRC3 circuit compares the signal I to a voltage V+ determined by the threshold VTH+ and to a voltage V- determined by the threshold VTH-. For example, the voltage V+ is determined by the threshold VTH+ and the potential VCL, and the voltage V- is determined by the threshold VTH- and the potential VCL. For example, the voltage V+ is equal to VCL + VTH+ and the voltage V- is equal to VCL + VTH-. The CIRC3 circuit is further configured to compare the difference between the signals Q and Qc at the two thresholds VTH+ and VTH-. To do this, the CIRC3 circuit compares the signal QQc to the voltages V+ and V-.According to one embodiment, the CIRC3 circuit includes at least one comparator, and the four comparisons described above are implemented by this comparator or these comparators of the CIRC3 circuit.

[0070] According to one embodiment, the thresholds VTH+ and VTH- are determined (or predetermined) such that the difference between signals I and the is greater than VTH+ or less than VTH- and / or the difference between signals Q and Qc is greater than VTH+ or less than VTH- when the frequency fR of the signal sigL is equal to the integration frequency fs. In other words, the absolute value of the thresholds VTH+ and VTH- is determined (or predetermined) such that the absolute value of one or both of the differences between signals I and the and between signals Q and Qc is greater than the absolute value of the thresholds VTH+ and VTH- when the beat frequency fR of the signal sigL is equal to the integration frequency fs.Put another way, the VTH+ and VTH- thresholds are determined (or predetermined) so that when either the Ile and QQc signals are greater than the V+ voltage and / or less than the V- voltage, it means that the sigL signal received by the PIX pixel has a beat frequency fR equal to the integration frequency fs. For example, the VTH+ and VTH- thresholds are determined during the design of the optoelectronic system, or sensor, that includes the PIX pixel. Alternatively, the VTH+ and VTH- thresholds are determined internally within the optoelectronic system, or sensor, that includes the PIX pixel; for example, they may be adapted according to the current transmission period.

[0071] By way of example, a person skilled in the art will be able to determine the absolute value of the VTH+ and VTH- thresholds, for example during a calibration phase or empirically.

[0072] Figure [Fig. 3] illustrates by curves the operation of the CIRC3 circuit of pixel PIX of [Fig. 1],

[0073] More specifically, [Fig.3] illustrates: - by curves 300 and 302 the evolution respectively of the difference between the signals I and the and of the difference between the signals Q and Qc as a function of the phase Phi between the signal at the frequency fs and the signal at the frequency fR when fR is equal to fs, or, in other words, as a function of the phase Phi between the signal reflected by the scene and the reference signal. - by curves 304 and 306 the evolution respectively of the difference between the signals I and the and of the difference between the signals Q and Qc as a function of the phase Phi between the signal at the frequency fs and the signal at the frequency fR when fR is equal to 3 times the frequency fs, - by curves 308 and 310 the evolution of the difference between signals I and le and of the difference between signals Q and Qc as a function of the phase Phi between the signal at frequency fs and the signal at frequency fR when fR is equal to 5 times the frequency fs.

[0074] Furthermore, although this is not visible in [Fig. 3], the difference between signals I and le and the difference between signals Q and Qc each have a value of zero or almost zero, regardless of the phase Phi when the frequency fR is equal to 1.001*fs or to 0.99*fs.

[0075] Thus, [Fig.3] shows that, regardless of the phase Phi, the difference between the signals I and the and / or the difference between the signals Q and Qc are, in absolute value, greater than the absolute value of the thresholds VTH+ and VTH- only when the beat frequency fR is equal to the integration frequency fs.

[0076] Referring back to [Fig. 1], according to one embodiment, the CIRC 3 circuit of the PIX pixel is configured to provide a detection signal det indicating whether or not the difference between the signals I and Q and / or the difference between the signals Q and Qc are, in absolute value, greater than the absolute value of the thresholds VTH+ and VTH-. For example, the signal det is active when one and / or the other of the signals I and Qc is greater than the voltage V+ or less than the voltage V-. In other words, the signal det is active if: - the signal Ile is greater than the voltage V+ or less than the voltage V-; and / or - the QQc signal is greater than the voltage V+ or less than the voltage V-.

[0077] Preferably, the active or inactive state of the det signal is valid only when an ENB signal is active.

[0078] According to one embodiment, the pixel PIX includes an output circuit CIRC4. The CIRC4 circuit receives the det signal from the CIRC3 circuit.

[0079] The CIRC4 circuit configured to provide, to a reading circuit of a system comprising the PIX pixel, for example to a reading circuit of a sensor comprising a matrix of PIX pixels, an indication that the PIX pixel has received a sigL signal at the frequency fR equal to fs for a given integration period, i.e. for a given emission period of the FMCW signal.

[0080] For example, the CIRC4 circuit is configured to implement, with the system's read circuit comprising the PIX pixel, an event-driven read of the PIX pixel. For example, the CIRC4 circuit is configured to provide the system's read circuit with a req signal indicating the address of the PIX pixel when the det signal is active. More specifically, the CIRC4 circuit provides the req signal with the address of the PIX pixel as soon as the det signal becomes active and as long as the read circuit does not provide an acknowledgment signal ack to the CIRC4 circuit. The ack signal provided by the read circuit indicates to the CIRC4 circuit that the read circuit has received the information that the PIX pixel has detected a sigL signal at the frequency fR equal to fs.

[0081] As an alternative example, the CIRC4 circuit is configured to implement, with the system's readout circuit comprising the PIX pixel, a readout of the PIX pixel during which the CIRC4 circuit indicates to the system's readout circuit whether or not the PIX pixel detected a sigL signal at the frequency fR equal to fs during one or more of the last integration periods, only when the readout circuit queries (or selects or reads) the CIRC4 circuit of the PIX pixel. For example, in a sensor comprising a PIX pixel array, this allows for the implementation of a sequential readout of the PIX pixels in the array, for example, a line-by-line readout.

[0082] According to one embodiment, a sensor is provided comprising one or more PIX pixels, for example a PIX pixel array, and further comprising a control circuit configured to control several emission periods of the FMCW signal by a coherent light source of the sensor. By way of example, this control circuit is configured to control, for each emission period of the FMCW signal, the value of the slope B / T of the frequency modulation of the FMCW signal emitted by the light source and / or the value of the integration frequency fs.

[0083] According to one embodiment, the control circuit is configured to maintain a constant B / T slope during a plurality of FMCW signal transmission periods and, at each of these multiple transmission periods, to modify the value of the integration frequency fs. Thus, each of these multiple transmission periods will allow the detection of a different distance from the sensor to a scene.

[0084] For example, if a first transmission period is performed with a value A0 of the ratio 2.B / (cT), and the frequency fs has a value f0, then a pixel PIX will provide, at the end of a corresponding integration period, an active det signal when this pixel is at a distance z0 = f0 / AO from the scene point associated with this pixel. Furthermore, if a second transmission period is performed with the same value A0 of the ratio 2.B / (cT) but with a frequency fs having a value fl, then the pixel PIX will provide, at the end of the corresponding integration period, an active det signal when this pixel is at a distance zl = fl / AO from the scene point associated with this pixel.

[0085] According to one embodiment, the control circuit is configured to maintain a constant frequency fs during several emission periods of the frequency-modulated continuous wave light signal, and, at each of these several emission periods, to modify the B / T slope of the modulation of the emitted light signal. Thus, each of these several emission periods will allow the detection of a different distance from the sensor to a scene.

[0086] For example, if a first emission period is performed with a value AO of the ratio 2.B / (cT), and the integration frequency fs has a value f0, then a pixel PIX will provide, at the end of a corresponding integration period, an active det signal when this pixel is at a distance zO = fO / AO from the scene point associated with this pixel. Furthermore, if a second emission period is performed with the same value fO of the integration frequency fs, but with a value Al of the ratio 2.B / (cT), then the pixel PIX will provide, at the end of the corresponding integration period, an active det signal when this pixel is at a distance zl = fO / Al from the scene point associated with this pixel.

[0087] In the PIX pixel, the CIRC3 circuit compares each of the signals I1 and QQc to the voltages V+ and V- to compare the absolute value of the difference between the signals I1 and I1 to the absolute values ​​of the thresholds VTH+ and VTH-, and the absolute value of the difference between the signals Q and Qc to the absolute values ​​of the thresholds VTH+ and VTH-. It could have been considered to replace the CIRC3 circuit with a circuit configured to calculate the root mean square (RMS) of the difference between the signals I1 and I1, and of the difference between the signals Q and Qc, and to compare the calculated RMS to a threshold VTHmq. The calculated RMS would then have been greater than the threshold VTHmq when the frequency fR of the signal sigL was equal to the integration frequency fs.

[0088] However, this would have required a more complex circuit than the CIRC3 circuit and a larger one than the CIRC3 circuit, which is not desirable, for example in a sensor comprising a PIX pixel matrix.

[0089] Furthermore, the root mean square calculation implemented by such a circuit would have been slower than the implementation of the comparisons of the Ile and QQc signals with the V+ and V- voltages. For example, the root mean square calculation time would not have been compatible with video stream capture applications, whereas the PIX pixel is suitable for such applications.

[0090] Fig. 4 represents an example of implementation of the PIX pixel of Fig. 1.

[0091] In the embodiment of [Fig. 4], the PIX pixel comprises only one PD photodetector.

[0092] In the embodiment of [Fig. 4], regardless of the fact that the pixel PIX comprises only one photodetector PD, the circuit CIRC1 is a circuit operating in the charge domain. The PD photodetector is then preferably a pinned photodiode.

[0093] In the embodiment of [Fig.4], independently of the fact that the pixel PIX includes only one photodetector PD and that the circuit CIRC1 operates in the charge domain, the circuit CIRC2 includes only one capacitor to generate the Ile and QQc signals.

[0094] In the embodiment of [Fig.4], independently of the fact that the pixel PIX includes only one photodetector PD, that the circuit CIRC1 operates in the charge domain, and that the circuit CIRC2 includes only one capacitor to generate the Ile and QQc signals, the circuit CIRC3 includes two comparators to implement the comparisons of the Ile and QQc signals to the voltages V+ and V-.

[0095] More particularly, in the embodiment of [Fig.4], the CIRC1 circuit comprises four transfer grids 400, 402, 404 and 406, each having a conduction terminal connected to the PD photodetector.

[0096] The gate 400 has its second conduction terminal connected to a memory 408, for example represented as a capacitor in [Fig. 4]. In addition, a control terminal of the gate 400 receives a control signal TI. The memory 408 is coupled to a read node SN of the CIRC1 circuit by a transfer gate 410 controlled by an RL signal

[0097] The gate 402 has its second conduction terminal connected to a memory 412, for example represented as a capacitor in [Fig. 4]. In addition, a control terminal of the gate 402 receives a control signal Tic. The memory 412 is coupled to the read node SN by a transfer gate 414 controlled by a signal RIc.

[0098] The gate 404 has its second conduction terminal connected to a memory 416, for example represented as a capacitor in [Fig. 4]. In addition, a control terminal of the gate 404 receives a control signal TQ. The memory 416 is coupled to the read node SN by a transfer gate 418 controlled by a signal RQ.

[0099] The gate 406 has its second conduction terminal connected to a memory 420, for example represented as a capacitor in [Fig. 4]. In addition, a control terminal of the gate 406 receives a control signal TQc. The memory 420 is coupled to the read node SN by a transfer gate 422 controlled by a signal RQc.

[0100] The signals TI, TQ, Tic and TQc are periodic at the frequency fs and allow the implementation of the respective integration times D1, D2, D3 and D4.

[0101] The CIRC1 circuit further includes an ITrst switch controlled by an rst signal. The ITrst switch is connected between the SN node and a continuous reset potential RST. When the ITrst switch is turned on, the SN node potential is initialized to the RST potential.

[0102] The CIRC1 circuit further includes a MOS (metal oxide semiconductor) transistor, referenced MSF in [Fig. 4]. The MSF transistor has its gate coupled, e.g., connected, to the SN node. The MSF transistor is coupled in series with a 424 current source configured to supply a bias current to the transistor, between a supply potential VDD and the reference potential GND. In this example, the VDD potential is referenced to the GND potential and is positive, the 424 current source is connected between the source of the MSF transistor and the GND potential, and the drain of the MSF transistor is coupled, e.g., connected, to the VDD potential. The MSF transistor is thus an N-channel MOS transistor.However, in other examples not shown, the MSF transistor can be replaced by a P-channel MOS transistor, for example when the 424 current source is connected between the source of the MSF transistor and the VDD potential, and the drain of the MSF transistor is coupled, preferably connected, to the GND potential.

[0103] In this example, the MSF transistor is configured to provide the I, le, Q and Qc signals sequentially on its source.

[0104] In the embodiment of [Fig. 4], the CIRC2 circuit includes a capacitor Cdiff. A first electrode 423 of the capacitor Cdiff is coupled, for example connected, to the output of the CIRC1 circuit, i.e., to the source of the MSF transistor in this example. A second electrode 425 of the capacitor Cdiff is selectively coupled to a DC potential VCL by a switch ITdiff. In the example of [Fig. 4], the switch ITdiff is connected between the potential VCL and electrode 425.

[0105] The second electrode 425 of the capacitor Cdiff constitutes, in this example, the output of the CIRC2 circuit providing the Ile and QQc signals. In this example, the Ile and QQc signals are provided sequentially.

[0106] In the embodiment of [Fig. 4], the CIRC3 circuit comprises two comparators, COMP1 and COMP2. Comparator COMP1 is configured to compare the signal Ile or QQc that it receives to the voltage V+. Comparator COMP2 is configured to compare the signal Ile or QQc that it receives to the voltage V-.

[0107] By way of example, the comparator outputs are supplied to a 428 circuit of the CIRC3 circuit. The 428 circuit is controlled by an ENB enable circuit. The 428 circuit is configured to receive the binary outputs of comparators COMP1 and COMP2 and to supply, when the ENB signal is active, the active det signal if either of comparators COMP1 and COMP2 indicates that the Ile or QQc signal that it receives is greater than VTH+ or less than VTH-. As an example, the active or inactive state of the det signal is then valid when the ENB signal is active.

[0108] By way of example, the 428 circuit comprises two NOR gates. One NOR gate has an input coupled to the output of comparator COMP1, an input coupled to the output of comparator COMP2, and an input connected to the output of the second NOR gate. The second NOR gate has an input connected to the output of the first NOR gate, an input receiving the ENB signal, and its output providing the det signal.

[0109] As an alternative example, circuit 428 is omitted, and the ENB signal is supplied to comparators COMP1 and COMP2, such that the comparator outputs are updated only when the ENB signal is active. In other words, comparators COMP1 and COMP2 are then latched comparators on the ENB signal. A logic circuit is provided, for example, to supply the det signal from the outputs of comparators COMP1 and COMP2. For example, the active or inactive state of the det signal is then valid when the ENB signal is active. For example, in the example in [Fig. 4], the logic circuit supplying the det signal from the comparator outputs is an OR logic gate, although, in other examples where the high and low levels of the comparator outputs are inverted, this logic circuit could be an AND logic gate.

[0110] As another alternative example, comparators COMP1 and COMP2 can be replaced by a single comparator.

[0111] For example, in a single comparator case, during a phase comparing the signal Ile to V+, one of the two inputs of this single comparator receives the signal Ile, and the other of the two inputs of the single comparator receives the voltage V+. Then, during a phase comparing the signal Ile to V-, one of the two inputs of the single comparator receives the signal Ile and the other of the two inputs of the single comparator receives the voltage V-. The implementation of comparing the signal QQc to the voltages V+ and V- is implemented similarly to that described above and is within the grasp of a person skilled in the art based on the description given above.

[0112] By way of example, in [Fig. 4], the PIX pixel includes the CIRC4 circuit, which is configured to implement an event readout. For example, the CIRC4 circuit includes a 430 circuit configured to detect an active state of the det signal and a 432 circuit coupled to the output of the 430 circuit and configured to provide the pixel address to an AER (Address Event Readout) type readout circuit, not shown in [Fig. 4], when the 430 circuit detects an active state of the det signal. Preferably, the CIRC4 circuit and the readout circuit then communicate with each other using a handshake protocol.

[0113] Although not illustrated in [Fig. 4], in practice the PIX pixel includes a control circuit configured to provide it with all its control signals. This control circuit is, for example, shared by several PIX pixels, for example by all the PIX pixels of a sensor comprising several PIX pixels.

[0114] Figure 5 illustrates, by means of timing diagrams, an example of the operation of the PIX pixel of Figure 4.

[0115] In this example, the gates 400, 402, 404, 406, 410, 414, 418, and 422 are conducting when their respective control signals TI, Tic, TQ, TQc, RI, RIc, RQ, and RQc are high. Furthermore, in this example, the ITdiff switch is controlled by an SC signal and is conducting when the SC signal is high. In the timing diagrams of [Fig. 5], the voltage across electrode 423, respectively 425, is referenced as V423, respectively V425. In this example, the output det of circuit 428 is updated from the outputs of comparators COMP1 and COMP2 when the ENB signal is active, the active state of the ENB signal being, in this example, the low state of the ENB signal.

[0116] Fig. 5 illustrates the evolution of the signals TI, Tic, TQ, TQc, RI, RIc, RQ, RQc, rst, SC, V423, V425, ENB and det.

[0117] As illustrated by the signals TI, Tic, TQ and TQc, during an integration period, the grids 400, 402, 404 and 406 are periodically switched on at the frequency fs, but with phase shifts between them, so that, at the end of the integration period, the charges transferred from the photosensitive element PD to the respective memories 408, 412, 416 and 420 correspond to the charges photogenerated in the element PD during the respective durations D1, D3, D2 and D4 of the integration period. For illustrative purposes, a duration D1, a duration D2, a duration D3, and a duration D4 are referenced in [Fig. 5].

[0118] At the end of the integration period, memories 408, 412, 416 and 420 are read one after the other by ordering grids 410, 414, 418 and 422 in the passing state one after the other.

[0119] Before each switching of a grid 410, 414, 418 or 422, the SN node is reset by switching the ITrst switch to the on state.

[0120] In the example of [Fig. 5], memory 408 is read first (signal RI high) and the voltage V423 then corresponds to signal I and is at a value determined by the photogenerated charges in pixel PIX during the durations DL. During the reading of memory 408, the ITdiff switch is in the conducting state, hence the voltage V425 is equal to the potential VCL. Then, the ITdiff switch is switched to the blocking state, and memory 412 is read (RIc high). During the reading of memory 412, the voltage V423 corresponds to signal I and is at a value determined by the photogenerated charges in pixel PIX during the durations D3. Furthermore, during the reading of memory 412, since the ITdiff switch is open and that Since electrode 425 is floating, applying the voltage le to electrode 423 results in the voltage V425 across electrode 425 being equal to Ile, and, more specifically in this example, to le - I + VCL. While memory 412 is being read, the ENB signal is switched to the active state (low state in the example of [Fig. 5]), and the det signal is updated from the outputs of comparators C0MP1 and C0MP2. As in the example of [Fig. 5] the voltage Ile is less than V+ and greater than V-, the det signal remains in the inactive state, i.e., low state in the example of [Fig. 5].

[0121] In the example of [Fig. 5], after circuit CIRC1 has successively supplied the signals I and the to circuit CIRC2, after circuit CIRC2 has supplied the signal Ile to circuit CIRC3, and after circuit CIRC3 has compared the signal Ile to the voltages V+ and V- and updated the signal det accordingly, memory 416 is read (signal RQ high). During the reading of memory 416, the voltage V423 corresponds to the signal Q and is at a value determined by the photogenerated charges in pixel PIX during the durations D2. During the reading of memory 416, the ITdiff switch is in the conducting state, hence the voltage V425 is equal to the potential VCL. Then, the ITdiff switch is switched to the blocking state, and memory 420 is read (RQc high). During the reading of memory 420, the voltage V423 corresponds to the signal Qc and is at a value determined by the photogenerated charges in the pixel PIX during the durations D4.Furthermore, during the reading of memory 420, since the ITdiff switch is open and electrode 425 is floating, applying the voltage Qc to electrode 423 results in the voltage V425 across electrode 425 being equal to QQc, and, more specifically in this example, to Qc - Q + VLC. While memory 420 is being read, the ENB signal is switched to the active state, and the det signal is updated from the outputs of comparators COMP1 and COMP2. As in the example in [Fig. 5] the voltage QQc is less than V-, the det signal is switched to the active state, namely the high state in the example in [Fig. 5]. Thus, during the steps described above, circuit CIRC1 successively provides the signals Q and Qc to circuit CIRC2, circuit CIRC2 provides the signal QQc to circuit CIRC3, and circuit CIRC3 compares the signal QQc to the voltages V+ and V- and updates the signal accordingly.

[0122] It will be noted that the reading order of memories 408 and 412 can be reversed, that the reading order of memories 416 and 410 can be reversed, and that the reading of memories 416 and 420 can be implemented before the reading of memories 408 and 412 without this affecting the detection that one and / or the other of the signals Ile and QQc is greater than the voltage V+ or less than the voltage V-.

[0123] Fig. 6 illustrates another example of implementation of the CIRC2 and CIRC3 circuits of the PIX pixel of Fig. 4.

[0124] In this example, the CIRC3 circuit includes only one comparator COMP.

[0125] Furthermore, in this example, the CIRC2 and CIRC3 circuits are configured to implement a calibration of the single comparator COMP of the CIRC3 circuit, so as to eliminate, when comparing the signal Ile to the voltages V+ and V-, and the signal QQc to the voltages V+ and V-, the input offset Voff of the comparator COMP.

[0126] By way of example, the calibration of the COMP comparator can be implemented in the following way.

[0127] Compared to the CIRC2 circuit of [Fig. 4], the CIRC2 circuit of [Fig. 6] comprises two outputs, 600 and 602, and two switches, IT1 and IT2. The electrode 425 of the capacitor Cdiff is coupled to the output 600 by switch IT1 and to the output 602 by switch IT2. The output 602 is further coupled to the potential VCL by switch ITdiff. The CIRC3 circuit comprises two inputs, 604 and 606, corresponding to the inputs, for example, inverting (-) and non-inverting (+) respectively, of the comparator COMP. Input 604 is connected to the output 600, and input 606 is connected to the output 602. The comparator COMP is controlled by the ENB signal, so that its output det is updated from its inputs only when the ENB signal is active. The CIRC3 circuit further includes an ITZ switch connected between the output of comparator COMP and the inverting input (-) of comparator COMP.An IT+ switch couples the inverting input (-) of the comparator COMP to the voltage V+ and an IT- switch couples the non-inverting input (+) of the comparator COMP to the voltage V-.

[0128] The operation of the CIRC2 and CIRC3 circuits is, for example, as follows when comparing the signal Ile to the voltages V+ and V-, that is to say when comparing the absolute value of the thresholds VTH+ and VTH- to the absolute value of the difference between the signals I and le.

[0129] In a first step, switches ITZ, ITdiff, and IT1 are conducting, while the other switches are blocked. The signal I is then applied to electrode 423 of capacitor Cdiff, which here corresponds to the input of circuit CIRC2. As a result: the voltage V423 is equal to the voltage I; the non-inverting input of comparator COMP receives the potential VCL (ITdiff conducting); the inverting input of comparator COMP, and therefore the voltage V425, are at a potential equal to VCL + Voff because comparator COMP is operating as a voltage follower (ITZ conducting), with Voff being the input offset voltage of comparator COMP. The voltage Voff is a voltage offset present at the inverting input of comparator COMP relative to its non-inverting input. More specifically, during this first step, electrode 425 of the Cdiff capacitor is coupled to the VCL potential by the conducting switch IT1, the comparator COMP and its conducting switch ITZ, and The ITdiff switch is closed, and the voltage on electrode 425 is therefore equal to VCL + Voff.

[0130] In a second step, the ITZ and ITdiff switches are switched to the blocked state, and then the signal le is applied to electrode 423 of the capacitor Cdiff. As a result: electrode 425 of the capacitor Cdiff is decoupled from the potential VCL and is floating, the voltage V423 is equal to the voltage le, and The voltage V425 is then equal to Ile, that is to say to the - I + VCL + Voff in this example.

[0131] In a third step, the IT- switch is switched to the conducting state. In this third step, electrode 425 of the Cdiff capacitor is floating. As a result: the non-inverting input of the comparator COMP receives the voltage V- equal to VCL + VTH- in this example, VTH- being negative; the inverting input of the comparator COMP receives the signal Ile equal to -I + VCL + Voff in this example; and The COMP comparator implements the comparison of its non-inverting input and its inverting input while there is the Voff offset between its non-inverting input and its inverting input.

[0132] In other words, at this third stage, the comparator COMP determines whether V- - Ile + Voff is greater than or not than 0, that is to say whether VCL + VTH- - (the -1) - VCL - Voff + Voff is greater than or not than 0, which amounts to comparing the - I to the threshold VTH- having removed the influence of the input offset voltage Voff.

[0133] During the third step, the ENB signal is switched to the active state to update the det signal.

[0134] In a fourth step, switch IT1 is switched to the blocked state and switch IT2 is switched to the conducting state, and, furthermore, switch IT+ is switched to the conducting state and switch IT- is switched to the blocked state. In this third step, electrode 425 of the Cdiff capacitor is floating.

[0135] During the fourth step, the comparator COMP compares the difference I - the threshold VTH+ having eliminated the influence of the voltage Voff.

[0136] During the fourth step, the ENB signal is switched to the active state to update the det signal.

[0137] Implementing the third and fourth steps above amounts to comparing the absolute value of the difference between the signals I and le with the absolute value of the thresholds VTH+ and VTH-, eliminating, during these two comparisons, the influence of the input offset voltage Voff. By way of example, the steps described above can be implemented by supplying the le signal to electrode 423 during the third step and the I signal to electrode 423 during the fourth step without this does not modify the implemented functionality, namely comparing the absolute value of the difference between the signals I and the with the absolute value of the thresholds VTH+ and VTH-.

[0138] The four steps described above are also implemented to compare the absolute value of the difference between the signals Q and Qc with the absolute value of the thresholds VTH+ and VTH-, by providing the signal Q to the electrode 423 during the second step, and the signal Qc to the electrode 423 during the third step (or vice versa).

[0139] Figure 7 shows another example of an implementation of the CIRC1 circuit of the pixel in Figure 4. To avoid cluttering the figure, the gates 400, 402, 404, 406, 410, 414, 418, and 422, and the memories 408, 412, 416, and 420 are not shown. In this example, the PIX pixel includes only one PD photodetector, preferably a pinched photodiode, and the transfer gates 400, 402, 404, and 406 are connected to the PD photodetector in the same way as in Figure 4.

[0140] In this example, the CIRC1 circuit is configured to suppress the thermal noise generated on the SN node during its reset operations, this noise being, for example, called KT / C noise.

[0141] Thus, in relation to what has been described in connection with [Fig.4], the CIRC1 circuit of [Fig.7] further comprises: a capacitor Cth having one electrode 700 connected to the source of the MSF transistor and another electrode 702 connected to the gate of a MOS transistor configured as a source follower MSF2, and an ITth switch connected between electrode 702 of capacitor Cth and reference potential GND.

[0142] The CIRC1 circuit further includes a current source 704 configured to supply a bias current to the MSF2 transistor, i.e., to a conduction terminal of the MSF2 transistor, for example, its source. The MSF2 transistor and the current source 704 are connected in series between the VDD and GND potentials. The source of the MSF2 transistor then corresponds to the output of the CIRC1 circuit, on which the signals I, le, Q, and Qc will be available sequentially in this example.

[0143] Optionally, but preferably, transistor MSF2 has a channel of the opposite type to that of transistor MSF to limit the voltage drops between the gate of transistor MSF and the source of transistor MSF2. For example, in [Fig. 7], transistor MSF is N-channel, transistor MSF2 is P-channel and has its source connected to the current source 704, and its drain connected to GND.

[0144] The operation of the CIRC1 circuit is then modified as follows. During an initialization step of the SN node (ITrst conducting), the ITth switch is turned on. The voltage across electrode 700 of capacitor Cth is then equal to RST + kTC (neglecting voltage drops across the ITrst switch and between the gate and source of the MSF transistor), with kTC being the thermal noise at the SN node. Then, The ITth switch is switched to the off state, and one of the gates 410, 414, 418, or 422 is turned on. As a result, the SN node is at a voltage equal to Vsig + kTc, where Vsig is determined by the charges stored in memory 408, 412, 416, or 420, which is coupled to the SN node by the on state of gate 410, 414, 418, or 422, respectively. The voltage across electrode 702 of capacitor Cth is then equal to Vsig + kTc - (RST + kTC) (neglecting the voltage drop between the gate and the source of the MSF transistor), therefore to Vsig - RST. This voltage Vsig - RST, from which the influence of the thermal reset noise has been removed, is then found on the source of the MSF2 transistor (neglecting the gate-source voltage drop of the MSF2 transistor) and corresponds to the signal I, le, Q or Qc depending on whether the gate that has been switched to the conducting state is gate 410, 414, 418 or 422 respectively.

[0145] The CIRC1 circuit described in relation to [Fig.7] can be used with CIRC2 and CIRC3 circuits as described in relation to [Fig.4], or with CIRC2 and CIRC3 circuits as described in relation to [Fig.6].

[0146] Figure [8] represents another example of implementation of the CIRC1 circuit of the PIX pixel of Figure [1],

[0147] In this example, the PIX pixel includes only one PD photodetector, preferably a pinched photodiode.

[0148] The CIRC1 circuit of [Fig.8] differs from the CIRC1 circuit of [Fig.4] in that: the set consisting of the elements ITrst, SN, MSF and 424 is duplicated (elements ITrst', SN', MSF' and 424' in [Fig.8]), the grids 418 and 422 couple the respective memories 416 and 420 to the node SN' rather than to the node SN.

[0149] Thus, in relation to the CIRC1 circuit of [Fig.4] comprising a single output on which the signals I, le, Q and Qc are available sequentially, the CIRC1 circuit of [Fig.8] comprises a first output providing the signals I and le sequentially, and a second output providing the signals Q and Qc sequentially.

[0150] In the example of [Fig.8], the first output of the CIRC1 circuit corresponds to the source of the MSF transistor, and the second output of the CIRC1 circuit corresponds to the source of the MSF' transistor.

[0151] In another example not shown, the CIRC1 circuit of [Fig. 8] is further configured to suppress thermal noise at the SN and SN' nodes, similarly to that described in relation to [Fig. 7]. For example, a first set of a capacitor Cth, a switch ITth, a transistor MSF2, and a current source 704 is connected to the source of the transistor MSF, and a second set of a capacitor Cth, a switch ITth, a transistor MSF2, and a current source 704 is connected to the source of the transistor MSF'. The source of the transistor MSF2 of the first set then constitutes a first output of the CIRC1 circuit providing the signals I and le, and the source of transistor MSF2 of the second set then constitutes a second output of the CIRC1 circuit providing the signals Q and Qc.

[0152] By way of example, these two outputs of the CIRC1 circuit can be selectively coupled to the input of a single CIRC2 circuit as described in relation to [Fig.4] or with [Fig.6], so that the operation of the CIRC2 and CIRC3 circuits is identical to that previously described in relation to this [Fig.4].

[0153] As an alternative example, the components of circuits CIRC2 and CIRC3 described in relation to [Fig. 4] or [Fig. 6] are duplicated. For example, one of these two sets is connected to the first output of circuit CIRC1, a second of these two sets is connected to the second output of circuit CIRC1, and the signal det is determined from the outputs of both sets. This allows for the comparison of the absolute value of the difference between signals I and the with the absolute value of the thresholds VTH+ and VTH- in parallel with the comparison of the absolute value of the difference between signals Q and Qc with the absolute value of the thresholds VTH+ and VTH-. However, manufacturing variations between the components of the first set and those of the second set may introduce a shift between signals Ile and QQc.A person skilled in the art will be able to adapt the control sequences of the grids and switches of the CIRC1, CIRC2 and CIRC3 circuits of this alternative example from the description made in relation to figures 4, 5, 6 and 7.

[0154] Although other implementation examples of the CIRC1 circuit have been described above for the case where the PIX pixel comprises only one PD photodetector, these CIRC1 circuit examples can be implemented in a PIX pixel comprising two PD photodetectors, preferably identical ones. For example, grids 400 and 402 are then connected to one of the two PD photodetectors, and grids 404 and 406 are connected to the other PD photodetector. In this case, the duration of each of the durations D1, D2, D3, and D4 can be greater than that of the durations D1, D2, D3, and D4 in the case where the PIX pixel comprises only one photodetector. For example, each of the durations D1, D2, D3, and D4 has a value equal to Ts / 2. The person skilled in the art will be able to adapt the control sequences of the grids and switches of the CIRC1, CIRC2 and CIRC3 circuits of this alternative example from the description made in relation to figures 4, 5, 6, 7 and 8.

[0155] Figure [Fig.9] represents another example of implementation of the CIRC1 circuit of the PIX pixel of Figure [1],

[0156] In this example, the PIX pixel includes two PD photodetectors.

[0157] The CIRC1 circuit comprises the four grids 400, 402, 404 and 406, controlled by the respective signals TI, Tic, TQ and TQc. Grids 400 and 402 each have a first conduction terminal connected to one of the two PD photodetectors, grids 404 and 406 each have a first conduction terminal connected to the second of the two PD photodetectors.

[0158] However, unlike the CIRC1 circuits described so far, in the CIRC1 circuit of [Fig.9], the grids 400, 402, 404 and 406 have their second terminals connected to respective nodes SN, SN', SN" and SN'", these nodes serving as memory to store the photogenerated charges transferred from the PD photodetectors by the grids 400, 402, 404 and 406. Advantageously, it is therefore not necessary to provide intermediate memories 408, 412, 416 and 420.

[0159] As described in relation to the CIRC1 circuit of [Fig.4], the SN node is coupled to the VDD potential by the ITrst switch and is connected to the gate of the follower transistor MSF, the MSF transistor being in series with the current source 424 between the VDD and GND potentials so that the voltage on its source is a picture of the voltage on its gate.Similarly, the SN' node is coupled to the VDD potential by a switch ITrst' and is connected to the gate of a follower transistor MSF', the transistor MSF' being in series with a current source 424' between the VDD and GND potentials so that the voltage on its source is an image of the voltage on its gate, the SN' node is coupled to the VDD potential by a switch ITrst' and is connected to the gate of a follower transistor MSF', the transistor MSF' being in series with a current source 424' between the VDD and GND potentials so that the voltage on its source is an image of the voltage on its gate, and the SN' node is coupled to the VDD potential by a switch ITrst' and is connected to the gate of a follower transistor MSF', the transistor MSF' being in series with a current source 424' between the VDD and GND potentials so that the voltage on its source is an image of the voltage on its gate.The switches ITrst, ITrsf, ITrst" and ITrsf" are controlled by respective signals rst, rsf, rst" and rsf".

[0160] In the example in [Fig.9], the durations D1, D2, D3 and D4 each have a value, for example, equal to Ts / 2. A person skilled in the art will be able to adapt the control signals TI, Tic, TQ and TQc to the example circuit CIRC1 in [Fig.9], from the description given previously in relation to Figures 4, 5, 6, 7 and 8 of the other PIX pixel examples.

[0161] In another example not shown, the pixel PIX of [Fig.9] comprises only one photodetector PD and all the grids have their first conduction terminals connected to this single photodetector PD. In this case, the durations D1, D2, D3 and D4 each have, for example, a value equal to Ts / 4.

[0162] In the example of [Fig.9], the source of the MSF transistor corresponds to a first output of the CIRC1 circuit providing the signal I, the source of the MSF transistor' corresponds to a second output of the CIRC1 circuit providing the signal le, the source of the MSF transistor" corresponds to a third output of the CIRC1 circuit providing the signal Q and the source of the MSF transistor'" corresponds to a fourth output of the CIRC1 circuit providing the signal Qc.

[0163] In another example not shown, the source of the MSF transistor is coupled to a first output of the CIRC1 circuit by a first set of components Cth, ITth, MSF2 and 704 as described in relation to [Fig.7], the source of the MSF' transistor is coupled to a second output of the CIRC1 circuit by a second set of components Cth, ITth, MSF2 and 704 as described in relation to [Fig.7], the source of the MSF" transistor is coupled to a third output of the CIRC1 circuit by a third set of components Cth, ITth, MSF2 and 704 as described in relation to [Fig.7], and the source of the MSF'" transistor is coupled to a fourth output of the CIRC1 circuit by a fourth set of components Cth, ITth, MSF2 and 704 as described in relation to [Fig.7].

[0164] Compared to the CIRC1 circuit of [Fig.4] comprising a single output or the CIRC1 circuit of [Fig.8] comprising two outputs, the CIRC1 circuit of [Fig.9] comprises four outputs providing the respective signals I, le, Q and Qc.

[0165] By way of example, these four outputs of the CIRC1 circuit can be selectively coupled to the input of a single CIRC2 circuit as described in relation to [Fig.4] or [Fig.6], so that the operation of the CIRC2 and CIRC3 circuits is identical to that which has been described previously.

[0166] As an alternative example, the components of circuits CIRC2 and CIRC3 described in relation to [Fig. 4] or [Fig. 6] are duplicated. For example, one of these two sets is selectively connected to the first and second outputs of circuit CIRC1, so as to selectively receive either the signal I or the signal le, and a second of these two sets is selectively connected to the third and fourth outputs of circuit CIRC1 so as to selectively receive either the signal Q or the signal Qc. The signal det is then determined from the outputs of the two duplicated sets. This allows the comparison of the absolute value of the difference between signals I and le with the absolute value of the thresholds VTH+ and VTH- to be implemented in parallel with the comparison of the absolute value of the difference between signals Q and Qc with the absolute value of the thresholds VTH+ and VTH-.A person skilled in the art will be able to adapt the control sequences of the grids and switches of circuits CIRC1, CIRC2 and CIRC3 in this alternative example from the description of the operation of the previously described examples of circuits CIRC1, CIRC2 and CIRC3.

[0167] Furthermore, embodiments of PIX pixels configured to operate in the charge domain have been described above, meaning that the PD photodetector(s) of the described pixels are preferably pinch-type photodiodes, and that the gates 400, 402, 404, 406 are transfer gates. In alternative embodiments, the PIX pixel, and in particular its CIRC1 circuit, are configured to operate in the voltage domain, meaning that the PD photodetector(s) of the pixel can be conventional (non-pinch-type) photodiodes and that currents supplied by these photodetectors are integrated, for example with capacitive transimpedance amplifiers (CTIAs).

[0168] Figure 10 represents another example of an implementation of a CIRC1 circuit of the PIX pixel of Figure 1. In this embodiment, the PIX pixel is configured to operate in the voltage domain.

[0169] In [Fig. 10], only the CIRC1 circuit is illustrated, the other circuits CIRC2, CIRC3 and CIRC4 being, for example, identical to what has been described previously.

[0170] In the CIRC1 circuit of [Fig.10], the grids 400, 402, 404 and 406 are replaced by switches 1000, 1002, 1004 and 1006 respectively. The switches 1000, 1002, 1004 and 1006 are controlled by signals TI, Tic, TQ and TQc respectively similar to those described in relation to the CIRC1 circuits operating in the load domain.

[0171] Switches 1000, 1002, 1004, and 1006 can, similarly to grids 400, 402, 404, and 406, have their first conduction terminals all connected to a single photodetector PD of the pixel, which can be a non-pinched photodiode. As an alternative example, in a PIX pixel with two photodetectors that can be non-pinched photodiodes, switches 1000 and 1002 have their first conduction terminals connected to one of the two photodetectors, and switches 1004 and 1006 have their first conduction terminals connected to the second of the two photodetectors. As another alternative example, in a PIX pixel with four photodetectors which may be unpinched photodiodes, switches 1000, 1002, 1004 and 1006 each have their first conduction terminal connected to a separate photodetector.

[0172] In the CIRC1 circuit of [Fig.10], the memories 408, 412, 416 and 420 are replaced by operational amplifiers mounted as capacitive transimpedance amplifiers (CTIAs) respectively referenced CTIAI, CTIAIc, CTIAQ and CTIAQc in [Fig. 10].

[0173] The switches 1000, 1002, 1004 and 1006 have their second conduction terminals coupled, for example connected, to the respective amplifiers CTIAI, CTIAIc, CTIAQ and CTIAQc.

[0174] Each capacitive transimpedance amplifier includes a reset switch coupling the output and the input, for example, the inverting input, of the amplifier. This reset switch is, for example, controlled by an rst signal. Turning the reset switch of a capacitive transimpedance amplifier on resets the value integrated into the amplifier, and, more specifically, the value integrated into the capacitance of the capacitive transimpedance amplifier.

[0175] In the CIRC1 circuit of [Fig. 10], the transfer gates 410, 414, 418, and 422 are replaced by switches 1010, 1014, 1018, and 1022, respectively. The switches 1010, 1014, 1018, and 1022 are controlled by signals RI, RIc, RQ, and RQc, respectively, similar to those described in relation to CIRC1 circuits operating in the load domain. Each switch 1010, 1014, 1018, and 1022 has a first conduction terminal connected to the output of an amplifier CTIAI, CTIAIc, CTIAQ, and CTIAQc, respectively.

[0176] By way of example, the second conduction terminals of the switches are all connected to the same node 1024, as in the example in [Fig. 10]. By way of example, this node 1024 can correspond to the output of the CIRC1 circuit. By way of alternative example, as illustrated in [Fig. 10], the node 1024 is coupled to the output of the CIRC1 circuit by a thermal noise suppression circuit.

[0177] This thermal noise suppression circuit comprises, similarly to what has been described previously, for example in relation to [Fig.7]: a capacitance Cth having an electrode 700 connected to node 1024 and another electrode 702 connected to the input of an analog buffer circuit Buff, and a switch ITth connected between the electrode 702 of the capacitance Cth and the reference potential GND.

[0178] The Buff circuit is an alternative to the MSF2 transistor follower, which is bulkier but has no gate-source voltage drop. As an example, the implementation described in relation to [Fig. 10] is relevant in a sensor where the PD photodiodes of several PIX pixels are arranged in a single row of PD photodetectors.

[0179] In the example of [Fig.10], all the switches 1010, 1014, 1018 and 1022 have their second conduction terminals connected to the same node 1024.

[0180] In other examples not shown, the second conduction terminals of switches 1010 and 1014 are connected to the same first node, and the second conduction terminals of switches 1018 and 1022 are connected to the same second node. The first and second nodes may correspond to the outputs of the CIRC1 circuit, or each may be connected to a corresponding output of the CIRC1 circuit by a thermal noise suppression circuit.

[0181] In other examples not shown, the second conduction terminals of switches 1010, 1014, 1018, and 1022 are each connected to a separate node that may correspond to an output of circuit CIRC1, or be connected to a corresponding output of circuit CIRC1 by a thermal noise suppression circuit. In such examples, switches 1010, 1014, 1018, and 1022 may be omitted.

[0182] In the PIX pixels described so far, to detect (or test or verify) whether a PIX pixel is at a distance z equal to zdet from a scene, it suffices to emit the frequency-modulated continuous wave light signal with a slope B / T equal to fs.c / (2.zdet). The value zdet can therefore be modified either by changing the slope B / T, or by changing the frequency fs, or by changing both parameters.

[0183] Thus, according to one embodiment, the control circuit is configured to maintain a constant frequency fs at each emission of a plurality of emissions of the frequency-modulated continuous wave signal, and to modify the slope of the frequency modulation at each emission. Therefore, at each emission of the plurality of emissions of the frequency-modulated continuous wave signal, the corresponding integration period allows for the detection of a different distance from the sensor to the scene.

[0184] Fig. 11 illustrates, by means of chronograms, an example of operation in which, during an acquisition time period, N integration periods are implemented and all correspond to the emission of a continuous frequency modulated light wave signal for a duration Ti with a slope Bi / Ti, with i an integer index ranging from 0 to N-1.

[0185] More specifically, in the example in [Fig. 11], the frequency fs is constant for each of the N emission periods, and the duration Ti is constant and equal to T for each of the N emission periods. Furthermore, at each emission period of duration T, the slope Bi / Ti is modified, in this example by changing the value of the amplitude Bi of the frequency range fL of the emitted optical signal since Ti is constant and equal to T.

[0186] In the example of [Fig. 1 1], for a given value of the frequency fs, which is kept constant during the N successive emission periods, it is therefore possible, with a PIX pixel, to detect N different distances zi equal to (fs.cT) / (2.Bi) at the end of the acquisition period Tac. In other words, in this case, the PIX pixel makes it possible to verify, for each of the N different distances zi, whether the PIX pixel is located at this distance zi from the scene, that is to say, whether the PIX pixel is located at this distance zi from the point in the scene associated with this PIX pixel.

[0187] Although not shown in [Fig. 1 1], in practice, between two successive emissions of indices i and i+1, a dead time can be provided, corresponding to a processing time by the PIX pixel, to determine whether or not the PIX pixel should put its signal det into the active state. This processing time corresponds, for example, to the The time required for the PIX pixel to produce each of the Ile and QQc signals and to compare them to the V+ and V- voltages. Alternatively, the determination of whether or not the PIX pixel should activate its det signal is made while the PIX pixel is integrating the signal for the next transmission period. This processing time is therefore hidden, and there is no need to provide dead time between two successive integration periods.

[0188] In the example above, when the absolute value of the VTH- and VTH+ thresholds is set too low, it may result that, for a given Bi / T slope corresponding to a detection distance zi, a received signal sigL with a beat frequency equal to (2.u+l).fs, where u is an integer greater than or equal to 1, triggers the PIX pixel (active detector at the output of the PIX pixel). For example, if the VTH- and VTH+ thresholds are too low, signals 304 and 310, see also signals 308 and 306, of [Fig. 3] may trigger the PIX pixel. Put another way, for a given slope Bi / T, the pixel PIX will provide an active det signal as if the scene point associated with the pixel PIX is at a distance zi = (fs.cT) / (2.Bi) from the pixel, whereas the scene point associated with the pixel PIX is in fact at a distance equal to (2.u+l).zi from the pixel.

[0189] According to one embodiment, when a PIX pixel detects N successive distances zi = zO.k1 = (fs.cT) / (2.Bi) = k'.(fs.cT) / (2.B0), with i increasing, zO an initial distance, B0 a frequency excursion determined by zO, and k a resolution factor between distances, it is provided, for each index i, to successively detect the distances (2.u+l).zi = (2.u+l).z0.k' = (2.u+l).k1.(fs.cT) / (2.B0) with u a decreasing integer from U to 0, and U a strictly positive integer, for example equal to 2. For this, for each value of index i, it is provided U+l successive emission periods of duration T and respective amplitudes (or excursions) Bi / (2.u+l) = B0 / (k'.(2.u+l)) with u a decreasing index going from U to 0. This allows, for a pair of slope and frequency fs, to first detect the distances corresponding to the odd harmonics of this frequency fs and to remove ambiguities concerning the distance detected.

[0190] For each given value of the index i, it is preferable that the frequency excursion ranges Bi / (2.u+l) for that given value of the index i have the same average value, so that the corresponding sigL signals received by the PIX pixel are comparable. Indeed, when the coherent light source is a semiconductor laser, the modulation of the injection current applied to the laser to modulate its optical frequency simultaneously produces a modulation of the laser's intensity (or optical power). It is therefore preferable to have a substantially identical average intensity value between the U+l emission periods of a index i given, because the amplitude of the oscillations (at the beat frequency fR) is proportional to this average value.

[0191] Fig. 12 illustrates, over an acquisition time Tac, the principle described above for U equal to 2 and for indices i equal to 0 and i equal to 1.

[0192] In this example, the durations Ti are all equal to the same duration T. For each emission period T, [Fig. 12] indicates the value of the index pair i and u, and the distance zdet actually detected (tested) by the PIX pixel.

[0193] In the example of [Fig. 12], between each two successive emissions corresponding to two different pairs of indices i and u, there is a dead time corresponding to a processing time by the pixel PIX to determine whether or not the pixel's det signal should be activated. Alternatively, as previously indicated, this processing time at the end of each emission period is masked during the beginning of the next emission period, and there is then no dead time between emission periods.

[0194] If, for the emission period corresponding to a given pair of indices i and u of the acquisition period Tac, the PIX pixel provides an active det signal, it is no longer necessary to check whether the PIX pixel will provide an active det signal for subsequent emission periods of this acquisition period Tac, and the PIX pixel can then be deactivated for these subsequent emission periods. The distance actually detected by the pixel is then the distance zdet = (2.u+l).zi = (2.u+l).z0.k' = (2.u+l).k1.(fs.cT) / (2.B0), with i and u the indices of the pair of indices i and u corresponding to the emission period that resulted in the provision of an active det signal by the PIX pixel.

[0195] Preferably, for each index value i, each distance zdet = zi which is equal to a distance zdet = (2.u+l).zj with j an integer index from 0 to i-1 and u between 1 and U, the emission of the signal corresponding to the pair of indices i and u=0 can be omitted since the distance zdet = zi = (2.u+l).zj has already been tested for the pair of indices j and u.

[0196] In other words, preferably, the emission periods satisfying, for u ranging from 1 to U, i ranging from 0 to N, and j ranging from 0 to i-1, the equality (2u+l)kj = k1, do not need to be duplicated. The above equality is equivalent to the equality ij = logk(2u+l), where logk is the logarithm operator in base k. By choosing the resolution factor k such that, for at least some values ​​of the index u between 1 and U, logk(2u+l) is equal to an integer, it is therefore possible to reduce the number of emission periods.

[0197] Thus, according to an embodiment with a constant integration frequency fs, it is therefore planned, for each value of an increasing index i from 0 to N-1, for a decreasing index u from U to 0, to emit a frequency-modulated continuous wave signal with a frequency excursion equal to B0 / (k'.(2.u+l) only if, For a given resolution value k and for an integer q from 1 to U, logk(2.q+l) is different from ij, with j an integer index from 0 to i-1. Preferably, during the successive emissions defined above, a PIX pixel providing an active signal for one of said emissions is deactivated for subsequent emissions.

[0198] Embodiments have been described above in which the slope of the frequency modulation is modified between successive emissions of a frequency-modulated continuous wave signal while the frequency fs is kept constant for the corresponding integration periods.

[0199] More specifically, in these embodiments, the slope of the frequency modulation is modified by changing the frequency deviation of the modulation, while the duration of the modulation (or transmission) is kept constant. In alternative embodiments, the slope is modified by changing the duration of each transmission, the frequency modulation deviation being either kept constant or also modified between successive transmissions. Adapting the above description to such alternative embodiments is within the capabilities of a person skilled in the art, based on the functional specifications given above for the case where the transmission duration is kept constant and equal to T.

[0200] Furthermore, to detect (or test) several distances from a pixel PIX to a scene, rather than varying the slope of the frequency modulation at each emission of a plurality of emissions of a frequency-modulated continuous wave signal, it is possible to keep a constant frequency modulation slope for all emissions by varying the frequency fs.

[0201] Thus, according to one embodiment, the control circuit is configured to maintain a constant slope of the frequency modulation at each emission of a plurality of emissions of the frequency-modulated continuous wave signal, and to change the value of the frequency fs at each emission. Therefore, at each emission of the plurality of emissions of the frequency-modulated continuous wave signal, the corresponding integration period allows for the detection of a different distance from the sensor to the scene.

[0202] Figure 13 illustrates, by means of timing diagrams, an example of operation in in which, during an acquisition time period, N emission periods are implemented and all correspond to the emission of a continuous wave light signal modulated in frequency with a constant slope, for example equal to B / T with B constant and T constant, but with a different integration frequency fsi, with i an index ranging from O to N-1.

[0203] More particularly, in the example of [Fig. 13], the frequency-modulated continuous wave signal is emitted continuously over the entire duration Tac with a frequency modulation excursion equal to Btot and a frequency modulation uninterrupted fL over the entire duration Tac. Btot is determined so that, for each of the N emission periods, the slope of the frequency modulation is constant and, in this example, equal to B / T. In addition, at each of the N emission periods, the integration frequency fsi is modified, with i an integer index ranging from 0 to N-1. Thus, each emission period of duration T and constant slope B / T corresponding to the index i allows the detection of a distance zi = (cTfsi) / (2.B).

[0204] As shown in [Fig. 13], in practice, between two successive transmissions of indices i and i+1, a dead time can be provided, corresponding to the processing time by the pixel PIX to determine whether the signal det should be activated or not. The excursion Btot is then determined taking these dead times into account, since, in this example, the modulation of the frequency fL does not stop during these processing times. Alternatively, as previously indicated, this processing time at the end of each transmission period is masked during the beginning of the following transmission period, and there is then no dead time between the transmission periods.

[0205] Fig. 14 illustrates, by means of chronograms, another example of operation in which, during an acquisition time step, N integration periods are implemented and all correspond to the emission of a continuous wave light signal modulated in frequency with a constant slope B / T, for example equal to B / T with constant B and constant T, but with a different integration frequency fsi, with i an index ranging from 0 to N-1.

[0206] More specifically, in the example of [Fig. 14], compared to the example of [Fig. 13], the modulation of the frequency fL is interrupted between each two successive emission periods of indices i and i+1, during the processing time by the PIX pixel. Furthermore, in the example of [Fig. 14], for each two successive emission periods of indices i and i+1, the modulation frequency fL at the beginning of the emission period of index i+1 is equal to the modulation frequency at the end of the emission period of index i.

[0207] It follows that, for identical values ​​of N, B and T, the frequency excursion Btot of the modulation over the entire duration Tac in the example of [Fig. 14] is lower than in the example of [Fig. 13].

[0208] Fig. 15 illustrates, by means of chronograms, another example of operation in which, during an acquisition time period, N integration periods are implemented and all correspond to the emission of a continuous wave light signal modulated in frequency with a constant slope, for example equal to B / T, but at a different integration frequency fsi, with i an index ranging from 0 to N-1.

[0209] More specifically, in the example of [Fig. 15], as in the example of [Fig. 14], the modulation of the frequency fL can be interrupted between each Two successive emission periods with indices i and i+1 occur during a dead time corresponding to the processing time of the PIX pixel. However, in the example in [Fig. 15], the value of the modulation frequency fL is the same at the beginning of each emission period. Alternatively, as previously mentioned, this processing time at the end of each emission period is masked during the beginning of the next emission period, and there is then no dead time between the emission periods.

[0210] One advantage of the embodiment of [Fig. 15] compared to those of Figures 13 and 14 is that the total excursion Btot of the frequency modulation is lower, and is equal to B in [Fig. 15]. Another advantage of the embodiment of [Fig. 15] compared to those of Figures 13 and 14 is that the average laser intensity and the amplitude of the oscillations of the signal sigL vary less between two successive emission periods.

[0211] A person skilled in the art will be able to foresee other examples of operation, by combining the examples in Figures 13, 14 and 15.

[0212] For example, the N successive emission periods can be grouped into Q successive sets, each comprising several successive emission periods, with Q an integer strictly greater than 1. In each of the Q sets of several successive emission periods, the modulation frequency fL can be modified continuously by interrupting or not the variation of the interrupted modulation frequency during each processing time separating two successive emissions, and by having the same modulation frequency value at the beginning of the first emission period of each of the Q sets of several successive emission periods.

[0213] In the examples above, for a given value of the frequency modulation slope, which is kept constant and equal to B / T during the N successive emissions (or integrations), it is therefore possible, with a PIX pixel, to detect N different distances zi equal to (fsi.cT) / (2.B) at the end of the acquisition period Tac. In other words, in this case, the PIX pixel makes it possible to verify, for each of the N different distances zi, whether the PIX pixel is located at that distance zi from the scene, that is to say, whether the PIX pixel is located at that distance zi from the point in the scene associated with that PIX pixel.

[0214] In the examples above, when the absolute value of the VTH- and VTH+ thresholds is set too low, it can result that, for a given frequency fsi corresponding to a detection distance zi, a received signal sigL having a beat frequency equal to fsi / (2.u+l), with u an integer greater than or equal to 1, triggers the PIX pixel (active detection at the output of the PIX pixel). For example, if the VTH- and VTH+ thresholds are too low, signals 304 and 310, see also signals 308 and 306, of the [Fig.3] can trigger the PIX pixel. In other words, for a given frequency fsi, the PIX pixel will provide an active det signal as if the PIX pixel had detected a point at a distance zi = (fsi.cT) / (2.B) while the point detected by the pixel is in fact at a distance equal to zi / (2.u+l).

[0215] According to one embodiment, when a PIX pixel detects N successive distances zi = zO.k1 = (fsi.cT) / (2.B) = k'.(fsO.cT) / (2.B), with i increasing, zO an initial distance, and k a resolution factor between distances, it is provided, for each index i, to successively detect the distances zi / (2.u+l) = (z0.k') / (2.u+l) = k1.(fsO.cT) / ((2.u+l).2.B) with u a decreasing integer from U to 0, and U a strictly positive integer, for example equal to 2. For this purpose, for each value of the index i, U+l successive emission periods are provided, corresponding to U+l successive values ​​of integration frequencies fsi / (2.u+l) = k'.fs0 / (2.u+l) with u a decreasing index going from U to 0. This allows, for a pair of slope and frequency fsi, to first detect the distances corresponding to the odd harmonics of this frequency fsi and to remove ambiguities concerning the distance detected.

[0216] Fig. 16 illustrates, over an acquisition time Tac, the principle described above for U equal to 2 and for indices i equal to 0 and i equal to 1, for an example where the frequency modulation at each emission period is of the type described in relation to Fig. 15.

[0217] For each emission period T, [Fig. 16] indicates the value of the index pair i and u, and the distance zdet actually detected (tested) by the PIX pixel.

[0218] If, for the emission period corresponding to a given pair of indices i and u of the acquisition period Tac, the PIX pixel provides an active det signal, it is no longer necessary to check whether the PIX pixel will provide an active det signal for subsequent emission periods of this acquisition period Tac, and the PIX pixel can then be deactivated for these subsequent emission periods. The distance actually detected by the pixel is then the distance zdet = zi / (2.u+l) = z0.k7(2.u+l) = k'.(fsO.cT) / ((2.u+l).2.B0), where i and u are the indices of the pair of indices i and u corresponding to the emission period that resulted in the provision of an active det signal by the PIX pixel.

[0219] Preferably, for each index value i, each distance zdet = zi which is equal to a distance zdet = zj / (2.u+l) with j an integer index from 0 to i-1 and u between 1 and U, the emission of the signal corresponding to the pair of indices i and u=0 can be omitted since the distance zdet = zi = zj / (2.u+l) has already been tested for the pair of indices j and u.

[0220] In other words, preferably, emission periods satisfying, for u ranging from 1 to U, the equality kj / (2.u+l) = k1, do not need to be duplicated. The above equality is equivalent to the equality ij = logk(l / (2.u+l)), with logk being the logarithm operator in base k. By choosing the resolution factor k such that, for at least some values of the index u between 1 and U, logk(l / (2.u+l)) is equal to an integer, it is therefore possible to reduce the number of emission periods.

[0221] Thus, according to an embodiment with constant frequency modulation slope, it is therefore provided, for each value of an increasing index i from 0 to N-1, for a decreasing index u from U to 0, to emit a frequency-modulated continuous wave signal with an integration frequency of the corresponding integration equal to k'.fs0 / (2.u+l) only if, for a given resolution value k and for an integer q from 1 to U, logk(l / (2.q+l)) is different from ij, with j an integer index from 0 to i-1. Preferably, during the successive emissions defined above, a PIX pixel providing an active signal for one of said emissions is deactivated for the following emissions.

[0222] In the examples of embodiments and variants of the PIX pixel described above in relation to Figures 1, 4, 6, 7, 8, 9 and 10, the CIRC4 circuit of the PIX pixel is configured to implement an event-driven read of the PIX pixel, that is to say, so that the PIX pixel is read only when the det signal of the PIXEL has been activated at the end of a corresponding integration.

[0223] However, in other examples, the CIRC4 circuit is configured to allow sequential reading of the PIX pixel, that is to say to read the PIX pixel after each integration, whether or not the det signal has been activated by the PIX pixel at the end of this integration period.

[0224] For example, to achieve this, the pixel's CIRC4 circuit is configured to store, after each integration period, the state of the det signal when that state is valid, for example, when the ENB signal is active. This stored value of the det signal state is then read by a readout circuit of the electronic system comprising the PIX pixel.

[0225] For example, this electronic system is an image sensor comprising a PIX pixel matrix, and the sensor reading circuit is configured to read, for example after each integration, the value stored in the CIRC4 circuit by reading the pixel lines of the matrix one after the other, and simultaneously all the PIX pixels of the line being read.

[0226] By way of another example, for an image sensor comprising a PIX pixel array in which: - for a given acquisition period Tac, each pixel PIX that provides an active det signal for a given integration period of the acquisition period Tac is deactivated for subsequent integration periods of that acquisition period; and - the CIRC4 circuit of each PIX pixel is configured to store, after each integration, a zero value if the det signal has remained inactive, and a detected distance value if the det signal has been activated, the sensor reading circuit can be configured to read the value stored in the CIRC4 circuit of each PIX pixel at the end of the acquisition period, by reading the pixel lines of the matrix one after the other, and simultaneously all the PIX pixels of the line being read.

[0227] An example of the implementation of such a CIRC4 circuit is illustrated in [Fig. 17].

[0228] In this [Fig. 17], the CIRC4 circuit of the PIX pixel receives, for example from a readout circuit of the electronic system comprising the PIX pixel, a digital word Valdet indicating, at each integration period, the value zdet of the distance detected by the PIX pixel. The CIRC4 circuit includes a register 1700 configured to store this digital word Valdet if the signal det switches to the active state, and to remain at a default value of zero otherwise. As an example, the Valdet signal is received by a data input D of register 1700, and the signal det is received by a synchronization input CK of register 1700.

[0229] Thus, during an acquisition period comprising several integration periods, each corresponding to an emission of a frequency-modulated continuous wave signal, when at the end of an integration period, a PIX pixel puts its signal det into the active state to indicate that it is at the corresponding distance zdet from the scene, this distance zdet is memorized by the CIRC4 circuit of the PIX pixel, and the PIX pixel is deactivated for the following integration periods of the acquisition period.

[0230] At the end of the acquisition period, the CIRC4 circuit is read by a sensor readout circuit comprising the PIX pixel; that is, the distance zdet that the PIX pixel detected during this acquisition period is read by the readout circuit. For example, the readout circuit reads a digital word OUT available at the output of register 1700, for example, at a Q output of register 1700. This word OUT corresponds to the default value of zero if the PIX pixel never activated its det signal during the acquisition period, and to the stored word Valdet if the PIX pixel activated its det signal at the end of an integration period of the acquisition period.Depending on the configuration of register 1700, the word Valdet stored in register 1700 when the det signal was active can be read bit by bit if the output of register 1700 is a serial output, or by reading all the flip-flops of register 1700 simultaneously if the output of register 1700 is a parallel output.

[0231] In this way, a single reading of each of the PIX pixels of the sensor implemented at the end of each acquisition period makes it possible to directly obtain an image of the distances from the sensor to the scene for that acquisition period.

[0232] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0233] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, the PD photodetectors of the PIX pixels, the other components of the PIX pixels, the undescribed circuits for reading the PIX pixels, and, for example, circuits for processing the information obtained following the readings of the PIX pixels can all be implemented in and on the same layer of a semiconductor material, i.e. in a single level ("tier"), or, alternatively, can be distributed between several layers of semiconductor materials, i.e. between several levels ("tiers"), for example according to the technology designated by the acronym 3DSL.

Claims

Demands

1. Pixel (PIX) comprising: at least one photodetector (PD); a first circuit (CIRC1) configured to provide, after each integration period corresponding to an emission period (T) of a frequency-modulated continuous wave light signal, first, second, third and fourth signals (I, Q, Ie, Qc) representative of a quantity of photogenerated charges in said at least one photodetector during respectively first, second, third and fourth durations (D1, D2, D3, D4) of the integration period repeated at an integration frequency (fs), the second durations (D2) being phase-shifted by n / 2 with respect to the first durations (D1), the third durations (D3) being phase-shifted by Il with respect to the first durations (D1), the fourth durations (D4) being phase-shifted by 3*11 / 2 with respect to the first durations (D1), and the first, second, third, and fourth durations all having the same duration; a second circuit (CIRC2) configured to provide a fifth signal (Ile) determined by the difference between the first and third signals (I, Ile), and a sixth signal (QQc) determined by the difference between the second and third signals (Q, Qc); and a third circuit (CIRC3) configured to: - compare each of the fifth and sixth signals (Ile, QQc) to a first voltage (V+) determined by a positive threshold (VTH+) and to a second voltage (V-) determined by a negative threshold (VTH-), the positive and negative thresholds having the same absolute value.

2. Sensor comprising: one or more pixels (PIX) according to claim 1; a coherent light source configured to provide, at each emission period (T), the frequency-modulated continuous wave light signal; an optical device configured, at each emission period (T), to emit a first part of the frequency-modulated continuous wave signal towards a scene and a second part of the frequency-modulated continuous wave light signal towards each pixel (PIX), such that a light signal (sigL) received by each pixel corresponds to the superposition of the second part of the signal frequency modulated continuous wave light and a reflection by a point in the scene associated with the pixel of the first part of the frequency modulated continuous wave light signal.

3. Sensor according to claim 2, wherein the sensor comprises a control circuit configured to control several emission periods (T) of the frequency-modulated continuous wave signal and, at each of said several emission periods, to maintain constant a slope of the frequency modulation of the frequency-modulated continuous wave light signal and to modify a value of the integration frequency (fs).

4. Sensor according to claim 2, wherein the sensor comprises a control circuit configured to control several emission periods (T) of the frequency-modulated continuous wave signal, and, at each of said several emission periods, to maintain constant a value of the integration frequency (fs) and modify a slope of the frequency modulation of the frequency-modulated continuous wave light signal.

5. Sensor according to any one of claims 2 to 4, wherein, after each integration period (T), the third circuit (CIRC3) of each pixel is further configured to provide an active detection signal (det) if one and / or the other of the fifth and sixth signals (Ile, QQc) is greater than the first voltage (V+) or less than the second voltage (V-).

6. Sensor according to claim 5, wherein the first, second and third circuits (CIRC2, CIRC3) are configured so that, after each integration period, the detection signal is active: if a difference between the first and third signals (I, le) is, in absolute value, greater than the absolute value of the positive and negative thresholds (VTH+, VTH-); and / or if a difference between the second and fourth signals (Q, Qc) is, in absolute value, greater than the absolute value of the positive and negative thresholds (VTH+, VTH-).

7. Sensor according to claim 5 or 6, wherein: the sensor includes an address event readout circuit; and each pixel includes an output circuit (CIRC4) configured to detect that the detection signal (det) is active and to provide, following detection that the detection signal is active, an address signal of the pixel to the address event readout circuit.

8. Sensor according to claim 2, wherein the sensor includes a control circuit configured to: maintain constant the integration frequency (fs) during an acquisition period (Tac); and during the acquisition period, for an increasing integer index i from 0 to N-1, with N a strictly positive integer, and, for each value of the index i, for a decreasing index u from U to 0, with U a strictly positive integer, to control, for each pair of indices i and u, an emission period (T) of the frequency-modulated continuous wave signal with a frequency modulation excursion equal to B0 / (k'.(2.u+l)), with B0 a frequency excursion value determined by an initial value of distance to be detected (zO) and k a positive resolution value, preferably only if, for q an integer from 1 to U, logk(2.q+l) is different from ij, with j an integer index from 0 to i-1.

9. Sensor according to claim 2, wherein the sensor includes a control circuit configured to maintain a constant frequency modulation slope at each emission period of an acquisition period; and during the acquisition period, for an increasing integer index i from 0 to N-1, with N a strictly positive integer, and, for each value of the index i, for a decreasing index u from U to 0, with U a strictly positive integer, to control, for each pair of indices i and u, a period of emission of the frequency-modulated continuous wave signal and a value of the integration frequency equal to k'.fs0 / (2.u+l) with fs0 an integration frequency value determined by an initial value of distance to be detected (ZO) and k a positive value of resolution, preferably only if, for q an integer from 1 to U, logk(l / (2.q+l)) is different from ij, with j an integer index from 0 to i-1.