Transmitter, receiver, transmission chain and associated data transmission method

Abstract

Transmitter, receiver, transmission chain and associated data transmission method The present invention relates to a transmitter (12) of signals representing digital input data (De), comprising a digital processing module (16) comprising: a first interlacer (21) configured to successively receive input data frames (Te), representing the digital input data (De) to separate them into words, and to interlace the words of the input data frames (Te) with each other according to a first logic in order to form first interlaced data frames (T1);and a second interleaver (22), configured to receive the first interleaved data frames (T1), to separate them into words and to interleave the words of the first interleaved data frames (T1) with each other according to a second logic in order to form second interleaved data frames (T2), the transmitter (12) further comprising a transmitting module (18) configured to transmit the signals. Figure for the abbreviation: Figure 2;

Description

Title of the invention: Transmitter, receiver, transmission chain and associated data transmission method

[0001] The present invention relates to a transmitter, a receiver, a transmission chain, and a method for transmitting associated data.

[0002] It is known to use radio frequency technologies to ensure data transmission. Optical technologies are also an interesting alternative to radio frequency technologies. In particular, optical communications, especially in free space between the surface and the ground, are a promising solution for increasing transmission rates.

[0003] However, the transmission media used in radio frequency or optical technologies have several drawbacks, in particular, the degradation of the transmitted signal. Specifically, optical transmissions suffer from significant signal degradation due to the variable composition of atmospheric layers and turbulence. These phenomena cause deep fading, thus interrupting transmission between a transmitter and a receiver for several milliseconds. Since the transmitted data frames are shorter than several milliseconds, such fading can cause the loss of the information contained in these data frames.

[0004] To limit information loss during these fading events, it is necessary to spread the information carried by the data frames over a period longer than the fading duration. This operation is achieved, in particular, by using a data frame interleaving function. In this case, a fading event lasting one frame will cause, instead of a completely lost frame, the information loss to be spread across several frames. It is possible to recover this information using, for example, error-correcting codes, and thus avoid the information loss caused by fading events.

[0005] However, the interleaving currently performed is complex and resource-intensive. Furthermore, the interleaving currently performed does not always allow the data frames to be spread over a sufficiently long period to avoid complete information loss.

[0006] The aim of the invention is then to improve the transmission of a signal in order to limit data loss, in a simple way.

[0007] To this end, the invention relates to a transmitter of signals representing digital input data, comprising a digital processing module including: - a first interleaver configured to successively receive input data frames, representing the input digital data, to separate them into words, and to interleave the words of the input data frames with each other according to a first logic in order to form first interleaved data frames; and - a second interleaver, configured to receive the first interleaved data frames, to separate them into words, and to interleave the words of the first interleaved data frames with each other according to a second logic in order to form second interleaved data frames,

[0008] the transmitter further comprising a transmission module configured to emit the signals.

[0009] Thanks to the invention, the data frames are interleaved twice, which increases the duration over which the data frames are interleaved, while also allowing for fine interleaving of the data frames. This reduces both the amount of data lost during a fade and allows for longer fade durations.

[0010] For example, the first interleaver forms initial interleaved data frames over short durations, allowing for optimal data distribution and thus high-quality interleaving. Specifically, the words formed by the first interleaver contain a small amount of data, so the initial data frames are finely interleaved to distribute the data within the frames evenly and limit information loss. The second interleaver, for instance, separates the initial interleaved data frames into larger words, allowing words to be interleaved over longer durations to limit information loss in the event of deep fading.

[0011] More generally, the invention makes it easier to interleave data frames according to user needs, and in particular over longer durations, without impacting the quality of the interleaving.

[0012] According to other advantageous aspects of the invention, the transmitter comprises one or more of the following features, taken individually or in all technically possible combinations:

[0013] - The first and second logics are convolution logics, and each The interlacer has the following parameters: - a predetermined number of branches defining an interlacing depth; and - the size of the interlaced data frames emitted by the interlacer, expressed in number of words.

[0014] - The two interlacers have an equal interlacing depth.

[0015] - The second interlacer is configured to separate the first frames of interlaced data emitted by the first interlacer in words whose size, expressed in bits, is equal to the size of the first interlaced data frames, expressed in bits.

[0016] - The second interleaver includes a memory, the size of which is the number of bits being equal to half the product between the depth of the second interleaver, the size of the second interleaved data frames and the size of each word forming the second interleaved data frames in number of bits.

[0017] - The second interleaver includes a double data rate type memory.

[0018] - Each interleaver is configured to separate the data frames it receives into words made up of at least one bit.

[0019] - The digital processing module further includes a channel coding unit, configured to receive input digital data, and to convert input digital data into input data frames, the input data frames being representative of the input digital data.

[0020] The invention also relates to a receiver comprising a receiving module configured to receive a signal emitted by a transmitter as described above, the receiver further comprising a digital processing module comprising: - a first deinterlacer, configured to successively receive received data frames, the received data frames being representative of the signal emitted by the transmitter, to separate the received data frames into words and to deinterlace the words of the received data frames according to the second logic in order to form first deinterlaced data frames; - a second deinterlacer, configured to successively receive the first deinterlaced data frames, to separate the first deinterlaced data frames into words and to deinterlace the words of the first deinterlaced data frames according to the first logic in order to form second deinterlaced data frames.

[0021] The invention also relates to a transmission chain comprising a transmitter and a receiver as described above.

[0022] The invention also relates to a data transmission method, implemented by a transmission chain as described above, the method comprising at least the following steps: - processing, by the first interleaver, of the successively received input data frames, the processing comprising a substep of separating the input data frames into words and a substep of interleaving the words from the input data frames are interleaved according to the first logic to form the first interleaved data frames; - successive reception by the second interlacer, of the first interlaced data frames; - processing, by the second interlacer, the processing comprising a sub-step of separating the first interlaced frames into words and a sub-step of interlacing the words of the first interlaced data frames with each other according to the second logic to form the second interlaced data frames; - emission by the transmission module of the signal representing the input digital data; - reception by the receiving module of the signal and conversion into received data frames; - processing, by the first deinterlacer, of the successively received data frames, the processing comprising a sub-step of separating the received data frames into words and a sub-step of deinterlacing the words of the received data frames according to the second logic to form the first deinterlaced data frames; - successive reception by the second deinterlacer of the first deinterlaced data frames; and - processing, by the second deinterlacer, of the first deinterlaced data frames, the processing comprising a sub-step of separating the first deinterlaced frames into words and a sub-step of deinterlacing the words of the first deinterlaced data frames according to the first logic to form the second deinterlaced data frames.

[0023] The invention will become clearer upon reading the following description, given solely by way of non-limiting example, and made with reference to the drawings in which: - [Fig.1] [Fig.1] is a representation of a transmission chain according to the invention; - [Fig.2] [Fig.2] is a block diagram of the transmission chain of the [Fig.l] ; - [Fig.3] [Fig.3] is a diagram of an interleaving performed by a transmitter of the transmission chain of the [Fig.2]; - [Fig.4] [Fig.4] is a diagram of an interlacer and a deinterlacer of the transmission chain of the [Fig.2]; and - [Fig.5] [Fig.5] is a flowchart of a data transmission method according to the invention.

[0024] Figure 1 represents a transmission chain 10 according to the invention. The transmission chain 10 comprises a transmitter 12 and a receiver 14. The transmission chain 10 is an optical transmission chain, or alternatively, not shown, a radio frequency transmission chain.

[0025] The transmitter 12 is advantageously located on the ground, for example in a telecommunications station.

[0026] The receiver 14 is advantageously carried on board an aircraft or a satellite.

[0027] Alternatively, the transmitter 12 is carried on board an aircraft or a satellite, and the receiver 14 is on the ground, for example in a telecommunications station. Alternatively still, both the transmitter 12 and the receiver 14 are on the ground.

[0028] As shown in [Fig.2], the transmitter 12 comprises a digital processing module 16 and, advantageously, a transmission module 18, connected to the digital processing module 16.

[0029] The digital processing module 16 is, for example, implemented partially or entirely as a programmable logic component, such as an FPGA 19 (Field Programmable Gate Array), as shown in [Fig. 2]. Alternatively, not shown, the digital processing module 16 is implemented as an integrated circuit such as an ASIC (Application-Specific Integrated Circuit). Alternatively, or in addition, the digital processing module 16 is implemented at least partially as one or more software programs stored in memory and executable by a processor associated with the memory.

[0030] The digital processing module 16 advantageously includes a channel coding unit 20. The digital processing module 16 further includes a first interleaver 21, a second interleaver 22 connected at the output of the first interleaver 21, and advantageously a synchronization unit 24, connected at the output of the second interleaver 22, and a modulated symbol generation unit 26, connected at the output of the synchronization unit 24.

[0031] The channel coding unit 20 is configured to convert input digital data De into input data frames Te, representative of the input digital data De. The digital data are, for example, observation data from sensors, audio data or images, or more generally data from a digital telecommunications node.

[0032] The first interleaver 21, shown in [Fig. 4], is configured to successively receive the input data frames Te, to separate them into words, and to interleave the words of the input data frames Te with each other according to a first logic in order to form first interleaved data frames Tl.

[0033] The first interleaver 21 is a convolutional interleaver and operates according to a convolution logic. The first logic is therefore a convolution logic.

[0034] Alternatively, the first interlacer 21 is a block interlacer and operates according to a block logic.

[0035] Advantageously, the words are formed of SW 1 bits, SW 1 being a predefined number. The frames have an STI size, expressed as the number of words. Advantageously, the first interleaved data frames T1 transmitted by the first interleaver 21 are formed of words, each consisting of one bit; in other words, SW1 = 1 bit. Thus, in this case, the first interleaved data frames T1 are formed of STI words, each of one bit.

[0036] The STI size of the first interleaved data frames Tl, and the SW1 size of the words of the first interleaved data frames Tl are advantageously parameters of the first interleaver 21, and are advantageously defined by a user.

[0037] The first interlacer 21 advantageously comprises a predetermined number of branches, an input pointer 32 and an output pointer 34.

[0038] As can be seen in [Fig. 4], the first interleaver 21 comprises four branches 30a to 30d. Alternatively, the first interleaver 21 comprises more than four branches. The number of branches is predetermined and defines an interleaving depth jt1, which is another parameter of the first interleaver 21. The interleaving depth jt1 is equal to the number of branches and is greater than or equal to two. Thus, the depth ir1 is equal to four for the first interleaver 21. The first interleaver 21 thus has the following parameters: an STI size of the first interleaved data frames T1, an SW1 size of the words forming the first interleaved data frames T1, and an interleaving depth ir1.

[0039] Each branch 30a to 30d includes a delay register, configured to delay a received word by a predefined duration, equal to a multiple of a STIfal delay z. In practice, the delay registers are implemented in memory, integrated into the FPGA 19. The operation of the first interleaver 21 is described in detail below.

[0040] The second interleaver 22 is configured to receive the first interleaved data frames T1, to separate them into words and to interleave the words of the first interleaved data frames T1 with each other according to a second logic in order to form second interleaved data frames T2.

[0041] The second interleaver 22 is a convolutional interleaver and operates according to convolution logic. The second logic is therefore a convolution logic.

[0042] Alternatively, the second interlacer 22 is a block interlacer.

[0043] Advantageously, the words are formed of at least one bit. Thus, each word has a size SW2, expressed in number of bits. In the case of the second interleaved data frames T2, advantageously, each word is formed of SW2 bits.

[0044] Advantageously, the second interleaved data frames T2 transmitted by the second interleaver 22 have a size ST2, expressed in number of words. In other words, the second interleaved data frames T2 are made up of ST2 words.

[0045] Thus, in this case, each second interleaved data frame T2 comprises ST2 words of SW2 bits each.

[0046] The ST2 size of the second interlaced data frames T2 and the SW2 size of the words of the second interlaced data frames T2 are advantageously parameters of the second interlacer 22, and are advantageously defined by the user.

[0047] The second interleaver 22 comprises a predetermined number of branches, defining a depth ir2. For example, the second interleaver 22 comprises two branches, thus its interleaving depth ir2 is equal to two. Alternatively, the depth ir2 is greater than two. Each branch of the second interleaver 22 comprises a delay register, configured to delay a received word by a predefined duration çm O Itt O, equal to a multiple of a delay z

[0048] In an unrepresented variant, the two interlacers 21 and 22 have the same number of branches, in other words, the same depth of interlacing, i.e. irl=jr2.

[0049] The second interlacer 22 thus has the following parameters: a size ST2 of the second interlaced data frames T2, expressed in number of words, a size SW2 of the words forming the second interlaced data frames T2, expressed in number of bits, and an interlacing depth ir2.

[0050] In practice, the second interleaver 22 is implemented in the form of a sequencing unit 32, a memory 34 and a memory controller 36, connected between the sequencing unit 32 and the memory 34, included in the second interleaver 22.

[0051] The delay registers are implemented in memory 34.

[0052] Advantageously, the memory 34 of the second interleaver 22 is a double data rate (DDR) type memory. In this case, the entire digital processing unit 16 except for the memory 34 is advantageously implemented in the FPGA 19, the memory 34 being implemented in a specific component, as shown in [Fig. 2].

[0053] A minimum size of DDR 34 memory, in number of bits, is equal to half the product of the interleaving depth ir2 of the second interleaver 22, the size ST2 of the second interleaved data frames T2, and the size SW2 of each word forming the second interleaved T2 data frames. In other words, the minimum size of the SDDR memory is expressed according to the following equation: [°°54] SDDR = ïX7t2xST2x SW2

[0055] Thus, advantageously, the size of the DDR 34 memory is chosen to be equal to the minimum size.

[0056] The memory controller 36 is configured to perform memory accesses during the operation of the second interleaver 22.

[0057] The synchronization unit 24 is configured to perform the insertion of unique words enabling the receiver 14 to detect the beginning of interlaced frames that it receives, before performing a deinterlacing operation, explained in detail later.

[0058] The generation unit 26 is configured to adapt the second interleaved T2 frames to a predefined modulation type. In particular, the generation unit 26 is configured to allocate a number of bits from the second interleaved T2 data frames to a modulated symbol. For example, for two-state modulation, one bit from a second interleaved T2 data frame is associated with one modulation bit, that is, with a modulated symbol consisting of one bit. For four-state modulation, two bits from a second interleaved T2 data frame are associated with a modulated symbol consisting of two bits.

[0059] The transmission module 18 includes, for example, an optical modulator 18, such as a Mach-Zehnder interferometer. The transmission module 18 is advantageously configured to emit signals representative of the second interlaced data frames T2. The signals are thus representative of the input data De. The signals here are optical signals So.

[0060] Alternatively, in the case where the transmission chain 10 is a radio frequency transmission chain, the modulator 18 is a radio frequency modulator and the signals are radio frequency signals.

[0061] The receiver 14 advantageously comprises a receiving module 42 and a digital processing module 44, connected to the receiving module 42. Advantageously, the receiving module 42 comprises an optical demodulator.

[0062] In an alternative not shown, in the case where the transmission chain 10 is a radio frequency transmission chain, the demodulator is a radio frequency demodulator.

[0063] The receiving module 42 is advantageously configured to receive the optical signal So emitted by the transmitter 12 and to demodulate it in order to convert it into demodulated digital signals, also called received digital signals Sr, representative of the optical signal So emitted by the transmitter 12.

[0064] The digital processing module 44, similarly to the digital processing module 16, is advantageously implemented, in whole or in part, in the form of a programmable logic component such as an FPGA 49.

[0065] In an alternative not shown or in addition, the digital processing module 44 is implemented at least partially in the form of an integrated circuit, such as an ASIC or one or more software programs stored in a memory and executable by a processor associated with the memory.

[0066] The digital processing module 44 advantageously includes a unit for rendering interlaced words from modulated symbols 46, connected at its output to a synchronization unit 48. The digital processing module 44 includes a first deinterlacer 51 connected at its output to a second deinterlacer 52, and advantageously, a channel decoding unit 54, connected at the output of the second deinterlacer 52. The unit for rendering interlaced words from modulated symbols 46, the synchronization unit 48, the first deinterlacer 51, the second deinterlacer 52, and the channel decoding unit 54 correspond respectively to the unit for generating the modulated symbols from the interlaced words 26, the synchronization unit 24, the second interlacer 22, the first interlacer 21, and the channel encoding unit 20.

[0067] The interleaved word rendering unit 46 from the modulated symbols 46 is advantageously configured to receive the demodulated digital signals Sr, and to convert the demodulated symbols into a likelihood ratio or LLR, from the English "Log Likelihood Ratio", in order to form again interleaved data frames corresponding to the second interleaved data frames T2 and the single words added by the synchronization unit 24.

[0068] The synchronization unit 48 is configured to detect the start of interleaved data frames by detecting unique words. The synchronization unit 48 is further configured to discard unique words inserted during transmission by the synchronization unit 24 and instead transmit a start-of-frame signal directly to the deinterleaving unit 51. The synchronization unit 48 is thus configured to form synchronized interleaved data frames, or received frames Tr, destined for the first deinterleaver 51.

[0069] Advantageously, the rendering unit 46 is configured to convert the modulated symbols into likelihood ratio, or LLR, encoded on QLLR bits. Thus, at the output of the synchronization unit 48, each received frame Tr, which corresponds to the second interleaved data frames T2, comprises ST2 words, and each word is encoded on SW2xQLLR bits, and not SW2 bits.

[0070] The first deinterlacer 51 is shown in [Fig. 4], and is configured to successively receive received data frames Tr, to separate them into words and to deinterlace the words of the received data frames Tr according to the second logic in order to form first deinterlaced data frames Tdl. In other words, the first deinterlacer 51 is configured to perform the inverse operation of the second interlacer 22.

[0071] The second interleaver 22 and the first deinterleaver 51 have the same logic. Thus, the first deinterleaver 51 is a convolutional deinterleaver. The first deinterleaver 51 comprises ir2=2 branches, 60a and 60b, an input pointer 62 and an output pointer 64.

[0072] Thus, the first deinterlacer 51 has the same interleaving depth ir2 and the same size ST2 of deinterlaced data frames emitted as the second interlacer 22.

[0073] Each branch 60a to 60d includes a delay register, configured to delay a ÇT'O / —rO word received of a predefined duration equal to a multiple of a delay z. In the case of branch 60a, this delay is zero.

[0074] In practice, the first deinterlacer 51 is implemented in the form of a unit of sequencing unit 56, of a memory 57 and of a memory controller 58, connected between the sequencing unit 56 and the memory 57, included in the first deinterlacer 51, in a manner similar to that which has been described for the second interlacer 22. The delay registers are in practice implemented in the memory 57.

[0075] Advantageously, memory 57 is DDR memory, the minimum size of which, in bits, is advantageously equal to: [°076] Sddr = STI x SW2 x QLLR

[0077] In this case, the entire digital processing unit 44 except for the memory 57 is advantageously implemented in the FPGA 49, the memory 57 being advantageously implemented in a specific component, as shown in [Fig.2],

[0078] The second deinterlacer 52 is configured to successively receive the first deinterlaced data frames Tdl, to separate the first deinterlaced data frames Tdl into words, and to deinterlace the words of the first deinterlaced data frames Tdl according to the first logic in order to form second deinterlaced data frames Td2. In other words, the second deinterlacer 52 is configured to perform the inverse operation of the first interlacer 21.

[0079] In particular, advantageously, the second deinterlaced data frames Td2 formed by the second deinterlacer 52 comprise SW1xQllr bit words. A size of the second deinterlaced data frames Td2 emitted by the second deinterlacer 52, expressed as a number of words, is equal to STI. The second deinterlaced data frames Td2 formed by the second deinterlacer 52 are therefore of size ST1xSW1xQllr bits.

[0080] The first interleaver 21 and the second deinterleaver 52 have the same logic, so, in the case where the first interleaver 21 is a convolutional interleaver, the second deinterleaver 52 is a convolutional deinterleaver.

[0081] In an unrepresented variant, the first interleaver 21 and the second deinterleaver 52 both have block logic, and are therefore a block interleaver and a block deinterleaver.

[0082] The second deinterlacer 52 comprises irl=4 branches, each branch comprising a delay register in a manner similar to branches 30a to 30d. The second deinterlacer 52 thus has the same interleaving depth ir1 and the same STI size of the transmitted deinterlaced data frames as the first deinterlacer 21.

[0083] The channel 54 decoding unit is configured to receive the second interlaced data frames Td2 and to convert them into digital output data Ds, representative of the input data De.

[0084] A data transmission method is now explained, with reference to Figures 3 to 5.

[0085] During an S100 step, the channel 20 coding unit converts the input digital data De into input data frames Te. For this purpose, advantageously, the channel 20 coding unit implements error correction codes, for example low-density parity codes, or LDPCs, from the English "Low Parity Density Codes".

[0086] The first interleaver 21 processes the input data frames Te received successively during a step S102. The processing step S102 comprises substeps S1022 and S1024. Substep S1022 is a substep for separating the input data frames Te into words of size SW1 bits. Substep S1024 is a substep for interleaving the words formed by separating the input data frames Te from each other according to the first logic to form the first interleaved data frames TL

[0087] The fact that the first interleaver 21 is convolutional requires that the STI size of the first interleaved data frames Tl be equal to a multiple of irl. In the example in Figures 3 and 4, STI and jtl are both equal to four.

[0088] During substep S1024, the words forming an input data frame Te are successively sent to branches 30a through 30d. The choice of branch is imposed by pointer 32. Input pointer 32 traverses each branch successively, advantageously starting with branch 30a, then successively 30b, 30c, and 30d, before starting again with branch 30a. Thus, the first word of The input data frame Te is sent to branch 30a, the second to branch 30b, etc.

[0089] The first interleaver 21 operates at a predetermined "word" clock frequency, of period Th. Thus, a word is sent to one of the branches 30a to 30d at each period Th. In other words, the pointer 32 changes branches every Th.

[0090] Once a word is sent to one of the branches 30a to 30d, the word passes into a delay register, and is thus delayed by a multiple of the delay zsTiZlti which corresponds to the time required for the input pointer 32 to traverse all branches 30a to 30d, in other words irlx Th. Thus, branch 30a does not delay the received word, branch 30b delays the received word by the delay zs, branch 30c delays the received word by twice the delay zs, and branch 30d delays the received word by three times the delay zs.

[0091] The output pointer 34 reads the words on each branch 30a to 30d, and its movement is synchronized with that of the input pointer 32 in order to read the words after they have been delayed by passing through the delay registers of branches 30a to 30d.

[0092] Word interleaving is shown in [Fig. 3]. Each cell represents a word, the input data frames Te are separated into words consisting of one bit each, and the first interleaved data frames Tl are formed from words from the current frame and the preceding (jtl-1) frames. For ease of understanding, the input data Te is represented as separated into frames composed of words, with one word corresponding to one cell, and a case is shown where an input data frame Te comprises four words, the input data frames Te being delimited by the dotted lines.

[0093] Due to the passage through the delay registers, the first word with coordinates (1, 1) is sent to branch 30a, is not delayed, and therefore becomes the first word of the first TL frame. The second word with coordinates (1, 2) is sent to branch 30b, is delayed by the delay z^ / ", and therefore becomes the second word of the next first interleaved Tl data frame. The third word with coordinates (1, 3) is sent to branch 30c, is delayed by twice the delay z, and therefore becomes the third word of the next first interleaved Tl data frame. Once each branch 30a to 30d has been traversed, the input pointer 32 returns to branch 30a and performs the process again.

[0094] Thus, in the example of [Fig. 3], each first word is sent to branch 30a and is not delayed, each second word is sent to branch 30b and is delayed by the delay z, each third word is sent to branch 30c and is delayed by twice the z delay, and every fourth word is sent to branch 30d and is delayed by three times the z delay

[0095] The white squares correspond to blank words, made up of padding bits. Blank words do not contain any information and allow a data frame to be completed if it is incomplete, for example at the beginning of transmission.

[0096] The words of the input data frames Te are thus interleaved to form the first interleaved data frames TL

[0097] The second interleaver 22 successively receives the first interleaved data frames Tl during a step S104. In particular, the first interleaved data frames Tl received by the second interleaver 22 are identical to those emitted by the first interleaver 21, and have not been modified by an electronic component.

[0098] The second interleaver 22 processes the second interleaved data frames T2 during a step S106. The step S106 comprises a substep S1062 and a substep S1064.

[0099] During substep S1062, the second interleaver 22 separates the first interleaved data frames T1 into words of size SW2. The fact that the second interleaver 22 is convolutional requires that the size ST2 of the second interleaved data frames T2 be equal to a multiple of ir2.

[0100] In the example in [Fig.3], the words are of size SW2=4 bits, in other words, each word is made up of four bits. Thus, the size SW2 of the words is equal to the size of the first interleaved data frames Tl, in bits, i.e. SW2=STlxSWl, SW1 being equal to 1.

[0101] During substep S1064, the words formed by the second interleaver 22 are sent to the branches of the second interleaver 22, which comprises ir2=2 branches. The second interleaver 22 operates in the same way as the first interleaver 21, with the parameters ST2 and ir2. Thus, the first branch does not delay the words, and the second branch delays the words by a delay of z ST 2Zlt2- Thus, in the example of [Fig.3], the first word formed by the second interleaver 22, which is the first interleaved data frame T1, becomes the first word of the interleaved data frame T2, the second word, which is the next interleaved data frame T1, becomes the second word of the next second interleaved data frame T2, the third word becomes the first word of the next second interleaved data frame T2, and so on.

[0102] The words formed by the second interlacer 22 from the first interlaced data frames Tl are thus interlaced with each other.

[0103] Unique words are inserted between the second interleaved data frames T2 by the synchronization unit 24, and the bits of the second interleaved data frames T2 are associated with modulated symbols via the generation unit 26 in step S108. Then the signal is emitted by the transmission module 18 in step S10, for example in the form of an optical signal S0. The optical signal S0 is representative of the second interleaved data frames T2.

[0104] Thus, the optical signal So is representative of the digital input data De, which are interleaved in order to be distributed in the optical signal So.

[0105] At step SI 12, the optical signal So is received by the receiving module 42 and converted into received data frames Tr. Advantageously, at step SI 12, the optical signal So is demodulated by the receiving module 42, the restitution unit 46 restores, or converts the demodulated symbols into a likelihood ratio coded on Qllr bits, and the synchronization unit 48 eliminates the unique words inserted by the synchronization unit 24, and forms the received data frames Tr and a start-of-frame signal, in order to synchronize the received data frames Tr.

[0106] Advantageously, during step SI 12, each received likelihood ratio, or LLR, which corresponds to a bit in the second interleaved data frames T2, is encoded on QLLR bits. Thus, each received LLR is encoded in the received data frames Tr as a symbol comprising QLLR bits.

[0107] The first deinterlacer 51 processes the data frames Tr, received successively from the synchronization unit 48 during a processing step SI 14. The processing step SI 14 includes a separation substep SI 142 and a deinterlacing step S1144.

[0108] During the SI 142 separation substep, the received data frames Tr are separated into SW2 QLLR bit symbol words, i.e., SW2 x QLLR bit words. The received data frames Tr are such that they can be separated into ST2 words of the same size, ST2 being a multiple of ir2, as previously indicated. In the example in Figures 3 to 5, the received data frames Tr can be separated into ST2 = 2 words containing SW2 QLLR bit symbols.

[0109] During substep SI 144, the words forming a received data frame Tr are successively sent into branches 60a and 60b of the deinterleaver, the choice of branch being imposed by the pointer 62, as is the case for the interleaver 51. The input pointer 62 traverses each branch successively, advantageously starting with branch 60b, then branch 60a. Thus, the first word of a received data frame Tr is sent into branch 60b, and the second into branch 60a.

[0110] When the first word is sent into branch 60b, it is delayed by a delay equal to z ST 2Zlt2 and when the second word is sent into branch 60a, it is not delayed.

[0111] The output pointer 64 reads the words on branches 60a and 60b, and the movement of the output pointer 64 is synchronized with that of the input pointer 62. Thus, the interleaver 51 deinterlaces the words by arranging them in a manner inverse to the interleaving performed by the second interleaver 22. The words formed by the first deinterleaver 51 are thus deinterlaced, forming first deinterlaced data frames Tdl, whose data are organized in a similar manner to the first interlaced data frames Tl, except that each word is formed of symbols comprising QLLR bits, and not of one-bit symbols.

[0112] In practice, on one of the targeted industrial applications, a word formed by the first deinterlacer 51 by separating a received data frame Tr comprises SW2 = 32768 symbols, each symbol comprising QLlr = 4 bits. Thus, the word size of the first deinterlaced data frames Tdl is on the order of ST1 x Qllr = SW2 x Qllr = 32768 x 4 = 131072 bits. Other values ​​are of course possible, depending on the application.

[0113] The maximum transfer speed of DDR memories is achieved for data to be transferred with a size greater than 100 kbit, for the DDR memories chosen for one of the applications envisaged. Thus, during deinterlacing by the first deinterlacer 51, the size of the words to be sent in branches 60a to 60d, in other words, to be written to and read from memory, is sufficient to ensure optimal speed operation of the DDR memory 57.

[0114] The first Tdl deinterlaced data frames are received successively by the second deinterlacer 52 during an SI step 16. In particular, the first Tdl deinterlaced data frames received by the second deinterlacer 52 are identical to those emitted by the first deinterlacer 51, and have not been modified by an electronic component.

[0115] The second deinterlacer 52 processes the first deinterlaced Tdl data frames during a processing step SI 18, which includes a separation substep SI 182 and a deinterlacing substep SI 184.

[0116] During substep SI 182, the second deinterlacer 52 separates the first Tdl deinterlaced data frames into SW1 symbol words of QLLR bits. The first Tdl deinterlaced data frames are formed of STI words of the same size, STI being a multiple of jri, during step SI 182.

[0117] During the SI 184 deinterlacing substep, the words formed by the second deinterlacer 52 are sent to the branches of the second deinterlacer 52, which includes irl=4 branches. The operation of the second deinterlacer 52 is similar to that of the first deinterlacer 51, with the parameters STI and irl. Thus, the first word is sent to the branch that delays words by four times the delay z ST / "i, the second word to the branch that delays by three times the delay zs T / "i, and so on. This allows the inverse operation of that performed by the first interlacer 21 to be carried out, and the words formed by separating the first deinterlaced data frames Tdl to form the second deinterlaced data frames Td2, whose words are organized similarly to those of the input data frames Te.

[0118] The second deinterlaced data frames Td2 are received and converted by the channel 54 decoding unit during a step S120. Advantageously, by implementing error correction codes, for example LDPC codes, the channel 54 decoding unit generates representative, and advantageously identical, digital output data Ds to the digital input data De.

[0119] Using two successive interleavers 21, 22, and two successive deinterleavers 51 and 52 allows for fine interleaving of the data, thus preventing the loss of an excessive number of bits from a frame in the event of a fade, while distributing them over longer periods, thereby enabling the handling of longer fade times. Furthermore, having two successive deinterleavers 51, 52 optimizes the use of DDR memory, since the size of the data to be transferred to DDR memory exceeds 100 kbits. The DDR memory then operates at its maximum speed, ensuring optimal data processing throughput.

[0120] Alternatively, the memories 57 and / or 34 are made from memories operating in burst mode, that is to say that a memory access speed is maximum when the data is transmitted in packets exceeding a predefined size, for example 100 kbit, and the size of the words formed by separation of the first deinterlaced data frames Tdl by the first deinterlacer 51 and / or the size of the words formed by separation of the first interlaced data frames Tl is greater than this predefined size.

[0121] Any feature described for an embodiment or variant in the foregoing may be implemented for the other embodiments and variants described above, provided that it is technically feasible.

Claims

Demands

1. Transmitter (12) of signals (So) representative of digital input data (De), comprising a digital processing module (16) comprising: - a first interleaver (21) configured to successively receive input data frames (Te), representative of the digital input data (De), to separate them into words, and to interleave the words of the input data frames (Te) with each other according to a first logic in order to form first interleaved data frames (T1); and - a second interleaver (22), configured to receive the first interleaved data frames (T1), to separate them into words and to interleave the words of the first interleaved data frames (T1) with each other according to a second logic in order to form second interleaved data frames (T2), the transmitter (12) further comprising a transmission module (18) configured to transmit the signals (So).

2. Transmitter (12) according to claim 1, wherein the first and second logics are convolution logics, and wherein each interleaver (21, 22) has the following parameters: - a predetermined number of branches (30a, 30b, 30c, 30d) defining an interleaving depth (jtl, ir2); and - a size (STI, ST2) of the interleaved data frames (Tl, T2) emitted by Interleaver (21, 22), expressed in number of words.

3. Emitter (12) according to claim 2, wherein the two interlacers (21, 22) have an equal interlacing depth (jtl, ir2).

4. Transmitter (12) according to any one of claims 2 to 3, wherein the second interleaver (22) is configured to separate the first interleaved data frames (Tl) emitted by the first interleaver (21) into words of a size (SW2), expressed in bits, equal to the size (STI) of the first interleaved data frames (Tl), expressed in bits.

5. Transmitter (12) according to any one of claims 2 to 4, wherein the second interleaver (22) comprises a memory (34), a memory size (SDDR) in number of bits being equal to half the product between the depth of the second interleaver (jt2), the size of the second interleaved data frames (ST2) and the size (SW2) of each word forming the second interleaved data frames (T2) in number of bits.

6. Transmitter (12) according to claim 5, wherein the second interleaver (22) comprises a memory (34) of the double data rate type.

7. Transmitter (12) according to any one of claims 1 to 6, wherein each interleaver (21, 22) is configured to separate the data frames (Te, Tl) that it receives into words consisting of at least one bit.

8. Transmitter (12) according to any one of claims 1 to 7, the digital processing module (16) further comprising a channel coding unit (20), configured to receive the digital input data (De), and to convert the digital input data (De) into input data frames (Te), the input data frames (Te) being representative of the digital input data (De).

9. Receiver (14) comprising a receiving module (42) configured to receive a signal (So) emitted by a transmitter (12) according to any one of claims 1 to 8, the receiver (14) further comprising a digital processing module (44) comprising: - a first deinterlacer (51), configured to successively receive received data frames (Tr), the received data frames (Tr) being representative of the signal (So) emitted by the transmitter (12), to separate the received data frames (Tr) into words and to deinterlace the words of the received data frames (Tr) according to the second logic in order to form first deinterlaced data frames (Tdl); - a second deinterlacer (52), configured to successively receive the first deinterlaced data frames (Tdl), to separate the first deinterlaced data frames (Tdl) into words and to deinterlace the words of the first deinterlaced data frames (Tdl) according to the first logic in order to form second deinterlaced data frames (Td2).

10. Transmission chain (10) comprising a transmitter (12) according to any one of claims 1 to 8 and a receiver (14) according to claim 9.

11. A data transmission method, implemented by a transmission chain (10) according to claim 10, the method comprising at least the following steps: - processing (S 102), by the first interlacer (1), of the input data frames (Te) received successively, the processing (S 102) comprising a substep of separation (S 1022) of the input data frames (De) into words and a substep of interleaving (S 1024) the words of the input data frames (De) with each other according to the first logic to form the first interleaved data frames (Tl); - successive reception (S 104) by the second interlacer (22), of the first interlaced data frames (Tl); - processing (S 106), by the second interlacer (22), the processing (S 106) comprising a substep of separation (S1062) of the first interleaved frames (T1) into words and a substep of interleaving (S 1064) the words of the first interleaved data frames (T1) with each other according to the second logic to form the second interleaved data frames (T2); - emission (SI 10) by the emission module (18) of the signal (So) representative of the digital input data (De); - reception (SI 12) by the receiving module (42) of the signal (So) and conversion into received data frames (Tr); - processing (SI 14), by the first deinterlacer (51), of the received data frames (Tr) successively, the processing (SI 14) comprising a substep of separation (SI 142) of the received data frames (Tr) into words and a substep of deinterlacing (SI 1144) the words of the received data frames (Tr) according to the second logic to form the first deinterlaced data frames (Tdl); successive reception (SI 16) by the second deinterlacer (52) of the first deinterlaced data frames (Tdl); and processing (SI 18), by the second deinterlacer (52), of the first deinterlaced data frames (Tdl), the processing (SI 18) comprising a substep of separation (SI 182) of the first deinterlaced data frames (Tdl) into words and a substep of deinterlacing (S 1184) the words of the first deinterlaced data frames (Tdl) according to the first logic to form the second deinterlaced data frames (Td2).

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