Method for manufacturing an electronic device, and associated electronic device

Abstract

Method for manufacturing an electronic device, and associated electronic device. This description relates to a method for manufacturing an electronic device (100) in and on a substrate (101) comprising: - the formation, in a first region (a) on a first fin of the substrate, of first sacrificial grids of a first length (L1) flanked by first spacers (131) of a first thickness and, in a second region (b) on the substrate, of a second sacrificial grid of a second length (L2) greater than the first length and flanked by second spacers (140) of a second thickness greater than the first thickness; - the formation, in the substrate, of first semiconducting regions (11) around the first sacrificial grids and of second semiconducting regions (12) around the second sacrificial grid;- the replacement of each first sacrificial gate with a first gate (110) to form FinFET transistors (10) and of the second sacrificial gate with a second gate (120) to form a MOSFET transistor (20). Figure for the abbreviation: Fig. 1;

Description

Title of the invention: Method for manufacturing an electronic device, and associated electronic device. Technical field

[0001] This description relates generally to electronic devices, and in particular to the manufacture of electronic devices.

[0002] The present description relates in particular to the manufacture of an electronic device comprising one (or more) metal-oxide-semiconductor field-effect transistor(s) (MOSFET), for example a high-voltage MOSFET, cointegrated with one (or more) fin-fin field-effect transistor(s). Previous technique

[0003] When manufacturing an electronic device comprising different electronic components in and on the same semiconductor substrate, a manufacturer may seek to use the same manufacturing process for all or part of the electronic components, particularly for manufacturing cost reasons. For example, the electronic components of the electronic device may be manufactured on the same production line. However, if the manufacturing process is implemented entirely on the entire semiconductor substrate, without separate treatment such as the application of protective measures like masks, any treatment applied will affect all the electronic components.However, a treatment used to form one electronic component may not be suitable for another electronic component, and it is generally necessary to provide safeguards, such as masks, to prevent certain treatments from being applied to all electronic components.

[0004] Depending on the electronic device to be manufactured, and in particular on the different electronic components to be formed in and on the same semiconductor substrate, it may be complicated, or even impossible, to manufacture the different electronic components on the same production line. For example, it may be necessary to implement specific technological steps to form a MOSFET transistor, for example a high-voltage MOSFET, using FinFET-type transistor manufacturing technology. The voltage considered is the maximum voltage that can be applied to a transistor without risking damage, a high voltage typically being a voltage greater than 3 volts.

[0005] Furthermore, the use of the smallest possible number of protective masks is generally sought. Summary of the invention

[0006] There is a need to improve at least in part certain aspects of known electronic devices, and of known manufacturing processes for electronic devices.

[0007] An embodiment overcomes all or part of the drawbacks of known electronic devices and known manufacturing processes for electronic devices.

[0008] One embodiment provides a method for manufacturing, in and on a semiconductor substrate, an electronic device comprising first finned field-effect transistors in a first region, and at least one second metal-oxide-semiconductor field-effect transistor in at least a second region, the method comprising: - the formation, in the first region, of first sacrificial grids, of a first length, along a first fin of the semiconductor substrate, said first fin having a first width at the level of a first face of the semiconductor substrate and being isolated by first trenches in the semiconductor substrate, and, in each second region, of a second sacrificial grid, of a second length greater than the first length, on the first face of the semiconductor substrate, the first and second sacrificial grids being in a sacrificial material; the formation of the first and second sacrificial grids including the formation of first spacers of a first thickness on the flanks of the first sacrificial grids, and of second spacers of a second thickness greater than the first thickness on the flanks of the second sacrificial grid; - the formation, in the semiconductor substrate, of first semiconductor regions in the first region on either side of the first sacrificial gates flanked by the first spacers, forming drain and source regions of the first transistors; - the formation, in the semiconductor substrate, of second semiconductor regions in each second region on either side of the second sacrificial gate flanked by the second spacers, forming drain and source regions of at least one second transistor; and - the replacement of each first sacrificial grid by a first grid structure and of each second sacrificial grid by a second grid structure.

[0009] According to one embodiment, the sacrificial material is a polycrystalline silicon.

[0010] According to one embodiment, the formation of the first and second sacrificial grids comprises: - the formation, on the semiconductor substrate, of a first portion of a first layer in the sacrificial material in the first region, and of a second portion of the first layer in each second region, said first portion extending over substantially the entire length of the first region, and said second portion extending over the second length, less than the length of the second region, forming all or part of the second sacrificial grid; - the formation, on the sides of the first and second portions of the first layer, of a stack of layers of dielectric material; the stacking of layers of dielectric material on the sides of the second portion of the first layer forming all or part of the second spacers.

[0011] According to one embodiment, the formation of the layer stack comprises: - the formation, on the sides of the first portion of the first layer, respectively of the second portion of the first layer, and on the semiconductor substrate, of first L-shaped portions, respectively second L-shaped portions, of a second layer of dielectric material, preferably of a low permittivity material; - the formation, on the first portions in L, respectively second portions in L, of first portions in D, respectively second portions in D, of a third layer in dielectric material, for example in a nitride, for example in a silicon nitride; - the formation, on the first portions in D, respectively second portions in D, of a fourth layer of dielectric material, for example in a silicon nitride.

[0012] According to one embodiment, the formation of the first and second portions of the fourth layer comprises the deposition and then the etching of said fourth layer so as to form: - in the first region: the first and third portions of the said fourth layer on the first portion of the first layer, the said third portions being arranged in a row and each extending over a length substantially equal to the first length; and - in each second region: the second portions and a fourth portion of said fourth layer on the second portion of the first layer.

[0013] According to one embodiment, the process includes engraving the first portion of the first layer so as to form third portions of said first layer arranged in a row and each extending over a length substantially equal to the first length, forming all or part of the first sacrificial grids.

[0014] According to one embodiment, the etching of the first portion of the first layer is carried out through the third portions of the fourth layer forming an etching mask, the third portions of the first layer extending between the semiconductor substrate and the third portions of the fourth layer.

[0015] According to one embodiment, the formation of the first and second spacers comprises, after the formation of the third portions of the first layer, the formation of first portions of a fifth layer of a dielectric material, preferably with low permittivity, on the flanks of the first sacrificial grids, forming the first spacers, and second portions of said fifth layer on the flanks of each second sacrificial grid covered by the stacking of layers, the second spacers including said second portions of said fifth layer.

[0016] According to one embodiment, the fifth layer comprises a fourth portion extending the second portions of said fifth layer so as to cover the fourth portion of the fourth layer.

[0017] According to one embodiment, the formation of the second semiconductor regions is carried out at the same time as the formation of the first semiconductor regions.

[0018] According to one embodiment, the formation of the second semiconductor regions is carried out before or after the formation of the first semiconductor regions.

[0019] According to one embodiment, the fifth layer comprises a third portion extending on either side of the second sacrificial grid and the second spacers in each second region, so as to mask the semiconductor substrate in said second region during the formation of the first semiconductor regions.

[0020] According to one embodiment, the formation of the first semiconductor regions, and possibly the second semiconductor regions, includes the formation of cavities in the semiconductor substrate from the first face, then the filling of said cavities by epitaxy and implantation of dopant atoms.

[0021] One embodiment provides for an electronic device comprising, in and on a semiconductor substrate, first finned field-effect transistors in a first region and at least one second metal-oxide-semiconductor field-effect transistor in at least a second region; the first transistors each comprising a first gate structure of a first length along a first fin of the semiconductor substrate, said first fin having a first width at the level of a first face of the semiconductor substrate and being isolated by first trenches in the semiconductor substrate, each first gate structure being flanked by a first spacer having a first thickness; each second transistor comprising a second gate structure of a second length on the first face of the semiconductor substrate, the second length being greater than the first length, each second gate structure being flanked by a second spacer having a second thickness greater than the first thickness.

[0022] According to one embodiment, a third transistor among the at least one second transistor is formed on and in an island flush with the first face of the semiconductor substrate, in a third region among the at least one second region.

[0023] According to one embodiment, a fourth transistor among the at least one second transistor is formed along a second fin of the semiconductor substrate, in a fourth region among the at least one second region, the second fin having a second width at the level of the first face of the semiconductor substrate, and being isolated by second trenches in the semiconductor substrate, the second width being greater than the first width; for example: - the second width is at least twice the width of the first width; and / or - the first width is less than 15 nm, for example less than or equal to 10 nm; and / or - the second width is greater than 20 nm, for example greater than or equal to 30 nm.

[0024] According to one embodiment, several second transistors are formed in several second regions; a third transistor from among the at least one second transistor being formed, in a third region from among the at least one second region, on and in an island flush with the first face of the semiconductor substrate; and a fourth transistor among the at least a second transistor being formed, in a fourth region among the at least a second region, on and in a second fin flush with the first face of the semiconductor substrate and isolated by second trenches in the semiconductor substrate, the second fin having a second width greater than the first width, for example at least twice greater than or equal to the first width.

[0025] According to one embodiment, the process comprises the formation of the first fin in the first region and the second fin in the fourth region, the formation of said first and second fins comprising: - the formation, on the first face of the semiconductor substrate, of first pillars in the first region and second pillars in the fourth region, the first and second pillars being arranged next to each other in a row, and being made of a first material, for example an amorphous silicon, the first pillars being separated from each other by a first distance, and the second pillars being separated from each other by a second distance; - the deposition, on the first and second pillars, of a sixth layer of a second material, for example a silicon oxide, selectively etchable compared to the first material, the sixth layer having a third thickness on the sides of the first and second pillars; - the removal of the sixth layer in the first region, said sixth layer being preserved on the sides of the second pillars in the fourth region; - the deposit, on the first and second pillars, of a seventh layer in the second material, the seventh layer having a fourth thickness defined to form, on the sides of the first pillars, first posts disjointed from each other between the first pillars; the sixth and seventh layers forming, on the sides of the second pillars, second posts, the third and fourth thicknesses being defined so that the second posts are joined between the second pillars, the joined second posts forming third posts connecting two adjacent second pillars; and - the removal, for example by engraving, of the first and second pillars in the first material; - the etching of the semiconductor substrate from the first face through the first, second and third posts in the second material forming the etching mask; the etching of the semiconductor substrate forming first trenches in the semiconductor substrate defining the first fin between the first trenches in the first region, and second trenches in the semiconductor substrate defining the second fin between the second trenches in the fourth region.

[0026] According to one embodiment, the fourth layer is less than the third layer.

[0027] According to one embodiment, the fourth thickness is less than half of the first distance.

[0028] According to one embodiment, the third thickness is greater than or equal to half of the second distance.

[0029] According to one embodiment, the first distance is substantially equal to the second distance.

[0030] According to one embodiment, the first thickness is less than or equal to 15 nm and the second thickness is greater than or equal to 30 nm.

[0031] According to one embodiment, the first length is less than or equal to 30 nm and the second length is greater than or equal to 150 nm.

[0032] One embodiment provides a method for manufacturing, in and on a semiconductor substrate, at least one first fin for first finned field-effect transistors (FinFETs) in a first region of an electronic device and at least a second fin for at least a second metal-oxide-semiconductor field-effect transistor (MOSFET) in a second region of the electronic device, the method comprising: - the formation, on a first face of the semiconductor substrate, of first pillars in the first region and second pillars in the second region, the first and second pillars being arranged next to each other in a row, and being made of a first material, the first pillars being separated from each other by a first distance, and the second pillars being separated from each other by a second distance; - the deposit, on the first and second pillars, of a sixth layer in a second material selectively engravable compared to the first material, the sixth layer having a third thickness on the sides of the first and second pillars; - the removal of the sixth layer in the first region, the sixth layer being preserved on the sides of the second pillars in the second region; - the deposit, on the first and second pillars, of a seventh layer in the second material, the seventh layer having a fourth thickness defined to form, on the sides of the first pillars, first posts disjointed from each other between the first pillars; the sixth and seventh layers forming, on the sides of the second pillars, second posts, the third and fourth thicknesses being defined so that the second posts are joined between the second pillars, the joined second posts forming third posts connecting two adjacent second pillars; and - the removal, for example by engraving, of the first and second pillars; - the etching of the semiconductor substrate from the first face through the first, second and third posts forming the etching mask; the etching of the semiconductor substrate forming first trenches in the semiconductor substrate defining at least the first fin of a first width between the first trenches in the first region, and second trenches in the semiconductor substrate defining at least a second fin of a second width between the second trenches in the second region, the second width being greater than the first width.

[0033] According to one embodiment, the second material is also selectively etchable with respect to the semiconductor substrate.

[0034] According to one embodiment, the first material comprises, for example, an amorphous silicon, and the second material comprises, for example, an oxide, for example a silicon oxide.

[0035] According to one embodiment, the fourth layer is less than the third layer.

[0036] According to one embodiment, the fourth thickness is less than half of the first distance.

[0037] According to one embodiment, the third thickness is greater than or equal to half of the second distance.

[0038] According to one embodiment, the first distance is substantially equal to the second distance.

[0039] According to one embodiment, the first pillars are all arranged according to the same first step, and the second pillars are all arranged according to the same second step.

[0040] According to one embodiment, the first step is substantially equal to the second step.

[0041] According to one embodiment, the first distance, the first step and the fourth thicknesses are determined so that the first posts are arranged according to the same third step.

[0042] According to one embodiment, the third step is substantially equal to half of the first step.

[0043] According to one embodiment, the second width is at least twice greater than or equal to the first width.

[0044] According to one embodiment, the first width is less than 15 nm, for example less than or equal to 10 nm, and the second width is greater than 20 nm, for example greater than or equal to 30 nm.

[0045] According to one embodiment, an eighth layer of an oxide, for example a silicon oxide, is disposed on the semiconductor substrate, a ninth layer of a nitride, for example a silicon nitride, is disposed on the eighth layer, the first and second pillars being formed on the ninth layer, the eighth and ninth layers being for example removed after the etching of the semiconductor substrate. Brief description of the drawings

[0046] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0047] [Fig.1] is a partial and schematic cross-sectional view of an example of an electronic device according to one embodiment;

[0048] [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7], [Fig.8], [Fig.9], [Fig.10], [Fig.11], [Fig.12], and [Fig.13] are cross-sectional or top views illustrating steps of a first example of a manufacturing process for an electronic device according to an embodiment;

[0049] [Fig.14], [Fig.15], [Fig.16], [Fig.17], [Fig.18], [Fig.19], [Fig.20], [Fig.21], [Fig.22], [Fig.23], [Fig.24], [Fig.25A], [Fig.25B], [Fig.26], Figures [Fig. 27], [Fig. 28], [Fig. 29], and [Fig. 30] are cross-sectional or top views illustrating steps in a second example of a manufacturing process for an electronic device according to an embodiment corresponding to the electronic device in [Fig. 1]; and

[0050] [Fig. 31 A] and [Fig. 31 B] are partial, schematic cross-sectional views of a another example of an electronic device according to one embodiment. Description of the implementation methods

[0051] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0052] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, not all manufacturing process steps are detailed, as the described embodiments are compatible with all or most manufacturing processes for electronic devices, including FinFET technology manufacturing processes, possibly with adaptations that are within the grasp of a person skilled in the art upon reading this description.

[0053] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0054] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0055] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0056] Throughout the description, the term "on" is used without distinction as to the spatial orientation of the element to which the term refers. For example, in the expression or feature "on a face of a layer," this face is not necessarily oriented upwards but can correspond to a face oriented in any direction. For example, when a layer is deposited on an element, this means that it is deposited on all exposed parts of the element. at the time of the deposition of this layer. In addition, the arrangement of a first element on a second element must be understood as being able to correspond to the arrangement of the first element directly against the second element, without any intermediate element between the first and second elements, or as being able to correspond to the arrangement of the first element on the second element with one or more intermediate elements arranged between the first and second elements.

[0057] In the following description, the terms "insulating" and "conducting" mean, unless otherwise specified, electrically insulating and electrically conductive respectively.

[0058] In the following description, when a substrate is referred to, unless otherwise specified, it refers to a semiconductor substrate.

[0059] In the following description, a channel length of a transistor corresponds substantially to the distance between the source region and the drain region of the transistor. A gate length, or gate structure length, is defined in the direction of the channel length.

[0060] In the following description, the term "fin" refers to a rib, generally elongated in shape, that protrudes. The fin is made of the semiconductor material of the substrate and is delimited by trenches formed in the substrate on either side of the fin.

[0061] Fig. 1 is a partial, schematic cross-sectional view of an example of an electronic device 100 according to one embodiment.

[0062] The electronic device 100 of [Fig.1] is for example an electronic chip, or is part of an electronic chip.

[0063] The electronic device 100 includes a semiconductor substrate 101. By way of example, the substrate 101 is made of silicon or silicon-based.

[0064] Figure 1 shows two regions (a) and (b) of the electronic device 100 in which three FinFET transistors 10 and one MOSFET transistor 20 are formed, respectively. The FinFET transistors 10 are formed along a thin fin of the semiconductor substrate 101. The MOSFET transistor 20 can be formed on and within an island of the semiconductor substrate 101, or on and within a wide fin of the semiconductor substrate 101, wider than the thin fin of the FinFET transistors 10. Examples of fins and islands are described later. The fins and islands are structures of the semiconductor substrate 101 that are flush with the top face 101A of the substrate 101 and are isolated by trenches formed in the substrate 101 from the top face 101A.

[0065] It will be understood that in practice, region (a) may contain a number of FinFET transistors other than three and region (b) may contain a number of MOSFET transistors greater than one. Furthermore, the electronic device 100 could include other electronic components, for example other transistors such as bipolar transistors, diodes, and / or resistors.

[0066] Region (a) is isolated from region (b) by an insulating trench 151, or insulating trenches 151. The MOSFET transistor is also isolated by another insulating trench 152 on the side opposite region (a). The insulating trenches 151, 152 are, for example, shallow insulating trenches, or STI trenches. The insulating trenches 151, 152 extend from the top face 101A of the semiconductor substrate 101, or even slightly above the top face 101A, into a layer 103 described later.

[0067] In region (a), semiconductor regions 11 extend into the substrate 101 on either side of gate structures 110. Similarly, in region (b), semiconductor regions 12 extend into the substrate 101 on either side of a gate structure 120. The semiconductor regions 11 and 12 are, for example, epitaxial layers or regions, for example, formed by epitaxy in cavities, for example, shallow cavities or trenches, made in the substrate 101 from the upper face 101A. The semiconductor regions 11 and 12 are flush with the upper face 101A and preferably extend to a depth less than, or even much less than, the thickness of the substrate 101.

[0068] For example, at least an upper portion 101S of the substrate 101, with a depth greater than or equal to the depth of the semiconductor regions 11, 12, is doped with the first type of conductivity or comprises cells doped with a first type of conductivity, for example, type N, and the semiconductor regions 11 and 12 are doped with the second type of conductivity, for example, type P, to form P-type transistors (PMOS and FinFET PMOS). By way of example, the semiconductor regions 11 and 12 comprise germanium and boron atoms in silicon (SiGeB).

[0069] In the following description, the first type of conductivity is considered to be of the N type, and the second type of conductivity is considered to be of the P type, although it could be the reverse.

[0070] Alternatively, the semiconductor regions 11 and / or the semiconductor regions 12 could be N-type doped, for example include phosphorus atoms in silicon (SiP), to form N-type transistors (NMOS and FinFET NMOS), the boxes in the substrate 101 would then be adapted accordingly, in particular according to the type of conductivity of the substrate 101.

[0071] A person skilled in the art may consider forming N-type FinFET transistors in and on another thin fin, and / or NMOS transistors in and on the semiconductor substrate 101 (broad fin or island). More broadly, the electronic device 100 could include PMOS FinFET transistors and / or NMOS FinFET transistors co-integrated with PMOS MOSFET transistors and / or NMOS MOSFET transistors, the MOSFET transistors being arranged on and in an island of the semiconductor substrate 101 and / or on and in a wide fin of the semiconductor substrate 101.

[0072] The semiconductor regions 11 correspond to the source and drain regions of the FinFET transistors 10. In such a structure, the drain of a FinFET transistor corresponds to the source of the neighboring FinFET transistor, and / or conversely the source of a FinFET transistor corresponds to the drain of the neighboring FinFET transistor.

[0073] The semiconductor regions 12 correspond to the source and drain regions of the MOSFET transistor 20.

[0074] Each grid structure 110, 120 is positioned on the upper face 101A of the substrate 101, being generally isolated from the substrate by a layer of grid insulator, or grid insulator 111, 121. The grid insulator is for example a silicon oxide, for example SiO2, or a nitride oxide (SiON).

[0075] In region (b), the gate insulator 121 also covers the side walls of the gate structure 120 over at least a partial height thereof, corresponding to the lower portion 120A described below. Furthermore, the gate insulator 121 of the MOSFET transistor 20 has a thickness e2 that is greater than the thickness e1 of the gate insulator 111 of the FinFET transistors 10, for example, at least twice as much. This allows for a high-voltage MOSFET, or HV transistor, in region (b). The HV transistor 20 operates, for example, at least at 3.3 volts (V). FinFET transistors 10 generally operate at a voltage lower than approximately 1 V.

[0076] For example, the thickness e2 is between 5 and 8 nm, for example equal to about 6.5 nm (corresponding to a GO2 transistor, "Gate Oxide 2" in English), and the thickness el is between 0.6 and 1.5 nm, for example equal to about 0.8 nm (corresponding to a GO1 transistor, "Gate Oxide 1" in English).

[0077] Each grid structure 110, 120 comprises a layer, or a multilayer structure, generally comprising at least one metallic material, for example titanium nitride (TiN), tantalum nitride (TaN) and / or tungsten (W).

[0078] For example, each grid structure 110, 120 comprises a lower portion 110A, 120A including: - a layer 112, 122 of a material of high permittivity, or dielectric constant (high-k), for example a hafnium oxide (HfO2), at the bottom on the grid insulator layer 111, 121, and on the side walls of the grid structure 110, 120; - a layer 113, 123 made of a metallic material, for example titanium nitride (TiN), on layer 112, 122; and - a layer 114, 124 in a metallic material different from that of layer 113, 123, for example in tungsten (W), on layer 113, 123.

[0079] It is recalled that a high permittivity material, or high-k material, is a material with a dielectric constant greater than that of silicon dioxide.

[0080] In region (a), the high-k layer 112 directly covers the side walls of each grid structure 110, while in region (b), the high-k layer 122 covers the grid insulator 121 on the side walls of the grid structure 120.

[0081] Layers 112, 122 and 113, 123 are for example U-shaped, and layers 114, 124 each correspond to a filling layer which fills the space in the grid structure 110, 120 not filled by the other layers.

[0082] In the example shown, each grid structure 110, 120 comprises an upper portion 110B, 120B on the lower portion 110A, 120A, this upper portion having a silicon nitride layer 115, 125. This layer 115, 125 forms a protective layer, during an operation to remove an oxide layer 104 described later, to deposit a silicide contact layer on the drain and source regions.

[0083] This example of a grid structure is not limiting, and other grid structures may be considered by a person skilled in the art.

[0084] The gate structure 120 of the MOSFET transistor 20 has a length L2 which is greater than the length L1 of the gate structure 110 of each FinFET transistor 10. It is recalled that the length of a gate structure is taken in the channel length direction of the transistor considered, visible in [Fig.1].

[0085] For example, the length L1 is less than or equal to 30 nm and the length L2 is greater than or equal to 150 nm.

[0086] Layers 131, 141 of a dielectric material are positioned on the flanks of each gate structure 110, 120, forming spacer layers, or spacers, on either side of the gate structures 110, 120. Advantageously, the dielectric material of the spacers 131, 141 is a low-permittivity, or low-dielectric constant (low-k) material, for example SiOCN or SiBCN. Applied to spacers, a low-permittivity, or low-k, material is a material having a dielectric constant lower than that of silicon nitride, typically a permittivity less than 7, but generally higher than that of silicon oxide, which is about 3.9.

[0087] For example, the spacers 131 have a thickness e8 (first thickness) of between 3 and 10 nm or less than 15 nm, and the spacers 141 have a thickness of between 3 and 10 nm or less than 15 nm.

[0088] The thicknesses given for all spacers are taken at the level of the upper face 101A of the substrate 101.

[0089] In region (a), the spacers 131 are mainly on the sides of the grid structures 110.

[0090] In region (b), the grid insulating layer 121 comprises, or is connected to, an insulating portion 126, for example a portion of oxide such as SiO2, on either side of the grid structure 120, and the spacers 141 also extend over this insulating portion 126. The spacers 141 thus have an L-shape.

[0091] In region (b), each spacer 141 is part of a spacer structure 140 which includes several other spacers made of dielectric material. Thus, there is a spacer structure 140 on each side of the grid structure 120. In the example shown, each spacer structure 140 comprises, in addition to the spacer 141: - a spacer 142 in the shape of half of D or of a triangle with a convex hypotenuse, designated D hereafter, positioned on the spacer 141 in L; - a curved spacer 143 on the spacer 142, conforming to the convex shape of the spacer 142: the spacer 143 does not necessarily extend over the entire height of the spacer 142, and may extend over the insulating portion 126; and - a curved spacer 144 on the spacer 143, following the curved shape of the spacer 143, and which does not extend over the insulating portion 126.

[0092] For example, the materials of the different spacers of the spacer structure 140 are not all the same.

[0093] For example, the spacers 141 are made of a low-k material, the spacers 142 are made of a nitride, for example a silicon nitride, the spacers 143 are made of a silicon nitride, and the spacers 144 are made of a low-k material.

[0094] For example, the spacers 142 have a thickness between 15 and 40 nm. For example, the spacers 143 have a thickness between 10 and 20 nm. For example, the spacers 144 have a thickness between 3 and 10 nm.

[0095] For example, the spacer structure 140 has a thickness e9 (second thickness), taken at the top face 101A of the substrate 101, of between 30 and 60 nm, or greater than 30 nm.

[0096] Thus, the spacer structure 140 of the MOSFET transistor 20 has a thickness e9 much greater than the thickness e8 of the spacer 131 of the FinFET transistors 10. This greater thickness of the spacer structure 140 of the MOSFET transistor 20 allows the source and drain regions 12 to be separated from the gate 120 of the MOSFET transistor 20, thereby preventing breakdown of this transistor under high-voltage operation, typically above 3V, so that the MOSFET transistor 20 is suitable for operating at this high voltage. Indeed, the spacers notably determine the spacing between the source and drain regions during the formation of these regions.

[0097] A layer 103 of a dielectric material, for example a silicon nitride, covers the portions not already covered of the upper face 101A of the substrate, as well as the sides of the grid structures 110 and 120 covered by the spacers 131 and 140, following the shapes of these spacers.

[0098] An oxide layer 104, for example in SiO2, fills the spaces between the portions of the upper face 101A covered by the layer 103 and the sides of the grid structures 110 and 120 covered by the spacers 131 and 140 and by the layer 103. Thus, the oxide layer 104 comprises several oxide portions, contained in these spaces.

[0099] Figures 2 to 30 below are views illustrating several examples of manufacturing processes, cointegrating in the same electronic device, of FinFET transistors and a MOSFET transistor, for example, but not necessarily, adjacent to the FinFET transistors.

[0100] In Figures 2 to 30 below, the first region a) of the substrate 101 in and on which the FinFET transistors are formed is shown, and the second region b) of the substrate 101 in and on which the MOSFET transistor is formed is shown.

[0101] Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12 and Fig. 13 are schematic cross-sectional or top views illustrating steps of a first example of a manufacturing process for an electronic device according to an embodiment.

[0102] The sectional views of figures 2 to 12 are made according to the section plane A'A' illustrated in dashed lines in [Fig. 13] which is a top view of [Fig. 12] after the removal of an engraving mask.

[0103] Figures 2 to 13 illustrate a first example of a first phase of the manufacturing process, which is then followed by a second phase, which may be similar to, or adapted from, the steps illustrated in Figures 20 to 30.

[0104] [Fig.2] illustrates, by a partial cross-sectional view, a starting structure comprising the semiconductor substrate 101 (SUB(Si)).

[0105] A layer of oxide 202, for example a silicon oxide (SiO2), rests on the substrate 101.

[0106] A protective layer 203 (or etching stop layer) of dielectric material, for example silicon nitride (SiN), rests on the oxide layer 202.

[0107] Alternatively, layer 202 may be a silicon nitride layer and layer 203 a silicon oxide layer. However, in this case, layers 210 and 220, described later, which are deposited on layer 203 and whose etching must be selective with respect to layer 203, are not silicon oxide, but are, for example, silicon nitride. More generally, a person skilled in the art will be able to adapt the materials of the layers, respecting at least the etching selectivity criteria.

[0108] Several pillars 204 (known by the English term "mandrel") are positioned on layer 203. The pillars 204 can be extended in the direction perpendicular to [Fig. 2], and thus can be in the form of beams. The pillars 204 are arranged in a row, that is, placed side by side along the same direction.

[0109] In the example in [Fig. 2], the pillars are made of amorphous silicon (aSi). The plurality of pillars comprises 204A pillars in region (a) and 204B pillars in region (b). In the example in [Fig. 2], the width 11 and the pitch pl of the 204 pillars are substantially the same for all 204A and 204B pillars. In other words, the spacings Dl, or distances Dl, between two adjacent 204A pillars in region (a) are substantially equal to the distances Dl between two adjacent 204B pillars in region (b). This is not limiting, and, for example, the distance between the 204A pillars may be greater than the distance between the 204B pillars. Furthermore, the width of the 204A pillars may be different from the width of the 204B pillars. The pillars 204A and 204B located between the two regions (a) and (b) have a spacing D2 which is preferably greater than the distance DL

[0110] The pitch pl of the pillars 204 is, for example, between 60 and 120 nm, for example equal to approximately 80 nm. The width 11 of the pillars 204 is, for example, between 20 and 40 nm, for example equal to approximately 30 nm.

[0111] The pillars 204 can be obtained by implementing a photolithography technique, for example by depositing a layer of amorphous silicon on the layer 203, then an etching mask comprising crenellation and protrusion patterns adapted to form the pillars 204 (in particular adapted to the desired widths of the pillars and the desired distances between the pillars), then by etching the amorphous silicon layer through the etching mask.

[0112] [Fig.3] illustrates, by a partial cross-sectional view, a structure obtained after a step of deposition of a layer of oxide 210, for example of SiO2, on the structure illustrated in [Fig.2].

[0113] The oxide layer 210 has a thickness e3 preferably adapted to fill the spaces between two adjacent pillars 204A in region (a) and two adjacent pillars 204B in region (b), and this over substantially the entire height hl of the pillars 204, forming inter-pillar portions (columns) 211. The thickness e3 is for example between 15 and 30 nm, for example equal to about 20 nm for a pitch pl of about 80 nm.

[0114] The oxide layer 210 further comprises substantially horizontal portions 212 on the pillars 204A and 204B, a substantially horizontal portion 213 which covers the layer 203 between the two regions (a) and (b), and substantially vertical portions (posts) 217 ​​against the sides of the pillars 204A at the edges of the plurality of pillars 204A in region (a) and against the flanks of pillars 204B at the edges of the plurality of pillars 204B in region (b).

[0115] The oxide layer 210 conforms to the crenellated shape of the plurality of pillars 204. Thus, the oxide layer 210 has a U-shaped portion 214 between the two regions (a) and (b), and may have hollows 215, typically of a few nanometers, in the inter-pillar (post) portions 211, the hollows 215 extending substantially to the level of the upper surface 204S of the pillars 204. Alternatively, there are no hollows 215.

[0116] Fig. 4 illustrates, by a partial cross-sectional view, a structure obtained after an etching step, preferably a dry etching, of the oxide layer 210 so as to remove the horizontal portions 212 and 213, while retaining the inter-pillar (post) portions 211 (with hollows 216 which can be deeper than the hollows 215 before etching, below the level of the upper surface 204S of the pillars 204), and leaving the vertical portions (posts) 217 ​​in region (a) and in region (b).

[0117] The engraving of [Fig.4] is preferably carried out on a thickness substantially equal to the thickness e3 of the oxide layer 210. This engraving can expose the pillars 204A and 204B.

[0118] Fig. 5 illustrates, by a partial cross-sectional view, a structure obtained after: - the formation of an etching mask 205 (PR1) covering the pillars 204B, the inter-pillar portions (posts) 211 and the vertical portions (posts) 217 ​​in the region (b), while leaving the pillars 204A, the inter-pillar portions (posts) 211 and the vertical portions (posts) 217 ​​exposed in the region (a); then - an etching step so as to remove the inter-pillar portions (posts) 211 and the vertical portions (posts) 217 ​​in the region (a): a wet etching is used which allows the oxide to be removed in a multidirectional manner (isotropic etching), and this, selectively with respect to the silicon of the pillars 204A and the material (resin) of the etching mask 205.

[0119] The engraving mask 205 is then removed.

[0120] Fig. 6 illustrates, by a partial cross-sectional view, a structure obtained after a step of deposition of another oxide layer 220, in the same material as the oxide layer 210, for example SiO2, on the structure illustrated in Fig. 5.

[0121] The oxide layer 220 has a thickness e4 that is less than the thickness e3 of the oxide layer 210, and such that it does not fill the spaces between two adjacent pillars 204A in region (a). Preferably, the thickness e4 is less than half the distance DI between two pillars 204A. The thickness e4 is, for example, between 5 and 15 nm, for example, approximately 10 nm for a pitch pl of approximately 80 nm.

[0122] The oxide layer 220 comprises substantially horizontal portions 222 on the pillars 204A and 204B in regions (a) and (b), substantially vertical portions (posts) 227 against the sides of the pillars 204A in region (a), and it forms, with the portions (posts) 217, substantially vertical portions (posts) 228 against the sides of the two pillars 204B at the edges of the plurality of pillars 204B in region (b). The adjacent vertical portions (posts) 227 in region (a) are disjoint from each other, that is, they are separated from each other by a non-zero distance. Between the two regions (a) and (b), the oxide layer 220 includes a substantially horizontal portion 223 which covers the layer 203. The vertical portions (posts) 227 and 228 which are between the two regions (a) and (b) are also disjoint.In region (a), the oxide layer 220 conforms to the crenellated shape of the plurality of pillars 204A, forming U-shaped portions 225 between two adjacent pillars 204A. The oxide layer 220 also includes a U-shaped portion 224 between the two regions (a) and (b). In region (b), the oxide layer 220 at least partially fills the hollows 216 in the inter-pillar portions (columns) 221, thus potentially forming hollows 225 of substantially the same depth as the hollows 215. Alternatively, there are no hollows 225. In either variant or not, the inter-pillar portions (columns) 221 fill the spaces between two adjacent pillars 204B in region (b). For example, the inter-pillar portions (columns) 221 correspond to the vertical portions (columns) 228 which are joined together between two pillars 204B.

[0123] Figure 7 illustrates, by means of a partial cross-sectional view, a structure obtained after an etching step, preferably a dry etching, of the oxide layer 220 so as to remove the horizontal portions 222 and 223, while retaining the inter-pillar portions (columns) 221 in region (b), the vertical portions (columns) 227 in region (a), and the vertical portions (columns) 228 in region (b). The etching of Figure 7 is preferably carried out over a thickness substantially equal to the thickness e4 of the oxide layer 220, so as to be able to expose the pillars 204A and 204B.

[0124] [Fig.8] illustrates, by a partial cross-sectional view, a structure obtained after a step of removing, by etching, the pillars 204A and 204B, leaving only the inter-pillar portions (posts) 221, the vertical portions (posts) 227 and the vertical portions (posts) 228 on the layer 203. Preferably, a wet etching is used which allows the silicon to be removed from the pillars 204A in a unidirectional manner (anisotropic etching), and this, selectively with respect to the silicon oxide of the portions 221, 227, 228 and the silicon nitride of the layer 203.

[0125] The inter-pillar portions (columns) 221 and the vertical portions (columns) 227 and 228 are generally elongated in the direction perpendicular to [Fig.8], in the form of beams.

[0126] The inter-pillar portions (posts) 221 in region (b) have a width 13 substantially equal to the distance DI between two pillars 204B, and they have a pitch pl substantially equal to the pitch between the pillars 204B.

[0127] The vertical portions (posts) 227 in region (a) have a width 12 substantially equal to the thickness e4 of the oxide layer 220, or even less due to the etching of [Fig. 7]. The vertical portions (posts) 227 have a width 12 less than half the distance DI between two pillars 204A, and thus much less than the width 13 of the inter-pillar portions (posts) 221. Moreover, since each pillar 204A has been replaced by two vertical portions (posts) 227, the vertical portions (posts) 227 have a pitch p2 much smaller than the pitch pl between the pillars 204A, for example about half the pitch pl. For example, for a pitch pl of approximately 80 nm, a pitch p2 of approximately 40 nm can be obtained.

[0128] The values ​​of distance Dl, width dl of the pillars 204, and thickness e4 of the oxide layer 220 can advantageously be defined so that the vertical portions (posts) 227 all have the same pitch p2.

[0129] The vertical portions (posts) 228 in region (b) have a width 14 which is substantially equal to, or probably less than, due to the engravings in figures 4 and 7, the cumulative thicknesses e3 and e4 of the oxide layer 210 and the oxide layer 220.

[0130] The inter-pillar portions (posts) 221 and the vertical portions (posts) 227 and 228 will serve as etching masks during the etching of the semiconductor substrate 101 in the following step, so as to form fins separated by trenches in the substrate 101, as explained below. Since the vertical portions (posts) 227 in region (a) have a width 12 and a pitch p2 that are smaller, respectively, than the width 13 and pitch pl of the inter-pillar portions (posts) 221 in region (b), finer and more closely spaced fins can be formed in region (a) than in region (b).

[0131] The inter-pillar portions (posts) 221 and the vertical portions (posts) 227 and 228 can be designated by the term fin spacers.

[0132] The formation of such fin spacers of different widths and pitches in the two regions (a) and (b), and thus the formation of fins of different widths and pitches in the two regions (a) and (b), is made possible by the two stages of formation of the oxide layers 210 and 220, with a thick oxide layer 210 to fill the spaces between the pillars, this thick layer being removed in region (a), and then another thin oxide layer 220 so as not to fill the spaces between the pillars in region (a). Alternatively, the spaces between the pillars in region (b) could be filled by combining the thicknesses of the two oxide layers 210 and 220, and not necessarily only with the oxide layer 210. Whether or not this alternative is used, a Once the pillars are removed, a pattern of thin, dense fin spacers is obtained in region (a) and a pattern of wider, less dense fin spacers in region (b). These fin spacers form the patterns of an engraving mask intended to create the trenches and thus the fins, as described below.

[0133] Fig. 9 illustrates, by a partial cross-sectional view, a structure obtained at the end of a step of etching the semiconductor substrate 101 through the layers 203 and 202 which are also etched.

[0134] As indicated above, this engraving is carried out through the engraving mask formed by the inter-pillar portions (posts) 221 and the vertical portions (posts) 227 and 228.

[0135] To obtain the structure of [Fig. 9] from [Fig. 8], a mask can be formed that covers at least the central region between the two vertical portions (posts) 227 and 228 positioned opposite each other between regions (a) and (b), so as not to engrave the substrate 101 between regions (a) and (b). This mask can encompass these two opposing vertical portions 227 and 228. The distance between regions (a) and (b) is generally greater than shown in the figures. In other words, regions (a) and (b) are generally farther apart.

[0136] This etching step forms, in the substrate 101, trenches 231 in region (a) and trenches 232 in region (b). The trenches 231, 232 extend from the upper face 101A of the substrate 101, to a depth e5 less than the thickness of the substrate 101.

[0137] The formation of the trenches 231, 232 allows the definition of fins 233, 234 between the trenches 231, 232. The fins 233, 234 correspond to the unetched portions of the semiconductor substrate 101, protected by the inter-pillar portions (posts) 221 and the vertical portions (posts) 227 during the etching.

[0138] The fins 233 in region (a) have a width 12, measured at the upper face 101A of the substrate 101, substantially equal to the width 12 of the vertical portions (posts) 227 and a pitch p2 substantially equal to the pitch p2 between the vertical portions (posts) 227. Similarly, the fins 234 in region (b) have a width 13, measured at the upper face 101A of the substrate 101, substantially equal to the width 13 of the inter-pillar portions (posts) 221 and a pitch pl substantially equal to the pitch pl between the inter-pillar portions (posts) 221. Thus, as explained further, the fins 233 (thin fins) in region (a) are thinner and closer together than the fins 234 (wide fins) in region (b). For example, width 13 is greater than or equal to twice width 12. The thin fins 233 form the fins of FinFET transistors 10. The wide fins 234 can form fins for a or several transistors, such as MOSFET transistors, for example HV transistors.

[0139] One advantage of forming a MOSFET with fins is that it provides a larger transistor width than with planar or island / mesa designs. Indeed, since the transistor gate surrounds the fin, the gate includes vertical portions around the fin that participate in conduction. A larger transistor width for the same top-view area gives this transistor better performance, for example, 30% for a transistor width that increases from 80 nm in planar design to 110 nm in fin design.

[0140] By way of example, trenches 231, 232 do not have, in cross-sectional view, a rectangular shape with a bottom orthogonal to the lateral faces. Trenches 231, 232 have, for example, in cross-sectional view, a trapezoidal shape in which the width of trenches 231, 232 at the level of the upper face 101A of the substrate 101 is greater than the width of trenches 231, 232 at the level of the bottom of these trenches.

[0141] By way of example, the thin fins 233 have a width 12, taken at the upper face 101A of the substrate 101, less than 15 nm, for example less than or equal to 10 nm.

[0142] By way of example, the wide fins 234 have a width 13, taken at the upper face 101A of the substrate 101, greater than or equal to 20 nm, for example equal to about 30 nm.

[0143] Layers 202 and 203 are then removed.

[0144] [Fig. 10] illustrates, by means of a partial cross-sectional view, a structure obtained after a step of deposition of another oxide layer 240, for example of SiO2, on the structure illustrated in [Fig. 9]. More particularly, during this step, the oxide layer 240 is deposited in the trenches 231 and 232, and on the fins 233 and 234, i.e. covers the upper face 101A of the substrate 101.

[0145] Fig. 11 illustrates, by a partial and schematic cross-sectional view, a structure obtained after a step of removing the oxide layer 240 from an upper part of the structure illustrated in Fig. 10.

[0146] More specifically, initially, the oxide layer 240 is removed from the upper face 101A of the substrate 101. This removal is carried out, for example, by chemical mechanical polishing (CMP). The removal of the oxide layer 240 is stopped, for example, when the upper face 101A of the substrate 101 is exposed.

[0147] In a second step, the oxide layer 240 is removed from an upper part in the trenches 231, 232 so as to retain only a portion of oxide 241, 242 of the oxide layer 240 in a lower part of the trenches 231, 232. This removal is carried out, for example, to a depth of between 10 nm and 100 nm, by example of the order of 50 nm. After this step, the thin fins 233, and wide fins 234 on which the different transistors will be made are formed.

[0148] Figure 12 illustrates, by means of a partial and schematic cross-sectional view, a structure obtained at the end of: - the formation of an insulating trench 250 (STI) in the substrate 101 between the two regions (a) and (b); then - the formation of an etching mask 206 (PR2) covering region (a), but leaving region (b) uncovered: more specifically, the etching mask 206 is deposited in the trenches 231 on the oxide portions 241, on the fins 233 and may be partially deposited on the insulating trench 250; then - of an implantation step 207 of a box in the region (b) of the substrate 101 not covered by the etching mask 206.

[0149] The etching mask 206 is then removed, as illustrated in the top view of [Fig. 13]. Note that, for simplification, the oxide portions 241, 242 in the trenches 231, 232 have not been shown in [Fig. 13]. Thus, [Fig. 13] shows thin fins 233 in region (a) and wide fins 234 in region (b) and an insulating trench 250 between regions (a) and (b).

[0150] As indicated above, this first phase of the manufacturing process, illustrated in Figures 2 to 13, is then followed by a second phase, which may be similar to, or adapted from, the steps illustrated in Figures 20 to 30 described later.

[0151] Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25A, Fig. 25B, Fig. 26, Fig. 27, Fig. 28, Fig. 29, and Fig. 30 are sectional and top views illustrating steps of a second example of a manufacturing process for an electronic device according to an embodiment, corresponding to the electronic device 100 of Fig. 1.

[0152] Figures 14 to 19 illustrate a second example of the first phase of the manufacturing process, which is then followed by a second phase, the steps of which are illustrated in Figures 20 to 30.

[0153] The sectional views of Figures 14 to 18 are made according to the section plane AA illustrated in dashed lines in [Fig.19], which is a top view of [Fig.18], after the removal of an engraving mask.

[0154] The sectional views in Figures 20 to 30 are formed along the section plane BB shown in dashed lines in [Fig. 19]. The section plane BB is formed along a thin fin 233 of the semiconductor substrate 101 and corresponds to the length direction of the finned field-effect transistor (FinFET) channels formed in and on this fin 233. The section plane BB is also carried out in the channel-length direction of a metal-oxide-semiconductor field-effect transistor, or MOSFET, formed in and on the semiconductor substrate 101 (in and on an island 235). The cross-sectional views in Figures 20 to 30 could be made along the section plane B'B' shown in dashed lines in [Fig. 13], which would then be along a thin fin 233 and along a wide fin 234 of the semiconductor substrate 101.

[0155] The second example of the first phase illustrated in Figures 14 to 19 differs from the first example illustrated in Figures 2 to 13 in that it does not include the formation of broad fins in region (b). Thus, the MOSFET transistor will be formed in region (b) on a planar portion of the semiconductor substrate 101, this planar portion being an island, that is, a planar portion surrounded by insulating trenches. An island may be designated by the term "mesa".

[0156] [Fig. 14] illustrates, by a partial and schematic cross-sectional view, a starting structure similar to the structure illustrated in [Fig. 6], but without the pillars 204B and the portions 221, 222, 228 in region (b). Thus, the starting structure comprises the semiconductor substrate 101 (SUB(Si)), the oxide layer 202, for example a silicon oxide (SiO2), on the substrate 101, the protective layer 203 of dielectric material, for example silicon nitride (SiN), on the oxide layer 202, and the pillars 204A of amorphous silicon (aSi) in region (a). A layer of oxide 320, for example of SiO2, is deposited on the pillars 204A and the layer 203. The oxide layer 320 is similar to the oxide layer 220 described in connection with [Fig.6], and in particular it has a similar thickness e4, such that it does not fill the spaces between two adjacent pillars 204A in the region (a).Preferably, the thickness e4 is less than half the distance DI between two 204A pillars.

[0157] The oxide layer 320 comprises: - portions 322 substantially horizontal on the pillars 204A; - substantially horizontal portions 323 on layer 203 in region (b), between the two regions (a) and (b), and between pillars 204A in region (a); and - portions (posts) 227 substantially vertical on the sides of the pillars 204A, similar to the vertical portions (posts) 227 described in connection with [Fig.6].

[0158] In region (a), the oxide layer 320 conforms to the crenellated shape of the plurality of pillars 204A, forming U-shaped portions 225 between two adjacent pillars 204A, similar to the U-shaped portions 225 described in connection with [Fig.6].

[0159] Fig. 15 illustrates, by means of a partial and schematic cross-sectional view, a structure obtained after an etching step, preferably a dry etching, of the oxide layer 320 so as to remove the horizontal portions 322 and 323, leaving the vertical portions (posts) 227 in region (a). The etching of Fig. 15 is preferably made to a thickness substantially equal to the thickness e4 of the oxide layer 220, so as to be able to uncover the pillars 204A.

[0160] Fig. 16 illustrates, by a partial and schematic cross-sectional view, a structure obtained after a step of removal, by anisotropic wet etching, of the pillars 204A, leaving only the vertical portions (posts) 227 on the layer 203. The vertical portions (posts) 227 are generally elongated in the direction perpendicular to Fig. 16, in the form of beams.

[0161] Similar to the vertical portions (posts) 227 described in connection with [Fig. 8], the vertical portions (posts) 227 of [Fig. 16] have a width 12 substantially equal to the thickness e4 of the oxide layer 320, or even less due to the etching of [Fig. 15]. Thus, the vertical portions (posts) 227 have a width 12 less than half the distance DI between two pillars 204A. Moreover, since each pillar 204A has been replaced by two vertical portions (posts) 227, the vertical portions (posts) 227 have a pitch p2 much smaller than the pitch pl between the pillars 204A, for example, about half the pitch pl. For example, for a pitch pl of approximately 80 nm, a pitch p2 of approximately 40 nm can be obtained.

[0162] The values ​​of distance Dl, width dl of the pillars 204A, and thickness e4 of the oxide layer 320 can advantageously be defined so that the vertical portions (posts) 227 have the same pitch p2.

[0163] Next, after this removal step, an etching mask 305 (PR3) is formed on the region (b).

[0164] Figure 17 illustrates, by means of a partial and schematic cross-sectional view, a structure obtained after etching the semiconductor substrate 101 through layers 203 and 202, which are also etched. The etching in Figure 17 is similar to that described in connection with Figure 9, except that it is carried out in region (a), but the semiconductor substrate 101 is not etched in region (b), which is protected by the etching mask 305.

[0165] This engraving is carried out through the vertical portions (posts) 227, also forming an engraving mask in the region (a).

[0166] This etching step forms, in the substrate 101, trenches 231 in region (a) similar to the trenches 231 illustrated in [Fig. 9]. The trenches 231 extend from the upper face 101A of the substrate 101, to a depth e5 less than the thickness of the substrate 101. The formation of the trenches 231 allows for the definition of fins 233 between the trenches 231. The fins 233 correspond to the unetched portions of the semiconductor substrate 101 in region (a), protected by the vertical portions (posts) 227. The trenches 231 and the fins 233 are formed only in region (a), region (b) remaining substantially flat.

[0167] The fins 233 have a width, measured at the upper face 101A of the substrate 101, substantially equal to the width 12 of the vertical portions (posts) 227 and a pitch p2 substantially equal to the pitch between the vertical portions (posts) 227.

[0168] The fins 233 form the fins of the FinFET transistors 10.

[0169] By way of example, the fins 233 have a width, taken at the level of the upper face 101A of the substrate 101, of less than 15 nm, for example less than or equal to 10 nm.

[0170] Layers 202 and 203 are then removed.

[0171] The steps of depositing another oxide layer in the trenches 231 and on the fins 233, and then removing this oxide layer from the top of the fins 233 and from an upper part of the trenches 231, can then be carried out so as to retain only a portion of oxide 241 in a lower part of the trenches 231, similarly to what is described in connection with Figures 10 and 11, but only in region (a). A new mask is therefore expected in this case on the upper face 101A of the substrate 101 in region (b). This can be carried out before, or after, the formation of the insulating trenches 151 and 152 described below.

[0172] Fig. 18 illustrates, by a partial and schematic cross-sectional view, a structure obtained at the end of the formation of an insulating trench 151 (STI) in the substrate 101 between the two regions (a) and (b) and of an insulating trench 152 (STI) on the other side of the region (b) with respect to the insulating trench 151. The trenches 151 and 152 form an island 235 of the semiconductor substrate 101 in the region (b).

[0173] Then, similarly to what is described in connection with [Fig. 12], an etching mask 306 (PR4) is formed, covering the region (a), but leaving the region (b) uncovered: more particularly, the etching mask 306 is deposited in the trenches 231 on the oxide portions 241, on the fins 233 and can be partially deposited on the insulating trench 151; then a step of implanting a box 307 is carried out in the region (b) of the substrate 101 not covered by the etching mask 306.

[0174] The etching mask 306 is then removed, as illustrated in the top view of [Fig. 19]. Note that, for simplification, the portions of oxide 241 in the trenches 231 have not been shown in [Fig. 19].

[0175] As previously stated, a second phase of the manufacturing process is described below, in relation to Figures 20 to 30, according to the BB sections shown in [Fig. 19]. This second phase notably enables the formation of sacrificial gates for the FinFET and MOSFET transistors, the formation of the semiconductor regions 11, corresponding to the source and drain regions of the FinFET transistors 10, and the semiconductor regions 12 corresponding to the source and drain regions of the MOSFET transistor 20, and then the finalization of the gate structures 110 and 120 of the FinFET and MOSFET transistors (so-called gate replacement steps, from the English "gate replacement").

[0176] The sacrificial grids described comprise a sacrificial material, generally a semiconductor material, which is polycrystalline silicon in the examples described. The sacrificial grids described may also comprise, on the sacrificial material, a dielectric layer, for example of silicon nitride, although this example is not limiting.

[0177] The steps described below (second phase) are based on a FinFET transistor fabrication technology and are adapted to form, through co-integration with FinFET transistors, MOSFET transistors that can be HV transistors. Note that the steps previously described (first phase) are also based on a FinFET transistor fabrication technology.

[0178] Figure [Fig. 20] illustrates, by a partial and schematic cross-sectional view, a structure obtained after deposition, on the structure of Figure [Fig. 19]: - a protective layer, or etching stop layer, 402 on the upper face 101A of the substrate 101; - of a layer of polycrystalline silicon 403, or polysilicon, (Poly) on the 402 layer; - a 404 protective layer, or hard mask (Nitride HM), on the 403 polysilicon layer.

[0179] The etching stop layer 402 is advantageously made of an oxide, for example a silicon oxide, for example SiO2. This etching stop layer 402 is more generally made of a material that allows for selective etching with respect to polysilicon. This selective etching step is described in the following description with reference to [Fig. 25A] and 25B.

[0180] The protective layer 404 can be in a nitride, for example a silicon nitride, or even an oxide, for example a silicon oxide.

[0181] Fig. 21 illustrates, by a partial and schematic cross-sectional view, a structure obtained at the end of the steps described below.

[0182] An engraving of the stacking 405 of layers 403 and 404 is carried out in the region (b).

[0183] Before carrying out this etching, an etching mask (not shown) is deposited on layer 404. The etching mask is configured to mask the whole region (a), for example up to above part of the insulating trench 151, as well as a substantially central part of the region (b), and leave the other parts of the region (b) uncovered.

[0184] After this engraving through this engraving mask, the stack 405 of the engraved layers 403 and 404 forms a stack 405a of unengraved portions 403a and 404a in region (a), and a 405b stack of unetched 403b and 404b portions in region (b), this 405b stack allowing the location of the future sacrificial gate structure of MOSFET transistor 20 to be drawn.

[0185] A layer 406 of a low-permittivity, or low-dielectric constant (low-k) material is deposited on the top faces and against the sides of the stacks 405a and 405b, as well as on the exposed portions of the layer 402. In other words, the layer 406 conforms to the shape of the structure obtained after etching the stack 405. The low-k material is, for example, SiOCN or SiBCN.

[0186] For example, layer 406 has a thickness e6 between 3 and 10 nm, for example equal to about 5 nm.

[0187] Then a mask 407 (PR5) is formed on the stack 405a, and extends over the side of the stack 405a to a portion of the layer 406 between the stacks 405a and 405b. This mask 407 makes it possible to mask the region (a), and possibly a portion of the region (b), during an ion implantation step of the substrate 101 in the region (b), from the top face 101A and on either side of the stack 405b, so as to form LDD semiconductor regions, from the English "Lightly Doped Drain", or lightly doped drain regions.

[0188] The 406 low-k layer allows the MOSFET transistor to have the same framework (the 406b low-k material spacers) around the polysilicon 403b in region (b) as will be found later in the process around the polysilicon 403c in region (a) (the 421 low-k material spacers described later) for the FinFET transistors (see Figures 25A and 25B and the corresponding description). Thus, when the sacrificial gates are removed, i.e., the polysilicon 403c and 403b in regions (a) and (b) respectively (see [Fig. 28] and the corresponding description), the etching can be selective with the same low-k material on both the FinFET and MOSFET transistor sides.

[0189] Mask 407 is then removed.

[0190] Fig. 22 illustrates, by a partial and schematic cross-sectional view, a structure obtained at the end of the steps described below.

[0191] After the removal of the mask 407, a nitride layer 408, for example silicon nitride, is deposited on the stacks 405a and 405b and on the layer 406. Then, a nitride etch is carried out, which includes the layer 408, the low-k layer 406, the portions 404a and 404b of the nitride layer 404, stopping on the portions 403a and 403b of the polysilicon layer 403 and on the layer 402. This results in the formation of spacers on the flanks of the polysilicon portions 403a and 403b.

[0192] In region (b), the formed spacers include: - 406b portions in L of layer 406: each 406b portion in L comprises a vertical part against a flank of the 403b polysilicon portion, the vertical part extending horizontally onto layer 402; and - 408b spacers in D in contact with the 406b spacers in L.

[0193] The portions 406b form, for example, the spacers 141 illustrated in [Fig. 1]. The spacers 408b correspond, for example, to the spacers 142 illustrated in [Fig. 1].

[0194] In region (a), the formed spacers include: - another portion 406a in L of layer 406: this other portion 406a comprises a vertical part against one flank of the polysilicon portion 403a (only one flank is visible in [Fig. 22] but generally there are two), the vertical part extending horizontally onto layer 402; and - a 408a spacer in D in contact with the 406a spacer in L in region (a).

[0195] Once the spacers 406b and 408b have been formed, a step of implantation of the substrate 101 in the region (b) can be carried out, from the upper face 101A and on either side of the portion 403b of polysilicon flanked by the spacers 406b and 408b, so as to form the drain and source regions (SD) of the MOSFET transistor 20.

[0196] This implantation step is preferably performed after the formation of a mask on region (a). Although only one MOSFET transistor is shown in region (b), several MOSFET transistors may be present, for example, of the NMOS and PMOS types. In this case, one or more masks can also be provided on region (b) to mask the future PMOS transistors during the implantation of the N-type transistor and similarly to mask the future NMOS transistors during the implantation of the P-type transistor.

[0197] This implantation step is however optional at this stage of the process and can be carried out in a later step, as described later in the description in relation to figures 25A and 25B.

[0198] [Fig.23] illustrates, by a partial and schematic cross-sectional view, a structure obtained after a step of deposition of a protective layer 410, or hard mask (SiN HM), in a dielectric material, for example a nitride, for example a silicon nitride, on the structure illustrated in [Fig.22].

[0199] The layer 410 has a thickness e7, measured from the top face of the polysilicon portion 403a, for example greater than 30 nm.

[0200] Figure 24 illustrates, by means of a partial and schematic cross-sectional view, a structure obtained after an etching step of layer 410 through an etching mask (mask not shown) configured to form: - in region (a): several portions 411 of layer 410 on portion 403a of polysilicon and a portion 412 of layer 410 forming another spacer on spacer 408a; and - in region (b): a portion 413 of layer 410 on the portion 403b of polysilicon and portions 414 of layer 410 forming other spacers on the spacers 408b.

[0201] The portions 411 are arranged in a row, that is to say arranged next to each other along the same direction, and appear in [Fig.24] in the form of posts, but they generally extend in the direction perpendicular to [Fig.24], forming for example beams.

[0202] The 414 spacers correspond for example to the 143 spacers illustrated in [Fig.1].

[0203] Portion 413 has a length L5 which is greater than the length L4 of the polysilicon portion 403b. Preferably, portion 413 extends on both sides of the polysilicon portion 403b, extending above the spacers 406b, or even above the spacers 408b.

[0204] For example, portion 413 protects portion 403b of polysilicon during the etching operations described in the following description.

[0205] Figures 25A and 25B illustrate, by two partial and schematic cross-sectional views, structures illustrating two variants for realizing the semiconductor regions 11 (sources and drains) of the FinFET transistors 10.

[0206] Before creating these semiconductor regions 11, in a manner common to both variants, the polysilicon portion 403a is etched in region (a), the polysilicon portion 403b in region (b) being protected from this etching in particular by the portion 413 of layer 410 and by the spacers 406b, 408b, 414. In addition, the posts 411 on the polysilicon portion 403a form patterns of an etching mask in region (a) by protecting from the etching the polysilicon portions located under these posts 411. The etching thus makes it possible to form polysilicon posts 403c aligned under the posts 411.

[0207] In region (a), the sacrificial grids 430 each comprise a stack of a post 411 of dielectric material on a post 403c of polysilicon.

[0208] In region (b), the sacrificial grid 440 comprises the polysilicon portion 403b covered on its sides by the dielectric material spacers 406b, 408b, 414 and on its upper face by the dielectric material portion 413.

[0209] The sacrificial grid 440 has a length L4, and the sacrificial grids 430 have a length L3 that is less than the length L4. The length L3 of the sacrificial grids 430 corresponds approximately to the length L1 of the grid structures 110 in [Fig. 1]. The The length L4 of the sacrificial grid 440 corresponds approximately to the length L2 of the grid structure 120 of [Fig.l].

[0210] The polysilicon etching stops at the oxide layer 402, which forms an etching stop layer. Another etching then removes all the portions of the oxide layer 402 exposed in regions (a) and (b). Portions 402a of the oxide layer 402 remain under the sacrificial grids 430, and a portion 402b of the oxide layer remains under the sacrificial grid 440 and the spacers 406b, 408b, 414. The portion 402b of the oxide layer 402 forms, for example, all or part of the insulating portion 126 illustrated in [Fig. 1].

[0211] The spacers 406a, 408a and 412 in region (a) are generally retained, although this does not appear in Figures 25A, 25B and the following: these spacers can serve as a transition between the FinFET transistors and the MOSFET transistor(s).

[0212] A layer 420 of a low-k dielectric material is then deposited on the sacrificial grids 430, 440 and on the upper face 101A of the substrate 101. Preferably, the low-k material of the layer 420 is the same as the low-k material of the layer 406.

[0213] This layer 420 is then engraved in the region (a) so as to remove the portions of the layer 420 located on the substrate 101 and above the sacrificial grids 430 and to retain in the region (a) only portions 421 on the sides of the sacrificial grids 430.

[0214] The portions 421 in the region (a) form spacers which will in particular allow the shape of the sacrificial grids 430 to be maintained during the grid replacement steps described later in relation to Figures 28 to 30. The portions 421 form for example the spacers 131 illustrated in [Fig.1], and have a thickness e8 for example between 3 and 10 nm, or less than 15 nm.

[0215] An engraving mask (not shown) is formed to mask all or part of region (b), leaving region (a) uncovered. This engraving mask is configured differently according to the variants of Figures 25A and 25B.

[0216] After deposition and etching of the layer 420, the semiconductor regions 11 are formed at least in the region (a), in the substrate 101, on either side of the sacrificial grids 430 coated with the spacers 421.

[0217] Preferably, the semiconductor regions 11 are formed by epitaxy in the substrate 101. In particular, cavities 409a are formed in the region (a) of the substrate 101 from the top face 101, on either side of the sacrificial gates 430 coated with the spacers 421, and then these cavities 409a are filled by in-situ doped epitaxy of type P (e.g. SiGeB) to form FinFET transistors of the PMOS type, and / or of type N (e.g. SiP) to form FinFET transistors of the NMOS type.

[0218] In the variant of [Fig. 25A], the etching mask covers the entire region (b), even extending onto the insulating trench 151, so that layer 420 is conserved entirely in region (b). In particular, horizontal portions 423 of layer 420 are conserved on the upper face 101A of substrate 101 on either side of sacrificial grid 440. In addition, portions 422 of layer 420 are conserved in region (b) on spacers 414, these portions 422 forming for example other spacers, and portions 424 covering portion 413.

[0219] The 422 spacers correspond for example to the 144 spacers illustrated in [Fig.1].

[0220] In this variant, layer 420 protects the entire region (b) from the etching and epitaxial operations performed in region (a). Thus, the semiconductor regions 12 of the MOSFET transistor 20 are not produced at the same time as the semiconductor regions 11 of the FinFET transistors 10.

[0221] The variant in [Fig. 25A] allows for the fabrication of semiconductor regions 12 that are not necessarily identical to the semiconductor regions 11, and which, for example, are closer to the drain and source regions conventionally fabricated for MOSFET transistors than to those fabricated for FinFET transistors. The semiconductor regions 12 can be formed by ion implantation in an earlier step, for example during the step illustrated in connection with [Fig. 24] or with [Fig. 22], or even after the formation of the semiconductor regions 11. Alternatively, the semiconductor regions 12 can be formed by epitaxy, similarly to the semiconductor regions 11, but in an earlier or later step.

[0222] In the variant of [Fig.25B], the engraving mask does not cover the region (b).

[0223] In this embodiment, the semiconductor regions 12 of the MOSFET transistor 20 are made at the same time as the semiconductor regions 11. Preferably, the semiconductor regions 12 are then formed by epitaxy in the substrate 101. In particular, cavities 409b are formed in the substrate 101 in the region (b) from the upper face 101A, on either side of the sacrificial gates 440 coated with the spacers 406b, 408b, 414 (or even 422), then these cavities 409b are filled by epitaxy and implantation of P-type dopant atoms (for example SiGeB) to form a PMOS-type MOSFET transistor, and / or N-type dopant atoms (for example SiP) to form an NMOS-type MOSFET transistor. These operations of forming and filling cavities 409b can advantageously be carried out at the same time as those of cavities 409a.

[0224] The variant of [Fig.25B] makes it possible to reduce the number of masks, and thus the manufacturing costs, since it is not necessary to mask the region (a) during the formation of the semiconductor regions 12 in the region (b) and to mask the region (b) during the formation of the semiconductor regions 11 in the region (a).

[0225] As shown in [Fig.25B], after etching a thin layer of the 420 layer may remain on the sacrificial grid 440: for example, a thin layer of portions 422 of the 420 layer on the spacers 414, which may form other spacers, and a thin layer of portions 424 covering the sides of the portion 413. Alternatively, the etching may remove all of the 420 layer in region (b) so that the 420 layer does not cover the sacrificial grid 440 at all.

[0226] The spacers 406b, 408b, 414, and possibly 422, form a multi-layer dielectric spacer structure similar to the spacer structure 140 illustrated in [Fig.1].

[0227] For example, the 406b spacers (141) have a thickness of between 3 and 10 nm, or less than 15 nm. For example, the 408b spacers (142) have a thickness of between 15 and 40 nm. For example, the 414 spacers (143) have a thickness of between 10 and 20 nm. For example, the 422 spacers (144) have a thickness of between 3 and 10 nm. For example, the spacer structure (140) has a total thickness e9, taken at the top face 101A of the substrate 101, of between 30 and 60 nm, or greater than 30 nm.

[0228] The resulting spacer structure has a significant thickness due to the stacking of these spacers. This significant thickness can be used to form the drain and source regions of the MOSFET 20, as it increases the channel length between the drain and source regions. This, in particular, allows for an increase in the operating voltage of the MOSFET 20, making it suitable for high-voltage operation. For example, the channel length of the MOSFET 20 is greater than or equal to 200 nm.

[0229] In the following description, we start from [Fig.25B], but a person skilled in the art can easily adapt the steps described below starting from [Fig.25A].

[0230] Figure 26 illustrates, by means of a partial and schematic cross-sectional view, a structure obtained at the end of the following steps: - deposition of an etching stop layer 451, for example a nitride layer, on the structure illustrated in [Fig.25B], i.e. on the substrate 101 and on the sacrificial grids 430 and 440 coated with their spacers; - deposition of a 452 layer of oxide, for example SiO2, on the 451 layer.

[0231] For example, an upper portion of the layer 452 which extends beyond the upper face of the sacrificial grids 430 and 440 is removed, for example by chemical mechanical polishing (CMP).

[0232] Layer 452 fills the spaces between the portions of the upper face 101A covered by layer 451 and the sides of the sacrificial grids 430 and 440 covered by spacers 421 and 406b, 408b, 414, 422 and by layer 451. Thus, layer 452 includes several portions in these spaces.

[0233] In addition, an upper portion of the sacrificial grids 430 and 440, and of the spacers 421 and 406b, 408b, 414, 422 of these sacrificial grids, and of layer 451 (upper portions of layer 451 which are on the sides of the sacrificial grids) is removed so as to access at least portions 411 and 413 in the sacrificial grids.

[0234] Thus, sacrificial grids 431 and 441 are obtained with reduced thickness, or height.

[0235] These recesses are preferably made so that the sacrificial grids 431 and 441, the spacers 421 and 406b, 408b, 414, 422, layer 451 and layer 452 are flush with the same upper level.

[0236] Figure 27 illustrates, by means of a partial and schematic cross-sectional view, a structure obtained at the end of the following steps: - removal of another upper portion of layer 452 by etching, preferably to a height h2 such that layer 452, once etched, is substantially at the level of, or even below, the upper face of the polysilicon portions 403c and 403b: this removal is carried out without etching the sacrificial grids 431 and 441, the spacers 421 and 406b, 408b, 414, 422, and layer 451; then - the deposition of a protective nitride layer 453, for example SiN, on the etched layer 452 and the sacrificial grids 431 and 441; - a flattening, for example by CMP, of the nitride layer 453, so as to remove the nitride on the sacrificial grids 431, 441: we obtain a thickness of layer 453 substantially equal to the height h2 of etching of layer 452.

[0237] Figure 28 illustrates, by means of a partial and schematic cross-sectional view, a structure obtained at the end of the following steps: - Removal down to the level of polysilicon 403c, 403b, for example by polysilicon-selective CMP, of portions 411 and 413 in sacrificial grids 431 and 441, of layer 453, and of a partial height of spacers 421, 406b, 408b, 414, 422 and of layer 451 (the removal of these layers and spacers corresponds approximately to a removal of height h3 of portions 431 and 441): for example, height h2 is greater than height h3 so that a height (h2 minus h3) of layer 453 may remain flush with the sacrificial grids 431 and 441, spacers 421, 406b, 408b, 414, 422 and layer 451; then - removal by engraving of portions 403c and 403b of polysilicon in sacrificial grids 431 and 441.

[0238] The height-reduced layer 451 forms, for example, layer 103 illustrated in the [Fig.l].

[0239] The reduced thickness layer 452 forms, for example, layer 104 illustrated in [Fig.1].

[0240] Sacrificial grids of reduced thickness, or height, are obtained with 432 and 442 of thickness, or height.

[0241] Fig. 29 illustrates, by a partial and schematic cross-sectional view, a structure obtained at the end of the following steps.

[0242] A layer 454 of oxide, for example of SiO2, is deposited on the structure illustrated in [Fig.28]. The layer 454 conforms to the shape of the structure of [Fig.28], and in particular is deposited inside, on the bottom and side walls, of the sacrificial grids 432 and 442.

[0243] Next, an etching mask 455 (PR6) is formed on the oxide layer 454 in region (b). The etching mask 455 leaves the portion of the oxide layer 454 in region (a) exposed, which is then removed.

[0244] The engraving mask 455 is then removed.

[0245] [Fig.30] illustrates, by a partial and schematic cross-sectional view, a structure obtained at the end of the steps of filling the sacrificial grids 432 and 442. The filling materials are for example those described in the description of [Fig.1], and are not described again here.

[0246] The structure of [Fig.30] corresponds to the electronic device 100 of [Fig.1], which will not be described again here.

[0247] The portion of the oxide layer 454 located on the layer 453 in region (b), outside the sacrificial grid 442, is removed after filling the grids with metallic material, which is generally followed by flattening using CMP. The reduced-thickness layer 453 was also removed at the same stage of the process.

[0248] There remains an unengraved portion of the oxide layer 454 located on the bottom and side walls inside the sacrificial grid 442, this unengraved portion of the oxide layer 454 forming for example the grid insulator layer 121 illustrated in [Fig.1].

[0249] A person skilled in the art may adapt the second phase of the manufacturing process starting from the structure of Figures 12 and 13, instead of Figures 18 and 19. In other words, instead of forming the MOSFET transistor on an island (or in addition as described below), the MOSFET transistor may be formed along a wide fin 234.

[0250] One advantage of forming the MOSFET transistor on an island is to limit the risks of hot carriers, while one advantage of forming the MOSFET transistor on a wide fin is to increase performance, especially if one opts for the variant described in [Fig.25B] to form the drain and source regions of the MOSFET transistor.

[0251] Fig. 31A and Fig. 31B are partial, schematic cross-sectional views, of another example of an electronic device 300 according to one embodiment. [Fig. 31 A] is a cross-sectional view taken through the insulating trenches and the substrate semiconductor 101. The [Fig.31B] is a cross-sectional view along the CC section plane shown in the [Fig.31A].

[0252] The electronic device 300 of Figures 31A and 31B differs from the electronic device 100 of Figures 1 and 30 in that it comprises three regions (a), (b-1), (b-2): a region (a) with fine fins, a region (b-1) with an island, and a region (b-2) with wide fins.

[0253] The thin fins 233 in region (a) are similar to the fins 233 described in connection with Figures 9 to 13, or Figures 18 and 19. The island 235 in region (b-1) is similar to the island 235 described in connection with Figures 18 and 19. The wide fins 234 in region (b-2) are similar to the fins 234 described in connection with Figures 9 to 13.

[0254] In [Fig.31B], FinFET transistors 10 are shown along a thin fin 233 in region (a), a MOSFET transistor 20-1 on and in the island 235 in region (bl), a MOSFET transistor 20-2 along a wide fin 234 in region (b2).

[0255] Region (a) is isolated from region (b-1) by an insulating trench 351, and region (b-2) is isolated from region (b-1) by another insulating trench 352. Region (b-2) is also isolated by another insulating trench 353 on the opposite side to the insulating trench 352.

[0256] Transistors 10, 20-1 and 20-2 are for example formed in the same manufacturing process, which may be similar to that described in connection with Figures 20 to 30, by adapting the described process.

[0257] It will be understood that in practice, instead of having region (b-1) between regions (a) and (b-2), one could have region (b-2) between regions (a) and (b-1), or region (a) between regions (b-1) and (b-2). One could also have other regions, and / or other orientations or configurations of regions, and more generally any other configuration of regions in which at least one region comprises one or more FinFET transistors and at least one other region comprises one or more MOSFET transistors, for example, one or more HV MOSFET transistors. The MOSFET transistors and / or the FinFET transistors may comprise at least one PMOS transistor and one NMOS transistor.

[0258] One advantage of these embodiments is that they allow the integration, within a single electronic device, of FinFET transistors and high-voltage MOSFET transistors, on a wide fin and / or on an island, while remaining compatible with conventional FinFET transistor manufacturing processes. In particular, these embodiments allow the formation of spacers in a MOSFET transistor using steps present in the conventional FinFET transistor manufacturing process.

[0259] Numerous applications are likely to benefit from the advantages provided by an electronic device according to an embodiment, this electronic device thus being able to be integrated into various types of devices. In particular, the embodiments described above are suitable for any type of device that must perform analog and logic functions on the same electronic chip, for example for a microcontroller.

[0260] By way of example, the electronic device can be integrated into a device intended for the automotive industry, for example in the field of automotive electrification or in the field of advanced driver assistance systems.

[0261] By way of example, the electronic device can be integrated into a device intended for industrial use.

[0262] By way of example, the electronic device may be integrated into a device intended for use in personal electronics.

[0263] By way of example, the electronic device may be integrated into a device intended for use in communication equipment, or in computers and peripherals.

[0264] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0265] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

1. Demands A method for manufacturing, in and on a semiconductor substrate (101), an electronic device (100; 300) comprising first finned field-effect transistors (FinFETs) (10) in a first region (a), and at least one second metal-oxide-semiconductor field-effect transistor (MOSFET) (20; 20b-1, 20b-2) in at least a second region (b; b1, b2), the method comprising: - the formation, in the first region, of first sacrificial grids (430) of a first length (L3) along a first fin (233) of the semiconductor substrate (101), said first fin having a first width (12) at the level of a first face (101A) of the semiconductor substrate and being isolated by first trenches (231) in the semiconductor substrate, and, in each second region, of a second sacrificial grid (440) of a second length (L4) greater than the first length (L3) on the first face (101A) of the semiconductor substrate, the first and second sacrificial grids being in a sacrificial material;the formation of the first and second sacrificial gates including the formation of first spacers (421) of a first thickness (e8) on the flanks of the first sacrificial gates (430) and of second spacers (406b, 408b, 414, 422) of a second thickness (e9) greater than the first thickness (e8) on the flanks of the second sacrificial gate (440); - the formation, in the semiconductor substrate, of first semiconductor regions (11) in the first region on either side of the first sacrificial gates (430) flanked by the first spacers, forming drain and source regions of the first transistors; - the formation, in the semiconductor substrate, of second semiconductor regions (12) in each second region on either side of the second sacrificial gate (440) flanked by the second spacers, forming drain and source regions of at least one second transistor; and - the replacement of each first sacrificial grid (430) by a first grid structure (110) and of each second sacrificial grid (440) by a second grid structure (120).

2. A method according to claim 1, wherein the formation of the first and second sacrificial grids comprises: - the formation, on the semiconductor substrate (101), of a first portion (403a) of a first layer (403) of the sacrificial material in the first region (a), and of a second portion (403b) of the first layer in each second region (b; 1b, b2), said first portion extending over substantially the entire length of the first region, and said second portion extending over the second length (L4), which is less than the length of the second region, forming all or part of the second sacrificial grid (440); - the formation, on the flanks of the first (403a) and second (403b) portions of the first layer (403) of a stack of layers of dielectric material;the stacking of layers of dielectric material on the sides of the second portion (403b) of the first layer (403) forming all or part of the second spacers (406b, 408b, 414, 422).;

3. A method according to claim 2, wherein the formation of the layer stack comprises: - the formation, on the flanks of the first portion (403a) of the first layer (403), respectively of the second portion (403b) of the first layer (403), and on the semiconductor substrate (101), of first L-shaped portions (406a), respectively second L-shaped portions (406b), of a second layer (406) of dielectric material, preferably of a low permittivity material; - the formation, on the first L-shaped portions (406a), respectively second L-shaped portions (406b), of first D-shaped portions (408a), respectively second D-shaped portions (408b), of a third layer of dielectric material, for example of a nitride, for example of a silicon nitride;- the formation, on the first portions in D (408a), respectively second portions in D (408b), of first portions (412), respectively second portions (414), of a fourth layer (410) of dielectric material, for example of a silicon nitride.;

4. A method according to claim 3, wherein the formation of the first (412) and second (414) portions of the fourth layer (410) comprises the deposition and then the etching of said fourth layer so as to form: - in the first region: the first portions (412) and third portions (411) of said fourth layer on the first portion (403a) of the first layer (403), said third portions being arranged in a row and each extending over a length substantially equal to the first length (L3); and - in each second region: the second portions (414) and a fourth portion (413) of said fourth layer on the second portion (403b) of the first layer (403).

5. A method according to any one of claims 2 to 4, comprising engraving the first portion (403a) of the first layer (403) so as to form third portions (403c) of said first layer arranged in a row and each extending over a length substantially equal to the first length (L3), forming all or part of the first sacrificial grids (430).

6. A method according to claim 5 in its dependence on claim 4, wherein the etching of the first portion (403a) of the first layer (403) is carried out through the third portions (411) of the fourth layer (410) forming an etching mask, the third portions (403c) of the first layer (403) extending between the semiconductor substrate (101) and the third portions (411) of the fourth layer (410).

7. A method according to claim 5 or 6, wherein the formation of the first and second spacers comprises, after the formation of the third portions (403c) of the first layer (403), the formation of first portions (421) of a fifth layer (420) of a dielectric material, preferably with low permittivity, on the flanks of the first sacrificial grids (430), forming the first spacers, and of second portions (422) of said fifth layer on the flanks of each second sacrificial grid (440) covered by the stacking of layers, the second spacers including said second portions of said fifth layer.

8. A method according to any one of claims 1 to 7, wherein the formation of the second semiconductor regions (12) is carried out at the same time as the formation of the first semiconductor regions (11).

9. A method according to any one of claims 1 to 7, wherein the formation of the second semiconductor regions (12) is carried out before or after the formation of the first semiconductor regions (11).

10. A method according to claim 9 in dependence on claim 7, wherein the fifth layer (420) comprises a third portion (423) extending on either side of the second sacrificial grid (440) and the second spacers in each second region, so as to mask the semiconductor substrate (101) in said second region during the formation of the first semiconductor regions (11).

11. Electronic device (100; 300) comprising, in and on a semiconductor substrate (101), first finned field-effect transistors (10) (FinFET) in a first region (a) and at least one second metal-oxide-semiconductor field-effect transistor (MOSFET) (20; 20-1, 20-2) in at least a second region (b; bl, b2); the first transistors each comprising a first gate structure (110) of a first length (L1) along a first fin (233) of the semiconductor substrate (101), said first fin having a first width (12) at the level of a first face (101A) of the semiconductor substrate and being isolated by first trenches (231) in the semiconductor substrate, each first gate structure (110) being flanked by a first spacer (131) having a first thickness (e8);each second transistor comprising a second gate structure (120) of a second length (L2) on the first face (101A) of the semiconductor substrate, the second length being greater than the first length, each second gate structure being flanked by a second spacer (140) having a second thickness (e9) greater than the first thickness (e8).;

12. A method according to any one of claims 1 to 10, wherein a third transistor (20; 20-1) among the at least one second transistor is formed on and in an island (235) flush with the first face (101A) of the semiconductor substrate (101), in a third region (b; b-1) among the at least one second region.

13. A method according to any one of claims 1 to 10 and 12, wherein a fourth transistor (20-2) among the at least a second transistor is formed along a second fin (234) of the semiconductor substrate (101), in a fourth region (b-2) among the at least a second region, the second fin (234) having a second width (13) at the level of the first face (101A) of the semiconductor substrate, and being isolated by second trenches (232) in the semiconductor substrate, the second width (13) being greater than the first width (12); for example: - the second width is at least twice greater than the first width; and / or - the first width is less than 15 nm, for example less than or equal to 10 nm; and / or - the second width is greater than 20 nm, for example greater than or equal to 30 nm.

14. A method according to claim 13, comprising the formation of the first fin (233) in the first region (a) and the second fin (234) in the fourth region (b-2), the formation of said first and second fins comprising: - the formation, on the first face (101A) of the semiconductor substrate (101), of first pillars (204A) in the first region (a) and of second pillars (204B) in the fourth region (b-2), the first and second pillars being arranged side by side in a row, and being made of a first material, for example an amorphous silicon, the first pillars being separated from each other by a first distance (Dl), and the second pillars being separated from each other by a second distance (Dl);- the deposition, on the first and second pillars, of a sixth layer (210) of a second material, for example a silicon oxide, selectively etchable with respect to the first material, the sixth layer having a third thickness (e3) on the flanks of the first and second pillars; - the removal of the sixth layer (210) in the first region (a), said sixth layer being retained on the flanks of the second pillars (204B) in the fourth region (b-2); - the deposition, on the first and second pillars, of a seventh layer (220) of the second material, the seventh layer having a fourth thickness (e4) defined to form, on the flanks of the first pillars (204A), first posts (227) disjointed from each other between the first pillars; the sixth and seventh layers forming, on the flanks of the second pillars (204B), second posts (228), the third; and fourth thicknesses being defined so that the second posts (228) are joined between the second pillars (204B), the joined second posts forming third posts (221) connecting two adjacent second pillars; and - the removal, for example by etching, of the first and second pillars in the first material; - the etching of the semiconductor substrate (101) from the first face (101 A) through the first, second and third posts in the second material forming etching mask; the etching of the semiconductor substrate forming first trenches (231) in the semiconductor substrate defining the first fin (233) between the first trenches in the first region (a), and second trenches (232) in the semiconductor substrate defining the second fin (234) between the second trenches in the fourth region (b-2).

15. A method according to claim 14, wherein: - the fourth thickness (e4) is less than the third thickness (e3); and / or - the fourth thickness (e4) is less than half of the first distance (Dl); and / or - the third thickness (e3) is greater than or equal to half of the second distance (Dl); and / or - the first distance (Dl) is substantially equal to the second distance (Dl).

16. A method according to any one of claims 1 to 10, 12 to 15, wherein: - the first thickness (e8) is less than or equal to 15 nm and the second thickness (e9) is greater than or equal to 30 nm; and / or - the first length (L1; L3) is less than or equal to 30 nm and the second length (L2; L4) is greater than or equal to 150 nm.

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