FREQUENCY ADJUSTED SYNCHRONIZER FOR CLOCK DOMAIN CROSSING

Abstract

In a clock domain crossover scenario, a flip-flop synchronizer features a reduced number of series-connected flip-flops (110, 113), receiving input data (A_q) from a first clock domain (107) and outputting data (120) from the second clock domain (114). The second clock signal has a variable frequency tuned to a target frequency by a division factor (k0). The flip-flops (110, 113) are clocked by a clock signal (CLK_k) that downsamples the second clock signal (CLK_B) by a factor of k1. The downsampled clock signal is generated by a frequency divider (301) that propagates a pulse of the signal (CLK_B) every k1 clock pulses, keeping the edges aligned. Theoretically, additional flip-flops (111, 112) are avoided. Figure for the abbreviation: Figure 3

Description

Title of the invention: FREQUENCY ADJUSTED SYNCHRONIZER FOR CLOCK DOMAIN CROSSING technical field

[0001] Embodiments and implementation methods relate to the field of data synchronization in systems having asynchronous clock domains.

[0002] TECHNICAL CONTEXT

[0003] A digital system is often composed of several digital subsystems. When these digital subsystems operate synchronously with the same clock, synchronization of the signals circulating between these digital subsystems is not necessary. On the other hand, if these digital subsystems are asynchronous, i.e., operate with asynchronous clocks that are at least in phase, the signals circulating between these digital subsystems must be synchronized. For example, a computer system may operate at a given frequency, while the processor may operate at another frequency.

[0004] An interface circuit that allows the transfer of data from one clock domain to another is called a synchronization unit or "synchronizer".

[0005] [Fig. 1] illustrates a prior art flip-flop synchronizer 100 for synchronizing a SIG_1 data signal. The flip-flop A 105 operates in the original clock domain A 107. The set of flip-flops B operates in the target clock domain B 114.

[0006] In a known way, a flip-flop is a logic circuit implementing an operator between its inputs and maintaining the values ​​of its output(s) - evaluated at a clock edge - for the duration of the clock cycle.

[0007] Clock domain A 107 and clock domain B 114 are asynchronous clock domains. Flip-flop A 105 receives the input signal SIG_1 at the data input "d" and is clocked at a first clock frequency fA by the first clock signal CLK_A at the clock input. [Fig. 1] illustrates a set of four flip-flops B1 110, B2 111, B3 112, and B4 113 operating in series or "cascade" (the output "q" of the preceding flip-flop feeding the input "d" of the following one). A different number of flip-flops can be considered. In particular, synchronizers with two B flip-flops are widely known.

[0008] The input signal SIG_1 is transferred to the output "q" of the flip-flop A 105 by the action of the first clock signal CLK_A. The flip-flops of set B are clocked at a second clock frequency fB by the second clock signal CLK_B, and the signal output to the output "q" of flip-flop A 105 is transferred serially via each of the flip-flops of set B up to the final output "q" at the output node 120.

[0009] If a clock source (for example fB) has a maximum operating frequency (fBmax), it can nevertheless have a variable frequency in the case where a user can adjust the frequency of the domain through a clock divider integrated into the clock source.

[0010] Figure 2 illustrates a timing diagram 200 of the signals from the synchronizer 100. Shown are the signal A_q 205 at the output of flip-flop A 105 – that is, at the input of the target clock domain B 114 –, the clock signal CLK_B 207 of the target clock domain B 114, the signal Bl_q 210 at the output of the first flip-flop B1 110, the signal B2_q 211 at the output of the next flip-flop B2 111, the signal B3_q 212 at the output of the following flip-flop B3 112, and the signal B4_q 213 at the output of the last flip-flop B4 114. The signal B4_q corresponds here to the output signal OUTPUT 120. Each output signal Bi_q of an intermediate flip-flop Bi corresponds to the input signal B(i + 1)_d of the next intermediate switch B(i+1).

[0011] There is a probability that when the signal A_q is sampled by flip-flop B1 110 in the target clock domain 114, the output B1_q of flip-flop B1 may enter a metastable state. This probability—which decreases over time—is symbolically represented by the gradient after each edge. The next flip-flop B2 will have a lower probability of doing the same (symbolically represented by the gradient), and so on.

[0012] These risks of a metastable state depend on the flip-flop parameters and the target frequency fB of the CLK_B clock. Connecting the four flip-flops in series reduces this risk of a metastable state at output 120, at the cost of a sampling offset by a number of clock cycles corresponding to the number of additional flip-flops (for example, compared to a two-flip-flop synchronizer). The number Nsync of B flip-flops to use is generally determined by the following formula: [00B] MTBF = g1 »

[0014] where t, the resolution time, is Tsetup " TCp^q "

[0016] MTBF is the desired mean time between failures.

[0017] t, (resolvement time of a flip-flop), Tw (metastability window), N (total number of flip-flops in the synchronizer or synchronization system), Tsetup (setup time of a flip-flop), Tcp^q (latency time CP - clock pulse - to Q - output) - of a flip-flop), Tuncertainty (constant) are fixed parameters, linked to the flip-flops and / or the chosen circuit design.

[0018] A higher number of Nsync flip-flops is detrimental to the compactness of the synchronizer 100, as well as to its power consumption. It also delays the conversion of the input signal SIG_1 into the target clock domain.

[0019] To contain this number, it is necessary to improve the performance of the flip-flops, which has a cost.

[0020] Furthermore, the pursuit of increased performance in the B 114 clock domain is generally accompanied by an increase in the fB frequency, and consequently by an ever-increasing number of flip-flops for a maintained MBTF. For example, the fB frequency can range from a few tens of MHz (e.g., 10 to 50 MHz) to several hundred MHz (e.g., 400 MHz).

[0021] There is therefore a need to improve the synchronizers between asynchronous clock domains to overcome the aforementioned disadvantages.

[0022] SUMMARY

[0023] It is observed that the multiple flip-flops connected in series aim to reduce the risk of a metastable state by extending the sampling time by a number of clock cycles corresponding to the number of additional flip-flops. Therefore, all or part of the intermediate flip-flops may appear superfluous since the sampling time is maintained.

[0024] In this perspective, a synchronization unit is proposed between a first clock domain clocked by a first clock signal and a second clock domain asynchronous to the first clock domain and clocked by a second clock signal, the synchronization unit comprising:

[0025] a set of flip-flops connected in series, receiving data as input from the first clock domain and providing data as output in the second clock domain (i.e., the first flip-flop receiving the input, the last flip-flop delivering the output),

[0026] wherein the second clock signal is variable frequency adjusted to a target frequency to feed a clock signal timing the flip-flops and / or the flip-flops are clocked by a clock signal subsampling the second clock signal.

[0027] Two mechanisms, which can be combined, allow the period between two rising (or falling) edges to be adjusted according to the number of flip-flops used. By adjusting, generally downwards, the clock frequency used by the flip-flops of the synchronization unit, the number of flip-flops can be reduced. Therefore, the synchronization unit can be compact and energy-efficient.

[0028] A variable-frequency clock source typically includes a clock divider that allows the output frequency to be adjusted by an integer factor of k0 (of the maximum operating frequency). The clock period is thus multiplied by k0. The frequency of the second clock signal can therefore be adjusted to the number of flip-flops used.

[0029] "Undersampling" means any process aimed at reducing the frequency of the clock signal by an integer factor 'kl' greater than 1. The clock period is thus multiplied by kl. In practice, clock cycles (or pulses) are removed from the clock signal. The clock and the undersampled clock signals remain in phase, meaning that the retained rising (or falling) clock edges are aligned with those of the original clock signal (the second clock signal).

[0030] Furthermore, by fixing the division factor kO and / or subsampling factor kl, it is possible to obtain a substantial reduction in the number of flips, typically to only two units.

[0031] It is also possible, by choosing the factor(s) k0 and kl, to compensate for other parameters of the above formula, typically the flip-flop parameters. Therefore, it is again possible to use any type of flip-flop, including less efficient ones, and thus avoids the need to develop new, more efficient component types.

[0032] According to another aspect, a synchronization method is proposed between a first clock domain clocked by a first clock signal and a second clock domain asynchronous to the first clock domain and clocked by a second clock signal, the method comprising the following steps: obtain at least one clock division or clock subsampling factor, adjust, using the clock division factor, a variable frequency of the second clock signal to a target frequency to feed a clock signal timing the flip-flops and / or generate, using the obtained clock subsampling factor, a clock signal subsampling the second clock signal, and drive, with the adjusted and / or generated clock signal, flip-flops connected in series in a synchronization unit which receives input data from the first clock domain and provides output data in the second clock domain.

[0033] An electronic system comprising a synchronization unit as defined in this disclosure is also proposed.

[0034] Optional embodiment characteristics are defined below with reference to the device, while they can be transposed into process characteristics.

[0035] In one embodiment, the synchronization unit includes a subsampler (or subsampling unit) configured to subsample an input signal by a subsampling factor kl, an integer greater than or equal to 2, the subsampler receiving, as input signal, the second clock signal.

[0036] In one embodiment, the synchronization unit includes a user interface to allow a user to configure the subsampling factor k. The user can thus easily adjust or tune a synchronization unit design (comprising, for example, two flip-flops) to a variable target frequency fb and / or to flip-flops of any type.

[0037] In one embodiment, a source of the second clock signal includes a clock divider configured to adjust the second clock signal by a division factor kO, an integer greater than or equal to 2. The division factor kO can, for example, be entered by a user via a dedicated interface.

[0038] In one embodiment, the subsampler (301, 400) includes a module for adapting the subsampling factor kl to a frequency adjustment fB of the second clock signal by the division factor kO. More generally, the adaptation module can adjust kO according to any frequency variation of the second clock signal, taking into account the number of flip-flops used. The description below shows, for example, how to determine kl as a function of the frequency of the second clock signal and the number of flip-flops.

[0039] In one embodiment, the subsampler includes a clock gating cell coupled to a pulse counter in the input signal. The counter counts 'kl' pulses to send an activation signal to the clock gating cell so that the latter allows the input signal to pass until the next pulse.

[0040] In one embodiment, the set of flippers comprises only two flippers in series. As described later, a larger number of flippers may be provided.

[0041] In one embodiment, when a desired mean time between failures (MTBF) formula links a theoretical number Nsync of flip-flops to a first frequency fA of the first clock signal and a second frequency fB (optionally adjusted) of the second clock signal: Nsync = function(fA, fB), a subsampling factor kl is fixed to a factor k2 chosen from among the factors of Nsync-1. A factor of Nsync-1 is understood in the sense of multiplication: any integer (including 1 and Nsync-1) that can divide Nsync-1 (Euclidean division without remainder). The subsampling factor kl is an integer greater than or equal to 2.

[0042] In this case, the number of flip-flops in series (in said flip-flop set) is equal to (N sync-1) / k2 + 1, in order to maintain a constant sampling time for the input data. For example, if we downsample by a factor equal to Nsync-1, then only two flip-flops are needed in series. If Nsync-1 is even and we downsample by a factor equal to (Nsync-1) / 2, then three flip-flops are used in series. And so on.

[0043] A synchronization system is also proposed comprising: a first synchronization unit as above between a first clock domain clocked by a first clock signal and a second clock domain asynchronous to the first clock domain and clocked by a second clock signal, a second synchronization unit as above between a third clock domain clocked by a third clock signal distinct from the first clock signal and the second clock domain asynchronous to the third clock domain, wherein a shared subsampler provides the same clock signal subsampling the second clock signal, to the flip-flops of the first and second synchronization units.

[0044] Of course, the subsampler can time the flip-flops of a larger number of synchronization units between various original clock domains and the same second target clock domain asynchronous to these original clock domains.

[0045] While reducing the number of flip-flops in a synchronizer should compensate for the addition of the subsampler, sharing the latter across several original clock domains guarantees a real benefit in terms of silicon area occupied and power consumption relative to each synchronizer. BRIEF DESCRIPTION OF THE FIGURES

[0046] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiment and implementation, which is by no means limiting, and the accompanying drawings in which:

[0047] [Fig. 1]; and

[0048] [Fig.2] illustrate known techniques;

[0049] [Fig.3] ;

[0050] [Fig.4] ;

[0051] [Fig.5] ;

[0052] [Fig.5A] ;

[0053] [Fig.5B] ;

[0054] [Fig.6] ; and

[0055] [Fig.7] schematically illustrate methods of implementation and realization of the invention. DETAILED DESCRIPTION

[0056] In a clock domain crossover context, a flip-flop synchronizer has a reduced number of flip-flops connected in series, receiving input data from a first clock domain and outputting data from the second clock domain. The second clock signal has a variable frequency adjusted to a target frequency by a division factor of k0. The flip-flops are clocked by a clock signal that downsamples the second clock signal by a factor of kl. The downsampled clock signal is generated by a frequency divider that propagates a pulse of the signal every kl clock pulses, keeping the edges aligned. Theoretically, additional flip-flops are avoided.

[0057] Electronic systems such as automotive systems can be implemented in the form of a system on chip (SoC for "System on Chip" in English) which is an integrated circuit comprising all the components of the system, often including, for example, components associated with different and asynchronous clock domains.

[0058] A clock domain crossing occurs when data is transferred from a flip-flop (a "source" flip-flop) driven or clocked by a first clock CLOCK_A to a flip-flop (a "destination" or "target" flip-flop) driven by a second clock CLOCK-B.

[0059] Depending on the relationship between the clocks, problems may arise during data transfer between the source flip-flop and the target flip-flop. For example, if a transition at the output of the source flip-flop occurs very close to the active (rising or falling) edge of the second clock, a configuration or hold violation may occur at the target flip-flop. This can cause the output of the second flip-flop to oscillate, becoming unstable and failing to stabilize at a stable value before the next active edge of the second clock. This condition is called metastability.

[0060] To reduce the uncertainty related to the metastability of the target flip-flop, it is classic to put several target flip-flops in series, allowing the data sampling time to be extended to several clock cycles, where the risks of metastability are almost zero.

[0061] The number Nsync of target flip-flops is generally obtained by the mean time between failures formula already mentioned above.

[0062] This number Nsync of flip-flops required for data synchronization in the second clock domain grows rapidly with the frequency fB of the second clock domain - a desired condition to improve its performance - but also with the use of less efficient flip-flops - a useful condition to reduce costs and have a simpler and less expensive design with the use of standard and identical flip-flops.

[0063] A high number of Nsync flip-flops is detrimental to the compactness of the synchronizer 100, as well as to its power consumption.

[0064] Since electronic systems can include a large number of synchronization units between asynchronous clock domains, any additional flip-flop in these units leads to the same detriment in terms of compactness and power consumption.

[0065] Adjusting a variable frequency of the second clock signal to a target frequency to drive a clock signal that clocks the flip-flops, and / or using flip-flops driven or clocked by a clock signal that subsamples the second target clock signal CLOCK_B, makes it possible to reduce the number of flip-flops while maintaining a constant input data sampling time, thus keeping the MTBF unchanged and minimizing the risk of metastability. Furthermore, creating a virtual clock that generates this adjusted and / or subsampled clock signal overcomes the drawbacks of known techniques.

[0066] Fig. 3 illustrates a synchronization unit according to embodiments.

[0067] For illustrative purposes only, the two intermediate flip-flops 111, 112 — now superfluous — are represented in dotted lines to illustrate how this synchronization unit improves upon that of [Fig.1] discussed above.

[0068] The flip-flop synchronizer 300 of [Fig.3] again includes the flip-flop A 105 in the original clock domain A 107 and the set of flip-flops B in the target clock domain B 114.

[0069] The flip-flops are typically D flip-flops (for Data), i.e., having a single data input: "d", the value of which is copied to the output "q" at each clock edge (here the rising edge, but alternatively it could be the falling edge). The D flip-flop ensures a stable output state between two clock edges.

[0070] The flip-flop set B comprises two flip-flops B1 110 and B4 113 in series, timed by a clock CLK_k.

[0071] The clock CLK_k can be the second clock CLK_B tuned to a target frequency, for example, adapted to the number of flip-flops used. The target clock signal CLK_B can be generated by any known clock generator—and therefore not detailed here—such as an electronic oscillator (typically an RLC circuit). It is known that a variable-frequency clock source is equipped with a clock divider 301 (by a integer clock factor kO) allowing the output clock frequency of the source to be adjusted downwards, relative to a maximum operating frequency fBmax.

[0072] The clock CLK_k can be a virtual clock CLK_k that downsamples the target clock CLK_B, optionally pre-adjusted by a clock factor k0. The virtual clock is implemented using the clock downsampling unit 301 which receives as input the clock signal CLK_B (optionally adjusted by k0) and the downsampling parameter kl, an integer greater than or equal to 2. In the example in the figure, k=3, allowing the clock frequency (e.g., rising edges) between the clock signal CLK_B (frequency: fB) and the downsampled clock signal CLK_k (frequency: fk=fB / kl) to be divided by k=3.

[0073] The parameter(s) kO and kl can be prefixed in a register or memory of the synchronizer 300. Alternatively, they can be adjusted by a user through a user interface (not shown). Alternatively still, they can be dynamically adapted (by an adaptation module not shown in [Fig. 4] below): for example, the subsampling factor kl can be adjusted to variations in the frequency fB of the target clock domain B by the division factor kO (e.g., when the user changes kO).

[0074] Fig. 4 illustrates an embodiment of a subsampling unit 400. Any other embodiment known to those skilled in the art may be used.

[0075] The subsampling unit allows the subsampled clock signal CLK_k to be generated by removing certain pulses from the clock signal CLK_B (or by copying the other pulses into a new signal). Thus, the CLK_k and CLK_B signals remain in phase (their pulse edges are aligned, for the common pulses), as illustrated in [Fig. 5].

[0076] The subsampling unit 400 shown includes a clock gating cell 410 coupled to a pulse counter 420 in the input signal, here CLK_B.

[0077] The pulse counter 420 is represented here in a very schematic way because there are many possible implementations accessible to those skilled in the art. The pulse counter 420 is configured to count the pulses of the input signal CLK_B, typically at each rising edge (or in a falling variant) and, depending on the parameter kl, to generate a "high" or "strong" state of an activation signal ACTIV to the clock trigger cell 410 each time kl pulses have been counted in the input signal CLK_B.

[0078] The clock trigger cell 410 essentially stops the propagation of the clock signal CLK_B through it when an ACTIV activation signal at a level "low" or "weak" is applied to it. Only the pulses of the clock signal CLK_B during a high ACTIV activation signal are propagated to CLK_k.

[0079] For example, when kl=3, only one pulse out of three is propagated to the output CLK_k.

[0080] The clock trigger cell 410 is of the AND-latch type, comprising a latch 411 and an AND gate 412. The latch 411 is controlled by the activation signal ACTIV to activate the AND gate 412 for one clock period, every kl periods. The AND gate 412 therefore allows the clock signal CLK_B to propagate for one clock period every k periods, thus allowing a pulse to pass through every kl.

[0081] [Fig.5] illustrates a time diagram 500 of the signals of the synchronizer 301 or 400, with kl=3. The signals B2_q and B3_q of [Fig.1] are left apparent (in dotted lines) for all practical purposes even though they no longer exist within the synchronizer.

[0082] The subsampling unit 400 allows one pulse out of three of the CLK_B signal to propagate, the subsampled clock signal consists of one clock pulse every three clock cycles B, therefore at a frequency fB / 3. The pulses of the CLK_k signal 507 are perfectly aligned in phase (at edges) with those of the initial CLK_B signal 207.

[0083] Since the B flip-flops are driven by the CLK_k signal, the first flip-flop B1 takes the value of the data A_q at one pulse of the CLK_k signal, and the second flip-flop B4 in series takes the value of the data Bl_q at the next pulse of the CLK_k signal. The second flip-flop B4 therefore does not operate at the clock cycle B following that of the first flip-flop Bl, but at a subsequent virtual clock cycle, i.e., after kl = 3 clock cycles B. This ensures that the sampling time remains unchanged: the B4 flip-flop of the synchronization unit 400 operates at the same times as the B4 flip-flop of the synchronization unit 100 ([Fig. 2]).

[0084] Although the example in [Fig.3] illustrates two B flip-flops, the 400 synchronization unit can contain a larger number, which is reduced compared to the theoretical number Nsync of flip-flops for the target frequency fB.

[0085] Similarly, although the above example in [Fig.3] is described with a subsampling factor of 3, other values ​​may be used.

[0086] The mean time between failures (MTBF) formula above relates the theoretical number Nsync of flip-flops to the frequency fA, the frequency fB, but also to the desired MTBF and the characteristics of the flip-flops used. This number Nsync can be 3, 4, 5, 6, or even more. If known techniques require specific hardware implementations anticipating this exact number (or more) of flip-flops, the approach described above makes it possible to reduce their number.

[0087] In particular, it allows the use of less efficient flip-flops (for example, conventional flip-flops) without increasing (or even reducing) the number of flip-flops actually used. The approach described above therefore offers broader access to the catalog of available flip-flops without impacting the performance of the synchronization unit.

[0088] It also makes it possible to improve the performance of the target clock domain B - via the increase of its operational frequency fB - without increasing (or even reducing) the number of flip-flops actually used.

[0089] Typically, the number Nsync-1 obtained according to the constraints at stake (desired MTBF, fA, fB, characteristics of the flip-flops used) has two or more factors, in the sense of multiplication, namely at least 1 and Nsync-1, and possibly any integer divisor of Nsync-1. Any factor k2 among these two or more factors can be chosen as the subsampling factor kl.

[0090] For example, for Nsync=5, the following factors are available: 1, 2, 4; for Nsync=6: 1 and 5; for Nsync=7: 1, 2, 3, 6; etc.

[0091] The choice of the k2 factor may depend on the number of flip-flops to be implemented, and / or the possibilities offered by the subsampling unit 301, 400.

[0092] The number NB of flip-flops B is indeed linked to the factor k2 chosen by the following formula, to maintain a constant sampling time of the input data: Nb = (Nsync-l) / k2 + 1.

[0093] Thus, if k2 = Nsync-1, then only two B flip-flops are needed instead of Nsync. This is the case in [Fig.3] where we go from four (Nsync=4) B flip-flops (see [Fig.1]) to only two by dividing the trigger frequency of the flip-flops by 3 (Nsync -1).

[0094] For illustrative purposes, if Nsync=5 and k2=2, then three B flip-flops can be used instead of five; if Nsync=7 and k2=2, then four B flip-flops are required, whereas with k2=3, three B flip-flops can be used instead of seven.

[0095] Although it is envisaged above to remain at the same sampling time for the input data, it is nevertheless possible to use the teachings above to reduce the number of flips, even by lengthening the sampling time of the input data.

[0096] For example, if a 301, 400 subsampling unit is already available with a subsampling factor kl that is incompatible with the theoretical number Nsync of B flip-flops (kl does not divide Nsync-1), then a theoretical Nsync' can be used higher which satisfies the condition: kl divides Nsync'-1. The lengthening of the sampling time is then equal to (Nsync'-Nsync) / fB.

[0097] By way of illustration, if Nsync=5 and the subsampling unit divides fB by 3, then Nsync' can be set to 7. Three B flip-flops will then be used instead of the 5 (Nsync). On the other hand, the sampling time will change from 5 / fB to 7 / fB.

[0098] Finally, there are scenarios where the frequency fB is adjusted (e.g., by a user) by a division factor k0 to slow down (or speed up) the clock in time, while the synchronization unit 301, 400 is in operation (so the number of B flip-flops is fixed as above). In this case, the subsampling unit 301, 400 can be equipped with a module for dynamically (i.e., automatically) adapting the subsampling factor k1 to variations in fB by the division factor k0.

[0099] As mentioned above, unit 301 in [Fig. 3] represents a clock divider when the frequency fB of the second clock CLK_B is tuned to a target frequency by the division factor k0, but also a subsampling unit of the target clock CLK_B by the clock factor k0. When the two operations (tuning and subsampling) are implemented in combination, a clock divider is provided within the clock source CLK_B and a separate subsampler is provided in front of the CLK_B signal.

[0100] Also, in embodiments, the subsampling unit 400 of [Fig.4] can be replaced (or supplemented) by a clock divider known to those skilled in the art.

[0101] [Fig.5A] illustrates a time diagram 510 of the signals from synchronizer 301 or 400, with k0=3, without subsampling of CLK_B. The signals B2_q and B3_q of [Fig.1] are left apparent (in dashed lines) for all practical purposes even though they no longer exist within the synchronizer.

[0102] Adjusting the clock frequency fB of CLK_B by k0=3 allows the clock period to be multiplied by k0. The pulses of the CLK_Badj 517 signal are perfectly aligned in phase (at edges) with those of the CLK_Bmax 207 signal corresponding to the maximum clock frequency of domain B, fBmax.

[0103] Since the B flip-flops are driven by the tuned signal CLK_Badj, the first flip-flop B1 takes the value of the data A_q at one pulse of the signal CLK_Badj, and the second flip-flop B4 in series takes the value of the data B l_q at the next pulse of the signal CLK_Badj, that is to say at the end of a period corresponding to three periods of the maximum frequency fBmax of CLK_Bmax.

[0104] The person skilled in the art understands that it is possible to combine the mechanisms for adjusting the frequency fB of the clock signal CLK_B by kO and sub- sampling of the clock signal CLK_B by kl in order to obtain a period T between two edges of CLK_k adjusted as best as possible: T = (kO.kl) / fBmax.

[0105] Figure 5B illustrates, for example, a time-domain diagram of the signal CLK_k, with k0=2 and kl=2. The adjusted signal CLK_Badj has a rising edge every k0=2 rising edges of the signal CLK_Bmax. The signal CLK_k thus has a rising edge every k0.kl=4 rising edges of the signal CLK_Bmax.

[0106] Typically, kO and kl can be chosen such that kO.kl is a factor of (Nsync-1) / (Nb-1), Nsync being determined using the maximum frequency fBmax.

[0107] Alternatively, if a user sets kO, the adjusted frequency fB is fBmax / kO. kl can then be chosen such that kl is a factor of (Nsync-1) / (NB-1), Nsync being determined using the adjusted frequency fB.

[0108] Figure 6 illustrates a 600 synchronization system based on flip-flop synchronizers. This synchronization system can be part of a more complex electronic system in which three or more clock domains coexist. For simplicity, reference is made to only three asynchronous clock domains: A 107, B 114, and C 607. Of course, any other number of clock domains can be implemented, as outlined in this disclosure.

[0109] Data from clock domains A 107 and C 607 are transmitted to the asynchronous clock domain B at A and C, requiring respective clock domain crossings: A to B and C to B.

[0110] If the synchronization unit 601 between domains A and B is, for the example, identical to that of [Fig.3], that 602 between domains C and B has three B flip-flops in series receiving the data from the A' flip-flop 605 of domain C and providing the output OUTPUT 620: B1' 610, B2' 611 and B3' 612. This is, however, only an example; the number of B flip-flops in the synchronization unit 602 may be the same as that in the synchronization unit 601, or may be greater.

[0111] The dashed flip-flops in the 602 synchronization unit are not used. They illustrate, for all practical purposes, the flip-flops theoretically required when Nsync = 7 for the clock domain crossover from C to B.

[0112] The flip-flops of the synchronization unit 602 may be identical (of the same nature) to those of the synchronization unit 601, or may be different.

[0113] The flip-flops of the synchronization unit 601 and those of the synchronization unit 602 are all driven by the same subsampled signal CLK_k from the clock subsampling unit 301. The latter is therefore shared between several clock domain crossings towards the same target clock domain (here B), therefore shared between several source clock domains (here A and C).

[0114] The costs (integrated circuit area, power consumption) of the subsampling unit 301 are thus reduced all the more per synchronization unit, as there are many clock domain crossings to be made towards the same clock domain.

[0115] Fig. 7 illustrates, using a flowchart, operations 700 in an electronic system exhibiting at least one clock domain crossover, i.e. an electronic system with several asynchronous clock domains that exchange data.

[0116] Operations 700 begin at step 710 with the recovery of the clock subsampling factor k.

[0117] In one embodiment, kO and / or kl are stored in memory or in a register internal to the electronic system.

[0118] In another embodiment, kO and / or kl are entered by a user at the start of the electronic system.

[0119] In yet another embodiment, k0 and / or kl are determined by the electronic system from a synchronization unit configuration 300, 601, 602. Typically, on the one hand, initial information such as the frequencies fA, fB, fc (for the C domain), the mean time between failures (MTBF), and the characteristics of the B flip-flops used are known, and on the other hand, secondary information such as the number NB of B flip-flops available in the synchronization unit 300, 601, 602 (for example, 2) is known. The electronic system can therefore determine the division factor(s) k0 and clock subsampling factor(s) kl by first calculating Nsync with the initial information and then determining k2 = (Nsync-1) / (NB-1). If k2 is an integer, k0 = k2 or kl = k2 or k0.kl = k2. Alternatively, a higher integer can be chosen for kO and / or kl, preferably the immediately higher integer: kO or kl or kO.kl=higher integer part(k2).

[0120] In step 720, the clock divider or clock subsampling unit 301, 400 is started with the clock factor k0 or clock subsampling kl respectively, as determined in step 710.

[0121] For example, in the case of downsampling, the downsampling unit 301, 400 propagates a clock pulse of the signal CLK_B over kl pulses. This forms the downsampled clock signal CLK_k. Thus, a clock signal CLK_k subsampling the clock signal CLK_B is generated.

[0122] At step 730, the subsampled clock signal CLK_k is supplied to the B flip-flops of the synchronization unit 300, 601, 602 in order to drive them at a frequency fB / kl.

[0123] This control allows the data from the source clock domain(s) to the target clock domain B to be transferred synchronously, while maintaining a desired mean time of proper operation.

[0124] Of course, this disclosure is not limited to the embodiments described above by way of example; it extends to other variations. Other embodiments are possible.

Claims

Demands

1. Synchronization unit (300, 601, 602) between a first clock domain (107, 607) clocked by a first clock signal (CLK_A, CLK_C) and a second clock domain (114) asynchronous to the first clock domain and clocked by a second clock signal (CLK_B), the synchronization unit comprising: a set of flip-flops (110, 113, 610, 611, 612) connected in series, receiving data (A_q) as input from the first clock domain and providing data (120, 620) as output in the second clock domain, wherein the second clock signal (CLK_B) is variable frequency tuned to a target frequency (fB) to drive a clock signal that clocks the flip-flops (110, 113, 610, 611, 612) and / or the flip-flops (110, 113, 610, 611, 612) are clocked by a clock signal (CLK_k) subsampling the second clock signal (CLK_B).

2. Synchronization unit (300, 601, 602) according to claim 1, comprising a subsampler (301, 400) configured to subsample an input signal by a subsampling factor (kl), an integer greater than or equal to 2, the subsampler receiving, as input signal, the second clock signal (CLK_B).

3. Synchronization unit (300, 601, 602) according to claim 1 or 2, wherein a source of the second clock signal comprises a clock divider (301, 400) configured to adjust the second clock signal by a division factor (k0), an integer greater than or equal to 2.

4. Synchronization unit (300, 601, 602) according to claims 2 and 3, wherein the subsampler (301, 400) includes a module for adapting the subsampling factor (kl) to an adjustment of a frequency (fB) of the second clock signal (CLK_B) by the division factor (kO).

5. Synchronization unit (300, 601, 602) according to claim 2 or 4, wherein the subsampler (301, 400) comprises a clock trigger cell (410) coupled to a pulse counter (420) in the input signal.

6. Synchronization unit (300, 601, 602) according to any one of the preceding claims, wherein the set of flippers comprises only two flippers in series (110, 113).

7. Synchronization unit (300, 601, 602) according to any one of the preceding claims, wherein, when a desired mean time between failures (MTBF) formula links a theoretical number Nsync of flip-flops to a first frequency (fA) of the first clock signal (CLK_A) and a second frequency (fB) of the second clock signal (CLK_B), a subsampling factor k is fixed to a factor k2 selected from the factors of N - 1

8. A synchronization system (600) comprising: a first synchronization unit (601) according to any one of the preceding claims between a first clock domain (107) clocked by a first clock signal (CLK_A) and a second clock domain (114) asynchronous to the first clock domain and clocked by a second clock signal (CLK_B), a second synchronization unit (602) according to any one of the preceding claims between a third clock domain (607) clocked by a third clock signal (CLK_C) distinct from the first clock signal (CLK_A) and the second clock domain (114) asynchronous to the third clock domain (607), wherein a shared subsampler (301, 400) provides the same clock signal (CLK_k) subsampling the second clock signal (CLK_B), to the flip-flops (110, 113, 610, 611, 612) of the first and second synchronization units (601, 602).

9. A method for synchronizing a first clock domain (107, 607) clocked by a first clock signal (CLK_A, CLK_C) and a second clock domain (114) asynchronous to the first clock domain and clocked by a second clock signal (CLK_B), the method comprising the following steps: obtaining (710) at least one clock division factor (kΩ) or clock subsampling factor (kΩ), adjusting, using the clock division factor, a variable frequency of the second clock signal to a target frequency to drive a clock signal clocking the flip-flops and / or generating (720), using the obtained clock subsampling factor,

10. a clock signal (CLK_k) subsampling the second clock signal (CLK_B), and drive (730), with the adjusted and / or generated clock signal (CLK_k), flip-flops (110, 113, 610, 611, 612) connected in series in a synchronization unit (300, 601, 602) which receives data (A_q) as input from the first clock domain and provides data (120, 620) as output in the second clock domain. Electronic system comprising a synchronization unit (300, 601, 602) according to any one of claims 1 to 7.