PCM Memory

Abstract

PCM Memory This description concerns a memory block (3) comprising rows (R1, RN) and columns (C1, C2, CM) of phase-change memory cells (100). A first MOS transistor (P1) couples a supply potential (Vdd) to an input (In) receiving a reference current (Iref), and has its gate connected to the input. For each column, a second transistor (P21, P22, P2M) couples the supply potential and a corresponding output (Out1, Out2, OutM) coupled to the column. A conductive rail (108) connects the input to the gates of the second transistors (P21, P22, P2M). A circuit (104) selects columns so that, during a write step, a write current pulse flows through each selected column. Another circuit (CMP) supplies the conductor rail (108), at the beginning of the writing current pulses, with a compensating current pulse determined by the selected columns. Figure for the abbreviation: Fig. 3

Description

Title of the invention: PCM Memory technical field

[0001] The present description relates generally to electronic circuits, and more particularly to PCM memories (from the English "Phase Change Memory"), that is to say memories comprising at least one block of several PCM memory cells, or, in other words, at least one PCM memory block. Previous technique

[0002] A PCM memory block comprises several memory cells organized in a matrix of memory cells, that is to say in rows and columns of memory cells.

[0003] Each PCM memory cell is configured to store information, for example a bit, having a value determined by a resistance value of the memory cell.

[0004] Writing or programming a value in a memory cell therefore amounts to programming a state, for example crystalline or amorphous, of a phase change material of the memory cell, so as to program a resistance value of the memory cell.

[0005] Programming a state of the phase-change material of a memory cell, and therefore the state of the memory cell, is done by circulating a current pulse in the memory cell, the shape of the pulse determining the programmed state in the memory cell.

[0006] Typically this current pulse is generated from a copy of a reference current supplied, for example, by a digital-to-analog converter controlling the gate of a transistor.

[0007] To speed up a writing step in the PCM memory block, it would be desirable to be able to program memory cells belonging to different columns simultaneously. However, this poses various problems. Summary of the invention

[0008] There is a need for a PCM memory block allowing simultaneous writing of several memory cells each belonging to different columns of the memory block.

[0009] One embodiment overcomes all or part of the disadvantages of known PCM memory blocks.

[0010] One embodiment provides a PCM memory block that overcomes all or part of the disadvantages of known PCM memory blocks.

[0011] One embodiment provides a memory block comprising: several phase-change memory cells arranged in rows and columns; a first circuit including: - at least one first MOS transistor coupling a supply potential to an input of the first circuit configured to receive a reference current, and having its gate connected to said input, - for each column, at least one second transistor coupling the supply potential and a corresponding output of the first circuit coupled to said column, and - a conductive rail connecting said input to the gates of the second transistors; for each column, at least a third MOS transistor coupling said column to the corresponding output of the first circuit; a second circuit configured for: - receive a first signal indicating which columns to write during a write step, and a second signal to control the write step, and - to control the third MOS transistors based on the first and second signals, so that, during the write step, a write current pulse flows through each selected column; and a third circuit configured to: - receive a third signal indicating the number of columns selected and a fourth signal indicating the start of write current pulses in the selected columns, and - supply to the conductor rail, at the beginning of the writing current pulses, a pulse of a compensation current determined by the third and fourth signals.

[0012] According to one embodiment, the compensation current pulse is determined from the third and fourth signals so as to compensate for a voltage variation on said rail resulting from a switching to the on state of the third MOS transistors of the columns selected at the beginning of the writing current pulses.

[0013] According to one embodiment, for each column, said at least one second MOS transistor coupling the supply potential and the corresponding output of the first circuit is mounted in current mirror with said at least one first MOS transistor.

[0014] According to one embodiment, the fourth signal determines a start of the compensation current pulse, and the third signal determines a maximum value of the compensation current pulse.

[0015] According to one embodiment, the third signal further includes an indication of a maximum value of the writing current pulses during the writing step.

[0016] According to one embodiment, the second signal indicates a start and end of the writing current pulses flowing in the selected columns.

[0017] According to one embodiment, the fourth signal is determined at least in part by the second signal.

[0018] According to one embodiment, the third circuit is further configured to receive a signal to selectively activate and deactivate the supply of the compensation current pulse to said rail.

[0019] According to one embodiment, the third circuit comprises a single output connected to said rail and configured to provide said compensation current pulse.

[0020] According to one embodiment, the third circuit comprises a plurality of capacitors in parallel, each connected to a first node by a first switch, and a second switch connecting the first node to the output of the third circuit, the third circuit being configured to pre-charge the capacitors before the writing step, to close the second switch at the beginning of the compensation current pulse, and to close all or part of the first switches before the closing of the second switch on the basis of the third signal.

[0021] According to one embodiment: the third circuit includes, for each column, a corresponding output connected to the gate of said at least one second MOS transistor coupled to said column; The third circuit includes, for each column, a sub-circuit configured to provide, at the output of the third circuit corresponding to that column, a first current pulse starting with the compensation current pulse if said column is selected; and The compensation current pulse corresponds to the set of the first pulses.

[0022] According to one embodiment: each sub-circuit comprises: - a plurality of capacitors in parallel, each connected to a first node of said sub-circuit by a first switch, and - a second switch connecting said first node of said subcircuit to the output of the third circuit to which this subcircuit is connected; and each subcircuit is configured to: - preload these capacities before the writing stage, - close its second switch at the beginning of the compensation current pulse if the column corresponding to the sub-circuit is selected, and - close all or part of the first switches before the second switch is closed based on the third signal.

[0023] According to one embodiment, for each column, the sub-circuit corresponding to that column is configured to receive a control signal from said at least one third switch corresponding to that column, and to control the switching of its second switch to the on state on the basis of that control signal.

[0024] One embodiment provides a memory comprising at least one memory block as defined above, and a circuit configured to supply the reference current. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0026] [Fig.1] represents an example of a PCM memory block of the type to which the described embodiments apply;

[0027] [Fig.2] illustrates, by means of a curve, a drawback of the memory block of [Fig.1];

[0028] [Fig.3] represents an example of an embodiment of a PCM memory block;

[0029] [Fig. 4] represents an example of the implementation of a memory block circuit [Fig.3];

[0030] [Fig. 5] represents an example of the implementation of another circuit of the memory block [Fig. 3]; and

[0031] [Fig. 6] represents an example of an alternative embodiment of the PCM memory block of [Fig. 3]; and

[0032] [Fig.7] represents an example of the implementation of a circuit of the memory block [Fig.6]. Description of the implementation methods

[0033] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular,...

[0035] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two connected (in English "coupled") elements between them, this means that these two elements can be connected or linked via one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0037] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0038] Fig. 1 represents an example of a PCM memory block, referenced 1 and delimited by dotted lines in Fig. 1, of the type to which the described embodiments apply.

[0039] Memory block 1 comprises a plurality of phase-change memory cells 100, represented in [Fig. 1] by bipolar transistors. In [Fig. 1], only one memory cell 100 is referenced to avoid cluttering the figure.

[0040] Memory cells 100 are organized into rows Ri and columns Cj, with i and j being integer indices, i belonging to the range from 1 to N with N an integer greater than or equal to 2, and j belonging to the range from 1 to M with M an integer greater than or equal to 2. As an example, the index j is greater than 5, for example greater than 10. In [Fig. 1], in order not to clutter the figure, the rows Ri and columns Cj of memory cells 100 are not all represented, and the rows Ri, respectively the columns Cj, which are represented are only partially represented.

[0041] Typically, in each column Cj, the memory cells are connected, for example, to the same column conductive rail capable of carrying a programming (or write) current pulse. Typically, the memory cells 100 of the same row Ri all receive the same selection signal WLi (WL1 and WLN in [Fig. 1]), the WLi signals allowing the selection of the cells 100 of a given row Ri and the deselection of the cells 100 of other rows Ri. Thus, when a write current pulse is supplied to a given column Cj, only the memory cell 100 whose row Ri is selected receives this write current pulse and is programmed by this current pulse. As an example, the WLi signals are supplied by a row selection circuit 102, which is, for example, part of block 1.

[0042] Block 1 includes a circuit 104. The circuit 104 is configured to receive a reference current Iref and to provide copies of this current to the columns Cj, i.e., to the conductive rails of the columns to which the memory cells 100 of the columns are coupled, for example, connected. Preferably, the copies of currents supplied to columns Cj correspond to a current amplified relative to the reference current Iref.

[0043] The circuit 104 comprises at least one PI MOSFET, for example a P-channel MOSFET, coupling a supply potential Vdd to an input In of the circuit 104, the input In being configured to receive the reference current Iref. The gate of the PI transistor is connected to the input In. In the example in [Fig. 1], the circuit 104 comprises only one PI transistor having its conduction terminals coupled, for example connected, respectively to the potential Vdd and to the input In. By way of example, the potential Vdd is positive with respect to a reference potential, for example ground Gnd.

[0044] The circuit 104 further comprises, for each column Cj, at least one MOS transistor P2j, for example a P-channel transistor like the PI transistor, coupling the potential Vdd to an output Outj coupled to that column Cj. In other words, the circuit 104 comprises M outputs OUTj, each connected to the corresponding column Cj. In the example of [Fig. 1], for each column Cj, the circuit 104 comprises only one transistor P2j having its conduction terminals coupled, for example connected, respectively to the potential Vdd and to the corresponding output Outj.

[0045] The circuit 104 includes a conductive rail 108 connecting the gate of the PI transistor to the gates of the P2j transistors.

[0046] Thus, for each column Cj, the circuit 104 comprises a current mirror formed by the PI transistor and by the P2j transistor mounted as a mirror of the PL transistor. The M current mirrors of the circuit 104 share the same PL transistor.

[0047] By way of example, the current Iref is supplied to the input In of the circuit 104 by a REF circuit configured to supply the current Iref. Preferably, this REF circuit is not part of block 1, and can be shared between, or common to, several blocks 1 in a memory circuit comprising several blocks 1.

[0048] Preferably, the value of the current Iref can be changed over time, and the REF circuit receives a Ref_val signal, for example a digital signal, controlling the value of the current Iref.

[0049] By way of example, the REF circuit includes a digital-to-analog converter (DAC), for example controlled by the Ref_val signal, and an analog output of the DAC circuit driving the gate of a NI transistor, for example an N-channel transistor, having a forward resistance that determines the value of the Iref current. The NI transistor is part of the REF circuit, or, alternatively, may be provided in each block 1, while the DAC circuit is preferably shared among several blocks. By way of example, the NI transistor couples the In input of the circuit 104 to a reference potential, for example ground (Gnd).

[0050] For each column Cj, block 1 comprises at least one column-selecting MOS transistor Tj. For each column Cj, the conducting or blocking state of the(s) The transistors Tj determine whether a current can be supplied by the output Outj of circuit 104 so as to flow in the corresponding column Cj. In the example in [Fig. 1], for each column Cj, the transistor(s) Tj couple the corresponding output Outj of circuit Tj to column Cj, that is, for example, to the conductive rail of column Cj to which the cells 100 of this column Cj are coupled, preferably connected. As an example, in [Fig. 1], for each column Cj, block 1 comprises only one transistor Tj having a first conduction terminal coupled, preferably connected, to column Cj, and a second conduction terminal coupled, preferably connected, to the corresponding output Outj of circuit 104. In other examples not shown, for each column Cj, block 1 comprises several transistors Tj in series between column Cj and the corresponding output Outj of circuit 104.

[0051] Block 1 includes a column control circuit 110. Circuit 110 is configured to control transistors Tj. Circuit 110 therefore provides, for each column Cj, a Selj control signal for the transistor(s) Tj.

[0052] More specifically, during a simultaneous write step in one or more columns Cj selected from among the M columns Cj, the circuit 110 is configured to control the transistors Tj so that a write current pulse flows in each of the selected columns Cj, and not in the other columns Cj. The circuit 110 controls the transistors so that the write current pulses flowing in the selected columns start and end simultaneously. For example, when block 1 includes only one transistor Tj per column Cj, for each column Cj, the Selj signal includes only one component supplied to the gate of the transistor Tj. As another example, when block 1 includes several transistors Tj per column Cj, for each column Cj, the Selj signal includes several components, each applied to the gate of one of the transistors Tj.

[0053] Circuit 110 receives a signal Sig1 indicating, for each write step, which columns Cj are to be selected during that write step, or, in other words, which columns Cj are to be written during that write step. Circuit 110 also receives a control signal Sig2 for the write step. For example, signal Sig2 indicates the start of the write current pulses flowing through the columns selected during the write step. As an example, signal Sig2 also indicates the end of the write current pulses flowing through the columns selected during the write step.

[0054] Although not detailed in [Fig. 1], circuit 110 can receive other signals. For example, circuit 110 can receive one or more selection coordination signals and / or a write mode activation signal.

[0055] Although not detailed in [Fig. 1], during a write step to several columns simultaneously, block 1 is configured so that the pulses circulating in the selected columns all have the same shape, determining the programmed state in the memory cells addressed during that write step. This pulse shape depends on the current Iref and, for example, on the signal Sig2 with respect to the pulse duration. For example, pulses used to program an amorphous state of the phase-change material have a shape exhibiting a sharp edge at the end of the pulses. Conversely, pulses used to program a crystalline state of the phase-change material have, for example, a shape exhibiting a slow edge at the end of the pulses compared to the previously mentioned sharp edge.

[0056] One drawback of block 1 described above is the following. At the beginning of a write step in several columns Cj simultaneously, the transistors Tj of these columns are switched to the conducting state by circuit 110 by means of the Selj signals. This results in a voltage variation on rail 108, for example, a voltage drop. This voltage variation at the beginning of the write current pulses alters the shape of the write current pulses compared to a target shape.

[0057] Furthermore, the value (amplitude) of this voltage variation on rail 108 depends on the number of columns Cj selected as illustrated in [Fig.2], this dependence of the voltage variation on rail 108 on the number of columns Cj selected not being desirable.

[0058] Fig. 2 illustrates by a curve 200 the evolution of the voltage variation on rail 108 (on the ordinate) at the beginning of the writing current pulses in the selected columns, as a function of the number of columns selected (on the abscissa).

[0059] As shown in curve 200, the amplitude of the voltage variation on rail 108 increases with the number of columns selected during a writing step.

[0060] To overcome the disadvantages of memory block 1, it is proposed here to add a compensation circuit configured to provide, at the beginning of the writing current pulses in the selected columns Cj, a compensation current pulse whose amplitude depends on the number of columns Cj selected.

[0061] This current pulse is configured to compensate for the voltage variation on rail 108, so that the voltage on rail 108 remains as stable as possible at the beginning of the write current pulses. In this way, the write current pulses have the expected shape, which is determined by the value of the current Iref and by the signal Sig2.

[0062] Fig. 3 represents an example of such an embodiment of a PCM3 memory block.

[0063] Memory block 3 shares many elements with memory block 1, and only the differences between these two memory blocks are highlighted here. In particular, unless otherwise indicated, everything previously stated with respect to memory block 1 applies to memory block 3.

[0064] Compared to memory block 1, memory block 3 circuit includes a CMP compensation circuit.

[0065] The CMP circuit is configured to receive a Sig3 signal. The Sig3 signal indicates the number of columns Cj selected for a read step. For example, the Sig3 signal indicates which columns Cj are selected, and therefore the number of columns Cj selected. The Sig3 signal allows the CMP circuit to determine the maximum amplitude of the compensation current pulse so that it compensates for the variation, for example, the drop in voltage of rail 108 at the beginning of the write current pulses.

[0066] By way of example, when the current Iref has a fixed maximum value regardless of the writing step considered, that is to say when the writing current pulses have an identical maximum amplitude regardless of the writing step considered, the signal Sig3 is, for example, entirely determined by the signal Sigl, and is, for example, identical to this signal Sigl or is representative of a single value equal to the number of columns Cj selected.

[0067] As another example, when the current Iref has a maximum value that depends on the writing step considered, that is to say when the writing current pulses have a maximum amplitude that varies according to the writing step considered, the signal Sig3 is, for example, at least partly determined by the signal Sigl and by the maximum value of the current Iref for the writing step considered.

[0068] The CMP circuit is further configured to receive a Sig4 signal indicating the start of the write current pulses in the columns Cj selected for the write step, that is, the start time of these write current pulses. This Sig4 signal synchronizes the start of the compensation current pulse with the start of the write current pulses. Thus, the Sig4 signal determines the start of the compensation current pulse.

[0069] By way of example, the Sig4 signal is at least partly determined by the Sig2 signal.

[0070] For example, the Sig4 signal includes the Sig2 signal and an indication of a delay, by A programmable example during a calibration phase involves a timing signal between a Sig2 edge that triggers the start of the writing current pulses and the start of the current compensation pulse. Alternatively, the Sig4 signal is determined solely by the Sig2 signal; for example, it is identical to the Sig2 signal. As yet another example, the Sig4 signal corresponds to the concatenation of the Selj signals, the latter being at least partially determined by the Sig2 signal.

[0071] Based on the received Sig3 and Sig4 signals, the CMP circuit determines the shape of the compensating current pulse, and, more specifically, at what time this pulse should begin and what its amplitude should be. In other words, the CMP circuit is configured to supply the conductor rail 108, at the beginning of the write current pulses, with a compensating current pulse determined by the Sig3 and Sig4 signals.

[0072] Although not illustrated in [Fig.3], in some embodiments the CMP circuit can receive a signal to selectively activate and deactivate compensation, i.e. a signal indicating whether or not the CMP circuit should provide a compensation current pulse for the writing step under consideration.

[0073] By way of example, in [Fig.3], circuit 104 comprises two PI transistors, and, for each column, 2 P2j transistors, it being understood that circuit 104 could have been implemented in the manner illustrated in [Fig.1], where with a number of PI transistors and a number of P2j transistors different from those of the examples in Figures 1 and 3.

[0074] According to one embodiment, the CMP circuit comprises only one CmpOut output configured to provide the compensation current pulse, this CmpOut output being connected to rail 108.

[0075] According to one embodiment, the CMP circuit comprises capacitors in parallel and is configured to provide the compensation current pulse by discharging these capacitors onto rail 108 at the beginning of the write current pulses. In this case, the amplitude of the compensation current pulse is determined by the number of capacitors that the CMP circuit will couple to rail 108 at the beginning of the write current pulses, and which will discharge and supply charges to rail 108. The number of capacitors selected and the time at which the selected capacitors begin discharging onto rail 108 are controlled by the CMP circuit based on the Sig3 and Sig4 signals.

[0076] For example, the CMP circuit comprises, as shown in [Fig. 3], a Capa circuit comprising a plurality of capacitors (not shown in [Fig. 3]). Each capacitor in the Capa circuit is connected to a Cout output node of the Capa circuit by a switch (not shown in [Fig. 3]). In other words, the Capa circuit comprises a plurality of capacitors in parallel, each connected to the Cout node by a corresponding switch. The Cout node is coupled to the CmpOut output, preferably by an IT switch as illustrated in [Fig. 3], although in other unillustrated examples, this Cout node may be directly connected to the CmpOut output. The CMP circuit is configured to precharge the capacitors in the Capa circuit before the write step and to electrically couple selected capacitors to the CmpOut output at the beginning of the compensation current pulse.

[0077] For example, the CMP circuit is configured to determine which capacitors to select based on the Sig3 signal, that is, to determine which capacitors to select so that the compensation current pulse properly compensates for the voltage variation on rail 108 at the beginning of the write current pulses.

[0078] By way of example, for each selected capacitance, the CMP circuit is configured to control the closing of the switch connecting that capacitance to the Cout node. In the example in [Fig. 3], where the CMP circuit includes the IT switch, this closing of the selected capacitance switches is implemented before the start of the write current pulses. Then, the CMP circuit controls the closing of the IT switch at the start of the write current pulses to trigger the start of the compensation current pulse. In another example not shown, where the CMP circuit does not include the IT switch, the CMP circuit controls the closing of the selected capacitance switches at the start of the write current pulses.However, in the absence of the IT switch, due to possible desynchronization of the closing of these switches, the compensation current pulse may have a shape further from a target shape than in the case where the IT switch is present.

[0079] By way of example, the switches connecting the capacitors of the Capa circuit to the Cout node are controlled by a signal Sig5 produced by the CMP circuit from the signal Sig3, for example by a CTRL circuit of the CMP circuit. For example, the signal Sig5 is configured to control the open or closed state of each of these switches, independently of the open or closed state of the other switches.

[0080] As an example, the IT switch is controlled by a Sig6 signal produced by the CMP circuit from the Sig4 signal, for example by the CTRL circuit of the CMP circuit.

[0081] Fig. 4 represents an example of the implementation of circuit 110 of Fig. 3.

[0082] In this example, the circuit 110 includes a logic circuit 400 implementing a Boolean AND function between the signals Sig1 and Sig2, and providing the set of Selj signals (Sel<l..M> in [Fig.4]) which correspond to the result of this boolean function.

[0083] In this example, the Sigl signal is an M-bit signal, each bit of the Sigl signal corresponding to a column Cj and being in logic state T' when the corresponding column Cj is to be selected during the read step. In this example, the Sig2 signal is a binary signal that switches from logic state '0' to logic state T' to indicate (control) the start of the write current pulses, and from logic state '0' to logic state '0' to indicate (control) the end of the write current pulses, if this is not caused by the zeroing of the Iref current. The Sel signal<l..M> corresponding to a signal of M bits, each bit corresponding to a Selj signal and being the result of a Boolean AND between the bit of the Sigl signal corresponding to column Cj and the Sig2 signal. In other words, the Sel signal<l..M> corresponds to the concatenation of the Selj signals.

[0084] Of course, a person skilled in the art will be able to foresee other examples of implementation of circuit 110 from the functional description previously given of circuit 110, for example in the case where circuit 110 receives one or more selection coordination signals and / or an activation signal of a writing mode.

[0085] Figure 5 represents an example of an implementation of the CTRL circuit of the CMP circuit of Figure 3. In this example, the CTRL circuit receives the signals Sig3 and Sig4, and provides the signals Sig5 and Sig6.

[0086] In this example, the signal Sig3 includes an indication (or signal) Sig31 indicating the number of columns Cj selected. For example, the signal Sig31 is identical to the signal Sigl. Furthermore, in this example, the maximum amplitude of the write current pulses depends on the write step considered, and the signal Sig3 further includes an indication (or signal) Sig32 indicating this maximum amplitude value.

[0087] Furthermore, in this example, the signal Sig4 includes an indication (or signal) Sig41 indicating the start of the write current pulses. For example, the signal Sig41 is identical to the signal Sig2. In addition, in this example, the signal Sig4 includes an indication (or signal) Sig42 determining a delay, preferably programmable during a calibration step, between an edge of the signal Sig41 corresponding to a command to start the write pulses, and the start time of the corresponding compensation current pulse that the CMP circuit must provide.

[0088] In this example, the CMP circuit also receives an EN signal for selective activation of the compensation, that is to say a signal for selective activation of the CMP circuit.

[0089] The CMP circuit includes a Circl circuit configured to receive the Sig41 and Sig42 signals, and to provide a Sig7 signal corresponding to the Sig41 signal delayed by a time determined by the Sig42 signal. In other examples not shown, where the Sig4 signal does not include the Sig42 indication of a delay, the Circl circuit can be omitted, and the Sig5 signal then corresponds to the Sig4 signal. In yet other examples not shown, where the Sig4 signal does not include the Sig42 indication of a delay, this delay can be hard-coded in the Circl circuit. In yet another example, where the Sig4 signal indicates the start time of the write current pulses and therefore does not include a Sig42 indication, the Sig7 circuit can be omitted, and the Sig7 signal then corresponds to the Sig4 signal.

[0090] In this example where the CMP circuit receives the EN signal, the CMP circuit includes a Circ2 circuit configured to receive the Sig7 signal and the EN signal, and to provide A Sig8 signal. The Sig8 signal indicates when the switches for the selectable capacitors in the Capa circuit are switched on to select those capacitors. It is understood that, in the case where the EN signal indicates that compensation should be disabled, the Sig8 signal does not indicate a specific time for switching these switches on. In other, unillustrated examples where the CMP circuit does not receive the EN signal, the Circ2 circuit can be omitted, and the Sig8 signal then corresponds to the Sig7 signal.

[0091] The CMP circuit includes, in this example, a Circ3 circuit configured to receive the Sig3 signal, i.e. the Sig31 and Sig32 signals in the example of [Fig.5], and to provide a Sig9 signal indicating which capacitances are selected in the Capa circuit, i.e. which switches coupling the capacitances of the Capa circuit to the CmpOut node ([Fig.3]) are to be switched on.

[0092] The CMP circuit further includes, in this example, a Circ4 circuit configured to receive the Sig8 and Sig9 signals, and to provide the Sig5 signal from these Sig7 and Sig8 signals. For example, the Sig5 signal corresponds to the Sig9 signal when the Sig8 signal is in a state indicating that the switches of the selected capacitors in the Capa circuit should be controlled to the closed state.

[0093] In this example, where the CMP circuit provides the Sig6 control signal for the IT switch, which determines (controls) the start of the compensation current pulse, the CMP circuit includes a Circ5 circuit configured to receive the Sig8 signal and to provide the Sig6 signal from the Sig8 signal. For example, the Sig6 signal corresponds to the Sig8 signal delayed by a fixed or programmable delay, for example, during a calibration step of the CMP circuit.

[0094] In the embodiment of the CMP circuit described in relation to [Fig.3], the compensation current pulse is supplied by a single CmpOut output of the CMP circuit, and is therefore supplied to rail 108 on a connection node of this rail 108 to the CmpOut output.

[0095] In alternative embodiments, it may be desirable, to improve the quality of the compensation, for the CMP circuit to provide the compensation current pulse in the form of a plurality of compensation current sub-pulses, each sub-pulse corresponding to a different selected column Cj and being supplied directly to the gate of the MOS transistor(s) P2j corresponding to that column Cj.

[0096] Figure 6 represents an example of such a variant embodiment of memory block 3.

[0097] Memory block 3 of [Fig. 6] includes many elements in common with that of [Fig. 3], and only the differences between these two memory blocks 3 are shown here. highlighted. Thus, unless otherwise indicated, everything previously indicated for memory block 3 described in relation to [Fig.3] applies to the memory block of [Fig.6].

[0098] Compared to memory block 3 of [Fig. 3], the CMP circuit of the memory block of [Fig. 6] comprises M CmpOutj outputs, each corresponding to a different column Cj. For each column Cj, the CmpOutj output of the CMP circuit is connected to the gate of the transistor(s) P2j corresponding to that column. Each CmpOutj output is configured to provide, for

[0099] In addition, in [Fig.6], the Sig3 signal includes, for each column Cj, an indication that the column Cj is or is not selected.

[0100] The CMP circuit is configured here to provide, for each column Cj, a compensation current sub-pulse starting with the compensation current pulse (i.e., with the write current pulses) if that column Cj is selected. Thus, according to one embodiment, the CMP circuit comprises M sub-circuits Locj corresponding respectively to the M columns Cj. For each column Cj, the Locj circuit corresponding to that column Cj has an output connected to the CmpOutj output of the CMP circuit, and is configured to provide, at this CmpOutj output, a compensation current sub-pulse starting with the compensation current pulse if, that is, only if, that column Cj is selected. By way of example, the Locj circuits are all identical.

[0101] According to one embodiment, for each column Cj, the indication that the column Cj is or is not selected can be included in the signal Sig3, for example when this signal Sig3 corresponds at least in part to the signal Sig2.

[0102] According to another embodiment, for each column Cj, the indication that this column Cj is selected or not corresponds to the Selj signal of the column, and the Sig4 signal comprises all the Selj signals. In [Fig. 6], both the Sig4 signal supplied to the CMP circuit and the Selj signals supplied to the CMP circuit are shown, although in such an embodiment the Sig4 signal actually corresponds to the Selj signals. For each column Cj, the Selj signal of that column is then, for example, supplied to the corresponding Locj circuit.

[0103] One advantage of the Sig4 signal comprising all the Selj signals is that these Selj signals can serve as a synchronization signal to control the start of the compensation current sub-pulses, and thus the compensation current pulse, relative to the start of the write current pulses. In particular, when a column Cj is selected, this allows the start of the compensation current sub-pulse corresponding to that column Cj to be synchronized with the start of the write current pulse flowing in that column Cj.

[0104] In one embodiment, each Locj circuit comprises a plurality of capacitors in parallel, each connected to an internal node of the Locj circuit by a switch. Optionally, but preferably, each Locj circuit comprises an ITloc switch connecting its internal node to the LocOutj output of the Locj circuit, and thus to the Cmpoutj output of the CMP circuit. Each Locj circuit is configured to pre-charge its capacitors before a write step, and to close its IT switch at the beginning of the write current pulses if the Cj column corresponding to that Locj sub-circuit is selected, that is, at the time when the compensation current sub-pulse provided by that Locj circuit is to begin when the corresponding Cj column is selected, or, put another way, at the time when the compensation current pulse comprising all the compensation current sub-pulses is to begin.Furthermore, each Locj circuit is configured to control the on-state of the switches coupling the selected capacities, preferably before switching to the on-state of its IT switch if the Cj column corresponding to this Cj circuit is selected.

[0105] By way of example, the CMP circuit is configured, from the signal Sig3, to indicate to each Locj circuit which capacities that this circuit should select, this indication being preferably identical for all Locj circuits.

[0106] For example, each Locj circuit receives the same SiglO signal indicating which capacities it must select. This SiglO signal is determined from the Sig3 signal, for example, by a CTRLg circuit of the CMP circuit. The CTRLg circuit is, for example, similar to the CTRL circuit described previously, except that it comprises only the Circ3 circuit and the SiglO signal it provides corresponds to the concatenation of the EN and Sig9 signals.

[0107] By way of example, each subcircuit Locj receives the corresponding Selj signal, and switches its IT switch to the conducting state when the Selj signal indicates that the transistor(s) Tj are switched to the conducting state, which allows better synchronization of the compensation because this synchronization is done locally for each column Cj.

[0108] Fig. 7 represents an example of the implementation of a Locj circuit, in the case where the Locj circuit receives the SiglO signal and the Selj signal.

[0109] The Locj circuit comprises, as shown in [Fig. 7], a CapaLoc circuit comprising a plurality of capacitors (not shown in [Fig. 7]). Each capacitor of the CapaLoc circuit is connected to a CLocOut output node of the CapaLoc circuit by a switch (not shown in [Fig. 3]). In other words, the CapaLoc circuit comprises a plurality of capacitors in parallel, each connected to the CLocOut node by a corresponding switch. The CLocOut node is coupled to the LocOutj output, preferably by an ITLoc switch as illustrated in [Fig. 3]. The circuit Locj is configured to pre-charge the capacitors of its CapaLoc circuit before the writing step, and to electrically couple selected capacitors to the LocOutj output at the beginning of the compensation current pulse.

[0110] For example, the Locj circuit is configured to determine which capacities to select from the SiglO signal.

[0111] As an example, for each selected capacity, the Locj circuit is configured to control the closing of the switch connecting this capacitance to the CLocout node. In the example of [Fig.7] where the Locj circuit includes the ITLoc switch, this closing of the selected capacitance switches is implemented before the start of the write current pulses, then, the Locj circuit controls the closing of the ITLoc switch at the start of the write current pulses.

[0112] By way of example, the switches connecting the capacitors of the Capa circuit to the CLocOut node are controlled by a Sigl 1 signal produced by the Locj circuit from the SiglO signal, for example by a CTRLLOC circuit of the Locj circuit. For example, the Sigl 1 signal is configured to control the open or closed state of each of these switches, independently of the open or closed state of the other switches.

[0113] As an example, the ITLoc switch is controlled by a Sigl2 signal produced by the Locj circuit from the Selj signal, for example by the CTRLLoc circuit of the Locj circuit.

[0114] An example of implementation of the CTRLLOC circuit is illustrated in [Fig.7].

[0115] In this example, the EN signal is included in the SiglO signal, and the CTRLLOC circuit includes a Circô circuit configured to receive the Selj signal and the EN signal. The Circô circuit is configured to provide, based on the Selj signal, a Sigl3 signal indicating which switches coupling the selected capacitors of the CapaLoc circuit to the CLocOut node should be switched on. For example, the Circô circuit implements a Boolean AND logic function between the Selj and EN signals when the logic '1' state of the Selj signal controls the on state of the corresponding Tj transistors and the logic '1' state of the EN signal controls the activation of the compensation.Thus, when the EN signal is in the logic state '0' indicating that compensation is disabled, or when the Selj signal is in the logic state '0' indicating that the corresponding Cj column is not selected, the Sigl3 signal does not indicate any moment when the switches should be switched to the conducting state.

[0116] In other examples not shown where the Locj circuit does not receive the EN signal, the Circô circuit can be omitted and the Sigl3 signal then corresponds to the Selj signal.

[0117] The Locj circuit includes, in this example, a Circ7 circuit configured to receive the SiglO signal indicating which capacities are selected in the CapaLoc circuit. The Circ7 circuit also receives the Sig 13 signal. The Circ7 circuit provides the The signal Sigl 1 is derived from the signals Sig 13 and Sigl0, that is, from the signals Sigl0 and Selj. For example, the signal Sigll corresponds to the signal Sigl0 when the signal Sigl3 is in a state indicating that the switches of the selected capacitors in the CapaLoc circuit should be closed.

[0118] The CMP circuit further includes, in this example, a Circ8 circuit configured to receive the Sig 13 signal and to provide the Sig 12 signal from the Sig 13 signal. For example, the Sigl2 signal corresponds to a delayed version of the Sig 13 signal.

[0119] Although an example of a Locj circuit has been described in relation to [Fig.7], a person skilled in the art will be able to foresee other examples of implementation of the Locj circuit from the functional description previously given of this Locj circuit.

[0120] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to them. In particular, the implementation of the CMP circuit is not limited to the examples described above, and those skilled in the art will be able to foresee other implementations of this circuit, whether configured to provide the compensation current pulse on a single CmpOut output of the CMP circuit connected to rail 108, or for the compensation current pulse in the form of several compensation current sub-pulses, each of these sub-pulses being provided by a corresponding CmpOutj output, only if the Cj column corresponding to that output is selected during the writing step.

[0121] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, a person skilled in the art will be able to implement the Capa and CapaLoc circuits.

Claims

Demands

1. Memory block (3) comprising: several phase-change memory cells (100) arranged in rows (RI, RN) and columns (Cl, C2, CM); a first circuit (104) comprising: - at least one first MOS transistor (PI) coupling a supply potential (Vdd) to an input (In) of the first circuit configured to receive a reference current (Iref), and having its gate connected to said input, - for each column (Cl, C2, CM), at least one second transistor (P21, P22, P2M) coupling the supply potential (Vdd) and a corresponding output (Outl, Out2, OutM) of the first circuit coupled to said column, and - a conductive rail (108) connecting said input (In) to the gates of the second transistors (P21, P22, P2M); for each column, at least one third MOS transistor (T1, T2, TM) coupling said column to the corresponding output of the first circuit;and a second circuit (104) configured to: - receive a first signal (Sig1) indicating columns to be written during a write step, and a second signal (Sig2) to control the write step, and - control the third MOS transistors (T1, T2, TM) on the basis of the first and second signals, so that, during the write step, a write current pulse flows in each selected column, wherein the memory block includes a third circuit (CMP) configured to: - receive a third signal (Sig3) indicating a number of selected columns and a fourth signal (Sig4) indicating the start of write current pulses in the selected columns, and - supply to the conductive rail (108), at the start of the write current pulses, a compensating current pulse determined by the third and fourth signals (Sig3, Sig4).

2. Memory block according to claim 1, wherein the compensation current pulse is determined from the third and fourth signals (Sig3, Sig4) so ​​as to compensate for a variation voltage on said rail (108) resulting from a switching to the on state of the third MOS transistors (T1, T2, TM) of the columns selected at the beginning of the writing current pulses.

3. Memory block according to claim 1 or 2, wherein, for each column (Cl, C2, CM), said at least one second MOS transistor (P21, P22, P2M) coupling the supply potential (Vdd) and the corresponding output (Outl, Out2, OutM) of the first circuit (104) is mounted in current mirror with said at least one first MOS transistor (PI).

4. Memory block according to any one of claims 1 to 3, wherein the fourth signal (Sig4) determines a start of the compensation current pulse, and the third signal (Sig3) determines a maximum value of the compensation current pulse.

5. Memory block according to any one of claims 1 to 4, wherein the third signal (Sig3) further includes an indication of a maximum value of the write current pulses during the write step.

6. Memory block according to any one of claims 1 to 5, wherein the second signal (Sig2) indicates a start and end of the write current pulses flowing in the selected columns (Cl, C2, CM).

7. Memory block according to claim 6, wherein the fourth signal (Sig4) is determined at least in part by the second signal.

8. Memory block according to any one of claims 1 to 7, wherein the third circuit (CMP) is further configured to receive a signal (EN) to selectively activate and deactivate the supply of the compensation current pulse to said rail (108).

9. Memory block according to any one of claims 1 to 8, wherein the third circuit (CMP) comprises a single output (CmpOut) connected to said rail (108) and configured to provide said compensation current pulse.

10. A memory block according to claim 9, wherein the third circuit (CMP) comprises a plurality of parallel capacitors, each connected to a first node (Cout) by a first switch (CAPA), and a second switch (IT) connecting the first node (Cout) to the output (CmpOut) of the third circuit, the third circuit being configured to pre-load the capacitors before the write step, to close the second switch (IT) at the beginning of the compensation current pulse, and to close all or part of the first switches before the closure of the second switch (IT) on the basis of the third signal (Sig3).

11. Memory block according to any one of claims 1 to 8, wherein: the third circuit (CMP) comprises, for each column (Cl, C2, CM), a corresponding output (CmpOutl, CmpOut2, CmpOutM) connected to the gate of said at least one second MOS transistor (P21, P22, P2M) coupled to said column (Cl, C2, CM); the third circuit comprises, for each column (Cl, C2, CM), a subcircuit (Locl, Loc2, LocM) configured to provide to the output (CmpOutl, CmpOut2, CmpOutM) of the third circuit corresponding to that column, a first current pulse beginning with the compensation current pulse if said column is selected; and the compensation current pulse corresponds to the set of first pulses.

12. Memory block according to claim 11, wherein: each subcircuit (Locl, Loc2, LocM) comprises: - a plurality of parallel capacitors (CapaLoc) each connected to a first node (LocOutl, LocOut2, LocOutM) of said subcircuit by a first switch, and - a second switch (ITLoc) connecting said first node (LocOutl, LocOut2, LocOutM) of said subcircuit to the output (CmpOutl, Cmpout2, CmpOutM) of the third circuit to which this subcircuit is connected; and each subcircuit is configured to: - pre-charge said capacitors before the write step, - close its second switch (ITLoc) at the beginning of the compensation current pulse if the column corresponding to the subcircuit is selected, and - close all or part of the first switches before the closing of the second switch on the basis of the third signal (Sig3).

13. Memory block according to claim 12, wherein, for each column (C1, C2, CM), the sub-circuit (Locl, Loc2, LocM) corresponding to that column is configured to receive a control signal (Selj) from said at least one third switch (T1, T2, TM) corresponding to that column, and to control the

14. switching its second switch (ITLOC) to the on state based on this control signal (Selj). Memory comprising at least one memory block (3) according to any one of claims 1 to 13, and a circuit (REF) configured to provide the reference current (Iref).

Images