Method for manufacturing a silicon-on-insulator type substrate
A cost-effective method for manufacturing silicon-on-insulator substrates by forming a silicon-germanium layer, creating cavities, and filling them with insulating material addresses the high cost of existing SOI substrate manufacturing, enabling efficient integration of electronic components.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- CENT NAT DE LA RECH SCI (C N R S)
- Filing Date
- 2024-12-05
- Publication Date
- 2026-06-12
AI Technical Summary
Existing silicon-on-insulator (SOI) substrates are typically manufactured on entire semiconductor wafers, which are expensive and there is a need to overcome the disadvantages of their manufacturing processes.
A manufacturing process for a silicon-on-insulator substrate involves forming a silicon-germanium layer on a silicon substrate, creating openings, selectively removing part of the silicon-germanium layer to form a cavity, and filling it with an insulating material, allowing for the formation of a silicon layer on the insulating material.
This process enables the production of a silicon-on-insulator substrate that is cost-effective and allows for the integration of electronic components, such as transistors, on a single substrate, with controlled insulation thickness.
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Abstract
Description
Title of the invention: Method for manufacturing a silicon-on-insulator substrate. Technical field
[0001] This description relates generally to the field of silicon-on-insulator semiconductor substrates. More specifically, it relates to a method for manufacturing such substrates. Previous technique
[0002] Silicon on insulator or SOI substrates consist of a multilayer structure comprising an insulating layer between two silicon layers.
[0003] Such substrates are particularly used in the manufacture of electronic components since they allow, for example, for an increase in their performance. However, these substrates are usually manufactured on entire semiconductor wafers and are often expensive.
[0004] It would be desirable to overcome all or part of the disadvantages of SOI substrates and their manufacturing processes. Summary of the invention
[0005] To this end, one embodiment provides a manufacturing process for a silicon-on-insulator substrate comprising the successive steps of: a) formation of a silicon-germanium layer on a top face of a silicon substrate; b) formation of a silicon layer on an upper face of the silicon-germanium layer; c) formation of at least one opening, passing through the silicon layer and opening into the silicon-germanium layer; d) selective removal of at least part of the silicon-germanium layer through the opening so as to create a cavity between the silicon substrate and the silicon layer; and e) filling the cavity, through the opening, with an insulating material.
[0006] According to one embodiment, at the end of step e), the cavity is completely filled with the insulating material.
[0007] According to one embodiment, at the end of step e), the cavity is partially filled by the insulating material.
[0008] According to one embodiment, the germanium silicon layer is doped.
[0009] According to one embodiment, during step a), the silicon-germanium layer is formed by epitaxy.
[0010] According to one embodiment, during step b), the silicon layer is formed by epitaxy.
[0011] According to one embodiment, during the filling of the cavity in step e), at least one opening through the silicon layer is further filled with the insulating material.
[0012] According to one embodiment, the process comprises, before step a), a localized removal step of a portion of the thickness of the silicon substrate, and in which, at step a), the silicon-germanium layer is formed only in a cavity formed by said localized removal of a portion of the thickness of the silicon substrate.
[0013] According to one embodiment, during step d), the silicon-germanium layer is fully or partially removed.
[0014] According to one embodiment, the process includes, between steps a) and b), a step of forming a silicon encapsulation layer on the upper face of the silicon-germanium layer.
[0015] According to one embodiment, during step a), the silicon-germanium layer is formed over the entire surface of the silicon substrate.
[0016] According to one embodiment, during step b), the silicon layer is formed over the entire surface of the silicon-germanium layer and is formed in contact with it.
[0017] According to one embodiment, the process includes, before step a), a step of forming a dielectric layer on a part of the substrate, the silicon-germanium layer is formed only outside the face of the dielectric layer.
[0018] Another embodiment provides for a method of manufacturing an electronic chip in and on a silicon-on-insulator substrate obtained by a process described above, comprising a step of forming a transistor in and on the silicon layer.
[0019] Yet another embodiment provides a silicon-on-insulator substrate comprising, in a first region: a layer of insulating material on a top face of a silicon substrate; and a silicon layer on a top face of the layer of insulating material, the silicon layer being traversed by at least one opening.
[0020] According to one embodiment, said at least one opening through the silicon layer is filled by said insulating material.
[0021] According to one embodiment, in at least a second region, the silicon layer rests directly on and in contact with the silicon substrate.
[0022] According to one embodiment, the lower face of the silicon layer, in the second region, is aligned with the lower face of the insulating material layer, in the first region.
[0023] According to one embodiment, in at least a second region, the silicon layer is separated from the silicon substrate by a silicon-germanium layer. Brief description of the drawings
[0024] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0025] [Fig.1], [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7A], [Fig.7B], [Fig.8], [Fig.9A], [Fig.9B], [Fig.9C], [Fig.10] and [Fig.11] are cross-sectional or top views of structures obtained at the end of successive stages of a manufacturing process of a substrate, of the silicon-on-insulator type, according to a first embodiment;
[0026] [Fig.12], [Fig.13], [Fig.14], [Fig.15], [Fig.16], [Fig.17] and [Fig.18] are cross-sectional views of structures obtained at the end of successive stages of a manufacturing process of a substrate, of the silicon-on-insulator type, according to a second embodiment;
[0027] Figures 19, 20, 21, 22, 23, 24 and 25 are cross-sectional views of structures obtained after successive stages of a manufacturing process for a substrate, of the silicon-on-insulator type, according to a third embodiment; and
[0028] Fig. 26A, Fig. 26B, Fig. 26C and Fig. 26D are top views illustrating different embodiments of the structure of Fig. 7A. Description of embodiments
[0029] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.
[0031] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.
[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0033] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.
[0034] Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7A, Fig. 7B, Fig. 8, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10 and Fig. 11 are cross-sectional or top views of structures obtained at the end of successive steps of an example of a manufacturing process for a substrate, of the silicon-on-insulator type, according to a first embodiment.
[0035] In particular, [Fig. 1] illustrates a starting structure comprising a silicon substrate 10. The silicon substrate 10 corresponds, for example, to a silicon wafer. The substrate 10 is, for example, a crystalline substrate. By way of example, the substrate 10 has a thickness in the range of 300 pm to 1 mm, for example, from 500 pm to 800 pm, the substrate 10 having, for example, a thickness of approximately 775 pm.
[0036] By way of example, the substrate 10 comprises a first region a) in which the substrate 10 will, during the process described below, be transformed into a silicon-on-insulator (SOI) substrate. The substrate 10 comprises, for example, a second region b) in which the substrate is not transformed and remains a silicon substrate.
[0037] By way of example, within the same plate 10, a plurality of parts a) and parts b) are formed. By way of example, parts a) and b) are organized according to a matrix in which parts a) and b) alternate.
[0038] By way of alternative, the substrate 10 comprises a single part a) and a single part b), for example, adjacent to each other. By way of example, part a) corresponds to a central part of the substrate 10 and part b) corresponds to a peripheral part of the substrate 10.
[0039] Fig. 2 is a partial and schematic cross-sectional view of a structure obtained after a step of depositing masking layers 11, 12 and 13 on, and for example in contact with, the upper face of the starting structure illustrated in Fig. 1.
[0040] More specifically, during this step, layer 11 is formed on the upper surface of the substrate 10, and is, for example, in contact with it. By way of example, layer 11 is formed over the entire upper surface of the substrate 10. Layer 11 is, for example, made of a dielectric material, for example, silicon oxide. The Lia layer for example a thickness in the range of 1 nm to 10 nm, the Lia layer for example a thickness of the order of 8 nm.
[0041] By way of example, layer 12 is formed on the upper surface of layer 11 and is, for example, in contact with it. By way of example, layer 12 is formed over the entire upper surface of layer 11. Layer 12 is, for example, made of a dielectric material, for example, silicon nitride. Layer 12 has, for example, a thickness in the range of 1 nm to 200 nm; layer 12 has, for example, a thickness on the order of 110 nm.
[0042] Alternatively, the stacking of layers 11 and 12 consists of silicon nitride, silicon oxide, or corresponds to a stacking of silicon oxide, silicon nitride, and silicon oxide, referred to as ONO. Figure 3 is a partial, schematic cross-sectional view of a structure obtained after a step of removing the masking layers 11 and 12 and part of the thickness of the substrate 10 so as to form a cavity 14 in the layers 11 and 12 and in the substrate 10.
[0043] By way of example, in this step, only the portions of layers 11 and 12 not covered by layer 13 are completely removed. Alternatively, in this step, the portions of substrate 10 not covered by layer 13 are partially removed, i.e., only a portion of the thickness of substrate 10 is removed. The etching process used in this step is, for example, a plasma etching process based on hydrogen bromide and dioxygen or carbon tetrafluoride and dioxygen, or a chemical vapor etching process, for example, based on hydrochloric acid. Alternatively, the process implemented in this step comprises consuming silicon by an oxidation process to consume the desired thickness of silicon, followed by selective etching to remove the oxidized silicon.
[0044] The thickness of the cavity 14 is for example within the range from 10 nm to 500 nm, for example within the range from 25 nm to 250 nm, for example within the range from 50 nm to 120 nm.
[0045] Fig. 4 is a partial and schematic cross-sectional view of a structure obtained after a formation step, in the cavity 14 of Fig. 3, of a silicon-germanium layer 16 and a silicon layer 18.
[0046] By way of example, initially, the silicon-germanium layer 16 is formed in the cavity 14 on and, for example, in contact with the substrate 10. By way of example, the silicon-germanium layer 16 is formed by epitaxy. By way of example, the silicon-germanium layer 16 is formed by selective epitaxy localized outside the area opposite the layer 12. Thus, the layer 16 is formed only in the cavities 14 and is not formed on the layer 12.
[0047] By way of example, the silicon-germanium 16 layer has a percentage of germanium in the range of 20% to 40%, for example a percentage of around 30% in atomic concentration.
[0048] By way of example, the silicon-germanium 16 layer has a thickness less than the depth of the cavity 14. By way of example, the silicon-germanium 16 layer has a thickness in the range from 10 nm to 150 nm.
[0049] By way of example, at the end of this step, the silicon-germanium layer 16 is in contact with the lower face and the sides of the cavity 14.
[0050] By way of example, in a second step, the silicon layer 18 is formed on, and for example in contact with, the silicon-germanium layer 16. By way of example, layer 18 is formed by epitaxy. By way of example, layer 18 is formed by selective epitaxy. Thus, layer 18 is not formed on layer 12.
[0051] By way of example, the silicon layer 18 encapsulates the silicon-germanium layer 16 in the cavity 14. Following the formation of the silicon layer 18, the silicon-germanium layer 16 is thus covered, on its upper face by the silicon layer 18 and, on its lower face and sides, by the substrate 10. The total encapsulation of the silicon-germanium layer 16 makes it possible to limit its exposure to air or to the controlled environment of the deposition or etching equipment, which can cause its degradation.
[0052] By way of example, the silicon layer 18 has a thickness allowing the upper face of the layer 18 to be flush with the upper face of the parts of the substrate 10 covered by the layer 12. By way of example, the layer 18 has a thickness in the range of 5 nm to 20 nm.
[0053] At the end of this step, the assembly corresponding to the substrate, layer 16 and layer 18 forms a continuous crystalline phase, for example without breaking of the crystalline phase between the different layers.
[0054] By way of example, layers 16 and 18 are doped in order to modify their properties, for example their conductivity properties. Layers 16 and 18 are, for example, doped with atoms of boron, arsenic, carbon, phosphorus, tin, or any other atoms, for example, of the electron donor or acceptor type.
[0055] Although an embodiment described here consists of layer 16 being covered by layer 18, layer 18 is optional. An alternative embodiment can therefore be envisaged in which layer 18 is omitted.
[0056] Fig. 5 is a partial, schematic cross-sectional view of a structure obtained after a step of removing layers 11 and 12.
[0057] By way of example, this step is carried out by wet etching, for example with phosphoric acid (H3PO4) or hydrofluoric acid (HF).
[0058] At the end of this step, the upper face of the structure is for example flat and is made of silicon.
[0059] Fig. 6 is a partial and schematic cross-sectional view of a structure obtained after a step of forming a silicon layer 20 on the upper face of the structure illustrated in Fig. 5.
[0060] By way of example, during this step, layer 20 is formed as a full plate on the upper surface of the structure illustrated in [Fig. 5]. For example, the silicon layer 20 is formed by epitaxy. The epitaxy enabling the formation of layer 20 is, for example, non-selective epitaxy, that is, non-localized epitaxy. Thus, layer 20 is formed simultaneously on the upper surface of layer 18 and on the upper surface of the substrate 10.
[0061] Layer 20 is, for example, a single-crystal silicon layer. Layer 20 is, for example, doped with atoms of boron, arsenic, carbon, phosphorus, or any other atoms, for example, of the electron donor or acceptor type.
[0062] The layer 20 has, for example, a thickness in the range from 15 nm to 250 nm, for example a thickness in the range from 60 nm to 80 nm, for example a thickness of around 70 nm.
[0063] Fig. 7A and Fig. 7B are partial and schematic top and cross-sectional views, respectively, of a structure obtained after a step of forming a hard mask and a layer of resin 26 on the upper face of the structure illustrated in Fig. 6. Fig. 7B is a cross-sectional view of the structure along a section plane BB of Fig. 7A.
[0064] By way of example, the hard mask comprises a dielectric layer 22 and an insulating layer 24.
[0065] In this step, initially, the insulating layer 22 is formed on the upper face of the layer 20. The dielectric layer 22 is, for example, formed as a solid plate so as to completely cover the surface of the silicon layer 20. As an example, the layer 22 is formed in contact with the layer 20. The layer 22 is made of an insulating material, for example, an oxide, for example, a silicon oxide, for example, tetraethyl orthosilicate (TEOS, from the English "TetraEthyl OrthoSilicate").
[0066] The layer 22 has, for example, a thickness in the range from 5 nm to 25 nm, for example a thickness of the order of 8 nm.
[0067] In this second step, the other insulating layer 24 is formed on the upper surface of layer 22. The insulating layer 24 is, for example, formed as a solid plate so as to completely cover the surface of the insulating layer 22. By way of example, layer 24 is formed in contact with layer 22. The layer 24 is in an insulating material, for example in a nitride, for example in silicon nitride.
[0068] The layer 24 has, for example, a thickness in the range from 30 nm to 250 nm, for example a thickness of the order of 120 nm.
[0069] In this third step, a resin layer 26 is formed on the upper face of layer 24. The resin layer 26 is, for example, formed as a solid plate so as to completely cover the surface of the insulating layer 24. As an example, layer 26 is formed in contact with layer 24. Layer 26 is, for example, made of a photosensitive resin, for example, a positive resin.
[0070] The layer 26 has, for example, a thickness in the range from 10 nm to 500 nm.
[0071] After its deposition, the layer 26 is, for example, exposed by photolithography in order to form patterns 27. More particularly, during this step, portions of the resin layer 26 are locally removed in order to reveal the upper face of the layer 24.
[0072] By way of example, as shown in [Fig.7A], the patterns 27 in the resin layer 26 correspond to parallel dotted lines.
[0073] By way of example, in order to ensure the mechanical stability of the structure during successive stages, and in particular during a step involving the removal of the silicon-germanium layer 16, illustrated in relation to Figures 9A, 9B and 9C, the motifs 27 are formed such that the layer 26 consists only of portions that are mechanically bonded to one another. In other words, during this step, the motifs 27 formed in the resin layer 26 do not isolate any portion of the resin layer 26.
[0074] Fig. 8 is a partial and schematic cross-sectional view of a structure obtained after an etching step of the structure illustrated in Figures 7A and 7B by creating openings 28 through the structure and extending into all or part of the silicon-germanium layer 16 and a step of removing the resin layer 26 from the upper face of the structure obtained.
[0075] As an example, during this step, the openings 28 are created by engraving.
[0076] The openings 28 pass through the silicon layer 20 and open into the layer in silicon-germanium 16. As an example, the openings 28 also pass through the insulating layers 22 and 24. In the embodiment illustrated in [Fig.8], the openings 28 also pass through the silicon layer 18.
[0077] Alternatively, the openings 28 pass through the silicon layer 20 and the silicon-germanium layer 16 and open into the substrate 10. By way of example, the openings 28 also pass through the insulating layers 22 and 24.
[0078] By way of example, the openings 28 have a width within a range from 100 nm to 500 nm.
[0079] At the end of the opening formation step 28, the resin layer 26 is removed so as to reveal the upper face of the insulating layer 24.
[0080] Fig. 9A and Figures 9B and 9C are respectively partial and schematic top and cross-sectional views of a structure obtained after a step of removing the silicon-germanium layer 16 through the openings 28 of the structure illustrated in Fig. 8, so as to create a cavity 30 between the substrate 10 and the silicon layer 20. Fig. 9B is a cross-sectional view of the structure along a section plane BB of Fig. 9A and Fig. 9C is a cross-sectional view of the structure along a section plane CC of Fig. 9A.
[0081] More particularly, during this step, the silicon-germanium 16 layer is selectively removed, that is to say, only the silicon-germanium 16 layer is removed during this step.
[0082] By way of example, the silicon-germanium 16 layer is removed by etching using a solution based on hydrochloric acid (HCl) in gaseous form.
[0083] Alternatively, the silicon-germanium 16 layer is removed by dry etching from tetrafluoromethane (CF4), dioxygen (O2) and helium (He)-based plasma.
[0084] As a further alternative, the silicon-germanium 16 layer is removed by humic etching with hydrofluoric acid (HF).
[0085] At the end of this step, the structure no longer has a silicon-germanium 16 layer. As an example, at the end of this step, the cavity 30 is filled with air or a gas, for example the gas present in the atmosphere of the etching chamber.
[0086] Fig. 10 is a partial and schematic cross-sectional view of a structure obtained after a filling step with a layer 32, through the openings 28, of the cavity 30 of the structure illustrated in figures 9A to 9C.
[0087] More particularly, during this step, the cavity 30 is filled, by the material of the layer 32, by the upper face of the structure illustrated in figures 9A, 9B and 9C.
[0088] Layer 32 is made of an insulating material, for example an oxide, for example silicon oxide.
[0089] By way of example, during this step, the cavity 30 is completely filled by the layer 32. By way of example, the deposition of the layer 32 is carried out by chemical vapor deposition (CVD). By way of example, the deposition of the layer 32 is preceded by an oxidation step of the surface of the cavity 30, for example by a regenerative thermal oxidation process (RTP).
[0090] At the end of this step, the openings 28 are for example also filled by the layer of insulating material 32. Thus, at the end of this step, the layer 20 is crossed by pillars of the insulating material of the layer 32.
[0091] Fig. 11 is a partial and schematic cross-sectional view of a structure obtained after a planarization step of the upper face of the structure illustrated in Fig. 10.
[0092] As an example, the planarization of the structure is carried out by chemical mechanical polishing (CMP).
[0093] By way of example, this step makes it possible to reveal the upper face of the nitride layer 24 without removing layers 22 and 24.
[0094] Although not shown, it can be anticipated that the insulating layers 22 and 24 are removed at the end of this step.
[0095] Following this step, in region a), a SOI-type substrate is thus obtained in and on which electronic components can, for example, be formed. By way of example, transistors or radio frequency switches of an electronic chip are formed in and on the silicon layer 20.
[0096] At the end of this step, the substrate thus formed comprises, a region a) of the silicon-on-insulator type and a region b) of the silicon type. By way of example, at the end of this step, the upper face of the substrate, in region a), is aligned with the upper face of the substrate, in region b).
[0097] In the manufacturing process described above, the thickness of the insulating layer 32 is defined by the depth of the cavity 30, itself defined by the thickness of the sacrificial silicon-germanium layer 16. The thickness of the insulating layer 32 in the final SOI substrate can then be modulated and adapted according to the technologies of the electronic components formed on the substrate.
[0098] Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17 and Fig. 18 are cross-sectional views of structures obtained at the end of successive steps of an example of a manufacturing process for a substrate, of the silicon-on-insulator type, according to a second embodiment.
[0099] The second embodiment described below differs from the first embodiment, described in relation to Figs 1 to 11, in that the second embodiment does not include a step of removing part of the thickness of the substrate 10 and in that the silicon-germanium layer 16 is formed full plate over the entire upper face of the substrate 10.
[0100] Fig. 12 is a partial and schematic cross-sectional view of a starting structure comprising a substrate 100 identical to the substrate 10 of the starting structure illustrated in Fig. 1.
[0101] Fig. 13 is a partial, schematic cross-sectional view of a structure obtained at the outcome of a step of formation of a silicon-germanium 160 layer on the upper face of the starting structure illustrated in [Fig. 12].
[0102] This step is similar to that described for the deposition of layer 16 in relation to [Fig. 4], except that, in [Fig. 13], layer 160 is formed as a full plate. Thus, layer 160 covers the entire surface of substrate 100. Layer 160 is, for example, in contact, by its lower face, with the upper face of substrate 100.
[0103] Fig. 14 is a partial, schematic cross-sectional view of a structure obtained at the result of a step of formation of a silicon 200 layer on the upper face of the structure illustrated in [Fig. 13]. The 200 layer is for example similar to the 20 layer illustrated in [Fig. 6].
[0104] This step is similar to that described in relation to [Fig. 6], except that, in [Fig. 14], layer 200 is formed on, and for example in contact with, silicon-germanium layer 160. In this step, layer 200 is formed only in contact with silicon-germanium layer 160. For example, layer 200 is formed over the entire upper surface of layer 160.
[0105] Fig. 15 is a partial, schematic cross-sectional view of a structure obtained following a successive formation step of an insulating layer 220, another insulating layer 240 and a resin layer 260 on the upper face of the structure illustrated in [Fig. 14].
[0106] Layers 220, 240 and 260 are respectively identical to layers 22, 24 and 26 described in relation to Figures 7A to 7C. This step is identical to that described in relation to Figures 7A and 7B.
[0107] By way of example, as described in relation to Figures 7A and 7B, the resin layer 260 undergoes a photolithography step to form patterns 270.
[0108] Fig. 16 is a partial and schematic cross-sectional view of a structure obtained after an etching step of the structure illustrated in Fig. 15 by creating openings 280 through the structure and opening into the silicon-germanium layer 160 and a step of removing the resin layer 260 from the upper face of the structure obtained.
[0109] These steps are identical to those described in relation to [Fig.8].
[0110] Fig. 17 is a partial, schematic cross-sectional view of a structure obtained at the result of a step of removing part of the silicon-germanium layer 160 from the structure illustrated in [Fig. 16] so as to create, between the substrate 100 and the silicon layer 200, a cavity 300.
[0111] This step is similar to that described in relation to Figures 9A, 9B and 9C except that, during this step, the silicon-germanium 160 layer is not completely removed.
[0112] Indeed, during this step, the silicon-germanium layer 160 is only partially removed so that the cavity 300 is bordered by a portion of the layer 160. This partial removal allows the structure to maintain mechanical stability and, more specifically, allows the layers 200, 220 and 240 to be held above the cavity 300. The unetched portions of the silicon-germanium layer 160 serve as mechanical support for the overlying layers 200, 220 and 240.
[0113] By way of example, in addition to being preserved on a peripheral part of the substrate 100, the layer 160 can also be preserved locally in the form of pillars supporting the lower face of the layer 220.
[0114] By way of example, the location of the openings 280 and the duration of the etching step define the location of the portions of layer 160 that remain after this etching step. Indeed, the portions of layer 160 that remain are those portions of layer 160 that are too far from an opening 28 to be etched during the etching step.
[0115] The [Fig. 18] is a partial and schematic cross-sectional view of a structure obtained after an etching step and followed by a step of filling the cavity 300 with a layer 320 identical to the layer 32 described in relation to the [Fig. 10].
[0116] These steps are identical to those described in relation to Figures 10 and 11.
[0117] [Fig. 19], [Fig.20], [Fig.21], [Fig.22], [Fig.23], [Fig.24] and [Fig.25] are cross-sectional views of structures obtained at the end of successive stages of a manufacturing process of a substrate, of the silicon-on-insulator type, according to a third embodiment.
[0118] The third embodiment described below differs from the second embodiment, described in relation to Figures 12 to 18, in that, in the third embodiment, the silicon germanium layer is formed on only a part of the upper surface of the substrate, the growth of the layer being guided by a dielectric layer.
[0119] Fig. 19 is a partial, schematic cross-sectional view of a starting structure comprising a substrate 1000 identical to the substrate 100 of the starting structure illustrated in Fig. 12, the structure further comprising a dielectric layer 3400 on a part of the upper face of the substrate 1000. By way of example, the dielectric layer 3400 is formed on a peripheral part of the substrate 1000. By way of example, the dielectric layer 3400 is formed in contact with the upper face of the substrate 1000.
[0120] Fig. 20 is a partial, schematic cross-sectional view of a structure obtained after a step of forming a silicon-germanium 1600 layer on the upper face of the starting structure illustrated in Fig. 19.
[0121] This step is similar to that described for the deposition of layer 160 in relation to [Fig. 13], except that, in [Fig. 20], layer 1600 is not formed across the entire plate. In fact, layer 1600 is formed only directly above the exposed faces of substrate 1000. Thus, the silicon-germanium layer 1600, formed by selective epitaxy with respect to silicon, has growth "guided" by the dielectric layer 3400. For example, layer 1600 is in contact, on its lower face, with the upper face of substrate 1000.
[0122] The [Fig.21] is a partial and schematic cross-sectional view of a structure obtained after a step of removing the dielectric layer 3400.
[0123] Figure 22 is a partial, schematic cross-sectional view of a structure obtained after a step of forming a silicon 2000 layer on the upper face of the structure illustrated in Figure 21. The 2000 layer is, for example, similar to the 200 layer illustrated in Figure 14.
[0124] This step is similar to that described in relation to [Fig. 14] except that, in [Fig.22], layer 2000 is formed on, and for example in contact with, layer 1600 in silicon-germanium and on, and for example in contact with, substrate 1000.
[0125] Fig. 23 is a partial, schematic cross-sectional view of a structure obtained after a successive formation step of an insulating layer 2200, another insulating layer 2400 and a resin layer 2600 on the upper face of the structure illustrated in Fig. 22, an etching step of the structure obtained by creating openings 2800 through the structure and into the silicon-germanium layer 1600 and a removal step of the resin layer 2600 from the upper face of the structure obtained.
[0126] Layers 2200, 2400 and 2600 are respectively identical to layers 220, 240 and 260 described in relation to [Fig. 15].
[0127] By way of example, as described in relation to [Fig.16], the resin layer 2600 undergoes a photolithography step to form patterns 2700.
[0128] These steps are identical to those described in relation to Figures 15 and 16.
[0129] Fig. 24 is a partial, schematic cross-sectional view of a structure obtained after a step of removing part of the silicon-germanium layer 1600 of the structure illustrated in Fig. 23 so as to create, between the substrate 1000 and the silicon layer 2000, a cavity 3000.
[0130] This step is similar to that described in relation to [Fig. 17] except that, in this step, the silicon-germanium 1600 layer is completely removed.
[0131] Fig. 25 is a partial and schematic cross-sectional view of a structure obtained after an etching step followed by a filling step of the cavity 3000 with a layer 3200 identical to the layer 320 described in relation to Fig. 18.
[0132] This step is identical to that described in relation to [Fig.18].
[0133] In the third embodiment, the interface between layer 2000 and substrate 1000 is aligned with the interface between layer 3200 and substrate 1000.
[0134] Fig. 26A, Fig. 26B, Fig. 26C and Fig. 26D are top views illustrating different variants of the realization of the structure of [Fig.7A].
[0135] More particularly, these figures illustrate other examples of patterns 27 formed in the resin layer 26 as a variant of what has been shown in [Fig.7A].
[0136] By way of example, as shown in [Fig.26A], the patterns 27 in the resin layer 26 can correspond to straight and parallel lines.
[0137] By way of example, as shown in [Fig.26B], the patterns 27 in the resin layer 26 can correspond to two combs whose fingers, solid or dotted, face each other without touching.
[0138] By way of example, as shown in [Fig.26C], the patterns 27 in the resin layer 21 can correspond to a double comb comprising a handle and two rows of fingers, solid or dotted, aligned on either side of the handle.
[0139] By way of example, as shown in [Fig.26D], the patterns 27 in the resin layer 21 can correspond to a grid of vertical and horizontal dotted lines.
[0140] More generally, other motifs 27 not shown can be provided by providing that they do not mechanically isolate a portion of the resin layer 26. Indeed, the layer 26 must, after the completion of the pattern formation step, maintain mechanical cohesion so that all portions of the layer 26 are bonded to each other.
[0141] An advantage of the present embodiment is that it allows the formation, in and on the same substrate, of one or more portions of SOI type and one or more portions of silicon substrate type.
[0142] Another advantage of the present embodiment is that it allows the formation of an SOI type substrate with a predefined insulation thickness.
[0143] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to the person of the trade. In particular, although an embodiment has been described in which the silicon-germanium layer 16, 1600 is completely removed from the cavity 30, 3000, a variant can be foreseen in which the silicon-germanium layer is intentionally retained in some parts of the cavity 30, 3000.
[0144] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. A method for manufacturing a silicon-on-insulator substrate comprising the successive steps of: a) forming a silicon-germanium layer (16; 160; 1600) on an upper face of a silicon substrate (10; 100; 1000); b) forming a silicon layer (20; 200; 2000) on an upper face of the silicon-germanium layer (16; 160; 1600); c) forming at least one opening (28; 280; 2800), passing through the silicon layer (20; 200; 2000) and opening into the silicon-germanium layer (16; 160; 1600); d) selective removal of at least part of the silicon-germanium layer (16; 160; 1600) through the opening (28; 280; 2800) so as to create, between the silicon substrate (10; 100; 1000) and the silicon layer (20; 200; 2000), a cavity (30; 300; 3000); and e) filling of the cavity (30; 300; 3000), through the opening (28; 280; 2800), with an insulating material (32; 320; 3200).
2. A method according to claim 1, wherein, at the end of step e), the cavity (30; 300; 3000) is completely filled by the insulating material (32; 320; 3200).
3. A method according to claim 1, wherein, at the end of step e), the cavity (30; 300; 3000) is partially filled by the insulating material (32; 320; 3200).
4. A method according to any one of claims 1 to 3, wherein the germanium silicon layer (16; 160; 1600) is doped.
5. A method according to any one of claims 1 to 4, wherein, in step a), the silicon-germanium (16; 160; 1600) layer is formed by epitaxy.
6. A method according to any one of claims 1 to 5, wherein in step b), the silicon layer (20; 200; 2000) is formed by epitaxy.
7. A method according to any one of claims 1 to 6, wherein, during the filling of the cavity (30; 300; 3000) in step e), at least one opening (28; 280; 2800) through the silicon layer (20; 200; 2000) is further filled with the insulating material (32; 320; 3200).
8. A method according to any one of claims 1 to 7, comprising, before step a), a localized removal step of a portion of the thickness of the silicon substrate (10), and in which, in step a), the silicon-germanium layer (16) is formed only in a cavity formed by said localized removal of a portion of the thickness of the silicon substrate (10).
9. A method according to claim 8, wherein in step d), the silicon-germanium layer (16) is fully or partially removed.
10. A method according to claim 8 or 9, comprising, between steps a) and b), a step of forming a silicon encapsulation layer (18) on the upper face of the silicon-germanium layer (16).
11. A method according to any one of claims 1 to 7, wherein, in step a), the silicon-germanium layer (160) is formed over the entire surface of the silicon substrate (100).
12. A method according to claim 11, wherein, in step b), the silicon layer (200) is formed over the entire surface of the silicon-germanium layer (160) and is formed in contact with it.
13. A method according to any one of claims 1 to 12, comprising, before step a), a step of forming a dielectric layer (3400) on a part of the substrate (1000), the silicon-germanium layer (16) is formed only outside the face of the dielectric layer (3400).
14. Method of manufacturing an electronic chip in and on a silicon-on-insulator type substrate obtained according to any one of claims 1 to 13, comprising a step of forming a transistor in and on the silicon layer (20; 200; 2000).
15. Silicon-on-insulator substrate comprising, in a first region (a): a layer of insulating material (32; 320; 3200) on an upper face of a silicon substrate (10; 100; 1000); and a silicon layer (20; 200; 2000) on an upper face of the layer of insulating material (32; 320; 3200), the silicon layer (20; 200; 2000) being traversed by at least one opening (28; 280; 2800).
16. Substrate according to claim 15, wherein said at least one opening (28; 280; 2800) through the silicon layer (20; 200; 2000) is filled by said insulating material (32; 320; 3200).
17. Substrate according to claim 15 or 16, wherein, in at least a second region (b), the silicon layer (20; 2000) rests directly on and in contact with the silicon substrate (10; 1000).
18. Substrate according to claim 17, wherein the lower face of the silicon layer (2000), in the second region (b), is aligned with the lower face of the layer in the insulating material (3200), in the first region (a).
19. Substrate according to claim 15 or 16, wherein, in at least a second region (b), the silicon layer (200) is separated from the silicon substrate (100) by a silicon-germanium layer (160).