Inverting memory device, electronic circuit, programming method and associated reading method
A memory device with ferroelectric and field-effect transistors and impedance reduces current consumption for logical operations in memory, overcoming the von Neumann bottleneck and high power usage in PIM systems.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Filing Date
- 2024-12-24
- Publication Date
- 2026-06-26
AI Technical Summary
Conventional computing systems face a von Neumann bottleneck due to significant data transfer between computing units and storage units, which is mitigated by performing logical operations directly in memory (PIM), but this approach involves high current consumption.
A memory device comprising a ferroelectric field-effect transistor and a field-effect transistor, along with an impedance, to perform logical inversion operations with reduced current consumption.
Enables logical operations in memory with limited current consumption, addressing the high power demands of stateful logic in PIM systems.
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Abstract
Description
Title of the invention: Inverting memory device, associated electronic circuit, programming method and reading method
[0001] The present invention relates to a memory device.
[0002] The invention also relates to an electronic circuit comprising a plurality of such memory devices; as well as a method for programming such a memory device and a method for reading such a memory device.
[0003] The invention relates to the field of electronics, and in particular to microelectronics.
[0004] Conventionally, a computing unit, such as a processor (for example, a CPU – Central Processing Unit), and a storage unit, such as memory, are physically separated and connected via a data bus. This implies a significant transfer of data over this bus between the computing unit, which performs the computational operations, and the storage unit, which stores the operands and then the results of the computational operations. The bandwidth of the data bus then often becomes a limiting factor, also known as the von Neumann bottleneck.
[0005] To mitigate this limiting factor, it is known to perform logical operations directly in memory, this technological field also being called PIM (from the English Processing In Memory).
[0006] A subdomain of the PIM domain is stateful logic, which consists of performing logical operations directly on memory locations without needing to read and process the information stored there. The logical operation is performed naturally and automatically depending on how the memory locations are connected to each other.
[0007] However, this technological sub-domain uses resistive components, and therefore involves a significant current consumption.
[0008] The aim of the invention is therefore to propose a memory device enabling a logical operation to be performed, while having a more limited current consumption.
[0009] To this end, the invention relates to a memory device comprising:
[0010] - a primary transistor comprising a primary gate electrode and first and second primary conduction electrodes;
[0011] - a secondary transistor comprising a secondary gate electrode and first and second secondary conduction electrodes; the secondary electrode the gate being connected to the second primary conduction electrode of the primary transistor; and
[0012] - an impedance connected to the second primary conduction electrode and to the secondary grid electrode;
[0013] the primary transistor being a ferroelectric field-effect transistor and the secondary transistor being a field-effect transistor.
[0014] The memory device according to the invention then makes it possible to perform a logical inversion operation directly in the memory, the primary transistor serving to store the value to be inverted, and the secondary transistor then to perform the conversion to carry out the inversion; while having a low current consumption, the primary transistor being a ferroelectric field-effect transistor and the secondary transistor being a field-effect transistor.
[0015] A person skilled in the art will also observe that the impedance does not generate a significant current consumption, since it is traversed by a current only in the reading phase.
[0016] According to other advantageous aspects of the invention, the memory device comprises one or more of the following features, taken individually or in all technically possible combinations:
[0017] - the impedance has a value equal to the resistance of the primary transistor when the primary transistor is in a non-conducting state;
[0018] - the primary transistor is chosen from the group consisting of: a transistor with an effect of a ferroelectric gate oxide field, and a field-effect transistor with a ferroelectric capacitance connected to the gate electrode; and
[0019] - the secondary transistor is chosen from the group consisting of: a transistor with ferroelectric gate oxide field effect, a field effect transistor with ferroelectric capacitance connected to the gate electrode, and a field effect transistor.
[0020] The invention also relates to an electronic circuit comprising a plurality of memory devices, a device for programming the memory devices, a device for reading the memory devices, each memory device being as defined above.
[0021] According to other advantageous aspects of the invention, the electronic circuit comprises one or more of the following features, taken individually or in all technically possible combinations:
[0022] - the circuit comprises word lines, source line pairs and pairs of bit lines, and each memory device is connected to a respective word line, a respective pair of source lines, and a respective pair of bit lines;
[0023] - the circuit includes word lines, source lines and bit lines; The primary transistor of each memory device is connected to a respective word line, source line, and bit line; and the secondary transistor and impedance are integrated into the read device; and
[0024] - the electronic circuit comprises a substrate, a set of near-level(s) of the substrate, called front end, for the connection of electronic component(s), and a set of level(s) distant from the substrate, called back end;
[0025] the primary transistor and the secondary transistor of each memory device being preferably included in the front end, the impedance of each memory device then being included in the back end; or
[0026] the primary transistor and the impedance of each memory device being preferably included in the back end, the secondary transistor of each memory device then being included in the front end.
[0027] The invention also relates to a method of programming a memory device as defined above, comprising a programming phase during which an input potential is applied to the primary gate electrode.
[0028] According to other advantageous aspects of the invention, the programming method comprises one or more of the following features, taken individually or in all technically possible combinations:
[0029] - during the programming phase, the first primary conduction electrode and the secondary conduction electrodes are connected to an electrical ground, and the second primary conduction electrode and the secondary grid electrode are connected to the electrical ground via the impedance;
[0030] - during the programming phase, the primary transistor is biased to a low level if the input potential is greater than a programming potential, and at a high level if the input potential is less than the opposite of the programming potential.
[0031] The invention also relates to a method of reading a memory device as defined above, the memory device being configured to perform an inversion of a value previously written in the primary transistor via a programming method as defined above, the reading method comprising a reading phase during which the primary transistor is in a non-biased state and the secondary transistor is in a biased state, a result of the inversion corresponding to a current value through the secondary transistor.
[0032] According to other advantageous aspects of the invention, the reading method comprises one or more of the following features, taken individually or in all technically possible combinations:
[0033] - for the non-polarized state of the primary transistor, the primary gate electrode and the The first primary conduction electrode is connected to an electrical ground, and for the biased state of the secondary transistor, a zero potential is applied to the first secondary conduction electrode, a read potential of the secondary transistor is applied to the second secondary conduction electrode, and during the read phase, the end of the impedance connected to the second primary conduction electrode receives a potential resulting from the prior programming of the primary transistor, and a potential equal to twice the threshold potential is applied to the other end of the impedance;
[0034] - the result of the inversion is a binary value determined via the comparison of the current value through the secondary transistor with a predefined current threshold;
[0035] the result of the inversion being preferably equal to 1 if said current value is greater than the predefined current threshold, and to 0 otherwise;
[0036] - the value to be inverted, written in the primary transistor during the phase of programming, corresponds to a level of primary transistor biasing resulting from the application of the input potential to the primary gate electrode;
[0037] the value to be reversed being preferably equal to 1 if the bias of the primary transistor is at a low level, and to 0 if said bias is at a high level;
[0038] - if the primary transistor was biased to a low level during its programming If the primary transistor was biased to a high level during its prior programming, then the secondary transistor is not conducting during the reading phase, and the result of the inversion is equal to 0; and if the primary transistor was biased to a high level during its prior programming, then the secondary transistor is conducting during the reading phase, and the result of the inversion is equal to 1.
[0039] These features and advantages of the invention will become clearer upon reading the following description, given solely by way of non-limiting example, and made with reference to the accompanying drawings, in which:
[0040] [Fig-1] [Fig.1] is a schematic representation of an electronic circuit according to the invention, comprising blocks of memory devices, as well as a programming device and a reading device, connected to each of the blocks for programming, and respectively reading, said memory devices;
[0041] [Fig.2] [Fig.2] is a schematic representation of a respective memory device, according to a first example of an embodiment; and
[0042] [Fig.3] [Fig.3] is a view analogous to that of [Fig.2], according to a second embodiment.
[0043] In [Fig.1], an electronic circuit 10 comprises one or more blocks 12 each having several memory devices 14, a programming device 16 and a reading device 18, the programming device 16 and respectively the reading device 18 being connected to each of the blocks 12 of memory device 14.
[0044] A person skilled in the art will observe that the number of block(s) 12 included in the electronic circuit 10 is variable, and typically depends on the amount of calculation operations to be performed per unit of time.
[0045] Each block 12 comprises a plurality of memory devices 14, arranged preferably in the form of a two-dimensional matrix, with the memory devices 14 then distributed according to rows and columns.
[0046] Each block 12 also includes WL word lines, BL bit lines, and SL source lines. The SL source lines and BL bit lines are advantageously parallel to each other; and the WL word lines are parallel to each other and perpendicular to the SL source and BL bit lines.
[0047] In the preceding notations, a word line is referenced as WL (from the English Word Line); bit lines are referenced with the abbreviation BL (from the English Bit Line) and source lines are referenced with the abbreviation SL (from the English Source Line).
[0048] The number of memory devices 14 within each respective block 12 is variable, and also typically depends on the amount of computational operations to be performed per unit of time, as well as on the architecture chosen for the electronic circuit 10, in particular the number of block(s) 12 included in the electronic circuit 10.
[0049] In the examples in Figures 2 and 3, the memory device 14 is connected to a respective word line WL; to a respective pair of source lines SL1, SL2, namely a first source line SL1 and a second source line SL2; and to a respective pair of bit lines BL1, BL2, namely a first bit line BL1 and a second bit line BL2.
[0050] In general, each memory device 14 is connected to a respective word line WLi, to a respective pair of source lines SLj, SLk, and to a respective pair of bit lines BLj, BLk; where i, j and k are integer indices, the indices j being for example even and the indices k odd.
[0051] Each memory device 14 in the same row of the matrix shares the same word line WL, so that the word lines WL can also be indexed with the index i. Thus, the first word line, that is to say the one which links the memory devices 14 of the first row, can be referenced WLI.
[0052] The memory devices 14 in the same column share the same pair of bit lines BLj, BLk and the same pair of source lines SLj, SLk. This pair of lines can therefore also be indexed with the indices j and k.
[0053] The memory devices 14 of the same row are then selectable by a word line WL, and the memory devices 14 of the same column are linked to a pair of bit lines BLj, BLk and to a pair of source lines SLj, SLk.
[0054] Alternatively, the primary transistor 20 of each memory device 14 is connected to a respective WL word line, a respective SL1 source line, and a respective bit line BL1, while the secondary transistor 25, the impedance 30 and the associated bit lines BL2 and source SL2 are integrated into the reading device 18. According to this variant, the corresponding primary transistor 20 and secondary transistor 25 are connected together by a bit line.
[0055] According to this variant, only the primary transistors 20 of the memory devices 14 are then integrated within each respective block 12.
[0056] In addition, the electronic circuit 10 comprises a substrate, a set of level(s) close to the substrate, called the front end, for connecting electronic component(s), and a set of level(s) far from the substrate, called the back end, not shown. The front end is also denoted FEOL (from the English Front End OfEine), and the back end is also denoted BEOL (from the English Back End OfEine).
[0057] According to a first example of arrangement, the primary transistor 20 and the secondary transistor 25 of each memory device 14 are included in the front end, and the impedance 30 of each memory device 14 is then included in the back end.
[0058] According to a second example of arrangement, the primary transistor 20 and the impedance 30 of each memory device 14 are included in the back end, and the secondary transistor 25 of each memory device 14 is then included in the front end.
[0059] According to a third arrangement example, the primary transistor 20 and the impedance 30 of each memory device 14 are included in the front end, and the secondary transistor 25 of each memory device 14 is then included in the back end. According to this arrangement example, the secondary transistor 25 is advantageously arranged with its gate electrode, hereinafter referred to as the secondary gate electrode 26, in a back-gate configuration.
[0060] A person skilled in the art will observe that the primary transistor 20 and the secondary transistor 25 of each memory device 14 are preferentially arranged on two different levels, namely one in the front end and the other in the back end, which then allows a gain in density of memory devices 14 per surface.
[0061] Each memory device 14 comprises a primary transistor 20 having a primary gate electrode 21 and first 22 and second 23 primary conduction electrodes. The first 22 and second 23 primary conduction electrodes are typically source and drain electrodes. In the examples in Figures 2 and 3, the first primary conduction electrode 22 is a source electrode, with an associated voltage Vsl, applied via the first source line SL1; and the second primary conduction electrode 23 is a drain electrode, with an associated voltage Vdl, applied via the first bit line BL1.
[0062] Each memory device 14 comprises a secondary transistor 25 having a secondary gate electrode 26 and first 27 and second 28 secondary conduction electrodes. The secondary gate electrode 26 is connected to the The second primary conduction electrode 23 of the primary transistor 20. The first 27 and second 28 secondary conduction electrodes are typically source and drain electrodes. In the examples in Figures 2 and 3, the first secondary conduction electrode 27 is a source electrode, with an associated voltage Vs2, applied via the second source line SL2; and the second secondary conduction electrode 28 is a drain electrode, with an associated voltage Vd2, applied via the second bit line BL2.
[0063] Each memory device 14 includes an impedance 30 connected to the second primary conduction electrode 23 and to the secondary grid electrode 26.
[0064] The programming device 16 is configured to program each memory device 14, implementing the programming method according to the invention for each memory device 14 to be programmed, the programming method being described in more detail later.
[0065] The programming device 16 is advantageously configured to program several memory devices 14 at once, and preferably simultaneously, as long as this does not require applying two distinct voltage values at the same time on the same word line WL, or on the same bit line BL, or on the same source line SL.
[0066] The reading device 18 is configured to read each memory device 14, implementing the reading method according to the invention for each memory device 14 to be read, the reading method being described in more detail later.
[0067] The reading device 18 is advantageously configured to read several memory devices 14 at once, and preferably simultaneously, as long as this does not require applying or reading two distinct voltage values at the same time on the same word line WL, or on the same bit line BL, or on the same source line SL.
[0068] The primary transistor 20 is a ferroelectric field-effect transistor. In the examples in Figures 2 and 3, the primary transistor 20 is a ferroelectric gate oxide field-effect transistor, or FeFET (Ferroelectric Field-Effect Transistor). Alternatively, the primary transistor 20 is a field-effect transistor with a ferroelectric capacitance connected to the gate electrode, or FeMFET (Ferroelectric Metal Field-Effect Transistor).
[0069] The primary transistor 20 has a primary threshold potential, denoted Vthl, corresponding to the potential difference Vgsl between its gate electrode and its source electrode, from which the primary transistor 20 is conducting.
[0070] The secondary transistor 25 is a field-effect transistor. In the example in [Fig. 2], the secondary transistor 25 is a ferroelectric gate oxide (FeFET) field-effect transistor, or a field-effect transistor with capacitance ferroelectric connected to the gate electrode or FeMFET. In the example of [Fig.3], the secondary transistor 25 is a field-effect transistor or FET (from the English Field-Effect Transistor).
[0071] The secondary transistor 25 has a secondary threshold potential, denoted Vth2, corresponding to the potential difference Vgs2 between its gate electrode and its source electrode, from which the secondary transistor 25 is conducting.
[0072] Impedance 30 is a resistance in the examples of Figures 2 and 3. Impedance 30 advantageously has a value equal to a resistance of the primary transistor 20 when the primary transistor 20 is in a non-conducting state.
[0073] The operation of the memory device 14 according to the invention will now be described, beginning with the programming process implemented by the programming device 16, and then continuing with the reading process implemented by the reading device 18.
[0074] The programming method includes a programming phase during which an input potential Vgl is applied to the primary gate electrode 21, in order to bias the primary transistor 20.
[0075] During the programming phase, the first primary conduction electrode 22 and the secondary conduction electrodes 27, 28 are connected to an electrical ground, not shown. The second primary conduction electrode 23 and the secondary grid electrode 26 are connected to electrical ground via the impedance 30. In other words, the voltages Vsl, Vs2, Vd2 applied respectively to the first primary conduction electrode 22 and the secondary conduction electrodes 27, 28 are each substantially zero. Similarly, the voltages Vdl, Vg2 applied respectively to the second primary conduction electrode 23 and the secondary grid electrode 26 are each substantially zero. In other words, Vsl < Vs2 < Vd2 < 0 and Vdl < Vg2 < 0.
[0076] During the programming phase, the primary transistor 20 is biased to a low level if the input potential Vgl is greater than a programming potential Vprog of the primary transistor 20. Conversely, the primary transistor 20 is biased to a high level if the input potential Vgl is less than the opposite -Vprog of said programming potential Vprog.
[0077] Thus, to store information in the memory device 14, the programming device 16 is configured to apply the input potential Vgl to the primary gate electrode 21 and to connect the other electrodes, namely the primary conduction electrodes 22, 23, the secondary conduction electrodes 27, 28, and the secondary gate electrode 26, to electrical ground, in order to bias the primary transistor 20. The applied input potential Vgl is a strong positive voltage, i.e., greater than the programming potential Vprog; or a strong negative voltage, that is to say less than the opposite -Vprog of the programming potential.
[0078] The information stored in the primary transistor 20 is then translated by a high threshold primary potential Vthl when the primary transistor 20 is biased to the high level with Vgl < -Vprog; and conversely by a low threshold primary potential Vthl when the primary transistor 20 is biased to the low level with Vgl > Vprog.
[0079] The method of reading the memory device 14 according to the invention, having as its purpose a logical inversion of a value previously written in the primary transistor 20 via the programming method according to the invention described above, will now be described.
[0080] The reading method includes a reading phase during which the primary gate electrode 21 of the primary transistor 20 is in a non-biased state and the effective biasing of the secondary gate electrode 26 of the secondary transistor 25 depends on the state stored in the primary transistor 20, the result of the inversion corresponding to a current value through the secondary transistor 25.
[0081] Thus, in order to read the memory device 14, and in particular to perform the logical inversion of the value, or information, previously stored in the primary transistor 20 by the programming device 16 during the programming phase, the reading device 18 is configured to put the primary gate electrode 21 of the primary transistor 20 in the non-biased state and to bias at the same time the voltages Vdl and Vd2, in order to read the value of current through the secondary transistor 25 and representing the result of the inversion.
[0082] For the unbiased state of the primary transistor 20, the primary gate electrode 21 and the first primary conduction electrode 22 are connected to electrical ground. In other words, to put the primary transistor 20 in the unbiased state, the readout device 18 is configured to connect the primary gate electrode 21 and the first primary conduction electrode 22 to electrical ground. Thus, the voltages Vgl, Vsl applied respectively to the primary gate electrode 21 and the first primary conduction electrode 22 are each substantially zero, i.e., Vgl ≤ Vsl ≤ 0.
[0083] For the biased state of the secondary transistor 25, a zero potential is applied to the first secondary conduction electrode 27, which is connected to ground, a read potential Vread of the secondary transistor 25 is applied to the second secondary conduction electrode 28, and during the read phase, the end of the impedance 30 connected to the second primary conduction electrode 23 receives a potential resulting from the prior programming of the primary transistor 20, and a potential equal to twice the secondary threshold potential Vth2 is applied to the other impedance end 30. The read potential Vread of the secondary transistor 25 is for example on the order of 100 mV.
[0084] In other words, to bias the secondary transistor 25 and read the value of the current through the secondary transistor 25 and representing the result of the inversion, the reading device 18 is configured to apply twice the secondary threshold potential Vth2 to the end of the impedance 30 which is connected to the first bit line BL1, i.e. Vdl ~ 2*Vth2; to apply the zero potential to the first secondary conduction electrode 27, i.e. Vs2 « 0; and to apply the reading potential Vread to the second secondary conduction electrode 28, i.e. Vd2 ~ Vread.
[0085] During this reading phase, the secondary gate electrode 26 receives the potential resulting from the prior programming of the primary transistor 20, via the second primary conduction electrode 23.
[0086] Thus, depending on the information previously stored in the primary transistor 20, the secondary transistor 25 will be either conducting or not. The result of the inversion is then a binary value determined by comparing the current value through the secondary transistor 25 with a predefined current threshold. The result of the inversion is, for example, equal to 1 if said current value is greater than the predefined current threshold, and to 0 otherwise.
[0087] Those skilled in the art will understand that the value to be inverted, written to the primary transistor 20 during the programming phase, corresponds to the bias level of the primary transistor 20 resulting from the programming phase. The value to be inverted is, for example, defined as 1 if the bias of the primary transistor 20 is at a low level, and consequently as 0 if said bias is at a high level.
[0088] Also, if the primary transistor 20 was biased low during its initial programming, corresponding to the stored value of 1, then the primary transistor 20 is conducting for a substantially zero voltage applied to its primary gate electrode 21, and the secondary transistor 25 is therefore not conducting, i.e., blocked, during this reading phase. Indeed, the voltage Vg2 is then equal to the voltage Vsl, itself substantially zero, i.e., Vsl ≈ Vg2 ≈ 0. The reading device 18 then does not measure any current through the secondary transistor 25, and the result of the inversion is 0. The stored value of 1 has therefore been inverted to the value 0.
[0089] Conversely, if the primary transistor 20 was biased high during its initial programming, corresponding to a stored value of 0, then the primary transistor 20 is not conducting, i.e., blocked, for a substantially zero voltage applied to its primary gate electrode 21, and the secondary transistor 25 is conducting during this read phase. Indeed, the voltage Vg2 is then equal to the voltage Vdl / 2 if the value of the impedance 30 is equal to the resistance of the primary transistor 20 in its non-conducting state, i.e., Vg2 ≈ Vd 1 / 2 ~ Vth2, and since Vsl ≈ Vgl ≈ 0 and Vs2 ≈ 0, Vd2 ≈ Vread, then the potential difference between the secondary gate electrode 26 and the first secondary conduction electrode 27 forming the source electrode, i.e., Vgs2, is equal to the secondary threshold potential Vth2 of the secondary transistor 25, i.e., Vgs2 = Vg2 - Vs2 ≈ Vth2 ≈ Vdl / 2, and it is therefore conducting. The reading device 18 then measures a current with a value exceeding the predefined current threshold through the secondary transistor 25, and the result of the inversion is equal to 1. The stored value of 0 has therefore been correctly inverted to the value 1.
[0090] A person skilled in the art will observe that the operation of the memory device 14 according to the invention is the same whether the secondary transistor 25 is a ferroelectric field-effect transistor, i.e. FeFET, according to the first embodiment of [Fig.2], or whether the secondary transistor 25 is a field-effect transistor, i.e. FET, according to the second embodiment of [Fig.3].
[0091] Thus, the memory device 14 according to the invention makes it possible to perform a logical operation, namely logical inversion, directly in the memory, i.e. an inversion in PIM, while having limited current consumption.
Claims
Demands
1. Memory device (14) comprising: - a primary transistor (20) having a primary gate electrode (21) and first (22) and second (23) primary conduction electrodes; - a secondary transistor (25) having a secondary gate electrode (26) and first (27) and second (28) secondary conduction electrodes; the secondary gate electrode (26) being connected to the second primary conduction electrode (23) of the primary transistor (20); and - an impedance (30) connected to the second primary conduction electrode (23) and to the secondary gate electrode (26); the primary transistor (20) being a ferroelectric field-effect transistor and the secondary transistor (25) being a field-effect transistor.
2. Memory device (14) according to claim 1, wherein the impedance (30) has a value equal to a resistance of the primary transistor (20) when the primary transistor (20) is in a non-conducting state.
3. Memory device (14) according to claim 1 or 2, wherein the primary transistor (20) is selected from the group consisting of: a field-effect transistor with a ferroelectric gate oxide, and a field-effect transistor with a ferroelectric capacitance connected to the gate electrode.
4. Memory device (14) according to any one of the preceding claims, wherein the secondary transistor (25) is selected from the group consisting of: a field-effect transistor with a ferroelectric gate oxide, a field-effect transistor with a ferroelectric capacitance connected to the gate electrode, and a field-effect transistor.
5. Electronic circuit (10) comprising a plurality of memory devices (14), a device (16) for programming the memory devices (14), a device (18) for reading the memory devices (14), each memory device (14) being according to any one of the preceding claims.
6. Electronic circuit (10) according to claim 5, wherein the circuit comprises word lines (WL), pairs of lines source (SL1, SL2) and bit line pairs (BL1, BL2), and each memory device (14) is connected to a respective word line (WL), a respective source line pair (SL1, SL2), and a respective bit line pair (BL1, BL2).
7. Electronic circuit (10) according to claim 5, wherein the circuit comprises word lines (WL), source lines (SL) and bit lines (BL); the primary transistor (20) of each memory device (14) is connected to a respective word line (WL), a respective source line (SL1), and a respective bit line (BL1); and the secondary transistor (25) and impedance (30) are integrated into the read device (18).
8. Electronic circuit (10) according to any one of claims 5 to 7, wherein the electronic circuit (10) comprises a substrate, a set of level(s) close to the substrate, called the front end, for the connection of electronic component(s), and a set of level(s) far from the substrate, called the back end; the primary transistor (20) and the secondary transistor (25) of each memory device (14) preferably being included in the front end, the impedance (30) of each memory device (14) then being included in the back end; or the primary transistor (20) and the impedance (30) of each memory device (14) preferably being included in the back end, the secondary transistor (25) of each memory device (14) then being included in the front end.
9. Method of programming a memory device (14) according to any one of claims 1 to 4, comprising a programming phase during which an input potential (Vgl) is applied to the primary grid electrode (21).
10. A programming method according to claim 9, wherein, during the programming phase, the first primary conduction electrode (22) and the secondary conduction electrodes (27, 28) are connected to an electrical ground, and the second primary conduction electrode (23) and the secondary grid electrode (26) are connected to the electrical ground via the impedance (30).
11. A programming method according to claim 10, wherein, during the programming phase, the primary transistor (20) is biased to a low level if the input potential (Vgl) is greater than a programming potential, and to a high level if the input potential (Vgl) is less than the opposite of the programming potential.
12. A method for reading a memory device (14) according to any one of claims 1 to 4, the memory device (14) being configured to perform an inversion of a value previously written in the primary transistor (20) via a programming method according to any one of claims 9 to 11, the reading method comprising a reading phase during which the primary transistor (20) is in a non-biased state and the secondary transistor (25) is in a biased state, a result of the inversion corresponding to a current value through the secondary transistor (25).
13. A reading method according to claim 12, wherein, for the non-biased state of the primary transistor (20), the primary gate electrode (21) and the first primary conduction electrode (22) are connected to an electrical ground, and for the biased state of the secondary transistor (25), a zero potential is applied to the first secondary conduction electrode (27), a reading potential of the secondary transistor (25) is applied to the second secondary conduction electrode (28), and during the reading phase, the end of the impedance (30) connected to the second primary conduction electrode (23) receives a potential resulting from the prior programming of the primary transistor (20), and a potential equal to twice the threshold potential is applied to the other end of the impedance (30).
14. A reading method according to claim 12 or 13, wherein the result of the inversion is a binary value determined via the comparison of the current value through the secondary transistor (25) with a predefined current threshold; the result of the inversion preferably being equal to 1 if said current value is greater than the predefined current threshold, and to 0 otherwise.
15. A reading method according to any one of claims 12 to 14, wherein the value to be reversed, written in the primary transistor (20) during the programming phase, corresponds to a level of a bias of the primary transistor (20) resulting from the application of the input potential (Vgl) to the primary gate electrode (21); the value to be reversed preferably being equal to 1 if the bias of the primary transistor (20) is at a low level, and to 0 if said bias is at a high level.
16. A reading method according to claim 15, wherein, if the primary transistor (20) was biased to a low level during its prior programming, then the secondary transistor (25) is not conducting during the reading phase, and the result of the inversion is equal to 0; and if the primary transistor (20) was biased to a high level during its prior programming, then the secondary transistor (25) is conducting during the reading phase, and the result of the inversion is equal to 1.