Isolation process within a microelectronic device

Abstract

Title: Isolation Method in a Microelectronic Device The invention relates to a microelectronic device comprising an isolation between a first region (1000a) and a second region (1000b). The device comprises a stack (1) including a semiconductor substrate (10), a buried oxide layer (20), and a thin film (30). The stack (1) comprises a first region (1000a) and a second region (1000b) separated by an isolation zone (1000). The insulation zone (1000) comprises an insulating spacer (200) extending over inner flanks (1a, 1b) of the stack (1), an epitaxial layer (300) extending between the inner flanks (1a, 1b) of the stack (1), an insulating separating layer (400) extending over the epitaxial layer (300), and an electrically conductive or insulating motif (500) extending over the separating layer (400). Figure for the abstract: Fig. 1H

Description

Title of the invention: Isolation method within a microelectronic device technical field

[0001] The present invention relates to the field of microelectronic devices, in particular transistors. It finds, for example, a particularly advantageous application in the field of integrated circuits. STATE OF THE ART

[0002] The realization of a set of microelectronic devices on the same wafer (more commonly referred to by the English term "wafer") is accompanied by electrical insulation problems related on the one hand to the appearance of parasitic diodes and on the other hand to the insulation between devices.

[0003] The first main problem therefore concerns parasitic diodes appearing in certain device architectures. It appears that when PMOS and NMOS are formed in n- and p-doped wells, respectively, parasitic diodes appear at the junction between wells with opposite doping levels. These parasitic diodes are particularly troublesome when they form at the junction between two horizontally juxtaposed wells with opposite doping levels. Indeed, in this case, the biasing range that can be applied to the devices is greatly reduced.

[0004] It is therefore necessary to implement shallow insulation to eliminate these horizontal parasitic diodes. It might seem feasible to achieve this insulation using a local oxidation process (commonly referred to as LOCOS, from the English "Local Oxidation of Silicon"). However, when local oxidation is implemented, an unwanted lateral extension of the oxidation, known as a "bird's beak," is systematically obtained, extending over at least twenty nanometers. This bird's beak creates unnecessary bulk: the use of a local oxidation technique therefore negatively impacts density. Furthermore, shallow insulation must be protected to prevent it from being completely consumed during the manufacturing process. It is therefore necessary to have insulation with small lateral dimensions so that a grid with a typical width of 20 nm can protect it. The lateral extension systematically generated by a local oxidation process is therefore incompatible.

[0005] The second main problem concerns electrical isolation between devices. Two main strategies exist today for achieving such isolation.

[0006] A first method consists of extending a positively biased gate between two PMOS transistors (or a negatively biased gate between two (NMOS transistors), which has the effect of repelling the majority carriers to opposite sides of the gate and isolating the two transistors. However, this technique is difficult to implement in wafer regions where NMOS and PMOS transistors are manufactured side by side. Indeed, since isolating NMOS and PMOS transistors requires opposite gate biases, it is not possible to use a common gate to isolate the two types of transistors. Therefore, two separate gates must be fabricated in line with each other, and separate contacts must be used to bias them differently, which increases the wafer size and reduces density.

[0007] A second method consists of isolating the transistors by forming a deep trench (commonly referred to as STI, from the English "Shallow Trench Isolation") between them. However, due to the required depth and the current state of technology, STI cannot have a high aspect ratio, which reduces space on the wafer and also negatively impacts density.

[0008] It is possible to combine these two methods, for example by isolating PMOS transistors using a positively biased gate and by isolating NMOS transistors with an STI. In this solution, the biased gate and the STI are aligned. However, this approach would only be advantageous if the STI could have a width as small as the biased gate. Yet, the gate typically has a width of 20 nm, a dimension that is not achievable for the STI due to its depth and current techniques, particularly filling techniques. Another way to achieve this isolation is by local oxidation. However, as described previously, local oxidation leads to a bird's beak extending laterally over approximately 20 nanometers. It is therefore impossible with current methods to produce an STI with a width comparable to that of the biased gate.The combination of the two methods is therefore not satisfactory, since one remains constrained by the dimensional limitations of the STI or local oxidation methods.

[0009] An objective of the present invention is therefore to solve at least one of the problems presented above, and preferably to solve both simultaneously. SUMMARY

[0010] To achieve this objective, a first object of the invention relates to a microelectronic device comprising an insulation between a first region and a second region, the device comprising a stacking arrangement along a so-called stacking direction: a. a substrate based on a first semiconductor material, called a semiconductor substrate, b. a layer based on an electrically insulating material, called a buried oxide layer, c. a layer based on a second semiconductor material, preferably identical to the first semiconductor material, called a thin film.

[0011] The stack comprises a first region and a second region separated by an insulation zone extending between internal flanks of the stack, the insulation zone passing through the thin layer and the buried oxide layer and opening onto the semiconductor substrate.

[0012] The insulation zone advantageously comprises: a. a spacer extending over the inner sides of the stack, the spacer being based on an electrically insulating material, b. a layer based on the first semiconductor material, called the epitaxial layer, extending between the inner flanks of the stack and being in contact with the substrate, c. a layer based on an electrically insulating material, called the separating layer, extending over the epitaxial layer, d. an electrically conductive or insulating pattern extending over the separating layer.

[0013] A second object of the invention relates to a method for manufacturing an isolation zone between a first region and a second region of a microelectronic device, the method comprising the following steps: a. provide a stacking comprising at least, in a so-called stacking direction: i. a substrate based on a first semiconductor material, called a semiconductor substrate, ii. a layer based on an electrically insulating material, known as a buried oxide layer, iii. a layer based on a second semiconductor material, preferably identical to the first semiconductor material, called a thin film, b. form an opening in the stack, the opening passing through the thin layer and the buried oxide layer and opening onto the semiconductor substrate, the opening being defined by internal flanks of the stack, the opening separating the first region from the second region of the stack, c. form a spacer extending from the inner sides of the stack, the spacer being based on an electrically insulating material, d. to grow by epitaxy from the semiconductor substrate a layer called the epitaxial layer, filling at least partially the opening, e. to form on the epitaxial layer a layer based on an electrically insulating material, called the separating layer, f. to form an electrically insulating pattern or an electrically conductive pattern intended to form a grid pattern on the separating layer.

[0014] Both the manufacturing process and the device according to the invention have numerous advantages over the prior art.

[0015] First, the method and device according to the invention make it possible to achieve double insulation: a. Initial isolation between the doped (N or P) well in which the assembly is typically formed and the active regions of the devices, achieved through a small isolation zone. The present invention makes it possible to achieve this small isolation. Furthermore, the small size of the isolation zone allows for an architecture in which the P-doped well is enclosed within the N-doped well (a well commonly referred to as a "deep N-well") (or vice versa). In this architecture, the N- and P-doped wells are not juxtaposed in the plane of the substrate but are stacked vertically on top of each other. This eliminates the horizontal parasitic diodes, which are the most detrimental to operation, and thus resolves the first problem raised in the introduction. b. A second isolation thanks to the presence of the spacer between two devices formed at the level of the first and second regions (typically two transistors), which solves the second problem raised in the introduction.

[0016] Both problems are therefore solved by manufacturing a spacer which, in the process according to the present invention, is cleverly made in order to limit the complexity and cost of the process.

[0017] Another advantage of the invention is that it is possible to use a single photolithography level to define isolation zones between two devices, in the middle of the active zone, and isolation zones separating devices and the substrate socket (bulk socket), at the periphery of the active zone. Furthermore, the spacer used for isolation at the periphery of the active zone does not affect the operation of the hybrid zones, that is, the zones where the buried oxide layer has been removed, typically found at the periphery of the substrate.

[0018] The process according to the invention also has the advantage of not requiring any mechano-chemical polishing step, a costly process that impairs efficiency and often alters the quality of the devices.

[0019] In general, the process according to the invention involves inexpensive steps (etching, oxidation).

[0020] Furthermore, the process according to the invention does not use a local oxidation step like some prior art processes. This makes it possible to avoid the bird's beak phenomenon described in the introduction.

[0021] Furthermore, the dimensions of the spacer and the epitaxial layer are defined not by a local oxidation step as in the prior art, but by an etching step used to define the opening in the stack. This allows for better control of these dimensions. Consequently, it is possible to reduce the margins required for isolation between devices and thus increase the density of devices manufactured from the same stack.

[0022] Furthermore, the insulation as achieved according to the present invention can be carried out before or after the formation of the active zones of the devices located on either side of the insulation zone. This makes the process more adaptable.

[0023] The present invention thus makes it possible to solve simultaneously the two problems raised in the introduction, and also presents many advantages compared to the prior art, making the solution easily integrable into current manufacturing processes and allowing both better density and better manufacturing yield. BRIEF DESCRIPTION OF THE FIGURES

[0024] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0025] [Fig.1A] [Fig.1B] [Fig.1C] [Fig.1D] [Fig.1E] [Fig.1F] [Fig.1G] [Fig.1H] Figures IA to 1H illustrate one embodiment of the process according to the invention.

[0026] [Fig. 2A][Fig. 2B][Fig. 2C][Fig. 2D][Fig. 2E][Fig. 2F] Figures 2A to 2E are top views of different transistor assemblies fabricated on the same wafer. These figures illustrate, in particular, different arrangements of the electrically conductive patterns connecting the transistors. [Fig. 2F] is a figure illustrating how the present invention can be integrated into hybrid areas to achieve electrical isolation between devices and the substrate socket.

[0027] [Fig.3A] [Fig.3B] [Fig.3C] [Fig.3D] Figures 3A to 3D represent the value of the electric field within different devices, including the device according to the present invention.

[0028] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0029] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0030] According to a preferred example, the separating layer extends from a first portion of the spacer covering a first internal flank of the stack to a second portion of the spacer covering a second internal flank of the stack facing the first internal flank.

[0031] According to a preferred example, the separating layer completely covers the epitaxial layer.

[0032] According to a preferred example, the spacer has a thickness e2Oo measured along a direction perpendicular to the inner sides of the stack, with e2Oo greater than or equal to 4 nm and / or less than or equal to 10 nm, preferably less than or equal to 6 nm.

[0033] According to a preferred embodiment, the spacer is buried in the stack, and preferably does not extend beyond an upper face of the thin layer opposite the buried oxide layer, for example is flush with the upper face of the thin layer.

[0034] According to a preferred embodiment, the spacer passes through the thin film and the buried oxide layer and preferably extends to an upper face of the semiconductor substrate facing the buried oxide layer.

[0035] According to a preferred example, the separating layer has a thickness e4Oo, measured along the stacking direction, greater than or equal to 3 nm.

[0036] According to a preferred example, the epitaxial layer exhibits P-type or N-type doping.

[0037] According to one example, the device further comprises a first transistor and a second transistor, the first transistor and the second transistor being located respectively in the first and second regions, the thin layer forming a first channel of the first transistor and a second channel of the second transistor.

[0038] According to a preferred embodiment of the process according to the second object of the invention, at the end of epitaxial growth, the epitaxial layer extends, along the stacking direction, at least to half the height of the buried oxide layer, preferably extending at least to an upper face of the layer buried oxide opposite the substrate, preferably extends at least to an upper face of the thin layer opposite the buried oxide layer, preferably exceeds the thin layer.

[0039] Another object of the invention relates to a method of using the device according to the first object of the invention, in which the motif is electrically conductive, the method further comprising a step of polarizing said motif.

[0040] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0041] A layer may also be composed of several sub-layers of the same material or of different materials.

[0042] A substrate, layer, or device "based" on a material M means a substrate, layer, or device comprising only that material M or that material M and possibly other materials, for example alloying elements, impurities, or dopant elements.

[0043] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. The selectivity is the ratio between the etching speed of material A and the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0044] A coordinate system, preferably orthonormal, comprising the X, Y, Z axes is shown in [Fig. 1A]. This coordinate system can be applied by extension to the other figures. The Z direction may be designated as the "stacking direction".

[0045] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the longitudinal plane XY. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along Z when it extends mainly along the longitudinal plane XY, and a projecting element, for example an insulation trench, has a height along Z. The relative terms "on," "under," "above," "below," and "underlying" preferentially refer to positions measured along the Z direction.

[0046] The terms "approximately", "about", "in the order of" mean "to within 10%, preferably to within 5%".

[0047] An example of an embodiment of the process according to the invention will now be described with reference to figures IA to 1H.

[0048] [Fig.1A] illustrates the provision of a stack 1. This stack comprises, stacked along the stacking direction Z: a ​​semiconductor substrate 10, a buried oxide layer 20 and a thin film 30. It may also include a dielectric layer 40 and / or a protective layer 50 overlying the thin film 30.

[0049] The substrate 10 is based on a first semiconductor material, typically silicon. It has a top face 11 extending mainly in an XY plane that can be designated the transverse XY plane. This plane is defined by a first direction X and a second direction Y. The longitudinal plane and the stacking direction Z are typically perpendicular.

[0050] The buried oxide layer 20 is based on an electrically insulating material such as SiO2. It has a thickness e20 measured along the stacking direction Z. e20 is, for example, greater than or equal to 10 nm and / or less than or equal to 145 nm, preferably greater than or equal to 20 nm and / or less than or equal to 30 nm. The buried oxide layer 20 has a lower face 22 facing the substrate 10 and an upper face 21 opposite its lower face 22 and opposite the substrate 10.

[0051] The thin film 30 is based on a second semiconductor material, for example, silicon. The thin film 30 may also be referred to as the active layer 30. It has a thickness e30 measured along the stacking direction Z. e30 is, for example, greater than or equal to 3 nm and / or less than or equal to 80 nm, preferably greater than or equal to 5 nm and / or less than or equal to 15 nm. The thin film 30 has a lower face 32 facing the substrate 10 and the buried oxide layer 20, and an upper face 31 opposite its lower face 32 and opposite the buried oxide layer 20.

[0052] The dielectric layer 40 is based on an electrically insulating material such as SiO2. It has a thickness e40 measured along the stacking direction Z. e40 is for example greater than or equal to Inm and / or less than or equal to lOnm, preferably greater than or equal to 2nm and / or less than or equal to 5nm.

[0053] The protective layer 50 is for example based on SiN.

[0054] The stack 1 has a top face 1', corresponding for example in the figures to the top face of the protective layer 50. This extends mainly in the transverse plane XY.

[0055] As illustrated in [Fig. IB], an opening 100 is then formed in the stack 1. The opening 100 extends from the upper face 1' of the stack 1. It opens onto the substrate 1, for example, onto its upper face. 11. The opening 100 thus completely passes through the protective layer 50, the dielectric layer 40 (if these are present), the thin layer 30 and the buried oxide layer 20.

[0056] The aperture 100 can be formed by conventional photolithography and engraving steps not illustrated.

[0057] Transversely, the aperture 100 extends within the stack 1 between internal flanks la, 1b of the latter defined during the engraving of the aperture 100. The internal flanks include, in particular, a first internal flank la and a second internal flank 1b facing each other. The aperture 100 has a width li Oo measured in the transverse XY plane, for example in the figures along the first X direction. h Oo is typically greater than or equal to 5 nm and / or less than or equal to 100 nm, preferably greater than or equal to 100 nm and / or less than or equal to 20 nm.

[0058] The opening 100 separates two regions of the stack 1: a first region bearing the reference 1000a on the [Fig.1B] and a second region bearing the reference 1000b.

[0059] As illustrated in [Fig.1C], a spacer 200 is then formed in the opening 100, against the inner sides la, 1b of the stack 1. The spacer 200 includes in particular a first portion 200a extending from the first inner side la of the stack and a second portion 200b extending from the second inner side 1b of the stack 1.

[0060] The spacer 200 is based on an electrically insulating material, such as SiO2. It can be formed by an atomic layer deposition process (commonly referred to as ALD, from the English "Atomic Layer Deposition"), which has the advantage of allowing the formation of a very conformal layer.

[0061] The spacer 200 has a width l2oo measured in each of its portions 200a, 200b. l2oo is measured perpendicular to the inner sides la, 1b of the stack. l2oo is typically greater than or equal to 1 nm and / or less than or equal to 20 nm, preferably greater than or equal to 3 nm and / or less than or equal to 6 nm.

[0062] Next, an epitaxial growth step is carried out in the aperture 100, from the substrate 10. This step allows the formation of a semiconductor layer called the epitaxial layer 300. The epitaxial layer 300 extends in the aperture 100 from the first portion 200a of the spacer 200 covering the first inner flank 1a of the stack 1 to the second portion 200b of the spacer 200 covering the second inner flank 2b of the stack 1.

[0063] The epitaxial layer 300 has a thickness e300 measured along the stacking direction Z. e300 is, for example, greater than or equal to 15 nm and / or less than or equal to 240 nm, preferably greater than or equal to 25 nm and / or less than or equal to 40 nm. Advantageously, the epitaxial layer 300 is typically raw so that to ensure that it extends at least as far as the thin layer 30 along the stacking direction Z, and preferably that it extends beyond the thin layer 30 along the stacking direction Z, as illustrated in [Fig. 1D]. Thus, preferably, e3oo > e2o + e30. In other words, the epitaxial layer 300 preferably crosses the buried oxide layer 20 and the thin layer 30. One advantage of growing the epitaxial layer 300 beyond the thin layer 30 is the ability to form an oxide on this epitaxial layer (see the next step of forming a separating layer 400) selectively at other surfaces present, for example by thermal or plasma oxidation.

[0064] After the formation of the epitaxial layer 300, it is possible to proceed with the formation of a separating layer 400 above the epitaxial layer 300 ([Fig. 1E]). The separating layer 400 is based on an electrically insulating material, for example SiO2. The separating layer 400 forms an electrically insulating unit with the first and second portions of the spacer 200a, 200b. These elements electrically insulate the epitaxial layer from the thin film 30. The formation of the separating layer 400 is typically accompanied by partial oxidation of the epitaxial layer 300 from its upper surface. This also explains the advantage of growing the epitaxial layer 300 beyond the dimension along the Z direction that we want to give it (see [Fig.lD]), and in particular beyond the thin layer 30: its thickness will be reduced due to oxidation during the formation of the overlying separating layer 400.

[0065] The separating layer 400 has a thickness e400 measured along the stacking direction Z. e4Oo is for example greater than or equal to 2 nm and / or less than or equal to 10 nm, preferably less than or equal to 5 nm.

[0066] As illustrated in [Fig.1F], it is then possible to remove the protective layer 50. The semiconductor substrate 10 is also preferably implanted. A doped well is thus formed.

[0067] The dielectric layer 40 can then be removed ([Fig.lG]), thus updating the thin layer 30, for example for the formation of microelectronic devices.

[0068] The separating layer 400 can also be formed between the removal of the protective layer 50 ([Fig.1F]) and the removal of the dielectric layer 40 ([Fig.1G]), or even after the removal of the dielectric layer 40. The separating layer 400 can, for example, be formed during a subsequent step of forming a grid 500 on the epitaxial layer 300, between the epitaxial layer 300 and said grid 500.

[0069] Figure 1H illustrates, for example, the formation of transistors 2000a, 2000b in the first 1000a region and the second 2000a region of stack 1. These two transistors 2000a, 2000b are electrically isolated from each other thanks to the presence of spacer 200.

[0070] Figures 2A to 2E are top views of several transistor arrays fabricated on the same wafer. These views are given as examples of possible integration of the present invention. Reference numeral 2000 points to rows of NMOS transistors and reference numeral 2000' to rows of PMOS transistors. The transistors are shown schematically, primarily to facilitate understanding of their location. Reference numeral 1000 points to the insulation area according to the present invention (hatched area in the figure). To make this area visible, the electrically conductive or insulating motif 500 has not been shown in this area, but it is understood that it is present there.

[0071] A first example of integration of the invention is illustrated in [Fig. 2A]. As shown, the electrically conductive motif 500 extends above the region of the wafer where the PMOS transistors are located. More precisely, it extends between a first PMOS transistor 2000a' and a second PMOS transistor 2000b'. By positively biasing this electrically conductive motif 500, it is possible to electrically isolate these two neighboring PMOS transistors 2000a', 2000b'. For reasons of simplifying manufacturing processes, streamlining costs, and saving space, it is advantageous for the electrically conductive motif 500 to extend above the region where the NMOS transistors are located. However, positively biasing the electrically conductive motif 500 does not allow for the isolation of the neighboring NMOS transistors 2000a, 2000b.The isolation zone 1000 according to the present invention can thus be integrated between the two neighboring NMOS transistors 2000a, 2000b in order to electrically isolate them. The electrically conductive motif 500 can thus be common to the PMOS and NMOS transistor zones.

[0072] A second example of integration is illustrated in [Fig. 2B]. In this example, the electrically conductive motif 500 is negatively biased so as to isolate the two neighboring NMOS transistors 2000a, 2000b. The isolation region 1000 according to the present invention is integrated between the two neighboring PMOS transistors 2000a', 2000b'.

[0073] According to a third integration example illustrated in [Fig.2C], an isolation zone 1000 according to the present invention is integrated both between the two neighboring NMOS transistors 2000a, 2000b and between the two neighboring PMOS transistors 2000a', 2000b'.

[0074] According to a fourth integration example illustrated in [Fig. 2D], the isolation zone 1000 according to the present invention is integrated between the two neighboring NMOS transistors 2000a, 2000b (or between the two neighboring PMOS transistors 2000a', 2000b') and the electrically conductive motif 500 is discontinuous, and in particular has a discontinuity between the isolation zone 1000 separating the NMOS transistors 2000a, 2000b and the portion of the pattern 500 separating the PMOS transistors 2000a', 2000b'.

[0075] According to a fifth integration example illustrated in [Fig.2E], motif 500 is electrically insulating.

[0076] Figure 2F illustrates how the present invention can be integrated into an active end-of-line system. As shown, to separate a region 1000b from a substrate socket 600 (bulk socket) located at the edge of the plate (gridded areas in Figures 2A to 2E), it is possible to form a spacer 200a separating the region 1000b from the substrate 10 and to place above the substrate 10 a separating layer 400 and an electrically conductive or insulating pattern 500, as in the other insulating areas 1000. This insulating area can be manufactured simultaneously with the insulating areas separating two devices. In particular, it is possible to form the spacer 200a at the same time as those of the other insulating areas, and to perform epitaxy from the substrate 10 at the same time as the formation of the epitaxial layer 300 of the other insulating areas. The 400 separating layers and the 500 patterns can also be formed simultaneously.The present invention therefore makes it possible to simultaneously create all the necessary isolation zones on a substrate.

[0077] Figures 3A to 3D are simulation results showing the interest of the present invention.

[0078] Figures 3A to 3C illustrate the distribution of the electric field within different transistor structures: [Fig.3A] corresponds to a prior art structure with conventional STI insulation, [Fig.3B] corresponds to a structure with insulation with an epitaxial layer underlying the transistor, while [Fig.3C] corresponds to a structure integrating the whole according to the present invention, with in particular an underlying epitaxial layer 300 and a separating layer 400.

[0079] Figure 3D is a graph showing the evolution of the electric field as a function of depth along the Z direction in the device. Different areas are referenced both in Figures 3A to 3C and in Figure 3D for better understanding of the figures: a. Zone "A": corresponds to the transistor gate, b. Zone “B”: corresponds to a dielectric layer (typically HfO2), c. Zone “C”: corresponds to an interlayer (commonly designated by the English term for "inter layer") of oxide, for example SiO2, d. Zone “D”: only present on [Fig.3C] relating to an assembly according to the present invention, it corresponds to the separating layer 400, e. Zone “E”: corresponds to the epitaxial layer 300.

[0080] Curves 3a, 3b and 3c of [Fig.3D] correspond to the electric field in each of the structures of figures 3A, 3B and 3C as a function of depth in the device.

[0081] It can be observed that in the case of structure 3B, the electric field value closely approaches the breakdown voltage of the device. The highest electric field values ​​are found in the interlayer (see area B in [Fig. 3B]). During operation, the voltage in certain areas of the transistor therefore approaches critical voltage values, which can lead to damage or even destruction of the device.

[0082] By comparison, it can be observed that the voltage prevailing in the structure implementing the present invention and illustrated in [Fig. 3C] does not reach such high values. In particular, the electric field within the interlayer is approximately three times lower than in the same layer within the structure of [Fig. 3B].

[0083] It is also observed that the electric field prevailing in the epitaxial layer of the structure in [Fig. 3C] is weaker than in the other structures. This notably reflects the reduction of parasitic capacitances under the transistor.

[0084] Through the various embodiments described above, it appears that the present invention offers an effective solution for isolating two regions intended to serve as a basis for manufacturing microelectronic devices such as transistors. The invention effectively solves the problem of lateral isolation between devices and that of parasitic diodes typically appearing in prior art structures.

[0085] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Demands

1. A microelectronic device comprising an insulation between a first region (1000a) and a second region (1000b), the device comprising a stack (1) comprising, along a so-called stacking direction (Z): • a substrate based on a first semiconductor material, called the semiconductor substrate (10), • a layer based on an electrically insulating material, called the buried oxide layer (20), • a layer based on a second semiconductor material, preferably identical to the first semiconductor material, called the thin layer (30), the stack (1) comprising a first region (1000a) and a second region (1000b) separated by an insulation zone (1000) extending between internal flanks (1a, 1b) of the stack, the insulation zone (1000) passing through the thin layer (30) and the buried oxide layer (20) and opening onto the semiconductor substrate (10),the insulation zone (1000) comprising: • a spacer (200) extending over the inner sides (la, 1b) of the stack (1), the spacer (200) being based on an electrically insulating material, • a layer based on the first semiconductor material, called the epitaxial layer (300), extending between the inner sides (la, 1b) of the stack (1) and being in contact with the substrate (10), • a layer based on an electrically insulating material, called the separating layer (400), extending over the epitaxial layer (300), • an electrically conductive or insulating motif (500) extending over the separating layer (400).

2. Device according to the preceding claim in which the separating layer (400) extends from a first portion (200a) of the spacer (200) covering a first inner flank (la) of the stack (1) to a second portion (200b) of the spacer (200) covering a second inner flank (1b) of the stack (1) facing the first inner flank (la).

3. Device according to any one of the preceding claims wherein the separating layer (400) completely covers the epitaxial layer (300).

4. Device according to any one of the preceding claims wherein the spacer (200) has a thickness e2Oo measured along a direction perpendicular to the inner flanks (la, 1b) of the stack (1), with e2oo greater than or equal to 4 nm and / or less than or equal to 10 nm, preferably less than or equal to 6 nm.

5. Device according to any one of the preceding claims wherein the spacer (200) is buried in the stack (1), and preferably does not extend beyond an upper face (31) of the thin film (30) opposite the buried oxide layer (20), for example is flush with the upper face (31) of the thin film (30).

6. Device according to any one of the preceding claims wherein the spacer (200) passes through the thin film (30) and the buried oxide layer (20) and preferably extends to an upper face (11) of the semiconductor substrate (10) facing the buried oxide layer (20).

7. A device according to any one of the preceding claims, wherein the separating layer (400) has a thickness e400, measured along the stacking direction (Z), greater than or equal to 3 nm

8. 11111. Device according to any one of the preceding claims wherein the epitaxial layer (300) has P-type or N-type doping.

9. Device according to any one of the preceding claims further comprising a first transistor (2000a) and a second transistor (2000b), the first transistor (2000a) and the second transistor (2000b) being located respectively in the first and second region (1000a, 1000b), the thin film (30) forming a first channel of the first transistor (2000a) and a second channel of the second transistor (2000b).

10. A method of using the device according to any one of the preceding claims, wherein motif (500) is

11. electrically conductive, the process further comprising a polarization step of said motif (500). A method for manufacturing an isolation zone (1000) between a first region (1000a) and a second region (1000b) of a microelectronic device, the method comprising the following steps: provide a stacking (1) comprising at least, along a so-called stacking direction (Z): i. a substrate based on a first semiconductor material, called a semiconductor substrate (10), ii. a layer based on an electrically insulating material, called a buried oxide layer (20), iii. a layer based on a second semiconductor material, preferably identical to the first semiconductor material, called a thin film (30), form an opening (100) in the stack, the opening (100) passing through the thin layer (30) and the buried oxide layer (20) and opening onto the semiconductor substrate (10), the opening (100) being defined by internal flanks (la, 1b) of the stack (1), the opening (100) separating the first region (1000a) from the second region (1000b) of the stack, forming a spacer (200) extending from the inner sides (la, 1b) of the stack (1), the spacer (200) being based on an electrically insulating material, growing by epitaxy from the semiconductor substrate (10) a so-called epitaxial layer (300) filling at least partially the opening (100), forming on the epitaxial layer (300) a layer based on an electrically insulating material called the separator layer (400), form an electrically insulating pattern or an electrically conductive pattern (500) intended to form a grid pattern on the separating layer (400).

12. A method according to the preceding claim wherein, at the end of epitaxial growth, the epitaxial layer (300) extends, along the stacking direction (Z), at least to half the height of the buried oxide layer (20), preferably extends at least to an upper face (21) of the buried oxide layer (20) opposite the substrate (10), preferably extends at least to an upper face (31) of the thin layer (30) opposite the buried oxide layer (20), preferably exceeds the thin layer (30).

13. A method according to any one of the two preceding claims comprising the formation of at least one first transistor (2000a) in the first region (1000a) and the formation of at least one second transistor (2000b) in the second region (1000b), each transistor (2000a, 2000b) having a channel formed by the thin film (30).

Images