Semiconductor structures
By using dilute nitride semiconductor materials as buffer layers in Ill-V semiconductor structures, the lattice mismatch issue is addressed, resulting in thinner, higher-performing semiconductor devices with improved manufacturing efficiency.
Patent Information
- Application Number
- GB2023014815
- Authority / Receiving Office
- GB · GB
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-27
- Publication Date
- 2025-04-09
AI Technical Summary
The challenge of forming Ill-V semiconductor layers on large diameter Si substrates is exacerbated by a significant lattice mismatch, leading to threading dislocations that detrimentally impact device performance and increase the thickness and production time of semiconductor devices.
Incorporating a first buffer layer of dilute nitride semiconductor material and a second buffer layer of Ill-V semiconductor material, which reduces lattice mismatch and allows for thinner buffer layers, thereby minimizing threading dislocations and device thickness.
This approach reduces the overall thickness of the epitaxial layer stack, enhances device performance by minimizing dislocations, and increases manufacturing throughput by reducing process time and resources.
Smart Images

Figure 00000000_0000_ABST
Abstract
Description
Technical field The present application relates to semiconductor structures. The present application also relates to a semiconductor device, an optical communications module, an electronic device and a vehicle. Background It is becoming increasingly desirable to form semiconductor devices from compound semiconductor materials. Compound semiconductor materials comprising elements from group III and group V of the periodic table exhibit many desirable photonic and electronic properties, which make them attractive for forming photonic semiconductor devices. Photonic semiconductor devices include optoelectronic semiconductor devices, such as a laser, light emitting diode (LED) or photodetector. Compound semiconductor materials including group III and group V elements are commonly referred to as lll-V semiconductor materials. Ill-V semiconductor materials are typically formed using epitaxial growth techniques. Such techniques can include molecular beam epitaxy (MBE) and metal organic chemical vapour deposition (MOCVD). In such techniques, group III elements and group V elements are deposited on to a substrate. Under the appropriate growth conditions, the elements combine to form a layer of Ill-V semiconductor material on the substrate. Typically a plurality of Ill-V semiconductor layers are grown on the substrate. The resulting semiconductor structure is commonly termed an epitaxial wafer. The epitaxial wafer is subsequently processed to a plurality of semiconductor devices. 100s or 1000s of semiconductor devices can be formed from one epitaxial wafer. It is desirable to form Ill-V epitaxial semiconductor layers on larger diameter substrates, as a greater number of semiconductor devices can be fabricated from wafers with a larger diameter. Ill-V semiconductor materials, such as GaAs, are not widely available in larger diameters of 8 or 12 inches. Fabricating Ill-V semiconductor materials on larger diameters substrates therefore commonly involves the formation of Ill-V semiconductor material on to group IV semiconductor substrates, such as, Si. Si substrates are widely available in larger diameters of 8 or 12 inches. Incorporating lll-V semiconductor material on to such substrates is therefore desirable to increase device fabrication yield from a wafer and thereby reduce device cost. However, there is a larger lattice mismatch between lll-V semiconductor materials and Si. Thus, forming lll-V semiconductor materials on large diameter Si substrates is notoriously challenging due to the large lattice mismatch between these materials. In particular, threading dislocations can form at the interface between a Si substrate and lll-V material such as GaAs. In extreme situations, the threading dislocations can propagate to the device layers of a lll-V semiconductor device which detrimentally impact device performance. To mitigate the presence of threading dislocations, it is common to grow a thick buffer layer of GaAs on the Si substrate. These layers are typically >1 pm and act to reduce the threading dislocation density (TDD), to help prevent the threading dislocations from impacting the device layers of a lll-V epitaxial layer stack. Additionally, a dislocation filter is commonly included on the thick GaAs buffer layer, which comprises a material that acts to prevent the egress of threading dislocations into device layers. Whilst the thick buffer layer and dislocation filter can act to prevent threading dislocations from affecting device layers of an epitaxial layer stack, they significantly increase the overall thickness of the epitaxial layer stack. Thicker epitaxial layer stacks are undesirable as they increase production time and result in larger semiconductor device size. Summary It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a semiconductor structure comprising: a substrate; a first buffer layer over the substrate comprising dilute nitride semiconductor material; a second buffer layer over the first buffer layer comprising lll-V semiconductor material; and one or more lll-V semiconductor layers over the second buffer layer. According to a second aspect there is provided a semiconductor device comprising the semiconductor structure according to the first aspect. According to a third aspect there is provided an optical communications module comprising the semiconductor device according to the second aspect. According to a fourth aspect there is provided an electronic device comprising the semiconductor device according to the second aspect or the optical communications module according to the third aspect. According to a fifth aspect there is provided a vehicle comprising the semiconductor device according to the second aspect or the optical communications module according to the third aspect. According to a sixth aspect there is provided a method for forming a semiconductor structure comprising: forming a first buffer layer over a substrate comprising dilute nitride semiconductor material; forming a second buffer layer over the first buffer layer comprising lll-V semiconductor material; and forming one or more lll-V semiconductor layers over the second buffer layer. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a semiconductor structure; Figure 2 is another example of a semiconductor structure; Figure 3 is another example of a semiconductor structure; Figure 4 is another example of a semiconductor structure; Figure 5 is a flowchart illustrating steps in a method. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus AI025GaAs means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb). A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100> crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. Lattice matched means that two crystalline layers have the same, or similar, lattice spacing and so the second layer will tend to grow isomorphically on the first layer. Lattice constant is the unstrained lattice spacing of the crystalline unit cell. Lattice coincident means that a crystalline layer has a lattice constant which is, or is close to, an integer multiple of the previous layer so that the atoms can be in registry with the previous layer. Lattice mismatch is where the lattice constants of two adjacent layers are neither lattice matched nor lattice coincident. Such mismatch introduces elastic strain into the structure, particularly the second layer, as the second layer adopts the in-plane lattice spacing of the first layer. The strain is compressive where the second layer has a larger lattice constant and tensile where the second layer has a smaller lattice constant. Where the strain is too great the structure relaxes to minimise energy through defect generation, typically dislocations, known as slip, or additional interstitial bonds, each of which allows the layer to revert towards its lattice constant. The strain may be too great due to a large lattice mismatch or due to an accumulation of small mismatches over many layers. A relaxed layer is known as metamorphic, incoherent, incommensurate or relaxed, which terms are also commonly interchangeable. A pseudomorphic system is one in which a single-crystal thin layer overlies a singlecrystal substrate and where the layer and substrate have similar crystal structures and nearly identical lattice constants. In a pseudomorphic structure the in-plane lattice spacing of the thin layer adopts the in-plane lattice constant of the substrate and is therefore elastically strained, either compressively where the layer has a larger lattice spacing than the substrate or tensilely where the layer has a smaller lattice spacing than the substrate. A pseudomorphic structure is not constrained in the out-of-plane direction and so the lattice spacing of the thin layer in this direction may change to accommodate the strain generated by the mismatch between lattice spacing. The thin layer may alternatively be described as “coherent”, “commensurate”, “strained” or “unrelaxed”, which terms are often used interchangeably. In a pseudomorphic structure all the layers adopt the lattice spacing of the substrate in their respective in-plane lattice spacing. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. Examples according to the present disclosure provide a semiconductor structure that comprises a substrate, a first buffer layer over the substrate comprising dilute nitride semiconductor material and a second buffer layer over the first buffer layer comprising lll-V semiconductor material. The semiconductor structure further comprises one or more lll-V semiconductor layers over the second buffer layer. Dilute nitrides are a class of lll-V semiconductor material, which contain a small concentration of N atoms. The nitrogen atoms are typically present in the lll-V semiconductor material with a concentration of less than 5% of the group V materials. Dilute nitrides have been widely used in the active regions of photonic semiconductor devices, such as VCSELs. Incorporating small amounts of N into a lll-V semiconductor active region results in a reduction of the bandgap and this shifts the operational wavelength of the semiconductor device to longer wavelengths. This is desirable in many applications involving long wavelength (>900nm) semiconductor emitters and detectors. Such semiconductor devices are useful in many applications, such as facial recognition systems. The use of dilute nitride semiconductor materials, has, however been restricted for use in the active region of photonic semiconductor devices. Examples, according to the present disclosure provide a dilute nitride semiconductor material layer, which is outside of an active region and is present in a buffer layer. In examples according to the present disclosure, the buffer layer may be present between a substrate and the 11 l-V semiconductor layers that provide a function in a semiconductor device. Such layers providing a function may be termed ‘device layers’. The incorporation of dilute nitride material in a 11 l-V semiconductor material results in an additional effect of decreasing the lattice constant of the material. This effect can be used to reduce lattice mismatch between the dilute nitride semiconductor layer and another semiconductor material in an epitaxial wafer, such as a Si substrate. Reducing the lattice mismatch with the substrate reduces the amount of threading dislocations that occur in a 11 l-V epitaxial layer stack. As such, the reduced threading dislocations mean that a thinner buffer layer can be grown between the substrate and the device layers of the epitaxial layer stack in order to achieve an acceptable TDD. The reduction in the thickness of the buffer reduces the overall thickness of the epitaxial layer stack. To provide additional context to the description of the examples according to the present disclosure, there now follows a further discussion of the drawbacks, which conventional semiconductor structures suffer from. Figure 1 is an example of a semiconductor structure 100. Semiconductor structure 100 comprises a substrate 110 that comprises Si. As described above, incorporating lll-V semiconductor material on to Si substrates is desirable due to the large diameters with which Si substrates are commonly found. However, there is a larger lattice mismatch between Si and many lll-V semiconductor materials, such as GaAs. Growing bulk lll-V semiconductor material directly on a Si substrate can lead to threading dislocations occurring in the epitaxially grown lll-V layers and / or the Si substrate. Techniques have thus been developed to epitaxially grow lll-V semiconductor material on Si substrate, some of which are present in semiconductor structure 100. Semiconductor structure 100 further comprises a nucleation layer 120 grown on the substrate 110. Nucleation layer 120 may provide a surface to improve the epitaxial growth of buffer layer 130. Semiconductor structure 100 further comprises a buffer 130 comprising GaAs over the nucleation layer 120. GaAs buffer 130 is relatively thick and may have a thickness of greater than 1 pm. The thickness of the GaAs buffer 130 helps to reduce the TDD and thus the effect of threading dislocations penetrating up the epitaxial wafer stack and into the device layer 150. In one example, the device layer may comprise an active region of a semiconductor device. In such examples, one or more device layers may thus be present between the GaAs buffer 130 and the active region. Semiconductor structure 100 comprises a dislocation filter 140 over the buffer 130. The dislocation filter comprises a material, which helps to annihilate threading dislocations and prevent their egress into device layer 150. However, the dislocation filter can only annihilate the dislocations if the TDD is sufficiently low. Therefore, the dislocation filter 140 is positioned over the GaAs buffer 130, which acts to reduce the TDD between the Si substrate 110 and the dislocation filter 140. In some examples, the dislocation filter 140 may comprise InGaAs. Semiconductor structure 100 further com prises device layer 150 over the dislocation filter 140. The device layer 150 may comprise a lll-V semiconductor material. In some examples, one or more further device layers may be present between the device layer 150 and the dislocation filter 140. In some examples, device layer 150 may comprise an active region of a semiconductor structure for emitting or absorbing photons. In such examples, the active region may comprise one or more quantum structures, such as quantum wells, quantum dots or a combination thereof. In some examples, the active region may comprise a dilute nitride semiconductor material. Semiconductor structure 100 thus comprises GaAs buffer 130 and dislocation 140 filter to supress the formation of threading dislocations in device layer 150. However, the presence of GaAs buffer 130 and dislocation 140 increases the thickness of an epitaxial layer stack for forming a semiconductor device. In particular, GaAs buffer 130 can comprise a thickness of greater than 1 pm. This can represent a significant contribution of the semiconductor device thickness. For example, Si photonics devices involve the incorporation of lll-V semiconductor material on to a Si substrate, where the total thickness of the device epitaxial layer stack is limited due to semiconductor device design constraints. The thick GaAs buffer layer 130 can represent a significant proportion of the device thickness, which limits the thickness and number of the device layers for forming the Si photonics semiconductor device. This, in turn, limits the semiconductor device functionality. Furthermore, as well as a lattice mismatch, there is a thermal budget mismatch between Si and lll-V materials such as GaAs. As such, during semiconductor device fabrication processes, the thicker the GaAs material grown on the Si substrate, the greater chance there is for wafer cracking during cooling, following heating of the wafer. This can be combated by cooling the wafer over a longer period of time. However, increasing fabrication processing time in this way reduces manufacturing throughput. In a similar manner, epitaxially growing the thick layers increases process time and resources, and reduces throughput. Examples according to the present disclosure provide a buffer comprising dilute nitride semiconductor material. As described above, the addition of nitrogen in dilute amounts in a lll-V semiconductor material reduces the lattice constant of the semiconductor material. In some examples, this can reduce the lattice mismatch between a lll-V semiconductor material and a substrate material, such as Si, and thereby reduce the threading dislocations in a lll-V epitaxial layer stack. Figure 2 illustrates an example of a semiconductor structure 200. Semiconductor structure 200 comprises elements in common with semiconductor structure 100. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor structure 200 comprises first buffer layer 230 comprising dilute nitride semiconductor material. Buffer layer 230 comprises GaAsN. In one example, the GaAsN material may comprise a dilute concentration of N. In one example, the GaAsN material may comprise a concentration of less than 5% of the group V material. The buffer layer 230 comprising N in dilute amounts reduces the lattice constant of the material. GaAs comprises a lattice constant of 5.653 A at 300 K and Si comprises a lattice constant of 5.431 at 300 K. The addition of N in dilute amounts to GaAs to form GaAsN results in a reduction of the lattice constant of the material and thus a reduction of the lattice mismatch between the first buffer layer 230 and the Si substrate 110. A reduction in the lattice mismatch between the first buffer layer 230 and the Si substrate 110 thus helps to reduce the formation of threading dislocations between the Si substrate 110 and the lll-V layers of the semiconductor structure 200. Semiconductor structure 200 further comprises a second buffer layer 240, which comprising GaAs. The second buffer layer 240 acts to reduce the threading dislocation density (TDD) between the Si substrate 110 and device layer 150, in a similar manner to that described above. However, second buffer layer 240 is thinner than the GaAs buffer layer 130 described above with respect to semiconductor structure 100. As the threading dislocations have been reduced by the dilute nitride material of the first buffer layer 230, the thickness of the second buffer layer 240 to achieve an acceptable TDD between the device layer 150 and Si substrate 110 of semiconductor structure 200 may also be reduced. For example, the second buffer 230 may be substantially less than 1 pm. The combined thickness of the first buffer layer 230 and second buffer layer 240 may thus be substantially less than the GaAs buffer layer 130 described above with respect to semiconductor structure 100. As such, semiconductor structure 200 may be thinner than semiconductor structure 100. Furthermore, the combined thickness of the first buffer layer 230 and second buffer layer 240 may enable more room in an epitaxial layer stack for device layers for forming a function in a semiconductor structure. Semiconductor structure 200 further does not comprise a dislocation filter. In some examples, the combined effect of the dilute nitride material of the first buffer layer 230 and the GaAs material of the second buffer layer 240 may reduce the TDD to such an extent that a dislocation filter is not used. However, in other examples, a dislocation filter may be present between the second buffer layer 240 and device layers, such as device layer 150 of the semiconductor structure 200. Figure 3 illustrates an example of a semiconductor structure 300. Semiconductor structure 300 comprises elements in common with semiconductor structures 100, 200. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor structure 300 comprises a period 360 comprising first GaAs layer 332 and first buffer layer 230 comprising dilute nitride semiconductor material. Period 360 is repeated N times to form a superlattice, which forms buffer region 370. The superlattice of the buffer region 370 comprises dilute nitride material in alternating layers, which may still provide appropriate threading dislocation suppression, in a similar manner to that described above. Accordingly, second buffer layer 240 can again be formed relatively thin and still provide appropriate TDD. In the example of semiconductor structure 300, first GaAs layer 332 and dilute nitride layer 230 may comprise equal thickness, such that, about one half of the buffer region 370 may comprise dilute nitride material. However, in other examples the thickness of the first GaAs layer 332 and dilute nitride layer 230 may be varied to vary the composition of the buffer region 370 that comprises dilute nitride material. Figure 4 illustrates an example of a semiconductor structure 400. Semiconductor structure 400 comprises elements in common with semiconductor structures 100, 200, 300. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor structure 400 comprises a buffer region 470 comprising first buffer layer 230 comprising dilute nitride semiconductor material, second dilute nitride layer 434 and third dilute nitride layer 438. Buffer region 470 further comprises first GaAs layer 332 and second GaAs layer 436. Semiconductor structure 400 thus comprises a plurality of dilute nitride layers 230, 436, 440, alternately stacked with a plurality of GaAs layers 432, 438. In some examples, the plurality of GaAs layers 432, 438 may be referred to as a plurality of 11 l-V semiconductor layers. As illustrated in Figure 4, the thickness of the layers varies in an upwards direction away from substrate 110 and towards the device layer 150. The varying thicknesses may thus provide a grading effect in a transition from the first buffer layer 230 to the second buffer layer 240. In this way, the dilute nitride layers can still provide a reduction in the threading dislocations at the interface between the Si substrate and the 11 l-V layers of the semiconductor structure 400 before the GaAs buffer layer 240 acts to appropriately reduce the TDD. It will be appreciated that whilst three dilute nitride layers 230, 436, 440 and two GaAs layers 332, 436 are illustrated between substrate 110 and second buffer layer 240, any suitable number of layers with any suitable thickness may be configured to provide an appropriate TDD between the substrate 110 and the device layer 150. Examples according to the present disclosure have described the effect of dilute nitride material to reduce strain in a GaAs material system. It will be appreciated that a ‘GaAs material system’ additionally comprises ternary, quaternary etc. alloys that comprise GaAs, such as AlxGai-xAs. In other examples according to the present disclosure, N may be incorporated in dilute amounts into other 11 l-V material systems to also result in strain reduction. For example, examples according to the present disclosure may further be applicable to GaSb, InP and InAs material systems. In particular, examples according to the present disclosure may comprise a semiconductor structure that comprises a substrate; a first buffer layer over the substrate comprising dilute nitride semiconductor material comprising GaSbN; and a second buffer layer over the first buffer layer comprising GaSb; and one or more 11 l-V semiconductor layers over the second buffer layer. In some examples, the substrate may comprise Si. The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a photonic semiconductor device. In some examples the photonic semiconductor device may comprise one of: a laser, a laser diode, a vertical cavity surface emitting laser (VCSEL), a distributed feedback (DFB) laser, an edge emitting laser (EEL), a resonant-cavity LED (RCLED), a photodetector, a photodiode, a PIN diode and an avalanche photodiode (APD). The present disclosure further provides an optical communications module comprising a semiconductor device according to examples of the present disclosure. In some examples the optical communications module may comprise one of: a transmitter module, a receiver module, a transceiver module, a modulator, an optical amplifier, a multiplexer and a demultiplexer. In some examples the communications infrastructure module may comprise a memory module, such as a read-and-write head. The present disclosure further provides an electronic device comprising an optical communications module according to examples of the present disclosure. In some examples the electronic device may comprise an optical communications infrastructure device, such as a communication infrastructure device for an optical communication network. In some examples the electronic device may comprise a component of a server rack. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console, or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar. The present disclosure further provides a vehicle comprising an optical communications module according to examples of the present disclosure. In some examples the vehicle may comprise an automotive vehicle such as a car, a van, a heavy goods vehicle (HGV), a bus, a motorbike, or similar. In some examples the vehicle may comprise an aviation vehicle, such as an aeroplane, helicopter, or similar. In some examples the vehicle may comprise an aeronautical vehicle, such as a boat, ship or similar. Figure 5 is a flowchart illustrating process steps in a method 500 for forming a semiconductor structure. The method comprises, in a first step 510, forming a first buffer layer over a substrate comprising dilute nitride semiconductor material. The method 500 further comprises, in a second step 520, forming a second buffer layer over the first buffer layer comprising 11 l-V semiconductor material. The method further comprises, in a third step 530, forming one or more 11 l-V semiconductor layers over the second buffer layer. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope. 5
Claims
1. A semiconductor structure comprising:a substrate;a first buffer layer over the substrate comprising dilute nitride semiconductor material;a second buffer layer over the first buffer layer comprising lll-V semiconductor material; andone or more lll-V semiconductor layers over the second buffer layer.
2. The semiconductor structure according to claim 1 wherein the Substrate comprises Si.
3. The semiconductor structure according to claim 1 or 2 wherein the dilute nitride semiconductor material comprises GaAsN.
4. The semiconductor structure according to any preceding claim wherein the second buffer layer does not comprise N.
5. The semiconductor structure according to any preceding claim wherein the second buffer layer comprises GaAs.
6. The semiconductor structure according to any preceding claim further comprising a buffer region comprising the first buffer layer and a third buffer layer, wherein the third buffer layer does not comprise N.
7. The semiconductor structure according to claim 6 wherein the third buffer layer comprises GaAs.
8. The semiconductor structure according to claim 6 or 7 wherein the buffer region comprises a superlattice comprising a period of semiconductor layers repeated a plurality of times; and wherein the period comprises the first buffer layer and the third buffer layer.
9. The semiconductor structure according to claim 6 or 7 wherein the buffer region comprises a plurality of dilute nitride semiconductor layers comprising the first buffer layer and a plurality of lll-V semiconductor layers comprising the third buffer layer; wherein the plurality of dilute nitride semiconductor layers and theplurality of lll-V semiconductor layers are alternately stacked between the substrate and the second buffer layer, wherein the first buffer layer is nearest the substrate; and wherein a thickness of each of the plurality of dilute nitride semiconductor layers decreases away from the substrate and a thickness of each of the plurality of lll-V semiconductor layers increases away from the substrate.
10. The semiconductor structure according to any preceding claim further comprising a nucleation layer between the substrate and the first buffer layer.
11. The semiconductor structure according to any preceding claim wherein the one or more lll-V semiconductor layers comprise an active region comprising the III-V semiconductor layer.
12. The semiconductor structure according to any preceding claim wherein the one or more lll-V semiconductor layers comprises a device layer.
13. The semiconductor structure according to claim 12 wherein the device layer is on a surface of the second buffer layer.
14. A semiconductor device comprising the semiconductor structure according to any preceding claim.
15. An optical communications module comprising the semiconductor device according to claim 14.
16. An electronic device comprising the semiconductor device according to claim 14 or the optical communications module according to claim 15.
17. A vehicle comprising the semiconductor device according to claim 14 or the optical communications module according to claim 15.
18. A method for forming a semiconductor structure comprising:forming a first buffer layer over a substrate comprising dilute nitride semiconductor material;forming a second buffer layer over the first buffer layer comprising lll-V semiconductor material; andforming one or more lll-V semiconductor layers over the second bufferlayer.17
Citation Information
Patent Citations
LED epitaxial wafers and their fabrication methods, LED
CN116190519B
Nitride semiconductor light emitting diode
JP1996236810A
Method for manufacturing semiconductor device
JP2003142404A
Method for manufacturing semiconductor device
JP2003142406A