Device with message passing algorithm core, and method therefor

Abstract

A device for processing message passing algorithms comprises a computation circuit (802) that receives a first set of nc,r values (720), and provides: a first output value (908) calculated as a non-li

Description

Description Field of the invention The field of the invention relates to a Message Passing Algorithm (MPA) core and a method for MPA core processing. The field of the invention is applicable to, but not limited to, Low Density Parity Check (LDPC) coding for current and future generations of communication standards. Background LDPC coding FIG. 1 depicts a communication scheme having an encoding chain 100 and a decoding chain 101, which uses a Low-Density Parity Check (LDPC) code to protect data from errors that are imposed during unreliable transmission or storage. The data is typically represented by a vector comprising K data symbols, each of which can take a value in the range '0' to 'M-l', where M is the radix of the code. While extensive research has been conducted on the topic of non-binary LDPC codes, with M typically adopting a value in the set {4, 8,16,...}, it is binary LDPC codes with M=2 that are typically adopted in practical applications. Hence, for the sake of simplicity, the remainder of this background discussion assumes that the data vector x 102 comprises K data bits, each of which can take a value of '0' or '1'. The known LDPC code operates using two processes, where the first comprises LDPC encoding before unreliable transmission or storage and the second comprises LDPC decoding afterwards. The LDPC encoder 103 and decoder 104 must adopt compatible parameterisations, which may be specified by a Parity Check Matrix (PCM) having N' columns, N'-K rows and populated with binary values of '0' and '1'. LDPC encoding uses the PCM H to convert the vector x 102 of K data bits into a vector y 105 of N' encoded bits, where N' is greater than K. This is typically achieved by setting the first K bits in the encoded bit vector (referred to as its systematic bits) equal to the K data bits of vector x 102, then setting the remaining N'-K bits (referred to as the parity bits), such that y.H = 0 in the Galois Field GF(M), where '0' is a syndrome vector comprising N'-K 0-valued bits. As understood in the field, the 'Galois Field' notation for the case where M=2 means binary with the arithmetic operation + mapping to an XOR function. Hence, it can be said that the first K columns in the PCM correspond to the data bits of vector x 102, while the set of all columns correspond to the N' encoded bits of vector y 105. During unreliable storage or transmission, the vector y 105 of N' encoded bits is exposed to errors and is typically converted into a vector of N' encoded soft bits, which express how likely each of the N' encoded bits of vector y 105 is to have a value of '0' or '1'. There are a number of ways that soft bits can be represented, including bit probabilities, stochastic bit sequences, likelihood ratios and Logarithmic Likelihood Ratios (LLRs). Among these, it is LLRs that are most frequently adopted and so throughout this document we refer to LLRs as an example implementation of soft bits, where: LLR = In Pr(bit = 0) Pr(bit = 1) LDPC decoding 104 may then use the PCM to convert the vector of N' encoded LLRs 106 into a vector of K decoded bits 107. Provided that the errors introduced during transmission or storage are not too severe, the K decoded bits 107 are typically a reproduction of the K data bits of vector x 102 that were input into the encoder 103. The 3GPP™ New Radio LDPC code Referring back to FIG. 1, a known schematic of LDPC coding and related signal processing operations in a 3rd generation partnership project (3GPP™) New Radio (NR) is shown. As shown in FIG. 1, LDPC codes are adopted to protect data from transmission errors in the 3GPP™ NR standard for fifth generation (5G) mobile communications [1], In this application, the K data bits of 102 are formed as a concatenation of three separate bit vectors, where the first vector comprises K'-L information bits 108, the second vector comprises L bits introduced by a Cyclic Redundancy Check (CRC) encoder 109 and the third vector comprises K-K' bits introduced by filler bit insertion 110. Following LDPC encoding 103, rate-matching 111 is used to convert the resultant vector y 105 of N' encoded bits into a vector of Er rate-matched bits 112. Following unreliable transmission, derate-matching 113 is used to convert the vector of Er rate-matched LLRs 114 into the vector of N' encoded LLRs 106, which are input into the LDPC decoder 104. Here, the N' encoded LLRs 106 may also include contributions from LLRs received during previous transmissions in a Hybrid Automatic Repeat Request (HARQ) process and stored using a HARQ buffer 115. Following LDPC decoding, filler bit removal 116 may be used to remove the K-K' filler bits from the vector of K decoded bits 107. Then a CRC decoder 117 may be used to check the CRC within the resultant vector of K' decoded bits 118, in order to determine if any uncorrected transmission errors remain. If not, then the CRC decoder can remove the L CRC bits and output the K'-L decoded information bits 119. Either way, the CRC decoder can also output a binary flag 120, to indicate whether or not the CRC check was successful. The 3GPP™ New Radio LDPC code is specified by PCMs that are derived from two basegraphs, called BG1 200 and BG2 300, FIG. 2 and 3 illustrate known representations of BG1 200 and BG2 300 from 3GPP™ New Radio, respectively. Each basegraph comprises a matrix populated with binary values of '0' and '1'. BG1 200 has ni=nc,i+ne,i=68 columns, which are split into nc,i=26 core columns 201 on the left and ne,i=42 extension columns 202 on the right. BG1 200 has mi=mc,i+ne,i=46 rows, which are split into mc,i=4 core rows 203 at the top and me,i=ne,i=42 extension rows 204 at the bottom. Meanwhile, BG2 300 has n2=nc,2+ne,2=52 columns, which are split into nc,2=14 core columns 301 on the left and ne,2=38 extension columns 302 on the right. BG2 300 has m2=mc,2+ne,2=42 rows, which are split into mc,2=4 core rows 303 at the top and me,2=ne,2=38 extension rows 304 at the bottom. In both basegraphs, the submatrix formed by the intersection of the core columns 201 and 301, and core rows 203 and 303, is densely populated with binary values of '1'. Indeed, 19 out of the nc,i=26 core columns 201 have the binary value of '1' in each of the core rows 203 in BG1 200. Meanwhile, up to 10 out of the nc,2=14 core columns 301 in FIG. 3 have the binary value of '1' in each of the core rows 303 in BG2 300. The submatrix formed by the intersection of the core columns 201 and 301 and the extension rows 204 and 304 is sparsely populated with binary values of '1', except for the first two columns that are referred to as the punctured core columns and which are densely populated with binary values of '1'. Indeed, no more than 9 out of the nc,i=26 core columns 201 have the binary value of '1' in any of the extension rows 204 in BG1 200. Meanwhile, no more than 5 out of the nc,2=14 core columns 301 have the binary value of '1' in any of the extension rows 304 in BG2 300. The submatrix formed by the intersection of the extension columns 202 and 302 and the core rows 203 and 303 is completed filled with binary values of 0 in both basegraphs 200 and 300. The square submatrix formed by the intersection of the extension columns 202 and 302 and the extension rows 204 and 304 is mostly filled with binary values of 'O', except for the elements that sit on the diagonal that runs from the top left corner of the submatrix to the bottom right corner, which adopt a binary value of '1' in both basegraphs 200 and 300. Note that depending on the operation of the rate-matching, some of the extension columns 202 and 302 and the corresponding extension rows 204 and 304 may be deleted from the basegraph at run-time, before it is used to generate the PCM. Here, the extension row 204 and 304 that corresponds to a particular extension column 202 and 302 is the one that it shares a binary value of 1 with. This deletion reduces the number of extension columns 202 and rows 204 in BG1 200 from ne,i to n'e,i and reduces the number of extension columns 302 and rows 304 in BG2 300 from ne,2 to n'e,2. Hence the number of columns becomes n'i=nc,i+n'e,i and n'2=nc,2+n'e,2, for BG1 200 and BG2 300 respectively, while the number of rows becomes m'i=mc,i+n'e,i and m'2=mc,2+n'e,2, for BG1 200 and BG2 300 respectively. The PCM used at run-time for a particular LDPC encoding and decoding process is obtained by selecting one or other of the basegraphs and lifting it using a lifting factor Z, for which 51 values of up to Zmax=384 are supported in 3GPP™ New Radio. Here, each binary element in the basegraph 200 and 300 is replaced by a submatrix having dimensions of Z x Z. Hence, each row or column in the basegraph 200 and 300 corresponds to a set of Z rows (referred to as a blockrow) or a set of Z columns (referred to as a blockcolumn) in the PCM. Furthermore, a PCM derived from BG1 200 comprises N'=n'iZ columns and N'-K=m'iZ rows, while a PCM derived from BG2 300 comprises N'=n'2Z columns and N'-K=m'2Z rows. In the case of BG1 200, K=22Z and the first 22 blockcolumns correspond to the data bits x 102. Meanwhile, K=10Z in the case of BG2 300, where the first 10 blockcolumns correspond to the data bits 102. In 3GPP™ New Radio, the values of K and Z are selected according to a set of rules, dependent on the value of K'. Binary elements in the basegraph having the value '0' are replaced by a Z x Z submatrix filled with binary values of 'O'. By contrast, binary elements in the basegraph having the value '1' are replaced by a submatrix in which Z elements adopt a binary value of '1' and the remaining Z x (Z-l) elements adopt a binary value of 'O'. In the extension blockcolumns, these Z 1-valued binary elements are positioned on the diagonal that runs from the top left corner of the Z x Z submatrix 401 to the bottom right corner. By contrast, in the core blockcolumns, these Z 1-valued binary elements are positioned according to a circular rotation 402 of this diagonal, as illustrated in FIG. 4. More specifically, FIG. 4 illustrates a known matrix interpretation of various rotations applied with exampling lifting factors Z, in order to convert between natural ordering 403 and rotated orderings 404 of variables. The diagonal used for each 1-valued binary element in the core blockcolumns is rotated by a different number of positions in the range '0' to 'Z-1', dependent on the particular basegraph and value of Z selected at run-time. A conventional LDPC decoder implementation While many LDPC decoder implementations have been proposed previously, this background discussion focuses on a row-parallel layered belief propagation implementation [2] of FIG. 5. FIG. 5 illustrates a known row-parallel layered belief propagation implementation of an LDPC decoder, with application for the 3GPP™ New Radio LDPC code. In general, this type of implementation can be designed to support any number of basegraphs at run-time, having any dimensions and sets of supported lifting factors Z. However, for the sake of simplicity, this background discussion considers an implementation that is specifically designed to offer run-time support for both 3GPP™ New Radio basegraphs and all corresponding lifting factors Z. The implementation of [2] 500 comprises nc,max=max(nc,i,nc,2) core Variable Node (VN) memories, one extension VN memory 502, nc,max rotators 505 and one Check Node (CN) processor, which are all operated under the control of a controller 506. Each of the nc,max core VN memories 503 is connected to an Input-Output (l-O) port 504 of the CN processor 501 via a corresponding one of the nc,max rotators 505. Meanwhile, the extension VN memory 502 is connected directly to an 1-0 port 507 of the CN processor 501. Hence, the CN processor 501 is connected to a total of nc,max+l VN memories 502 and 503, either via a corresponding rotator 505 or directly. The VN memories 502 and 503, rotators 505 and CN processor 501 may be designed to adopt a parallelism of P, such that each connection can transfer P number of LLRs at a time. Thus, different memory configurations are known. In the considered row-parallel architecture, each of the nc,i or nc,2 core blockcolumns in the PCM is mapped to a different one of the core VN memories 503 and the set of the n'e,i or n'e,2 extension blockcolumns is mapped to the extension VN memory 502. Here, the extension VN memory 502 comprises n'e,i or n'e,2 sub-memories, each of which is mapped to a different one of the extension blockcolumns. Note that there is only a single binary value of '1' in each extension blockcolumn 202 and 302 respectively of the basegraphs of FIG. 2 and FIG. 3. The inventors of the present invention have recognised and appreciated that each sub-memory in the extension VN memory 502 is equivalently mapped to the one of the m'e,i or m'e,2 extension blockrows that corresponds to the row of the basegraph that accommodates this binary value of '1'. The LDPC decoding process is initialised by loading each successive set of Z LLRs from the vector of N' encoded LLRs 106 into the VN memory or sub-memory that corresponds to each successive blockcolumn in the PCM. Note that the LLRs loaded into the core VN memories 503 corresponding to the first two blockcolumns (which are referred to as the punctured blockcolumns) typically adopt values of 0 in the 3GPP™ New Radio LDPC code. Meanwhile, the LLRs that correspond to the K-K' filler bits typically adopt large positive LLR values. The conventional LDPC decoder implementation performs an LDPC decoding process using a number of iterations, where each iteration completes one pass of processing over the PCM. Each iteration is comprised of processing performed for each blockrow of the PCM, where the order in which the blockrows are processed within each iteration is dictated by a layered belief propagation schedule. The processing of each blockrow of the PCM is comprised of a number of LDPC decoding operations, where each operation performs processing for a set of P rows within the blockrow. Each LDPC decoding operation comprises a first sub-step and a second sub-step. A number of processes are performed during each sub-step and these may be spread over a number of consecutive clock cycles. More specifically, the LDPC decoding process is completed over a number of operations. Each operation processes LLRs associated with P rows within the same blockrow of the PCM, where these rows are typically consecutive. Typically, the complete set of rows within a blockrow are processed during a group of ceil(Z / P) consecutive operations, with each successive operation typically processing successive sets of P rows in order. Note that the 'ceil' function rounds a fraction up to the lowest integer having a greater or equal value. Furthermore, the blockrows are typically processed in an order dictated by a schedule, which may repeat the processing of some or all of the blockrows over numerous iterations. During each operation of the LDPC decoding process, binary values of '1' in the core columns 201 and 301 of the corresponding row of the basegraph are used to activate the associated rotators 505, core VN memories 503 and CN processor 1-0 ports 504 and 507 of FIG. 5. During the first sub-step of each operation the LDPC decoding process, each of the activated core VN memories (say core VN memories 503 in FIG. 5) are read under the direction of the controller (say controller 506 in FIG. 5), in order to provide the P LLRs that are required to complete the processing of the P rows of the PCM. Furthermore, each of the activated rotators (say activated rotators 505 in FIG. 5) is configured to rotate these P LLRs into the order required to complete this processing, which is performed under the direction of the controller and according to the rotations used to convert the basegraph 200 and 300 into the PCM. Each activated rotator provides the corresponding set of P LLRs (referred to as alpha J LPDC input LLRs 512) to the input of the corresponding 1-0 port (say 1-0 port 504 of the CN processor 501 in FIG. 5). The set of P LLRs provided by each activated rotator are accompanied by a corresponding deactivated null column flag from the set of nc,max+l null column flags 508, which is provided by the controller 506. In this way, the controller 506 instructs the CN processor 501 to process the alphaj LDPC input LLRs 512. By contrast, the controller 506 provides activated null column flags in the set of nc,max+l null column flags 508 in correspondence to the deactivated rotators, in order to instruct the CN processor 501 to ignore any spurious signals provided at the input of the corresponding 1-0 port 504 in the absence of LLRs being provided by the VN memories. Furthermore, during the first sub-step in each operation of the LDPC decoding process that corresponds to an extension row 204 and 304 in the basegraph, the input of the corresponding 1-0 port 507 of the CN processor 501 is also provided with a set of P LLRs (referred to as alphaJi Low-Density Generator Matrix (LDGM) input LLRs 510) that are read from the extension VN memory (say extension VN memory 502 in FIG. 5). More specifically, these LLRs are provided by the particular sub-memory in the extension VN memory that is mapped to that extension row 204 and 304. In this case, the corresponding null column flag from the set of nc,max+l null column flags 508 is deactivated by the controller 506, in order to instruct the CN processor 501 to process the alpha Ji LDGM input LLRs 510. By contrast, the extension VN memory is deactivated during the first sub-step of each operation of the LDPC decoding process that corresponds to a core row 203 and 303 in the basegraph, with the result that it does not provide any LLRs to the CN processor. In this case, the corresponding null column flag from the set of nc,max+l null column flags 508 is activated by the controller 506, in order to instruct the CN processor 501 to ignore any spurious signals provided at the input of the corresponding 1-0 port 507 in the absence of LLRs provided by the VN memories. In the manner described above, the subset comprising the nc,r activated connections to the inputs of the 1-0 ports 504 and 507 of the CN processor each provide it with a set of P LLRs 510 or 512 in the first sub-step of each operation of the LDPC decoding process. In response to this, the CN processor performs P sets of calculations in parallel, for the P associated rows of the PCM. This may be achieved using a variety of message passing algorithms [3], including the sum-product, min-sum, normalised min-sum, offset min-sum or adjusted min-sum. Note that the adjusted min-sum algorithm is also known as the A-min*-BP algorithm [4], The CN processor typically employs internal Random Access Memory (RAM) 514 to assist these calculations using results (referred to as betajj_prev values) obtained during the previous iteration of processing the P associated rows of the PCM. These results are typically overwritten with new results (referred to as betajj values), which can be used to assist the next iteration of processing the P associated rows of the PCM. In the second sub-step in each operation of the LDPC decoding process, and following the completion of all calculations performed by the CN processor, it may use outputs from its 1-0 ports 504 and 507 to provide a set of P LLRs to each of its nc,r connections that are activated in the current operation of the LDPC decoding process. In the case of the CN processor 1-0 port 507, this set of P LLRs are referred to as the alphaj LDGM output LLRs 511. In the case of each CN processor 1-0 port 504, this set of P LLRs are referred to as the alphaj LDPC output LLRs 513. The function of the CN processor for the specific example of the Min-Sum Algorithm (MSA) is described first below, before the corresponding function for the generalised Message Passing Algorithm (MPA) is described, including an example of its application for the Adjusted Min-Sum Algorithm (AMSA). In the detailed description, the inventors identify a problem that arises during the practical implementation of this generalised MPA, as well as a solution to this problem that is offered by the present invention, which has applicability to the AMSA and to other MPAs. In the first sub-step of an LDPC decoding process performed for a set of P rows in the PCM using the MSA, the CN processor may combine P LLRs provided by inputs to each of its nc,r activated 1-0 ports. Here, we may represent the input LLRs using the notation aj,p where 'i' is in the range 1 to nc,r and indicates which of the nc,r activated 1-0 ports 504 or 507 (having deactivated null column flags 508) the LLR is provided on and 'p' is in the range 1 to P and indicates which of the P LLRs 510 or 512 provided on that 1-0 port this LLR is. In a first calculation, the CN processor may perform a calculation bj,p = 3j,p - mi,p corresponding to each input LLR aj,p provided by a core VN memory, where mi,p is a corresponding internally stored value (referred to as a beta_ij_prev value), which is read from the RAM 514 and is initialised to '0' at the start of the LDPC decoding process, before being updated in each iteration of the processing of the P rows in the PCM. Following this, the minimum and next minimum of the absolute values | bj,p| are identified for each value of 'p' and the corresponding values of the index 'i' are referred to as mini and min2, respectively. Note that if more than one of the absolute values | bi,p| share the same minimum, then an arbitrary one of these may be selected to be the minimum and another may be selected to be the next minimum. Furthermore, the product of the signs sign(bi,p) is identified for each value of 'p' and referred to as signp, where sign(x) is '+1', if x is not less than 'O', and '-1' otherwise. In the second sub-step when employing the MSA, the CN processor may perform a calculation mmini,P = sign(bmini,P) x signp x | bmin2,P | corresponding to the input LLR aj,p having the index T that equals mini for each value of 'p'. Meanwhile, a calculation mi,p = sign(bi,p) x signp x | bmini,P | is performed corresponding to all other input LLRs for each value of 'p'. Here, the value of all mi,p values (referred to as a betajj value) including Rimini,p is written into the RAM 514, in order to update the internally stored value for each combination of 'i' and 'p', so that it can be used during the next iteration of the processing of the P rows, as described above. Finally, the CN processor may perform a calculation dj,p = bj,p + mi,p, in order to obtain an output LLR dj,p for each of the P output LLRs 511 or 513 provided as outputs on each of the nc,r activated 1-0 ports 504 or 507 (having deactivated null column flags 508), in correspondence with the input LLR ai,p. In an alternative description of the generalised MPA, the CN processor begins in a similar manner to the MSA. More specifically, in the first sub-step of an LDPC decoding process performed for a set of P rows in the PCM using the MPA, the CN processor may combine P LLRs provided by inputs to each of its nc,r activated 1-0 ports. Again, we may represent the input LLRs using the notation aj,p where 'i' is in the range 1 to nc,r and indicates which of the nc,r activated 1-0 ports 504 or 507 (having deactivated null column flags 508) the LLR is provided on and 'p' is in the range 1 to P and indicates which of the P LLRs 510 or 512 provided on that 1-0 port this LLR is. As in the specific example of the MSA, the generalised MPA performs a first calculation, wherein the CN processor may perform a calculation bj,p = 3j,p - mi,p corresponding to each input LLR aj,p, where mi,p is a corresponding internally stored value, which is read from the RAM 514 and is initialised to '0' at the start of the LDPC decoding process, before being updated in each iteration of the processing of the P rows in the PCM. As in the MSA, the index (referred to as minjdx) of the absolute value | bminjdx,p I having the minimum value among the set of nc,r absolute values | bi,p| for each value of 'p' is determined in an MPA. Note that the index of the next minimum is not required in an MPA. However, in common with the MSA, the generalised MPA also calculates the product of the signs sign(bi,p) for each value of 'p' and referred to as signp, where sign(x) is '+1', if x is not less than 'O', and '-1' otherwise. In the second sub-step when employing an MPA, the CN processor may perform a calculation rnmin_idx,P = sign(bmin_idx,P) x signp x d_app_notmin corresponding to the input LLR ai,p having the index 'i' that equals minjdx for each value of 'p'. Meanwhile, a calculation mj,p = sign(bi,p) x signp x d_app is performed corresponding to all other input LLRs for each value of 'p'. Here, the calculation of the values d_app_notmin and d_app constitutes the core functionality of an MPA, which requires the repeated computation of a non-linear function. In generalised terms, a non-linear function may be defined to have two inputs 'a' and 'b' and one output nlf(a,b). For other numbers of inputs, the following definitions apply: nlf(a) = a; nlf(a,b,c) = nlf( nlf(a,b), c ) = nlf( a, nlf(b,c)), etc. The MPA core functionality computes d_app as the non-linear function of all nc,r non-null input LLRs, whereas d_app_notmin is the non-linear function of all nc,r non-null input LLRs except for the LLR having the index minjdx. This calculation may be defined by the following pseudocode: 1. Initialise d_app_notmin = +inf 2. fori = l:nc,r if i != minjdx d_app_notmin = | nlf(d_app_notmin, bj,p) | 3. d_app = | nlf(d_app_notmin, bminjdx,P) | Depending on the choice of non-linear function, this calculation may be used to perform any specific MPA. As mentioned previously, in the specific case of the AMSA, a non-linear function that may be used is minstar(a,b) (alternatively sometimes known as the boxplus operator), which is defined as follows: minsta r(a,b)=sign(a)xsign(b)x(min( |a I, I b|)+y( |a |+| b|)-y( |a |-1 b|)), where: y(x)=ln(l+exp(-|x|)). Other possible formulations of the minstar(a,b) function include: minsta r(a,b) = sign(a)xsign(b)xmin( |a |, | b |) + y(a+b) -y(a-b) minsta r(a,b) = sign(a)xsign(b)xmin( | a |, | b |) + sign(a)xsign(b)x(y( | a | +1 b |) - y( | a | -1 b |)) minsta r(a,b) = sign(a)xsign(b)xmin( | a |, | b | )+ln((l+exp(-1 a+b | )) / (l+exp(-1 a-b |))) minstar(a,b) = 2xtanh-1(tanh(a / 2)xtanh(b / 2)) A skilled practitioner would recognise that other formulations could also be used here. Here, it may be observed that the minstar operator comprises either a minimum function and an arithmetic addition of one or more terms y(x), or an inverse hyperbolic tangent function and two hyperbolic tangent functions. It is possible to determine the value of minjdx in conjunction with calculating the values d_app_notmin and d_app; alternatively, this minimum index finding may be performed separately in a parallel set of operations. As in the MSA, in the generalised MPA the value of mi,p is written into the RAM 514, in order to update the internally stored value for each combination of 'i' and 'p', so that it can be used during the next iteration of the processing of the P rows, as described above. Finally, the CN processor using an MPA may perform a calculation dj,p = bj,p + mi,p, in order to obtain an output LLR dj,p for each of the P output LLRs 511 or 513 provided as outputs on each of the nc,r activated 1-0 ports 504 or 507 (having deactivated null column flags 508), in correspondence with the input LLR aj,p. Following the operation of the CN processor (whether using the MSA, the AMSA, or any other MPA), the second sub-step, in each operation of the LDPC decoding process, proceeds with each of the activated rotators being configured to rotate the set of P LLRs (referred to as the alphaj LDPC output LLRs 513) that it is provided with, into an order that is appropriate for storage in the corresponding activated core VN memory. Furthermore, during the second sub-step in each operation of the LDPC decoding process, the CN processor may also calculate a set of P syndrome bits 509 corresponding to the P associated rows of the PCM. These syndrome bits may be provided to the controller 506, in order to enable the early termination of the LDPC decoding process when all parity checks are satisfied. Additionally, during the second sub-step in each operation of the LDPC decoding process that corresponds to an extension row (for example 204 and 304 in the basegraphs of FIG. 2 and FIG. 3), the set of P LLRs (referred to as the alphaj LDGM output LLRs 511) that the CN processor provides to the extension VN memory may be written to the one of its sub-memories that is mapped to that extension row. Alternatively, or additionally, in some applications, these LLRs may be fed back to a concatenated MIMO detector, to enable iteration with the LDPC decoder. In applications where iterative MIMO detection is not employed, the generation of the alphaj LDGM output LLRs 511 and the associated circuitry may be omitted from the implementation. Following the completion of the decoding iterations within the LDPC decoding process, a vector of N' decoded LLRs may be obtained by concatenating the sets of Z LLRs that were most recently stored in the VN memories 502 and 503. The vector of K decoded bits 107 may then be obtained with consideration of the signs of the first K decoded LLRs, where positive LLRs may be converted into the binary values of 'O', while negative LLRs may be converted into binary values of '1'. In summary, FIG. 5 shows a row parallel design for a LDPC decoder. Here, the CN processor 501 accepts input LLRs from multiple column memories 503 in each step. This enables processing for each of these columns to occur in the same step, achieving a high throughput. In a quasi-cyclic LDPC code like that of 3GPP™, the basegraph dictates that a different cyclic shift value should be applied to the LLRs read from each blockcolumn RAM. This results in the CN processor being connected to each column RAM through a rotator 505, each may be operating with a different rotation value. In order to achieve a high throughput, the CN processor may operate on P rows in parallel within the Z rows of the blockrow. This means that the CN processor requires P LLRs from each blockcolumn in each step. The output from the RAM, and the input and output of the rotator will therefore have to convey P LLRs in each step. Summary The examples herein described provide circuits for message passing algorithm processors and methods for message passing algorithm processing using parallel processing in an electronic device, for example with reduced critical path length and circuit area. In particular, examples describe efficient mappings between hardware components and algorithmic features. Specific example embodiments are set forth in the dependent claims. These and other aspects will be apparent from, and elucidated with reference to, the example embodiments described hereinafter. In a first aspect, a device for processing message passing algorithms comprises a computation circuit arranged to receive a first set of nc,r values, and is arranged to provide: a first output value that is calculated as a non-linear function of the first set of nc,r values; and a second output value that is calculated as a non-linear function of a second set of values, wherein the second set of values comprises nc,r-l values that are derived from the first set of nc,r values by excluding a minimum value in the first set of nc,r values; and the computation circuit comprises a network of a plurality of computation nodes arranged in a tree structure with two or more layers, wherein at least one upper layer receives top-level circuit input values, and output values from each upper layer serve as input values to one or more lower layers, with output values from a final layer constituting top-level circuit output values; and at least one of the plurality of computation nodes is associated with a third set of values and a fourth set of values, wherein each of the third set of values and fourth set of values are subsets of the first set of nc,r values, and each of the third and fourth sets of values comprises a number of values that is a number in a range from zero to nc,r inclusive; and the at least one of the plurality of computation nodes is arranged to receive: a first input value that is a nonlinear function of the third set of values, a second input value that is a non-linear function of the fourth set of values, a third input value that is a non-linear function of a fifth set of values, wherein the fifth set of values is a subset of the first set of nc,r values that is derived from the third set of values by excluding a minimum value in the third set of values, and a fourth input value that is a non-linear function of a sixth set of values, wherein the sixth set of values is a subset of the first set of nc,r values that is derived from the fourth set of values by excluding a minimum value in the fourth set of values; and the at least one of the plurality of computation nodes provides: a third output value that is calculated as a non-linear function of a seventh set of values, wherein the seventh set of values is a further subset of the first set of nc,r values that constitutes a union of the third set of values and fourth set of values, and a fourth output value that is calculated as a non-linear function of an eighth set of values, wherein the eighth set of values is a subset of the first set of nc,r values that is derived from the seventh set of values by excluding a minimum value in the seventh set of values. In this manner, the computation of the nonlinear function of the first set of values and the second set of values is performed simultaneously and using shared hardware components, leading to a reduction in the critical path length of the calculation and a reduced hardware resource requirement. In an optional example, the plurality of computation nodes of the device comprises: one or more non-linear function circuits configured to provide at least one of the third output value and the fourth output value, and to receive at least two of the first input value, the second input value, the third input value and the fourth input value; and one or more multiplexer circuits operably coupled to provide at least one of the first input value, the second input value, the third input value and the fourth input value to at least one of the third output value and the fourth output value, depending on which of the third set of values or fourth set of values contains the minimum value in the seventh set of values, wherein the minimum value in the seventh set is determined by minimum-finding circuitry, which is located either: internally to the plurality of computation nodes and operably coupled to the one or more multiplexer circuits directly, or externally to the plurality of computation nodes and configured to provide an additional input value to the plurality of the two or more computation nodes indicative of the result. In this manner, the second set of values is determined from the first set of values simultaneously to the computation of the non-linear functions and using shared hardware components, leading to a reduction in the critical path length of the calculation and a reduced hardware resource requirement. In an optional example, the one or more non-linear function circuits of the device is arranged to perform at least one of the following operations on input values that it receives, and to provide a result as at least one of the third output value and the fourth output value: a minimum function and one or more arithmetic additions, or an inverse hyperbolic tangent function and two hyperbolic tangent functions. In this manner, the computation circuit may be adapted to perform a variety of different non-linear functions of the first and second sets of values by modifying only a single internal component. In an optional example, a number of layers in the two or more layers in the tree structure of the device is at least ceil(log2(nc,r)). In this manner, the number of layers in the tree structure may scale appropriately with the size of the first set of values. In an optional example, a layer in the two or more layers of the device, having an index 'L' in a range of '1' to the number of layers, comprises a number of computation nodes, wherein the number of computation nodes in the layer is at least floor((nc,r+2L-l-l) / (2L)). In this manner, the number of computation nodes in each layer may scale appropriately and consistently with the layer's position within the tree structure. In an optional example, the plurality of computation nodes of the device further comprises a comparator circuit configured to identify which of the third set of values or fourth set of values contains the minimum value in the seventh set of values, and the at least one of the plurality of computation nodes is further arranged to receive: a fifth input value that is equal to the minimum value in the third set of values, and a sixth input value that is equal to the minimum value in the fourth set of values. In this manner, the determination of the minimum value in the seventh set of values is performed in close proximity to its point of utilisation within each computation node, reducing the wire delay and improving the modularity of the computation circuit. In an optional example, the at least one of the plurality of computation nodes of the device further provides a fifth output value that is equal to the minimum value in the seventh set of values. In this manner, the minimum value in each set of values is passed through the tree structure alongside the results of the non-linear functions of those sets, improving the modularity of the computation circuit and reducing the number of external inputs required. In an optional example, the computation circuit of the device further provides a sixth output value that is an index of the minimum value in the first set of nc,r values. In this manner, the outputs from the computation circuit identify which value in the first set of values has not affected the second output value, which is the non-linear function of the first set of values excluding the minimum. In an optional example, the at least one of the plurality of computation nodes of the device is further arranged to receive: a seventh input value that is an index of the minimum value in the third set of values, and an eighth input value that is an index of the minimum value in the fourth set of values; and the at least one of the plurality of computation nodes further provides a seventh output value that is an index of the minimum value in the seventh set of values; and wherein the at least one of the plurality of computation nodes further comprises an index finder circuit arranged to set the seventh output value as equal to either one of: the seventh input value when the third set of values contains the minimum value in the seventh set of values, or the eighth input value when the fourth set of values contains the minimum value in the seventh set of values. In this manner, the determination of the index of the minimum value in each set of values is performed within the respective computation nodes alongside the other operations, reducing wire delay and improving the modularity of the computation circuit. In an optional example, the computation circuit of the device is further arranged to receive external inputs of: a set of (nc,max+l-nc,r) null values, a set of nc,r deactivated null column flags, and a set of (nc,max+l-nc,r) activated null column flags; wherein each one of the set of nc,r deactivated null column flags corresponds to a corresponding one of the values in the first set of nc,r values and each one of the set of (nc,max+l-nc,r) activated null column flags corresponds to a corresponding one of the values in the set of (nc,max+l-nc,r) null values, and the value of each null column flag indicates whether the corresponding one of the valuesis provided by the first set of nc,r values or by the set of (nc,max+l-nc,r) null values. In this manner, the computation circuit can be used to receive sets of values in which zero or more values may be null at run-time, for example in the decoding of irregular LDPC codes. In an optional example, the at least one of the plurality of computation nodes of the device further comprises at least two of: a ninth input value that indicates when the third set of values has a size of zero, a tenth input value that indicates when the fourth set of values has a size of zero, an eleventh input value that indicates when the fifth set of values has a size of zero, and a twelfth input value that indicates when the sixth set of values has a size of zero. In this manner, each computation node may adjust its operation at run-time if its inputs correspond to sets of values which are derived wholly from null values. In an optional example, the at least one of the plurality of computation nodes of the device is further configured to, in the calculation of the third output value and the calculation of the fourth output value: ignore the first input value when the ninth input value indicates that the third set of values has a size of zero, and ignore the second input value when the tenth input value indicates that the fourth set of values has a size of zero, and the at least one of the plurality of computation nodes of the device is further configured to, in the calculation of the fourth output value: ignore the third input value when the ninth input value or eleventh input value indicates that the fifth set of values has a size of zero, and ignore the fourth input value when the tenth input value or twelfth input value indicates that the sixth set of values has a size of zero. In this manner, the calculations of the third and fourth output values may adapt at run-time to ignore any input values derived wholly from null values. In an optional example, the at least one of the plurality of computation nodes of the device is further configured to: ignore the fifth input value when the ninth input value indicates that the third set of values has a size of zero, and ignore the sixth input value when the tenth input value indicates that the fourth set of values has a size of zero, in the calculation of the fifth output value. In this manner, the calculation of the fifth output value may adapt at run-time to ignore any input values derived wholly from null values. In an optional example, the at least one of the plurality of computation nodes of the device is further configured to: ignore the seventh input value when the ninth input value indicates that the third set of values has a size of zero, and ignore the eighth input value when the tenth input value indicates that the fourth set of values has a size of zero, in the calculation of the seventh output value. In this manner, the calculation of the seventh output value may adapt at run-time to ignore any input values derived wholly from null values. In an optional example, the at least one of the plurality of computation nodes of the device further comprises: an eighth output value that indicates when the seventh set of values has a size of zero, and a ninth output value that indicates when the eighth set of values has a size of zero. In this manner, an indication of the absence of any non-null values within the seventh and eighth sets of values is passed through the tree structure alongside the non-linear functions of these sets, allowing nodes in later layers to adjust their operation at run-time when passed values which are wholly derived from null values. In a second aspect, a method for processing message passing algorithms in a device comprises: receiving, by a computation circuit, a first set of nc,r values, wherein the computation circuit comprises a network of a plurality of computation nodes arranged in a tree structure with two or more layers, wherein at least one upper layer receives toplevel circuit input values, and wherein output values from each upper layer serve as input values to one or more lower layers, with output values from a final layer constituting toplevel circuit output values; providing a first output value that is calculated as a non-linear function of the first set of nc,r values; providing a second output value that is calculated as a non-linear function of a second set of values, wherein the second set of values comprises nc,r-l values that are derived from the first set of nc,r values by excluding a minimum value in the first set of nc,r values; associating at least one of the plurality of computation nodes with a third set of values and a fourth set of values, wherein each of the third set of values and fourth set of values are subsets of the first set of nc,r values and wherein each of the third and fourth sets of values comprises a number of values that is a number in a range from zero to nc,r inclusive; receiving, by the at least one of the plurality of computation nodes, a first input value that is a non-linear function of the third set of values, a second input value that is a non-linear function of the fourth set of values, a third input value that is a non-linear function of a fifth set of values, wherein the fifth set of values is a subset of the first set of nc,r values that is derived from the third set of values by excluding a minimum value in the third set of values, and a fourth input value that is a non-linear function of a sixth set of values, wherein the sixth set of values is a subset of the first set of nc,r values that is derived from the fourth set of values by excluding a minimum value in the fourth set of values; providing, by the at least one of the plurality of computation nodes, a third output value that is calculated as a non-linear function of a seventh set of values, wherein the seventh set of values is a further subset of the first set of nc,r values that constitutes a union of the third set of values and fourth set of values, and a fourth output value that is calculated as a non-linear function of an eighth set of values, wherein the eighth set of values is a subset of the first set of nc,r values that is derived from the seventh set of values by excluding a minimum value in the seventh set of values. In this manner, the computation of the non-linear function of the first set of values and the second set of values is performed simultaneously and using shared hardware components, leading to a reduction in the critical path length of the calculation and a reduced hardware resource requirement. Brief description of the drawings Further details, aspects and embodiments will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the FIG's are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 illustrates a known schematic of LDPC coding and related signal processing operations in 3GPP™ New Radio. FIG. 2 illustrates a known representation of BG1 from 3GPP™ New Radio. FIG. 3 illustrates a known representation of BG2 from 3GPP™ New Radio. FIG. 4 illustrates a known matrix interpretation of various example rotations applied with exampling lifting factors Z, in order to convert between natural and rotated orderings of variables. FIG. 5 illustrates a known row-parallel layered belief propagation implementation of an LDPC decoder, with example application for the 3GPP™ New Radio LDPC code. FIG. 6 illustrates an example circuit diagram for the structure of a CN processor that supports the parallel processing of P PCM rows in a single operation. FIG. 7 illustrates an example flow diagram for a NPU that performs the min-sum algorithm, with example application for the 3GPP™ New Radio LDPC code. FIG. 8 illustrates an example flow diagram for a NPU that may perform any Message Passing Algorithm (MPA), with example application for the 3GPP™ New Radio LDPC code. FIG. 9 illustrates an example flow diagram for a MPA core computation circuit implementation having the problem of a high critical path length. FIG. 10 illustrates an example circuit diagram for a serial-structured MPA core computation circuit implementation having the problem of a high critical path length, with example application for the 3GPP™ New Radio LDPC code. FIG. 11 illustrates an example circuit diagram for a parallel-structured MPA core computation circuit implementation having the problem of a high hardware complexity, with example application for the 3GPP™ New Radio LDPC code. FIG. 12 illustrates an example circuit diagram for the proposed tree-structured MPA core computation circuit implementation having a low critical path and a low hardware complexity, with example application for the 3GPP™ New Radio LDPC code. FIG. 13 illustrates an example circuit diagram for an ams_branch node in the proposed tree-structured MPA core computation circuit implementation. FIG. 14 illustrates an example circuit diagram for an ams_leaf node in the proposed tree-structured MPA core computation circuit implementation. FIG. 15 illustrates an example circuit diagram for an ams_trunk node in the proposed tree-structured MPA core computation circuit implementation. FIG. 16 illustrates an example circuit diagram for a non-linear function operator performing the minstar function. FIG. 17 illustrates example output values of the LUT(X) submodule as a function of its input value. FIG. 18 illustrates an example flow diagram for the generalised operation of the proposed MPA core computation circuit implementation. FIG. 19 illustrates an example flow diagram for the generalised operation of a computation node in the proposed tree-structured MPA core computation circuit implementation. Detailed description The device and concepts described herein are applicable in a wide range of applications involving message passing algorithms, including decoding LDPC codes and probabilistic inference within graphical machine learning models. Of these, without loss of generality, LDPC coding is chosen as the described example. The background discussion above has detailed the requirement for performing CN processing functions during LDPC decoding. In a practical communication device, these functions may be performed by an LDPC CN processor circuit. However, the following discussions will identify that a conventional implementation of a CN processor circuit for many message passing algorithms suffers from inefficiencies, which degrade the throughput, latency, hardware efficiency and power efficiency of a communication device that implements LDPC decoding. This motivates the subsequent discussions, which describe some example features that aim to provide a solution of an efficient implementation of a CN processor circuit for message passing algorithms. Parallel CN processing FIG. 6 illustrates an example circuit diagram for a CN processor 501 that supports the parallel processing of P PCM rows in a single operation. Here, the example is provided for the case of the 3GPP™ New Radio LDPC code [1], which has a maximum of nc,max=26 core columns. However, a skilled practitioner would appreciate that the schematic could be readily adapted to support any LDPC code, having any number of maximum number nc,max of core columns. As shown in FIG. 6, the example CN processor 501 comprises a number P of one or more independent Node Processor Units (NPUs), where each node processing unit (NPU) 601 supports the CN processing of a single PCM row in a single operation. As shown in FIG. 6, the CN processor 501 has nc,max+l=27 null columns flag inputs 508, which are replicated P number of times in the replication node 610, before each replica is provided as a set of nc,max+l=27 null columns flag inputs 602 to a different one of the P NPUs. Furthermore, the example CN processor 501 accepts a number P of alpha Ji LDGM input LLRs 510, which are provided on the input of the 1-0 port 507 of the example CN processor 501. These are split in the bus splitter 611 and each is provided as an alpha Ji LDGM input LLR 603 to a different one of the P NPUs. Furthermore, the example CN processor 501 accepts a number nc,max' P of alpha J LDPC input LLRs 512, which are provided on the inputs of the nc,max 1-0 ports 504 of the example CN processor 501. These are split in the bus splitter 612 and each set of nc,max alpha J LDPC input LLRs 604 is provided to a different one of the P NPUs. In response, each of the P NPUs provides an alpha J LDGM output LLR 605. This set of P outputs is combined by the bus combiner 613, in order to produce a number P of alpha J LDGM output LLRs 511, which are provided on the output of the 1-0 port 507 of the example CN processor 501. Furthermore, each of the P NPUs provides a set of nc,max alphaj LDPC output LLRs 606. This set of nc,max' P outputs is combined by the bus combiner 614, in order to produce a number nc,max' P of alpha J LDPC output LLRs 513, which are provided on the output of the nc,max 1-0 ports 504 of the example CN processor 501. Furthermore, each of the P NPUs provides a syndrome output bit 607. This set of P outputs is combined by the bus combiner 615, in order to produce a number P of syndrome output bits 509, which are output by the example CN processor 501. At the beginning of each operation of the P NPUs, a set of nc,max' P beta_ij_prev input LLRs is read from the RAM 514. These are split in the bus splitter 617 and each set of nc,max beta_ij_prev input LLRs 609 is provided to a different one of the P NPUs. At the completion of each operation of each of the P NPUs, a set of nc,max betajj output LLRs 608 is generated. This set of nc,max' P betajj output LLRs is combined by the bus combiner 616, before being written to the RAM 514. NPU processing As detailed in the background discussion, the Message Passing Algorithm (MPA) employed by hardware implementations of LDPC decoders is often the Min-Sum Algorithm (MSA), which is a special case of the generalised MPA which benefits from a significantly reduced implementational complexity, compared to the ideal Sum-Product Algorithm (SPA), albeit at the cost of reduced error correction performance. The Adjusted Min-Sum Algorithm (AMSA) is another MPA that achieves an error correction performance which is close to the SPA but with a hardware complexity that is significantly lower. All MPAs may use NPUs as the basis of their computation. FIG. 7 provides an example flow chart 700 for the operation of an NPU 715 that performs the MSA, for the example of the 3GPP™ LDPC code, where nc,max = 26. FIG. 8 provides a more generalised example flow chart 800 for the operation of an NPU 804 that performs any MPA, for the example of the 3GPP™ LDPC code, where nc,max = 26. However, a skilled practitioner would appreciate that either schematic could be readily adapted to support any LDPC code, having any value of nc,max. Here, either the MSA NPU 715 or the MPA NPU 804 may provide the NPU 601 of FIG. 6, in order to select between the MSA or another MPA. Note that both the MSA NPU 715 and the MPA NPU 804 have the same inputs as the NPU 601 of FIG. 6, namely nc,max alpha J LDPC inputs 604, nc,max beta Jj_prev LDPC inputs 609, an alpha Ji LDGM input 603 and nc,max+l null column flags 602. Likewise, both the MSA NPU 715 and the MPA NPU 804 have the same outputs as the NPU 601 of FIG. 6, namely a syndrome bit 607, nc,max alpha J LDPC outputs 606, an alpha J LDGM output 605 and nc,max betajj outputs 608. The MSA NPU 715 includes an MSA Check Node Processor Unit (CNPU) 701, while the MPA NPU 804 includes an MPA Check Node Processor Unit (CNPU) 801. The MPA CNPU contains a computation circuit 802, which is used to perform the MPA core functionality. More specifically, this computation circuit 802 computes the non-linear function of all non-null inputs, in addition to the non-linear function of all nonnull inputs except for the minimum. In the case of the AMSA, a specific non-linear function that may be used is minstar(a,b); alternatively, this computation circuit 802 could perform the core processing of other MPAs, such as the offset min-sum algorithm or the adaptive normalised min-sum algorithm, by utilising different non-linear function operators. Examples herein described focus on computation circuit 802 for MPA core processing. In both the MSA NPU 715 and the MPA NPU 804, nc,max alphaJi LDPC values 716 are calculated at 702 by subtracting the nc,max betajj_prev LDPC inputs 609 from the nc,max alpha J LDPC inputs 604. Following this, each of the nc,max alpha Ji LDPC values 716 and the alpha Ji LDGM input 603 is masked if the corresponding one of the nc,max+l null column flags 602 is enabled at 703. Here, masking is achieved by replacing the alpha Ji value with the maximum positive value +MAX supported by the number representation employed. For example, if an 8-bit two's-complement integer representation is employed, then the maximum positive value supported is +MAX = +127. Alternatively, a fixed-point number representation may be adopted, in which a total number of bits and a number of fraction bits are specified. For example, in the case where 8 bits are used, of which 4 bits are fraction bits, then the maximum value supported is +MAX = 15.9375. A skilled practitioner would recognise that a floating-point implementation could also be realised. Note that in some MPAs such as the AMSA, the nc,max+l null column flags 602 must be additionally applied in a different manner, as detailed below. This is because in contrast to the MSA, setting an alpha Ji value equal to the maximum positive value +MAX supported in a number representation is not fully equivalent to nulling it in the AMSA. To elaborate further, this is because min(alphaji, +MAX) will always equal alpha Ji in the MSA, since each alpha Ji value is required to be less than or equal to +MAX. Hence, any alpha Ji values set to +MAX can be treated identically to all non-nulled alpha Ji values in the MSA CNPU 701 and will not contribute to the search for the minimum and next minimum alpha Ji values, effectively nulling them. However, in the AMSA, minstar(alphaji, +MAX) does not equal alpha Ji in general, even when the alpha Ji value is less than or equal to +MAX. As a result, setting an alpha Ji value to +MAX is not sufficient to exclude it from the calculations of d_app and d_app_notmin detailed in the background discussion above. Note that in contrast to the MSA, the alpha Ji values can be masked to any positive value in the AMSA owing to its requirement for nulling to be additionally applied in a different manner. Hence, it is not necessary to use the maximum supported value +MAX at 703 for the MPA NPU 804, although this is often convenient. In both the MSA NPU 715 and the MPA NPU 804, the nc,max+l alphaJi values may be converted to a different number representation at 704, in order to produce the nc,max+l conditioned alpha Ji values 717. For example, a CN_LLR_WIDTH=6-bit two's-complement integer representation may be employed within the CNPU 701 or 801. Here, the conversion from an 8-bit to a 6-bit two's-complement integer representation may be achieved by saturating any values greater than +31 to +31, as well as by saturating any values lower than -32 to -32. A skilled practitioner would recognise that a fixed-point or floating-point implementation could also be realised. The MSA CNPU 701 takes input from the nc,max+l conditioned alpha Ji values 717, which comprises nc,r activated alpha Ji values and (nc,max+l-nc,r) null values, and outputs the nc,max betajj outputs 608, as well as the nc,max+l CNPU output values 718. In addition to these inputs and outputs, the MPA CNPU 801 may also take input from the nc,max+l null column flags 602. At 705, the sign and magnitude of each of the nc,max+l conditioned alpha Ji values 717 are separated. For example, a conditioned alpha Ji value of +12 has a sign of +1 and a magnitude of 12. Meanwhile, a conditioned alpha Ji value of -7 has a sign of -1 and a magnitude of 7. Furthermore, a conditioned alpha Ji value of 0 has a sign of +1 and a magnitude of 0. Here the sign of a conditioned alpha Ji value may be represented using a single bit. In some examples, the magnitude may be represented using 1 fewer bit than the conditioned alpha Ji value, by saturating the magnitude of the largest-magnitude negative value to be equal to the magnitude of the largest-magnitude positive value. For example, a CN_LLR_WIDTH=6-bit two's-complement integer representation would support conditioned alphaJi values in the range -32...31 (inclusive); the magnitudes of these values could be represented using a 5-bit two's-complement integer representation, if the magnitude of any conditioned alpha Ji value equal to -32 was represented as +31. Alternatively, it is possible to represent the magnitudes using the same number of bits as the conditioned alpha Ji values. At 706, the product of all nc,max+l signs is calculated, which will either be +1 or -1. Following this, at 707 output signs are calculated corresponding to each of the nc,max+l conditioned alpha Ji values 717 by multiplying its corresponding sign input at 706 with the product of signs output at 706. The magnitudes of the nc,max+l conditioned alpha Ji values 717 are referred to as the nc,max+l alpha Ji magnitudes 719, which comprise nc,r activated alpha Ji magnitudes 720 and (nc,max+l-nc,r) null magnitudes 721, and which are processed in parallel with the signs, but this operation differs significantly between the MSA CNPU 701 and the generalised MPA CNPU 801. In the MSA CNPU 701, the indices of the minimum and the next minimum values of the nc,max+l alpha Ji magnitudes 719 (referred to as mini and min2, respectively) are found at 708, as detailed in the background discussion. At 709, scaling may be applied to the minimum and the next minimum values, in order to implement variations of the MSA, such as the offset-min-sum or normalised-min-sum algorithm. Following this, at 710 output magnitudes are assigned corresponding to each of the nc,max+l alpha Ji magnitudes 719. Here, the scaled minimum magnitude is assigned in all but one of the nc,max+l cases, where the scaled next minimum is instead assigned in the case of the magnitude that provided the minimum value. By contrast, in the generalised MPA CNPU 801, the computation circuit 802 performs the MPA core processing to find the values of d_app and d_app_notmin, as detailed in the background discussion. Following this, at 803 output magnitudes are assigned corresponding to each of the nc,max+l alpha Ji magnitudes 719. Here, the d_app is assigned in all but one of the nc,max+l cases, where d_app_notmin is instead assigned in the case of the magnitude that had the minimum value, as detailed in the background discussion and elaborated in the sections below for the present invention. Having determined an output sign at 707 and a magnitude at 710 or 803 corresponding to each of the nc,max+l conditioned alpha Ji values 717, these signs and magnitudes may be combined at 711 and 712. Here, the nc,max+l CNPU output values 718 are produced at 711, while the nc,max betajj outputs 608 are produced at 712. In the latter case, the nc,max betajj outputs 608 may be converted to a different number representation, in order to reduce the number of bits required for a fixed-point number representation, for example. A skilled practitioner would recognise that a floating-point implementation could also be realised. Furthermore, the nc,max betajj outputs 608 may be further compressed at 712 by storing only the minimum and next minimum or d_app and d_app_notmin values in the RAM 514, as well as the minjdx and corresponding sign information. Following the completion of the MSA CNPU 701 or MPA CNPU 801 operation, the nc,max alphaj LDPC outputs 606 and the alphaj LDGM output 605 may be calculated at 713. Here, the nc,max alphaj LDPC outputs 606 are obtained by adding the corresponding ones of the nc,max+l CNPU output values 718 to the nc,max alpha Ji LDPC values 716 and then converting the number representation. For example, a VN_LLR_WIDTH=8-bit two's-complement integer representation may be employed within the CNPU 701 or 801. Here, the conversion to an 8-bit two's-complement integer representation may be achieved by saturating any values greater than +127 to +127, as well as by saturating any values lower than -128 to -128. A skilled practitioner would recognise that a fixed-point or floatingpoint implementation could also be realised. Similarly, the alphaj LDGM output 605 may be obtained by converting the number representation of the corresponding one of the nc,max+l CNPU output values 718. As an additional optional operation, early termination checks may be performed at 714, which may generate the syndrome bit 607. Here, the syndrome bit may be set to one if a parity check is successful, for example. A skilled practitioner would recognise that the hardware complexity implied by the flow diagram 800 of FIG. 8 is dominated by the computation circuit 802, which converts the nc,max+l alphaJi magnitudes 719 and the nc,max+l null columns flag inputs 602 into d_app, d_app_notmin and the minjdx of all nc,r non-null inputs. The following sections will describe three different implementations of the computation circuit 802 for performing the MPA core processing. A first implementation adopts the serial structure that is implied by the data dependencies that must be adhered to in the MPA core processing, but which has the problem of a high critical path length as a result. A second implementation adopts a parallel structure which has the problem of a high hardware complexity. Finally, the third implementation adopts a novel tree structure, which yields a low critical path length and a low hardware complexity, and hence avoids the shortcomings of the first two implementations. Here, a tree structure is defined as a circuit having one or more inputs (or input sets) and one output (or output set), comprising a hierarchical network of a plurality of computation nodes arranged in a number Niayer of layers, with Niayer >= 1. Each computation node receives up to two inputs (or input sets) and generates one output (or output set); data flows unidirectionally from computation nodes in lower-index layers to computation nodes in higher-index layers. Consequently, the number of nodes in the layer having index 'L' is less than or equal to the number of nodes in the layer having index 'L-l', and the layer having index Niayer comprises only a single computation node. More specifically, the inputs (or input sets) to computation nodes in the layer having index '1' are provided by the inputs (or input sets) to the tree structure; the inputs (or input sets) to computation nodes in any layer having index 'L' where 1 <L <= Niayer are each provided by either the output (or output set) of a computation node in a layer having an index less than 'L' or from an input (or input set) to the tree structure. The outputs (or output sets) from computation nodes in any layer having index 'L' where 1 <= L <Niayer are each provided as an input (or input set) to a computation node in a layer having an index greater than 'L'; the output (or output set) of the computation node in the layer having index Niayer is the output (or output set) of the tree structure. Note that it is possible for a tree to contain only a single computation node in a single layer; by definition, this tree has up to two inputs (or input sets) and one output (or output set). A skilled practitioner would recognise that if a regular LDPC code were used, then every row of the basegraph would comprise an equal number of '1' elements and every operation of the computation circuit 802 would have the same number nc,r of non-null alpha Ji magnitudes 719. In this case, nc,max+l can be set equal to nc,r and hence all of the nc,max+l alpha Ji magnitudes 719 will always be non-null. As a result, the nc,max+l null columns flag inputs 602 will never be activated and these inputs can be omitted from the computation circuit 802. An MPA core computation circuit implementation having the problem of a high critical path length FIG. 9 illustrates an example flow diagram 900 for a computation circuit 802 that adopts a serial structure that is implied by the data dependencies associated with the core computations of a generalised MPA, described previously. Meanwhile, FIG. 10 illustrates a corresponding circuit diagram 1000 of the computation circuit 802 for the example application for the 3GPP™ New Radio LDPC code, where nc,max=26. The operation of the MPA core processing begins at 901, where the value and the index (referred to as minimum 909 and min Jdx 902, respectively) of the minimum among the nc,max+l alphaJi magnitudes 719 are found. Here, the minjdx 902 and the minimum 909 may be determined using a set of min operators. Each min operator 1001 has two input magnitudes and one output magnitude, where the output magnitude is set equal to the value of the minimum among the two input magnitudes. Note that if the nc,max+l alpha Ji magnitudes 719 are represented using a two's-complement fixed-point number representation, then the min operator 1001 may be implemented by subtracting one input magnitude from the other and then using the most significant bit (i.e. the sign bit) of the resultant two's-complement fixed-point number to select which input magnitude to output. A skilled practitioner would recognise that a floating-point implementation could also be realised. Additionally, each min operator 1001 takes two indices as additional inputs (not shown in FIG. 10) and provides an index as an additional output (not shown in FIG. 10). Here, the output index may be set equal to the value of whichever of the two input indices corresponds to the input magnitude that has the minimum value. Furthermore, each min operator 1001 may take two null column flags as additional inputs (not shown in FIG. 10) and provide a null column flag as an additional output (not shown in FIG. 10). Here, if a null column flag input is enabled, then the corresponding input magnitude may be ignored when determining the minimum of the two input magnitudes. Furthermore, if both null column flag inputs are enabled, then the null column flag output may be enabled, and an arbitrary value can be chosen for the output magnitude and index. Alternatively, rather than having null columns flag inputs and outputs for the min operators 1001, the MPA NPU 804 may mask the alpha Ji values to the maximum supported positive value +MAX at 703, which has the same effect of causing the input magnitudes for null columns to be ignored in the min operators 1001. In some examples, the set of min operators at 901 may be arranged in a tree structure, comprising nc,max min operators arranged into ceil(log2(nc,max+l)) layers 1003. Here, the 'ceil' function returns the smallest integer that is greater than or equal to its argument. The first layer takes all nc,max+l alpha Ji magnitudes 719 as inputs, together with their indices in the range 1 to nc,max+l (or equivalently 0 to nc,max) and the corresponding null column flags, if provided. The final layer comprises a single min operator 1001, which provides minjdx 902 and minimum 909. Alternatively, other configurations of min operators 1001 could be used, including tree structures with greater numbers of layers. Following this, the nc,max+l null columns flag inputs 602 and the minjdx 902 are processed at 903 to produce an output set of nc,max+l updated null flags 904. This is achieved by enabling the null column flag in the set of nc,max+l null columns flag inputs 602 that has the index minjdx 902. Next, at 905 the nc,max+l alpha Ji magnitudes 719 and the nc,max+l updated null flags 904 are converted into the value of d_app_notmin 906. Here, d_app_notmin 906 may be determined using a set of non-linear function operators. As detailed in a section below, each non-linear function operator 1002 has two input magnitudes (which we may refer to as a and b) and one output magnitude (which we may refer to as nlf(a,b)). In the specific case where the non-linear function operator is performing the minstar function, the output magnitude is given by: nlf(a,b) = minstar(a,b) = min(a,b)+y(a+b)-y( | a-b |), where: y(x) = ln(l+exp(-x)). Note that the minstar expression given here is simpler than the one provided in the background discussion owing to the separation of the signs from the magnitudes of the nc,max+l conditioned alpha Ji values 717 at 705 within the MPA Check Node Processor Unit (CNPU) 801. However, a skilled practitioner would recognise that the more complex formulation of the minstar expression could be used in the MPA core computation circuit 802 if the MPA CNPU 801 did not use a separation of the signs from the magnitudes of the nc,max+l conditioned alpha Ji values 717. Furthermore, each non-linear function operator 1002 may take two null column flags as additional inputs (not shown in FIG. 10) and provide a null column flag as an additional output (not shown in FIG. 10). Here, if a null column flag input is enabled, then the corresponding input magnitude may be ignored when determining the value of the output magnitude, which may instead be set equal to the value of the other input magnitude. Furthermore, if both null column flag inputs are enabled, then the null column flag output may be enabled, and an arbitrary value can be chosen for the output magnitude. In some examples, the set of non-linear function operators at 905 may be arranged in a tree structure, comprising nc,max non-linear function operators arranged into ceil(log2(nc,max+l)) layers 1004. The first layer takes all nc,max+l alpha Ji magnitudes 719 as inputs, together with the corresponding nc,max+l updated null flags 904. The final layer comprises a single non-linear function operator 1002 which provides d_app_notmin 906. Alternatively, other configurations of non-linear function operators 1002 could be used, including tree structures with greater numbers of layers. Finally, d_app 908 is calculated at 907, which may perform a non-linear function operator 1002 to combine minimum 909 with d_app_notmin 906. Alternatively, minjdx 902 may be used to select which of the nc,max+l alpha Ji magnitudes 719 to combine with d_app_notmin 906. Here, an additional layer 1004 of non-linear function operators is required at 907. In total, the serial MPA core of FIG. 10 requires nc,max min operators and nc,max+l nonlinear function operators. These operators are arranged into at least ceil(log2(nc,max+l)) layers of min operators 1003, followed by at least ceil(log2(nc,max+l))+l layers of nonlinear function operators 1004, giving a critical path length of at least 2'ceil(log2(nc,max+l))+l operators. As shall be shown in the following sections, this is a high critical path length. In a hardware implementation of the MPA core of FIG. 10, this high critical path length would result in either a low clock frequency or a requirement for pipelining registers with a pipelining warmup delay, which would result in a low throughput, high latency, low hardware efficiency and / or low energy efficiency. An MPA core computation circuit implementation having the problem of a high hardware complexity FIG. 11 illustrates a circuit diagram 1100 for a computation circuit 802 for performing the MPA core processing that adopts a parallel structure, with example application for the 3GPP™ New Radio LDPC code, where nc,max=26. This circuit achieves a low critical path length relative to the serial structure described in the section above, at the cost of a much higher circuit complexity. Rather than computing the non-linear function of all nonnull inputs 905 after finding the index of the minimum value 901 as in FIG. 10, these two operations are performed concurrently in the parallel structure of FIG. 11. More specifically, nc,max+l repetitions of computing the non-linear function of all non-null inputs 905 (referred to as 1101 in FIG. 11) are performed concurrently, each assuming that a different one of the nc,max+l alpha Ji magnitudes 719 will be identified as the minimum 909 by the minimum finding at 901. Once the nc,max+l repetitions of computing the non-linear function of all non-null inputs 1101 has been completed in parallel with finding the index of the minimum value 901, the resultant minjdx 902 may be used to control the multiplexer 1102, to select the output of the appropriate instance of 1101 to provide d_app_notmin 906. Finally, d_app 908 is calculated at 907, which may be performed using a non-linear function operator 1002 to combine minimum 909 with d_app_notmin 906. Alternatively, minjdx 902 may be used to select which of the nc,max+l alpha Ji magnitudes 719 to combine with d_app_notmin 906. Note that each of the nc,max+l instances of 1101 takes input from a different subset of nc,max alpha Ji magnitudes from the set of nc,max+l alpha Ji magnitudes 719. Furthermore, each instance of 1101 takes input from the corresponding subset of nc,max null column flags from the set of nc,max+l null column flags 602. Owing to this, each instance of 1101 requires only nc,max-l non-linear function operators 1002 arranged into a tree structure comprising at least ceil(log2(nc,max)) layers 1004. As in the serial structure of FIG. 10, the minimum finding operation 901 of FIG. 11 comprises nc,max min operators 1001 arranged into a tree structure comprising at least ceil(log2(nc,max+l)) layers 1003, but these are computed in parallel with the non-linear functions within the nc,max+l instances of 1101. Due to the relative complexity of a non-linear function operator 1002 compared to a min operator 1001, it may be assumed that the path through the tree of ceil(log2(nc,max)) layers 1004 of non-linear function operators is longer than the parallel path through the ceil(log2(nc,max+l)) layers 1003 of min operators. Furthermore, as in the serial structure of FIG. 10, the parallel structure of FIG. 11 requires an additional layer 1004 of non-linear function operators at 907. Hence, the parallel structure of FIG. 11 has a minimum critical path length comprising only ceil(log2(nc,max))+l operators, which is approximately half that of the serial structure of FIG. 10. However, the hardware complexity of the parallel structure of FIG. 11 is approximately nc,max+l times higher than that of the serial structure of FIG. 10. This is because a total of (nc,max+l)'(nc,max-1) non-linear function operators 1002 are required across the nc,max+l instances of 1101, together with the non-linear function operator at 907 and the nc,max min operators 1001 at 901. As a result, the parallel structure may be expected to give a low hardware efficiency and energy efficiency, albeit with a high clock frequency, high throughput and low latency. The following section describes a novel third implementation, which achieves the low critical path length of the parallel structure of FIG. 11 at the same time as approaching the low hardware complexity of the serial structure of FIG. 10, achieving the best of both worlds. A proposed MPA core computation circuit implementation having a low critical path length and a low hardware complexity The present invention is comprised by a proposed computation circuit 802 that utilises a tree structure, which may be used to perform the core processing of any MPA. Like the parallel structure described above, the proposed tree structure computes the non-linear function of all nc,r non-null inputs 905 concurrently with finding the index of the minimum value 901 and hence achieves a low critical path length. However, this is achieved without requiring many parallel instances of the non-linear function computation 905 and so the proposed tree structure also has a low hardware complexity, like the serial structure described above. As a result, the proposed computation circuit targets a high clock frequency, high throughput, low latency, high hardware efficiency and a high energy efficiency. The overall functionality of the computation circuit 802 may be summarised by the flowchart 1800 of FIG. 18, in which at 1801 a set of nc,r values, comprised wholly of the nc,r activated alpha Ji magnitudes 720, is received. At 1802, the minimum of these nc,r values 720 is determined and excluded from the first set of nc,r values 720 in order to derive a second set of nc,r - 1 values. Subsequently, as a result of the processing performed by the proposed tree structure, at 1803 a first output value 908 is calculated as a non-linear function of the first set of nc,r values 720. Finally, at 1804 a second output value 906 is calculated as a non-linear function of the second set of nc,r - 1 values. Note that whilst the flowchart 1800 depicts the operation of the computation circuit 802 in a serialised manner, in practice much of the operations at 1802, at 1803 and at 1804 may be performed concurrently, as described here. An example circuit diagram for a computation circuit 802 adopting the proposed tree structure is illustrated in FIG. 12, with example application for the 3GPP™ New Radio LDPC code, where nc,max=26. The proposed tree structure is composed of several layers, where each layer 1201 comprises a number of computation nodes. More specifically, the proposed tree structure comprises nc,max computation nodes arranged in ceil(log2(nc,max+l)) layers, where the layers are indexed by the index 'L' which adopts values in the range from 1 to ceil(log2(nc,max+l)). Here, each layer 1201 comprises floor( (nc,max+2L T) / (2L)) computation nodes. Here, the 'floor' function returns the largest integer that is less than or equal to its argument. A skilled practitioner would recognise that the same functionality could be achieved by adding some additional layers or adding more computation nodes in some layers, albeit at the cost of increased hardware complexity. The proposed computation circuit 802 comprises three different types of computation nodes, namely ams_leaf, ams_branch and ams_trunk nodes, as described below. However, a skilled practitioner would recognise that it is possible to implement an equivalent computation circuit by re-distributing the functionalities of the computation node types described here into alternative arrangements. Each computation node in an intermediate layer having an index 'L' in the range 2 to ceil(log2(nc,max+l))-l has a particular set of functionality and is referred to as an ams_branch node 1205. Each ams_branch node 1205 includes two non-linear function operators 1002. Here, the non-linear function operators 1002 are performed in parallel with each other, as will be detailed below, hence the critical path length through an ams_branch node 1205 is dominated by the critical path length of a single non-linear function operator 1002. Meanwhile, each computation node in the first layer 1202 (i.e. having the index L=l) has a particular subset of the ams_branch node functionality and is referred to as an ams_leaf node 1204. Each ams_leaf node 1204 includes a single nonlinear function operator 1002. Hence the critical path length through an ams_leaf node 1204 is dominated by the critical path length of a single non-linear function operator 1002. The final layer (i.e. having the index ceil(log2(nc,max+l))) comprises a single computation node, which has a different particular subset of the ams_branch node functionality and is referred to as an ams_trunk node 1206. The ams_trunk node 1206 includes two non-linear function operators 1002. Here the non-linear function operators 1002 are performed in parallel with each other, as will be detailed below, hence the critical path length through an ams_branch node 1205 is dominated by the critical path length of a single non-linear function operator 1002. In some applications, every ams_branch node 1205, amsjeaf node 1204 and ams_trunk node 1206 additionally includes a comparator 1207; alternatively, comparators may be instantiated externally to the computation nodes, with the comparison results provided to the computation nodes as additional inputs (not described here). Note that since the critical path through a nonlinear function operator is typically much longer than that of a comparator, this does not significantly change the critical path length of each computation node. Hence, the critical path length of a computation circuit 802 adopting the proposed tree structure of FIG. 12 is equal to ceil(log2(nc,max+l)) non-linear function operators, which is half that of the serial structure of FIG. 10 and slightly lower than that of the parallel structure of FIG. 11. The hardware complexity of a computation circuit 802 adopting the proposed tree structure of FIG. 12 is dominated by the number of non-linear function operators 1002 implemented, which is given by 2'nc,max- floor((nc,max+l) / 2). This is much lower than the number of non-linear function operators 1002 used by the parallel structure of FIG. 11 and only about 1.5 times that used by the serial structure of FIG. 10. In order to further reduce the critical path length of a computation circuit 802 adopting the proposed tree structure of FIG. 12, the ams_branch nodes 1205 and ams_trunk node 1206 could adopt three non-linear function operators, so that the result of the comparator 1207 does not have to be produced before the non-linear function calculation can begin. In this case, the number of non-linear function operators required is 3'nc,max- 2'floor((nc,max+l) / 2), which is approximately double that used by the serial structure of FIG. 10. Each ams_leaf node 1204 in the first layer 1202 takes input from two of the nc,max+l alphaJi magnitudes 719. In some applications, each amsjeaf node 1204 may additionally take input from the two corresponding null column flags from the nc,max+l null column flags 602; alternatively, these null column flags may not be required, for example if a regular LDPC code were used, or if the corresponding input alpha Ji magnitudes were masked to some value which is ignored by the amsjeaf node's nonlinear function operator 1002. In some applications, each amsjeaf node 1204 may additionally take input from the two corresponding indices in the range 1 to nc,max+l; alternatively, these indices may be processed by an independent minimum-finding circuit which is external to the tree structure described here. Each amsjeaf node 1204 produces a set of outputs, which is provided to an ams_branch node 1205 or ams_trunk node 1206 in a layer having an index greater than 1. Each ams_branch node 1205 in an intermediate layer having an index 'L' in the range 2 to ceil(log2(nc,max+l))-l takes two sets of inputs, which are provided by a different pair of computation nodes in the layer having the index 'L-l'. There is an exception to this however, if the layer having the index 'L-l' has fewer than double the number of computation nodes in the layer having the index 'L'. In this case, one of the ams_branch nodes in the layer having the index 'L' will take one set of its inputs from the layer having the index 'L-l' and the second set of inputs will be taken from a layer having an index less than 'L-l', or will be derived from the set of inputs to the computation circuit 802. An example of the former is shown in FIG. 12, for the layer having the index L=4, which takes one set of inputs from the layer having the index L=2. Likewise, an example of the latter is shown in FIG. 12, for the layer having the index L=2, which takes one set of inputs from the inputs to the computation circuit 802. Each ams_branch node 1205 produces a set of outputs, which is provided to a computation node in a layer having an index greater than 'L'. Finally, the ams_trunk node 1206 in the final layer 1203 having the index L = ceil(log2(nc,max+l)) takes two set of inputs, which are provided by the pair of computation nodes in the layer having the index 'L-l'. There is an exception to this however, if the layer having the index 'L-l' comprises only a single computation node. In this case, the ams_trunk node 1206 will take one set of its inputs from the layer having the index 'L-l' and the second set of inputs will be taken from a layer having an index less than 'L-l'. The ams_trunk node 1206 produces the d_app_notmin 906 and d_app 908 outputs of the computation circuit 802. In some applications, the ams_trunk node additionally produces the minjdx 902 output for the computation circuit 802; alternatively, this minjdx output may be computed by an independent minimum-finding circuit, which is external to the tree structure described here. FIG. 13, FIG. 14 and FIG. 15 illustrate example circuit diagrams 1300,1400 and 1500, respectively, for an ams_branch node 1205, an ams_leaf node 1204 and an ams_trunk node 1206, respectively. The ams_branch node is detailed first below, since the ams_leaf and ams_trunk both represent different specialisations of the more generalised ams_branch node. Ams_branch node operation As shown in FIG. 12, each ams_branch node 1205 takes two sets of inputs, which are derived from a different subset of the nc,max+l alpha Ji magnitudes 719. In some applications, each set of inputs additionally includes the corresponding subsets of null column flags from the nc,max+l null column flags 602 and the corresponding subsets of indices in the range 1 to nc,max+l. For example, each ams_branch node 1205 in the layer having the index L=3 in the example of FIG. 12 has two sets of inputs, each of which are derived from a different subset comprising four of the nc,max+l alpha Ji magnitudes 719, as well as the corresponding null columns flags and indices. In the example of FIG. 13, each of the two sets of inputs to an ams_branch node 1205 comprises six inputs, where each input name has a suffix of '_1' for an input in the first set of inputs and a suffix of'2' for an input in the second set of inputs. A skilled practitioner would recognise that alternative applications exist without some, or all, of the inputs denoted here as being specific to the application depicted in FIG. 13, as described below. For example, a skilled practitioner would recognise that if a regular LDPC code were used, then the in_d_app_null_l 1302, in_d_app_null_2 1301, in_d_app_notmin_null_l 1305, and in_d_app_notmin_null_2 1306 inputs, as well as all associated functionality, can be removed from the ams_branch node 1205. In the example application depicted in FIG. 13, in_min_l 1309 or in_min_2 1310 provides the minimum value among all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719. These values may then be compared to determine which of the subsets contains the minimum value in their union. Here, the union of two sets may be defined as another set containing precisely the elements that belong to either or both of the original sets, with no additional elements. Alternatively, this comparison could be performed externally to the tree of computation nodes, and its result could be provided as an alternative input. In the example application depicted in FIG. 13, injndex_l 1304 or injndex_2 1303 provides the index of the minimum value among all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719. Alternatively, the in Jndex_l 1304 and in Jndex_2 1303 inputs could be removed, if the computation of the minjdx output 902 of the computation circuit 802 was performed externally to the tree of computation nodes. ln_d_app_notmin_l 1311 or in_d_app_notmin_2 1312 provides the non-linear function of all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719, except for that which provides the minimum value among this subset. In_d_app_l 1307 or in_d_app_2 1308 provides the non-linear function of all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719, including that which provides the minimum value among this subset. In the example application depicted in FIG. 13, in_d_app_notmin_null_l 1305 or in_d_app_notmin_null_2 1306 is activated if there are fewer than two non-null magnitudes in the corresponding subset of the nc,max+l alpha Ji magnitudes 719 and hence the corresponding in_d_app_notmin_l 1311 and in_d_app_notmin_2 1312 inputs can be considered to be null and ignored, since at least two non-null magnitudes are needed in order to have at least one magnitude left over when the minimum has been excluded. Alternatively in_d_app_notmin_null_l 1305 or in_d_app_notmin_null_2 1306 are not required if it is known that there will always be at least two non-null magnitudes within the corresponding subset of the nc,max+l alpha Ji magnitudes 719, for example if a regular LDPC code is used. In the example application depicted in FIG. 13, in_d_app_null_l 1302 or in_d_app_null_2 1301 is activated if there are no non-null magnitudes in the corresponding subset of the nc,max+l alpha Ji magnitudes 719 and hence the corresponding in_min_l 1309, in_min_2 1310, injndex_l 1304, injndex_2 1303, in_d_app_l 1307 and in_d_app_2 1308 inputs can be considered to be null and ignored. Alternatively in_d_app_null_l 1302 or in_d_app_null_2 1301 are not required if it is known that there will always be at least one non-null magnitude within the corresponding subset of the nc,max+l alpha Ji magnitudes 719, for example if a regular LDPC code is used. In the case where one set of inputs to an ams_branch node 1205 are derived from the set of inputs to the computation circuit 802 (as exemplified for one of the ams_branch nodes in the layer having the index L=2 in FIG. 12), the corresponding set of six inputs are obtained as: • in_min_l 1309 or in_min_2 1310, when used, is provided by the corresponding magnitude from the nc,max+l alpha Ji magnitudes 719. • injndex_l 1304 or injndex_2 1303, when used, is provided by the corresponding index in the range 1 to nc,max+l. • in_d_app_notmin_l 1311 or in_d_app_notmin_2 1312 can be set to any value, since the configuration of the ams_branch node will prevent this input having any impact on the operation of the computation circuit 802. • in_d_app_l 1307 or in_d_app_2 1308 is provided by the corresponding magnitude from the nc,max+l alpha Ji magnitudes 719. • in_d_app_notmin_null_l 1305 or in_d_app_notmin_null_2, when used, is activated in order to indicate that the value of in_d_app_notmin_l 1311 or in_d_app_notmin_2 1312 should not impact the operation of the computation circuit 802. • in_d_app_nu11_1 1302 or in_d_app_null_2 1301, when used, is provided by the corresponding null column flag from the nc,max+l null column flags 602. As shown in FIG. 12, each ams_branch node 1205 provides one set of outputs, which are directly generated by the ams_branch node 1205 as a function of its two sets of inputs, which are derived from a different subset of the nc,max+l alpha Ji magnitudes 719, and optionally from the corresponding null column flags from the nc,max+l null column flags 602 and the corresponding indices in the range 1 to nc,max+l, as detailed above. As a result, it may be said that the set of outputs generated by an ams_branch node 1205 are indirectly derived from a subset of the nc,max+l alpha Ji magnitudes 719 that is provided by the union of the two subsets that correspond to the two sets of inputs to that ams_branch node, and optionally also from the corresponding null column flags from the nc,max+l null column flags 602 and the corresponding indices in the range 1 to nc,max+l. For example, each ams_branch node 1205 in the layer having the index L=3 in the example of FIG. 12 has one set of outputs, which is indirectly derived from a different subset comprising eight of the nc,max+l alpha Ji magnitudes 719, as well as the corresponding null columns flags and indices. In the example of FIG. 13, the set of outputs provided by an ams_branch node 1205 comprises six outputs; however, a skilled practitioner would recognise that alternative applications exist without some, or all, of the outputs denoted here as being specific to the application depicted in FIG. 13, as described below. For example, a skilled practitioner would recognise that if a regular LDPC code were used, then the out_d_app_null output 1315, out_d_app_notmin_null output 1314 and all associated functionality can be removed from the ams_branch node 1205. In the example application depicted in FIG. 13, out_d_app_null 1315 is activated if both the in_d_app_null_l 1302 and in_d_app_null_2 1301 inputs are activated. In some examples, this may be achieved using an AND gate 1319, although a skilled practitioner would recognise that this depends on how the in_d_app_null_l 1302 and in_d_app_null_2 1301 inputs are represented and that alternative implementations could be used to implement the same effect. In this way, out_d_app_null 1315 is activated if there are no non-null magnitudes in the corresponding subset of the nc,max+l alpha Ji magnitudes 719 and hence the corresponding out_d_app 1316 output, as well as the out_min 1317 and outjndex 1313 outputs where used, can be considered to be null. Note that out_d_app_null 1315 is connected to the in_d_app_null_l 1302 or in_d_app_null_2 1301 input of another computation node of the computation circuit 802. Alternatively, out_d_app_null 1315 is not required if it is known that there will always be at least one non-null magnitude within the corresponding subset of the nc,max+l alpha Ji magnitudes 719, for example if a regular LDPC code is used. In the example application depicted in FIG. 13, out_d_app_notmin_null 1314 is activated if both the in_d_app_null_l 1302 and in_d_app_null_2 1301 inputs are activated, or if both the in_d_app_null_l 1302 and in_d_app_notmin_null_2 1306 inputs are activated, or if both the in_d_app_null_2 1301 and in_d_app_notmin_null_l 1305 inputs are activated. This functionality may be implemented using a set of multiplexers 1320. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_d_app_notmin_null 1314 is activated if there are fewer than two non-null magnitudes in the corresponding subset of the nc,max+l alpha Ji magnitudes 719 and hence the out_d_app_notmin 1318 output can be considered to be null, since at least two non-null magnitudes are needed in order to have at least one magnitude left over when the minimum has been excluded. Note that out_d_app_notmin_null 1314 is connected to the in_d_app_notmin_null_l 1305 or in_d_app_notmin_null_2 1306 of another computation node of the computation circuit 802. Alternatively, out_d_app_notmin_null 1314 is not required if it is known that there will always be at least two non-null magnitudes within the corresponding subset of the nc,max+l alpha Ji magnitudes 719, for example if a regular LDPC code is used. In the example application depicted in FIG. 13, out_min 1317 adopts the minimum value between in_min_l 1309 and in_min_2 1310, unless in_d_app_null_l 1302 or in_d_app_null_2 1301 is activated. If in_d_app_null_l 1302 is activated, then out_min 1317 adopts the value of in_min_2 1310. If in_d_app_null_2 1301 is activated, then out_min 1317 adopts the value of in_min_l 1309. If both in_d_app_null_l 1302 and in_d_app_null_2 1301 are activated, then an arbitrary value can be chosen for out_min 1317. This functionality may be implemented using a comparator 1207, which compares the values of in_min_l 1309 and in_min_2 1310 and identifies the minimum. This may be implemented as a subtractor, which subtracts one of in_min_l 1309 and in_min_2 1310 from the other then checks the sign of the result. Having identified the minimum of in_min_l 1309 and in_min_2 1310, a set of multiplexers 1321 may be used to also consider the values of in_d_app_null_l 1302 and in_d_app_null_2 1301 and select the appropriate value for out_min 1317. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_min 1317 provides the minimum value among all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719. Note that out_min 1317 is connected to the in_min_l 1309 or in_min_2 1310 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_null 1315 is activated and hence an arbitrary value can be chosen for out_min 1317 in this case. Alternatively, this minimum finding could be performed externally to the tree of computation nodes. In the example application depicted in FIG. 13, outjndex 1313 adopts the value of injndex_l 1304 when in_min_l 1309 is less than in_min_2 1310 and adopts the value of injndex_2 1303 when in_min_2 1310 is less than in_min_l 1309. In the case where in_min_l 1309 is equal to in_min_2 1310, an arbitrary selection between injndex_l 1304 and in Jndex_2 1303 may be made for the value of outjndex 1313. More specifically, outjndex 1313 adopts the value of whichever of injndex_l 1304 and injndex_2 1303 corresponds to the minimum of in_min_l 1309 and in_min_2 1310, unless in_d_app_null_l 1302 or in_d_app_null_2 1301 is activated. If in_d_app_null_l 1302 is activated, then outjndex 1313 adopts the value of injndex_2 1303. If in_d_app_null_2 1301 is activated, then outjndex 1313 adopts the value of injndex_l 1304. If both in_d_app_null_l 1302 and in_d_app_null_2 1301 are activated, then an arbitrary value can be chosen for outjndex 1313. This functionality may be implemented using an indexjinder circuit 1322, which takes input from the comparator 1207 and comprises a set of multiplexers. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, outjndex 1313 provides the index of the minimum value among all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719. Note that outjndex 1313 is connected to the inJndex_l 1304 or inJndex_2 1303 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_null 1315 is activated and hence an arbitrary value can be chosen for outjndex 1313 in this case. Alternatively, this minimum index finding could be performed externally to the tree of computation nodes. Out_d_app 1316 adopts the value of the non-linear function of in_d_app_l 1307 and in_d_app_2 1308, unless in_d_app_null_l 1302 or in_d_app_null_2 1301 is activated. If in_d_app_nu11_1 1302 is activated, then out_d_app 1316 adopts the value of in_d_app_2 1308. If in_d_app_null_2 1301 is activated, then out_d_app 1316 adopts the value of in_d_app_l 1307. If both in_d_app_null_l 1302 and in_d_app_null_2 1301 are activated, then an arbitrary value can be chosen for out_d_app 1316. This functionality may be implemented using a non-linear function operator 1002 and a set of multiplexers 1323 to select the value for out_d_app 1316. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_d_app 1316 provides the non-linear function of all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719, including that which provides the minimum value among this subset. Note that out_d_app 1316 is connected to the in_d_app_l 1307 or in_d_app_2 1308 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_null 1315 is activated and hence an arbitrary value can be chosen for out_d_app 1316 in this case. Out_d_app_notmin 1318 adopts the value of the non-linear function of in_d_app_notmin_l 1311 and in_d_app_2 1308 when injndex_l 1304 is selected to provide the value of outjndex 1313 and adopts the value of the non-linear function of in_d_app_notmin_2 1312 and in_d_app_l 1307 when injndex_2 1303 is selected, unless any of in_d_app_notmin_null_l 1305, in_d_app_notmin_null_2 1306, in_d_app_null_l 1302 or in_d_app_null_2 1301 are activated. If in_d_app_null_l 1302 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_notmin_2 1312. If in_d_app_null_2 1301 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_notmin_l 1311. If both in_d_app_null_l 1302 and in_d_app_null_2 1301 are activated, then an arbitrary value can be chosen for out_d_app_notmin 1318. Otherwise, if in_d_app_notmin_null_l 1305 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_2 1308 when injndex_l 1304 is selected to provide the value of outjndex 1313 and adopts the value of the non-linear function of in_d_app_notmin_2 1312 and in_d_app_l 1307 when injndex_2 1303 is selected. Likewise, if in_d_app_notmin_null_2 1306 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_l 1307 when injndex_2 1303 is selected to provide the value of outjndex 1313 and adopts the value of the non-linear function of in_d_app_notmin_l 1311 and in_d_app_2 1308 when injndex_l 1304 is selected. If both in_d_app_notmin_null_l 1305 and in_d_app_notmin_null_2 1306 are active, then out_d_app_notmin 1318 adopts the value of in_d_app_2 1308 when in_index_l 1304 is selected to provide the value of outjndex 1313 and adopts the value of in_d_app_l 1307 when in_index_2 1303 is selected. This functionality may be implemented using a second non-linear function operator 1002 and a set of multiplexers 1324 to select the value for out_d_app_notmin 1318 as a function of the output of the comparator 1207. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_d_app_notmin 1318 provides the non-linear function of all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719, except for that which provides the minimum value among this subset. Note that out_d_app_notmin 1318 is connected to the in_d_app_notmin_l 1311 or in_d_app_notmin_2 1312 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_notmin_null 1314 is activated and hence an arbitrary value can be chosen for out_d_app_notmin 1318 in this case. The processing performed by each computation node, as described above for the case of the ams_branch node, may be summarised by the flowchart 1900 of FIG. 19. Here, each computation node is shown to be associated with a third and a fourth set of values derived in initial operations at 1901 and 1905, whereby each set of values comprises a non-overlapping subset of the first set of nc,r values 720, whereby each subset is independently sized from zero to nc,r values. In subsequent operations at 1902 and 1906, a fifth and a sixth set of values are derived as subsets of the third and fourth sets of values respectively by determining and excluding the minimum value in each of the third and fourth sets of values, respectively. Once the third and fifth sets of values have been determined, in, say in one example, concurrent operations at 1903 and 1904 each computation node receives a first input value 1307 and a third input value 1311 respectively, which are non-linear functions of the third and fifth sets of values, respectively. Similarly, once the fourth and sixth sets of values have been determined, in concurrent operations at 1907 and 1908 each computation node receives a second input value 1308 and a fourth input value 1312 respectively, which are non-linear functions of the fourth and sixth sets of values, respectively. Concurrently to the derivation of the fifth and sixth sets of values and to receiving the first, second, third and fourth input values, a seventh set of values is derived at 1909 as the union of the third and fourth sets of values, before an eighth set of values is then derived at 1910 as a subset of the seventh set of values by determining and excluding the minimum value in the seventh set. At 1911 and 1912, the first, second, third and fourth input values are used to calculate a third output value 1316 which is a non-linear function of the seventh set of values, as well as a fourth output value 1318 which is a non-linear function of the eighth set of values, respectively. Note that as mentioned above, the two non-linear function operators 1002 are performed in parallel with each other in FIG. 13. Hence the critical path through an ams_branch node 1205 includes only one of these operations (plus some multiplexers). Note that the lower non-linear function operator 1002 shown in FIG. 13 is in series with the comparator 1207, since it drives the multiplexers that provide the inputs to the lower non-linear function operator 1002. However, the critical path length could be reduced further by replacing the lower non-linear function operator 1002 with a pair of parallel non-linear function operators 1002, each using a different one of the two possible pairings of the multiplexed inputs. In this way, the comparator 1207 can be operated in parallel with the non-linear function operator 1002 and the result of the comparator 1207 could be used to select which result of the two parallel non-linear function operators 1002 to use. Note that replacing the lower non-linear function operator 1002 with a pair of non-linear function operators 1002 increases the total number of nonlinear function operators used in the ams_branch node 1205 from two to three. amsjeaf node operation As shown in FIG. 12 and FIG. 14, each amsjeaf node 1204 takes two sets of inputs, each of which comprises a different one of the nc,max+l alpha Ji magnitudes 719 (referred to as alpha Ji_magnitude_l 1401 or alpha Ji_magnitude_2 1402). Here, each input name has a suffix of '1' for an input in the first set of inputs and a suffix of '2' for an input in the second set of inputs. In some applications, each set of inputs additionally includes the corresponding null column flag (null_column_flag_l 1403 or null_column_flag_2 1404) from the nc,max+l null column flags 602; alternatively, null_column_flag_l 1403 or null_column_flag_2 1404 are not required if it is known that the corresponding alpha Ji magnitude will never be null, for example if a regular LDPC code is used. In some applications, each set of inputs additionally includes the corresponding index (injndex_l 1405 or injndex_2 1406) in the range 1 to nc,max+l; alternatively, injndex_l 1405 or in Jndex_2 1406 are not required if the computation of the min Jdx output 902 of the computation circuit 802 is performed externally to the tree of computation nodes. As shown in FIG. 12, each amsjeaf node 1204 provides one set of outputs, which are generated by the amsjeaf node 1204 as a function of its two sets of inputs, which comprise two of the nc,max+l alpha Ji magnitudes 719, and optionally from the corresponding null column flags from the nc,max+l null column flags 602 and the corresponding indices in the range 1 to nc,max+l, as detailed above. In the example of FIG. 14, the set of outputs provided by an amsjeaf node 1204 comprises six outputs; however, a skilled practitioner would recognise that alternative applciations exist without some or all of the outputs denoted here as being specific to the application depicted in FIG. 14, as described below. For example, a skilled practitioner would recognise that if a regular LDPC code were used, then the out_d_app_null output 1315, out_d_app_notmin_null output 1314 and all associated functionality can be removed from the amsjeaf node 1204. In the example application depicted in FIG. 14, out_d_app_null 1315 is activated if both the null_column_flag_l 1403 and null_column_flag_2 1404 inputs are activated. In some examples, this may be achieved using an AND gate 1319, although a skilled practitioner would recognise that this depends on how the null_column_flag_l 1403 and null_column_flag_2 1404 inputs are represented and that alternative implementations could be used to implement the same effect. In this way, out_d_app_null 1315 is activated if there are no non-null magnitudes in the corresponding pair of the nc,max+l alpha Ji magnitudes 719 and hence the corresponding out_d_app 1316 output, as well as the out_min 1317 and outjndex 1313 outputs where used, can be considered to be null. Note that out_d_app_null 1315 is connected to the in_d_app_null_l 1302 or in_d_app_null_2 1301 input of another computation node of the computation circuit 802. Alternatively, out_d_app_null 1315 is not required if it is known that there will always be at least one non-null magnitude within the corresponding pair of the nc,max+l alpha Ji magnitudes 719, for example if a regular LDPC code is used. In the example application depicted in FIG. 14, out_d_app_notmin_null 1314 is activated if either of the null_column_flag_l 1403 and null_column_flag_2 1404 inputs are activated. In some examples, this may be achieved using an OR gate 1407, although a skilled practitioner would recognise that this depends on how the null_column_flag_l 1403 and null_column_flag_2 1404 inputs are represented and that alternative implementations could be used to implement the same effect. In this way, out_d_app_notmin_null 1314 is activated if there are fewer than two non-null magnitudes in the corresponding pair of the nc,max+l alpha Ji magnitudes 719 and hence the out_d_app_notmin 1318 output can be considered to be null, since at least two non-null magnitudes are needed in order to have at least one magnitude left over when the minimum has been excluded. Note that out_d_app_notmin_null 1314 is connected to the in_d_app_notmin_null_l 1305 or in_d_app_notmin_null_2 1306 of another computation node of the computation circuit 802. Alternatively, out_d_app_notmin_null 1314 is not required if it is known that both of the corresponding pair of the nc,max+l alpha Ji magnitudes 719 will always be non-null, for example if a regular LDPC code is used. In the example application depicted in FIG. 14, out_min 1317 adopts the minimum value between alphaji_magnitude_l 1401 and alphaji_magnitude_2 1402, unless null_column_flag_l 1403 or null_column_flag_2 1404 is activated. If null_column Jlag_l 1403 is activated, then out_min 1317 adopts the value of alpha Ji_magnitude_2 1402. If null_column_flag_2 1404 is activated, then out_min 1317 adopts the value of alphaji_magnitude_l 1401. If both null_column_flag_l 1403 and null_column_flag_2 1404 are activated, then an arbitrary value can be chosen for out_min 1317. This functionality may be implemented using a comparator 1207, which compares the values of alpha Ji_magnitude_l 1401 and alpha Ji_magnitude_2 1402 and identifies the minimum. This may be implemented as a subtractor, which subtracts one of alpha Ji_magnitude_l 1401 and alpha Ji_magnitude_2 1402 from the other then checks the sign of the result. Having identified the minimum of alpha Ji_magnitude_l 1401 and alphaji_magnitude_2 1402, a set of multiplexers 1321 may be used to also consider the values of null_column_flag_l 1403 and null_column_flag_2 1404 and select the appropriate value for out_min 1317. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_min 1317 provides the minimum value among all non-null magnitudes from the corresponding pair of the nc,max+l alpha Ji magnitudes 719. Note that out_min 1317 is connected to the in_min_l 1309 or in_min_2 1310 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_null 1315 is activated and hence an arbitrary value can be chosen for out_min 1317 in this case. Alternatively, this minimum finding could be performed externally to the tree of computation nodes. In the example application depicted in FIG. 14, outjndex 1313 adopts the value of in_index_l 1405 when alphaji_magnitude_l 1401 is less than alpha_ji_magnitude_2 1402 and adopts the value of in_index_2 1406 when alphaji_magnitude_2 1402 is less than alphaji_magnitude_l 1401. In the case where alphaji_magnitude_l 1401 is equal to alpha Ji_magnitude_2 1402, an arbitrary selection between in_index_l 1405 and in_index_2 1406 may be made for the value of outjndex 1313. More specifically, outjndex 1313 adopts the value of whichever of injndex_l 1405 and injndex_2 1406 corresponds to the minimum of alpha Ji_magnitude_l 1401 and alpha Ji_magnitude_2 1402, unless null_column_flag_l 1403 or null_column_flag_2 1404 is activated. If null_column_flag_l 1403 is activated, then outjndex 1313 adopts the value of injndex_2 1406. If null_column_flag_2 1404 is activated, then outjndex 1313 adopts the value of injndex_l 1405. If both null_column_flag_l 1403 and null_column_flag_2 1404 are activated, then an arbitrary value can be chosen for outjndex 1313. This functionality may be implemented using an index_finder circuit 1322, which takes input from the comparator 1207 and comprises a set of multiplexers. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, outjndex 1313 provides the index of the minimum value among all non-null magnitudes from the corresponding pair of the nc,max+l alphaJi magnitudes 719. Note that outjndex 1313 is connected to the injndex_l 1304 or injndex_2 1303 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_null 1315 is activated and hence an arbitrary value can be chosen for outjndex 1313 in this case. Alternatively, this minimum index finding could be performed externally to the tree of computation nodes. out_d_app 1316 adopts the value of the non-linear function of alpha Ji_magnitude_l 1401 and alphaji_magnitude_2 1402, unless null_column_flag_l 1403 or null_column_flag_2 1404 is activated. If null_column_flag_l 1403 is activated, then out_d_app 1316 adopts the value of alpha Ji_magnitude_2 1402. If null_column_flag_2 1404 is activated, then out_d_app 1316 adopts the value of alpha Ji_magnitude_l 1401. If both null_column_flag_l 1403 and null_column_flag_2 1404 are activated, then an arbitrary value can be chosen for out_d_app 1316. This functionality may be implemented using a non-linear function operator 1002 and a set of multiplexers 1323 to select the value for out_d_app 1316. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_d_app 1316 provides the non-linear function of all non-null magnitudes from the corresponding pair of the nc,max+l alpha Ji magnitudes 719, including that which provides the minimum value among this pair. Note that out_d_app 1316 is connected to the in_d_app_l 1307 or in_d_app_2 1308 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_null 1315 is activated and hence an arbitrary value can be chosen for out_d_app 1316 in this case. out_d_app_notmin 1318 adopts the maximum value between alphaji_magnitude_l 1401 and alphaji_magnitude_2 1402, unless null_column_flag_l 1403 or null_column_flag_2 1404 is activated. If either null_column_flag_l 1403 or null_column_flag_2 1404 are activated, then an arbitrary value can be chosen for out_d_app_notmin 1318. This functionality may be implemented using the comparator 1207 and a multiplexer 1408 to select the appropriate value for out_d_app_notmin 1318. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_d_app_notmin 1318 provides the non-linear function of all non-null magnitudes from the corresponding pair of the nc,max+l alpha Ji magnitudes 719, except for that which provides the minimum value among this pair. Note that out_d_app_notmin 1318 is connected to the in_d_app_notmin_l 1311 or in_d_app_notmin_2 1312 of another computation node of the computation circuit 802. As detailed above, this input will be ignored by this other computation node if out_d_app_notmin_null 1314 is activated and hence an arbitrary value can be chosen for out_d_app_notmin 1318 in this case. Note that as mentioned above, the comparator 1207 and the non-linear function operator 1002 are both performed in parallel with each other in FIG. 14. Hence the critical path through an amsjeaf node 1204 is equal to the longest one of these operations (plus some multiplexers). Note that the comparator 1207 shown in FIG. 14 could be removed by taking an additional output from the non-linear function operator 1002, which naturally includes a comparator function, as discussed in a section below. The result of this comparator function could be output by the non-linear function operator 1002 and used to drive the various multiplexers shown in FIG. 14. ams_trunk node operation As shown in FIG. 12, the ams_trunk node 1206 takes two sets of inputs, which are derived from a different subset of the nc,max+l alpha Ji magnitudes 719. In some applications, each set of inputs additionally includes the corresponding null column flags from the nc,max+l null column flags 602 and the corresponding indices in the range 1 to nc,max+l. For example, the ams_trunk node 1206 in the example of FIG. 12 has a first set of inputs that is derived from a subset comprising sixteen of the nc,max+l=27 alpha Ji magnitudes 719, as well as the corresponding null columns flags and indices. The ams_trunk node 1206 in the example of FIG. 12 also has a second set of inputs that is derived from a subset comprising the remaining eleven of the nc,max+l=27 alpha Ji magnitudes 719, as well as the corresponding null columns flags and indices. In the example of FIG. 15, each of the two sets of inputs to the amsjrunk node 1206 comprises six inputs, where each input name has a suffix of '_1' for an input in the first set of inputs and a suffix of'2' for an input in the second set of inputs. A skilled practitioner would recognise that alternative applications exist without some or all of the inputs denoted here as being specific to the application depicted in FIG. 15, as described below. For example, a skilled practitioner would recognise that if a regular LDPC code were used, then the in_d_app_null_l 1302, in_d_app_null_2 1301, in_d_app_notmin_null_l 1305 and in_d_app_notmin_null_2 1306 inputs can be removed from the amsjrunk node 1206, together with all associated functionality. In the example application depicted in FIG. 15, in_min_l 1309 or in_min_2 1310 provides the minimum value among all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719. These values may then be compared to determine which of the subsets contains the minimum value in their union. Alternatively, this comparison could be performed externally to the tree of computation nodes, and its result could be provided as an alternative input. In the example application depicted in FIG. 15, injndex_l 1304 or injndex_2 1303 provides the index of the minimum value among all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719. Alternatively, the in Jndex_l 1304 and in Jndex_2 1303 inputs could be removed, if the computation of the minjdx output 902 of the computation circuit 802 was performed externally to the tree of computation nodes. in_d_app_notmin_l 1311 or in_d_app_notmin_2 1312 provides the non-linear function of all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719, except for that which provides the minimum value among this subset. in_d_app_l 1307 or in_d_app_2 1308 provides the non-linear function of all non-null magnitudes from the corresponding subset of the nc,max+l alpha Ji magnitudes 719, including that which provides the minimum value among this subset. In the example application depicted in FIG. 15, in_d_app_notmin_null_l 1305 or in_d_app_notmin_null_2 1306 is activated if there are fewer than two non-null magnitudes in the corresponding subset of the nc,max+l alpha Ji magnitudes 719 and hence the corresponding in_d_app_notmin_l 1311 and in_d_app_notmin_2 1312 inputs can be considered to be null and ignored, since at least two non-null magnitudes are needed in order to have at least one magnitude left over when the minimum has been excluded. Alternatively in_d_app_notmin_null_l 1305 or in_d_app_notmin_null_2 1306 are not required if it is known that there will always be at least two non-null magnitudes within the corresponding subset of the nc,max+l alpha Ji magnitudes 719, for example if a regular LDPC code is used. In the example application depicted in FIG. 15, in_d_app_null_l 1302 or in_d_app_null_2 1301 is activated if there are no non-null magnitudes in the corresponding subset of the nc,max+l alpha Ji magnitudes 719 and hence the corresponding in_min_l 1309, in_min_2 1310, injndex_l 1304, injndex_2 1303, in_d_app_l 1307 and in_d_app_2 1308 inputs can be considered to be null and ignored. Alternatively in_d_app_null_l 1302 or in_d_app_null_2 1301 are not required if it is known that there will always be at least one non-null magnitude within the corresponding subset of the nc,max+l alpha Ji magnitudes 719, for example if a regular LDPC code is used. As shown in FIG. 12, the ams_trunk node 1206 provides one set of outputs, which are directly generated by the ams_trunk node 1206 as a function of its two sets of inputs, which are derived from a different subset of the nc,max+l alpha Ji magnitudes 719, and optionally from the corresponding null column flags from the nc,max+l null column flags 602 and the corresponding indices in the range 1 to nc,max+l, as detailed above. As a result, it may be said that the set of outputs generated by the ams_trunk node 1206 are indirectly derived from the entire set of the nc,max+l alpha Ji magnitudes 719 that is provided by the union of the two subsets that correspond to the two sets of inputs to that ams_trunk node, and optionally also from the corresponding null column flags from the nc,max+l null column flags 602 and the corresponding indices in the range 1 to nc,max+l. For example, the ams_trunk node 1206 in the example of FIG. 12 has one set of outputs, which is indirectly derived from the complete set of the nc,max+l=27 alpha Ji magnitudes 719, as well as the corresponding null columns flags and indices. In the example of FIG. 15, the set of outputs provided by the ams_trunk node 1206 comprises three outputs; however, a skilled practitioner would recognise that alternative applications exist without the outjndex 1313 output denoted here as being specific to the application depicted in FIG. 15, as described below. In the example application depicted in FIG. 15, outjndex 1313 adopts the value of injndex_l 1304 when in_min_l 1309 is less than in_min_2 1310 and adopts the value of injndex_2 1303 when in_min_2 1310 is less than in_min_l 1309. In the case where in_min_l 1309 is equal to in_min_2 1310, an arbitrary selection between injndex_l 1304 and injndex_2 1303 may be made for the value of outjndex 1313. More specifically, outjndex 1313 adopts the value of whichever of injndex_l 1304 and injndex_2 1303 corresponds to the minimum of in_min_l 1309 and in_min_2 1310, unless in_d_app_null_l 1302 or in_d_app_null_2 1301 is activated. If in_d_app_null_l 1302 is activated, then outjndex 1313 adopts the value of injndex_2 1303. If in_d_app_null_2 1301 is activated, then outjndex 1313 adopts the value of injndex_l 1304. It should never be the case that both in_d_app_null_l 1302 and in_d_app_null_2 1301 are activated at the same time. This functionality may be implemented using a comparator 1207, which compares the values of in_min_l 1309 and in_min_2 1310 and identifies the minimum. This may be implemented as a subtractor, which subtracts one of in_min_l 1309 and in_min_2 1310 from the other then checks the sign of the result. Having identified the minimum of in_min_l 1309 and in_min_2 1310, the rest of the functionality may be implemented using an index_finder circuit 1322, which takes input from the comparator 1207 and comprises a set of multiplexers. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, outjndex 1313 provides the index of the minimum value among all non-null magnitudes from the complete set of the nc,max+l alpha Ji magnitudes 719. Note that outjndex 1313 provides the minjdx 902 output for the computation circuit 802. Alternatively, this minimum index finding could be performed externally to the tree of computation nodes. out_d_app 1316 adopts the value of the non-linear function of in_d_app_l 1307 and in_d_app_2 1308, unless in_d_app_null_l 1302 or in_d_app_null_2 1301 is activated. If in_d_app_nu11_1 1302 is activated, then out_d_app 1316 adopts the value of in_d_app_2 1308. If in_d_app_null_2 1301 is activated, then out_d_app 1316 adopts the value of in_d_app_l 1307. It should never be the case that both in_d_app_null_l 1302 and in_d_app_null_2 1301 are activated at the same time. This functionality may be implemented using a non-linear function operator 1002 and a set of multiplexers 1323 to select the value for out_d_app 1316. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_d_app 1316 provides the non-linear function of all non-null magnitudes from the complete set of the nc,max+l alpha Ji magnitudes 719, including that which provides the minimum value among this set. Note that out_d_app 1316 provides the d_app 908 output of the computation circuit 802. out_d_app_notmin 1318 adopts the value of the non-linear function of in_d_app_notmin_l 1311 and in_d_app_2 1308 when injndex_l 1304 is selected to provide the value of outjndex 1313 and adopts the value of the non-linear function of in_d_app_notmin_2 1312 and in_d_app_l 1307 when injndex_2 1303 is selected, unless any of in_d_app_notmin_null_l 1305, in_d_app_notmin_null_2 1306, in_d_app_null_l 1302 or in_d_app_null_2 1301 are activated. If in_d_app_null_l 1302 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_notmin_2 1312. If in_d_app_null_2 1301 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_notmin_l 1311. It should never be the case that both in_d_app_null_l 1302 and in_d_app_null_2 1301 are activated at the same time. Otherwise, if in_d_app_notmin_null_l 1305 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_2 1308 when injndex_l 1304 is selected to provide the value of outjndex 1313 and adopts the value of the non-linear function of in_d_app_notmin_2 1312 and in_d_app_l 1307 when injndex_2 1303 is selected. Likewise, if in_d_app_notmin_null_2 1306 is activated, then out_d_app_notmin 1318 adopts the value of in_d_app_l 1307 when injndex_2 1303 is selected to provide the value of outjndex 1313 and adopts the value of the non-linear function of in_d_app_notmin_l 1311 and in_d_app_2 1308 when injndex_l 1304 is selected. If both in_d_app_notmin_null_l 1305 and in_d_app_notmin_null_2 1306 are active, then out_d_app_notmin 1318 adopts the value of in_d_app_2 1308 when injndex_l 1304 is selected to provide the value of outjndex 1313 and adopts the value of in_d_app_l 1307 when injndex_2 1303 is selected. This functionality may be implemented using a second non-linear function operator 1002 and a set of multiplexers 1324 to select the value for out_d_app_notmin 1318 as a function of the output of the comparator 1207. However, a skilled practitioner would recognise that the functionality could also be achieved using various configurations of logic gates, for example. In this way, out_d_app_notmin 1318 provides the non-linear function of all non-null magnitudes from the complete set of the nc,max+l alpha Ji magnitudes 719, except for that which provides the minimum value among this set. Note that out_d_app_notmin 1318 provides the d_app_notmin 906 output of the computation circuit 802. Note that as mentioned above, the two non-linear function operators 1002 are performed in parallel with each other in FIG. 15. Hence the critical path through an ams_branch node 1205 includes only one of these operations (plus some multiplexers). Note that the lower non-linear function operator 1002 shown in FIG. 15 is in series with the comparator 1207, since it drives the multiplexers that provide the inputs to the lower non-linear function operator 1002. However, the critical path length could be reduced further by replacing the lower non-linear function operator 1002 with a pair of parallel non-linear function operators 1002, each using a different one of the two possible pairings of the multiplexed inputs. In this way, the comparator 1207 can be operated in pa ra I Ie I with the non-linear function operator 1002 and the result of the comparator 1207 could be used to select which result of the two parallel non-linear functions operators 1002 to use. Note that replacing the lower non-linear function operator 1002 with a pair of non-linear function operators 1002 increases the total number of nonlinear function operators used in the ams_trunk node 1206 from two to three. Minstar operator As mentioned above, each non-linear function operator 1002 has two input magnitudes (which we may refer to as 'a' 1601 and 'b' 1602) and one output magnitude (which we may refer to as nlf(a,b) 1603. In the specific case where the non-linear function operator is performing the minstar function, the output magnitude is given by: nlf(a,b) = minstar(a,b) = min(a,b)+y(a+b)-y( | a-b |), where: y(x) = ln(l+exp(-x)). FIG. 16 illustrates an example circuit diagram 1600 for a non-linear function operator 1002 performing the minstar(a,b) equation described above. This input to the non-linear function operator 1002 is a pair of unsigned fixed-point binary numbers 'a' 1601 and 'b' 1602, which each comprise Wc-1 bits, including Wf bits for the fraction part of the fixed-point number representation. Note that Wc-1 bits may be used, since performing an absolute operator to find the magnitude of a Wc-bit two's complement fixed-point number will always produce a sign bit of zero, which can be discarded. The output nlf(a,b) 1603 of the non-linear function operator 1002 is also an unsigned fixed-point binary number, comprising Wc-1 bits and including Wf bits for the fraction part. Since nlf(a,b) 1603 uses the same number representation as 'a' 1601 and 'b' 1602, successive nonlinear function operators 1002 can be daisy-chained with no number representation conversion required. An addition circuit 1605 may be used to obtain the intermediate result a+b 1604, which may be represented as an unsigned fixed-point binary number, comprising Wc bits (to avoid overflow) and including Wf bits for the fraction part. Meanwhile, the intermediate result min(a,b) 1606 may be obtained using a comparator 1607 to determine which of 'a' 1601 and 'b' 1602 has the minimum value and using a multiplexer 1608 to select this value for min(a,b) 1606, which may be represented as an unsigned fixed-point binary number, comprising Wc-1 bits and including Wf bits for the fraction part. Note that the comparator may be implemented by prepending a zero-valued sign bit to each of its inputs and then performing a two's-complement subtraction and inspecting the value of the result's the sign bit. Similarly, the intermediate result max(a,b) 1609 may be obtained using the output of the comparator 1607 to determine which of 'a' 1601 and 'b' 1602 has the maximum value and using a multiplexer 1610 to select this value for max(a,b) 1609, which may be represented as an unsigned fixed-point binary number, comprising Wc-1 bits and including Wf bits for the fraction part. Following this, the intermediate result | a-b| 1611 may be obtained by using a subtraction circuit 1612 to perform the subtraction of min(a,b) 1606 from max(a,b) 1609. Again, the intermediate result | a-b | 1611 may be represented as an unsigned fixed-point binary number, comprising Wc-1 bits and including Wf bits for the fraction part. A look-up table (LUT) circuit 1613 may be used to convert the intermediate results a+b 1604 and | a-b | 1611 into the intermediate results y(a+b) 1614 and y( | a-b |) 1615. These results may comprise only Wf fraction bits, since the value of y(x)=ln(l+exp(-x)) is guaranteed to be less than 1. These results may therefore be determined by comparing the input a+b 1604 or | a-b | 1611 against up to 2wf-l pre-calculated values. Each comparison may be implemented by prepending a zero-valued sign-bit to each input of the comparison and then performing a two's-complement subtraction and inspecting the result's sign bit. The complete set of comparisons can be implemented in hardware using a binary search tree structure in order to minimise the associated critical path length. Example plots of the fixed-point LUT output against the true floating-point value are provided in FIG. 17 for Wf=2 1701 and Wf=3 1702. Here, the inputs and outputs of the LUT 1613 are depicted using their fixed-point fractional representation, where every value that can be represented by a fixed-point number is a multiple of 0.25 for Wf=2 and a multiple of 0.125 for Wf=3. Following this, an addition circuit 1616 may be used to add min(a,b) 1606 to y(a+b) 1614 to produce the intermediate result min(a,b)+y(a+b) 1617, which may be represented as an unsigned fixed-point binary number, comprising Wc-1 bits and including Wf bits for the fraction part. Note that there is no danger of this addition overflowing, since y(a+b) 1614 only adopts a large value when 'a' 1601 and 'b' 1602 are small, in which case min(a,b) 1606 will be small. Finally, a subtraction circuit 1618 may be used to subtract y( | a-b |) 1615 from min(a,b)+y(a+b) 1617, in order to produce the output nlf(a,b) 1603. A skilled practitioner would recognise that the non-linear function operator 1002 functionality could also be implemented using alternative circuits, which perform the various operations in a different order, for example. Furthermore, a skilled practitioner would recognise that a floating-point implementation could also be realised. Application In the foregoing specification, the invention has been described with reference to specific examples of embodiments. It will, however, be evident that various modifications and changes may be made therein without departing from the scope of the invention as set forth in the appended claims and that the claims are not limited to the specific examples described above. The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals. Those skilled in the art will recognize that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. Any arrangement of components to achieve the same functionality is effectively 'associated' such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as 'associated with' each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being 'operably connected,' or 'operably coupled,' to each other to achieve the desired functionality. Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. The present invention is herein described with reference to an integrated circuit device comprising, say, a microprocessor configured to perform the functionality of a LDPC computation. However, it will be appreciated that the present invention is not limited to such integrated circuit devices, and may equally be applied to integrated circuit devices comprising any alternative type of operational functionality. Examples of such integrated circuit device comprising alternative types of operational functionality may include, by way of example only, application-specific integrated circuit (ASIC) devices, field-programmable gate array (FPGA) devices, or integrated with other components, etc. Furthermore, because the illustrated embodiments may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details have not been explained in any greater extent than that considered necessary, for the understanding and appreciation of the underlying concepts and in order not to obfuscate or distract from the teachings herein. Alternatively, the circuit and / or component examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner. Also for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type. Also, the examples are not limited to physical devices or units implemented in nonprogrammable hardware but can also be applied in programmable devices or units able to perform the desired LDPC computation by operating in accordance with suitable program code, such as minicomputers, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices, commonly denoted in this application as 'computer systems'. However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms 'a' or 'an,' as used herein, are defined as at least one than one. Also, the use of introductory phrases such as 'at least one' and 'at least one' in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles 'a' or 'an' limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases 'at least one' or 'at least one' and indefinite articles such as 'a' or 'an.' The same holds true for the use of definite articles. Unless stated otherwise, terms such as 'first' and 'second' are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage. The word 'subset' refers to a selection of elements from a set, where that selection may comprise one, some or all of the elements in the set. References [1] "3rd Generation Partnership Project; Technical Specification Group Radio Access Network; NR; Multiplexing and channel coding (Release 15)", 3GPP™ TS 38.212 V15.2.0, June 2018. [2] K. Shimizu, T. Ishikawa, N. Togawa, T. Ikenaga, and S. Goto, "Partially-parallel LDPC decoder based on high-efficiency message- passing algorithm," in Proc. Int. Conf. Comput. Design, Oct. 2005, pp. 503-510. [3] X. Wu, Y. Song, M. Jiang and C. Zhao, "Adaptive-Normalized / Offset Min-Sum Algorithm," in IEEE Communications Letters, vol. 14, no. 7, pp. 667-669, July 2010. [4] C. Jones, E. Valles, M. Smith and J. Villasenor, "Approximate-MIN constraint node updating for LDPC code decoding," IEEE Military Communications Conference, 2003. MILCOM 2003., Boston, MA, USA, 2003, pp. 157-162 Vol.l.

Claims

1. A device for processing message passing algorithms comprising:a computation circuit (802) arranged to receive a first set of nc,r values (720), and arranged to provide:a first output value (908) that is calculated as a non-linear function of the first set of nc,r values (720);a second output value (906) that is calculated as a non-linear function of a second set of values, wherein the second set of values comprises nc,r-l values that are derived from the first set of nc,r values (720) by excluding a minimum value in the first set of nc,r values (720);wherein the computation circuit (802) comprises a network of a plurality of computation nodes (1204,1205,1206) arranged in a tree structure with two or more layers (1201), wherein at least one upper layer receives top-level circuit input values, and wherein output values from each upper layer serve as input values to one or more lower layers, with output values from a final layer constituting top-level circuit output values, and wherein at least one of the plurality of computation nodes (1205,1206) is associated with a third set of values and a fourth set of values, wherein each of the third set of values and fourth set of values are subsets of the first set of nc,r values (720) and wherein each of the third and fourth sets of values comprises a number of values that is a number in a range from zero to nc,r inclusive, and wherein the at least one of the plurality of computation nodes (1205, 1206) is arranged to receive:a first input value (1307) that is a non-linear function of the third set of values;a second input value (1308) that is a non-linear function of the fourth set of values;a third input value (1311) that is a non-linear function of a fifth set of values, wherein the fifth set of values is a subset of the first set of nc,r values (720) that is derived from the third set of values by excluding a minimum value in the third set of values; anda fourth input value (1312) that is a non-linear function of a sixth set of values, wherein the sixth set of values is a subset of the first set of nc,r values (720) that is derived from the fourth set of values by excluding a minimum value in the fourth set of values;and wherein the at least one of the plurality of computation nodes (1205,1206) provides:a third output value (1316) that is calculated as a non-linear function of a seventh set of values, wherein the seventh set of values is a further subset of the first set of nc,r values (720) that constitutes a union of the third set of values and fourth set of values; anda fourth output value (1318) that is calculated as a non-linear function of an eighth set of values, wherein the eighth set of values is a subset of the first set of nc,r values (720) that is derived from the seventh set of values by excluding a minimum value in the seventh set of values.

2. The device of Claim 1, wherein the plurality of computation nodes (1204,1205,1206) comprises:one or more non-linear function circuits (1002) configured to provide at least one of the third output value (1316) and the fourth output value (1318) and to receive at least two of the first input value (1307), the second input value (1308), the third input value (1311) and the fourth input value (1312); andone or more multiplexer circuits (1324,1408) operably coupled to provide at least one of the first input value (1307), the second input value (1308), the third input value (1311) and the fourth input value (1312) to at least one of the third output value (1316) and the fourth output value (1318) depending on which of the third set of values or fourth set of values contains the minimum value in the seventh set of values, wherein the minimum value in the seventh set is determined by minimum-finding circuitry, located either:internally to the plurality of computation nodes (1204,1205,1206) and operably coupled to the one or more multiplexer circuits (1324,1408) directly; orexternally to the plurality of computation nodes (1204,1205,1206) and configured to provide an additional input value to the plurality of computation nodes (1204, 1205,1206) indicative of the result.

3. The device of Claim 2, wherein the one or more non-linear function circuits (1002) is arranged to perform at least one of the following operations on input values that it receives, and to provide a result as at least one of the third output value (1316) and the fourth output value (1318):(i) a minimum function and one or more arithmetic additions; or(ii) an inverse hyperbolic tangent function and two hyperbolic tangent functions.

4. The device of any preceding claim, wherein a number of layers in the two or more layers (1201) in the tree structure is at least: ceil(log2(nc,r)).

5. The device of Claim 4, wherein a layer of the two or more layers (1201), having an index 'L' in a range of '1' to the number of layers (1201), comprises a number of computation nodes (1204,1205,1206), wherein the number of computation nodes (1204, 1205,1206) in the layer is at least: floor((nc,r+2L-1-1) / (2L)).

6. The device of any preceding claim, wherein the plurality of computation nodes (1204, 1205,1206) further comprises a comparator circuit (1207) configured to identify which of the third set of values or fourth set of values contains the minimum value in the seventh set of values; and wherein the at least one of the plurality of computation nodes (1205,1206) is further arranged to receive:a fifth input value (1309) that is equal to the minimum value in the third set of values; anda sixth input value (1310) that is equal to the minimum value in the fourth set of values.

7. The device of Claim 6, wherein the at least one of the plurality of computation nodes (1205) further provides a fifth output value (1317) that is equal to the minimum value in the seventh set of values.

8. The device of any preceding claim, wherein the computation circuit (802) further provides a sixth output value (902) that is an index of the minimum value in the first set of nc,r values (720).

9. The device of Claim 8, wherein the at least one of the plurality of the computation nodes (1205,1206) is further arranged to receive:a seventh input value (1304) that is an index of the minimum value in the third set of values;an eighth input value (1303) that is an index of the minimum value in the fourth set of values;and wherein the at least one of the plurality of computation nodes (1205,1206) further provides a seventh output value (1313) that is an index of the minimum value in the seventh set of values;and wherein the plurality of computation nodes (1204,1205,1206) further comprises an index finder circuit (1322) arranged to set the seventh output value (1313) as equal to either one of:the seventh input value (1304) when the third set of values contains the minimum value in the seventh set of values, orthe eighth input value (1303) when the fourth set of values contains the minimum value in the seventh set of values.

10. The device of any preceding claim, wherein the computation circuit (802) is further arranged to receive external inputs of:a set of (nc,max+l-nc,r) null values (721);a set of nc,r deactivated null column flags (602);a set of (nc,max+l-nc,r) activated null column flags (602);wherein each one of the set of nc,r deactivated null column flags (602) corresponds to a corresponding one of the values in the first set of nc,r values (720) and each one of the set of (nc,max+l-nc,r) activated null column flags corresponds to a corresponding one of the values in the set of (nc,max+l-nc,r) null values (721), and the value of each null column flag indicates whether the corresponding one of the values is provided by the first set of nc,r values (720) or by the set of (nc,max+l-nc,r) null values (721).

11. The device of Claim 10, wherein the at least one of the plurality of computation nodes (1205,1206) further comprises at least two of:a ninth input value (1302) that indicates when the third set of values has a size of zero;a tenth input value (1301) that indicates when the fourth set of values has a size of zero;an eleventh input value (1305) that indicates when the fifth set of values has a size of zero; anda twelfth input value (1306) that indicates when the sixth set of values has a size ofzero.

12. The device of Claim 11, wherein the at least one of the plurality of computation nodes (1205,1206) is further configured to, in the calculation of the third output value (1316) and the calculation of the fourth output value (1318):ignore the first input value (1307) when the ninth input value (1302) indicates that the third set of values has a size of zero, andignore the second input value (1308) when the tenth input value (1301) indicates that the fourth set of values has a size of zero, and wherein the at least one of the plurality of computation nodes (1205,1206) is further configured to, in the calculation of the fourth output value (1318):ignore the third input value (1311) when the ninth input value (1302) or eleventh input value (1305) indicates that the fifth set of values has a size of zero, andignore the fourth input value (1312) when the tenth input value (1301) or twelfth input value (1306) indicates that the sixth set of values has a size of zero.

13. The device of Claim 11 when dependent on claim 7, wherein the at least one of the plurality of computation nodes (1205) is further configured to:ignore the fifth input value (1309) when the ninth input value (1302) indicates that the third set of values has a size of zero, andignore the sixth input value (1310) when the tenth input value (1301) indicates that the fourth set of values has a size of zero, in the calculation of the fifth output value (1317).

14. The device of Claim 11 when dependent on claim 9, wherein the at least one of the plurality of computation nodes (1205,1206) is further configured to:ignore the seventh input value (1304) when the ninth input value (1302) indicates that the third set of values has a size of zero, andignore the eighth input value (1303) when the tenth input value (1301) indicates that the fourth set of values has a size of zero, in the calculation of the seventh output value (1313).

15. The device of Claim 11, wherein the at least one of the plurality of computation nodes (1205) further comprises:an eighth output value (1315) that indicates when the seventh set of values has a size of zero; anda ninth output value (1314) that indicates when the eighth set of values has a size of zero.

16. A method for processing message passing algorithms in a device comprising:receiving, by a computation circuit (802), a first set of nc,r values (720), wherein the computation circuit (802) comprises a network of a plurality of computation nodes (1204, 1205,1206) arranged in a tree structure with two or more layers (1201), wherein at least one upper layer receives top-level circuit input values, and wherein output values from eachupper layer serve as input values to one or more lower layers, with output values from a final layer constituting top-level circuit output values;providing a first output value (908) that is calculated as a non-linear function of the first set of nc,r values (720);providing a second output value (906) that is calculated as a non-linear function of a second set of values, wherein the second set of values comprises nc,r-l values that are derived from the first set of nc,r values (720) by excluding a minimum value in the first set of nc,r values (720);associating at least one of the plurality of computation nodes (1205,1206) with a third set of values and a fourth set of values, wherein each of the third set of values and fourth set of values are subsets of the first set of nc,r values (720) and wherein each of the third and fourth sets of values comprises a number of values that is a number in a range from zero to nc,r inclusive;receiving, by the at least one of the plurality of computation nodes (1205,1206),a first input value (1307) that is a non-linear function of the third set of values;a second input value (1308) that is a non-linear function of the fourth set of values;a third input value (1311) that is a non-linear function of a fifth set of values, wherein the fifth set of values is a subset of the first set of nc,r values (720) that is derived from the third set of values by excluding a minimum value in the third set of values; anda fourth input value (1312) that is a non-linear function of a sixth set of values, wherein the sixth set of values is a subset of the first set of nc,r values (720) that is derived from the fourth set of values by excluding a minimum value in the fourth set of values; providing, by the at least one of the plurality of computation nodes (1205,1206):a third output value (1316) that is calculated as a non-linear function of a seventh set of values, wherein the seventh set of values is a further subset of the first set of nc,r values (720) that constitutes a union of the third set of values and fourth set of values; anda fourth output value (1318) that is calculated as a non-linear function of an eighth set of values, wherein the eighth set of values is a subset of the first set of nc,r values (720) that is derived from the seventh set of values by excluding a minimum value in the seventh set of values.

Images