Negative voltage converter

Abstract

A negative voltage conversion (NVC) apparatus comprises: a first input A1 and a second input B1 for connecting to a source; a ground connection G; a first DC output line +DC1; a first arm 1 connected

Description

BACKGROUND OF THE INVENTION A power conversion system, such as an energy harvester Power Management Integrated Circuit (PMIC), has one or more input channels. Each of the input channels can connect to an input source. The input sources may generate a direct current (DC) or an alternating current (AC) signal, and may be of widely different voltage levels. For example, the input sources can have voltages which range from tens of millivolts (mV) to tens of Volts, and currents which range from microamps (pA) to milliamps (mA). SUMMARY OF THE INVENTION An aspect of the present invention provides a negative voltage conversion apparatus comprising: a first input and a second input for connecting to a source; a ground connection; a first DC output line; a first arm connected between the first input and the first DC output line, the first arm comprising a first switching unit; a second arm connected between the second input and the first DC output line, the second arm comprising a second switching unit, wherein each of the first switching unit and the second switching unit is each capable of bi-directionally blocking current flow when the switching units are turned off; a third arm connected between the first input and the ground connection, the third arm comprising a third switching unit; a fourth arm connected between the second input and the ground connection, the fourth arm comprising a fourth switching unit; a control circuit configured to operate the conversion apparatus in: a first configuration, wherein the first switching unit is turned on to connect the first input to the first DC output line, the fourth switching unit is turned on to connect the second input to ground, and the second switching unit and the third switching unit are turned off; a second configuration, wherein the second switching unit is turned on to connect the second input to the first DC output line, the third switching unit is turned on to connect the first input to ground, and the first switching unit and the fourth switching unit are turned off; and a third configuration, wherein at least the first switching unit and the second switching unit are turned off, and current is blocked from flowing to the first DC output line by the first switching unit and the second switching unit. In the first configuration and the second configuration, the negative voltage conversion apparatus converts an input signal with negative polarity portions (such as an AC signal) to a positive DC signal. In the third configuration, the negative voltage conversion apparatus isolates the source connected to the first input and the second input from the DC output line. Optionally, in the third configuration, the control circuit is configured to: turn off the first switching unit and the second switching unit; and turn on one of the third switching unit and the fourth switching unit. Optionally, in the third configuration, the control circuit is configured turn on one of the third switching unit and the fourth switching unit based on a relative polarity of the first input and the second input, wherein: the third switching unit is turned on when the second input is greater than the first input; and the fourth switching unit is turned on when the first input is greater than the second input. Optionally, the conversion apparatus comprises: a second DC output line; an additional first arm connected between the first input and the second DC output line, the additional first arm comprising an additional first switching unit; an additional second arm connected between the second input and the second DC output line, the additional second arm comprising an additional second switching unit, wherein each of the first switching unit and the second switching unit is each capable of bi-directionally blocking current flow when the switching units are turned off; and the control circuit is configured to operate the conversion apparatus in: a first configuration, wherein the additional first switching unit is turned on to connect the first input to the second DC output line, the fourth switching unit is turned on to connect the second input to ground, and the first switching unit, the second switching unit, the additional second switching unit and the third switching unit are turned off; a second configuration, wherein the additional second switching unit is turned on to connect the second input to the second DC output line, the third switching unit is turned on to connect the first input to ground, and the first switching unit, the additional first switching unit, the second switching unit, and the fourth switching unit are turned off; and a third configuration, wherein at least the first switching unit, the first additional switching unit, the second switching unit and the second additional switching unit are turned off, and current is blocked from flowing to the first DC output line by the first switching unit and the second switching unit and current is blocked from flowing to the second DC output line by the additional first switching unit and the additional second switching unit. Optionally, the third switching unit comprises a low voltage FET switching device and a high voltage FET switching device in a cascode configuration; the fourth switching unit comprises a low voltage FET switching device and a high voltage FET switching device in a cascode configuration. Optionally, the control circuit is configured to: output a third switching unit control signal to control an operating state of the low voltage FET switching device in the third switching unit; output a fourth switching unit control signal to control an operating state of the low voltage FET switching device in the fourth switching unit; output a bias signal to the third switching unit and the fourth third switching unit. Optionally, the bias signal is configured to turn on the high voltage FET switching device in the third switching unit when the third switching unit control signal turns on the low voltage FET switching device in the third switching unit and the bias signal is configured to turn on the high voltage FET switching device in the fourth switching unit when the fourth switching unit control signal turns on the low voltage FET switching device in the fourth switching unit. Optionally, each of the third switching unit and the fourth switching unit is configured to receive a range of voltages, wherein the bias signal is configured to maintain the high voltage FET switching device at least partially on for a lower subset of the range of voltages when the low voltage FET switching device is turned off. Optionally, the first arm, the second arm, the third arm and the fourth arm form an outer converter, the third switching unit comprises an intermediate node and the fourth switching unit comprises an intermediate node, the conversion apparatus comprising an inner converter which is selectively connectable to the intermediate nodes to generate a low voltage DC output. Optionally, the conversion apparatus is configured to start up in a configuration in which the inner converter is connected to the intermediate nodes to generate a low voltage DC output. Optionally, the inner converter is connected to the intermediate nodes via a first connecting switch and a second connecting switch, and the first connecting switch and a second connecting switch are each configured to turn on with a zero voltage control signal. Optionally, the inner converter is connected to the intermediate nodes via a first connecting switch and a second connecting switch, wherein: the first connecting switch forms a cascode with the high voltage FET switching device of the third switching unit to provide a constrained low voltage at the first input node; the second connecting switch forms a cascode with the high voltage FET switching device of the fourth switching unit to provide a constrained low voltage at the second input node. Optionally, the inner converter comprises: a first input node and a second input node; a low voltage DC output line; a fifth arm connected between the first input node and the low voltage DC output line, the fifth arm comprising a fifth switching device; a sixth arm connected between the second input node and the low voltage DC output line, the sixth arm comprising a sixth switching device; a seventh arm connected between the first input node and the ground connection, the seventh arm comprising a seventh switching device; an eighth arm connected between the second input node and the ground connection, the eighth arm comprising an eighth switching device; wherein the apparatus is configured to selectively: operate a first configuration, wherein the fifth switching device is turned on to connect the first input node to the low voltage DC output line and the eighth switching device is turned on to connect the second input node to ground; and operate the switching units in a second configuration, wherein the sixth switching device is closed to connect the second input node to the low voltage DC output line and the seventh switching device is turned on to connect the first input node to ground. There is also provided an energy harvesting power management apparatus comprising: a first input stage comprising a first negative voltage conversion apparatus according to the previous aspect for connecting to a first electrical energy harvesting source; an energy storage element connection for connecting to an energy storage element; an inductor connection for connecting to an inductor; and a controller. Optionally, the controller is configured to selectively connect the first input stage to the inductor by operating the first switching unit and the second switching unit in the first negative voltage conversion apparatus. Optionally, the energy harvesting power management apparatus comprises: a second input stage comprising a second negative voltage conversion apparatus according to any one of the preceding claims, wherein the first negative voltage conversion apparatus and the second negative voltage conversion apparatus are connected in parallel. Optionally, the controller is configured to selectively connect the first input stage to the inductor by operating the first switching unit and the second switching unit in the first negative voltage conversion apparatus and to selectively connect the second input stage to the inductor by operating the first switching unit and the second switching unit in the second negative voltage conversion apparatus. Optionally, when the first input stage and the second input stage are connected to a single energy harvesting input source, the controller is configured to connect both the first input stage and the second input stage to the inductor by operating the first switching unit and the second switching unit in the first negative voltage conversion apparatus and by operating the first switching unit and the second switching unit in the second negative voltage conversion apparatus. Optionally, each of the first switching unit and the second switching unit of the negative voltage conversion apparatus comprises: a first terminal; a second terminal; a central node; a first group of switching devices in a cascode configuration between the central node and the first terminal, the first group of switching devices comprising a first low voltage FET switching device and a first high voltage FET switching device; a second group of switching devices in a cascode configuration between the central node and the second terminal, the second group of switching devices comprising a second low voltage FET switching device and a second high voltage FET switching device, wherein the first group of switching devices and the second group of switching devices are connected back-to-back about the central node with a source of the first low voltage FET switching device connected to a source of the second low voltage FET switching device; drive circuitry for driving the first group of switching devices and the second group of switching devices, wherein the drive circuitry is configured to operate the first group of switching devices and the second group of switching devices in: a first mode in which current is not permitted to flow in a direction between the first terminal and the second terminal and not permitted to flow in a direction between the second terminal and the first terminal; a second mode in which at least one of: current is permitted to flow in a direction between the first terminal and the second terminal; current is permitted to flow in a direction between the second terminal and the first terminal. Optionally, the drive circuitry is configured to turn on the first high voltage FET switching device when the first low voltage FET switching device is turned on, and the drive circuitry is configured to turn on the second high voltage FET switching device when the second low voltage FET switching device is turned on. Optionally, each of the first switching unit and the second switching unit is configured to receive a range of positive voltages between the first terminal and the second terminal, wherein the drive circuitry is configured to maintain the first high voltage FET switching device at least partially on for a lower subset of the range of positive voltages when the first low voltage FET switching device is turned off. Optionally, each of the first switching unit and the second switching unit is configured to receive a range of positive voltages between the second terminal and the first terminal, wherein the drive circuitry is configured to maintain the second high voltage FET switching device at least partially on for a lower subset of the range of positive voltages when the second low voltage FET switching device is turned off. Optionally, the central node is a floating node with respect to ground and the drive circuitry is configured to output: a first low voltage drive signal to a gate of the first low voltage FET switching device, wherein the first low voltage drive signal has a first value with respect to a voltage of the central node to turn on the first low voltage FET switching device and a second value with respect to a voltage of the central node to turn off the first low voltage FET switching device; a first bias signal to a gate of the first high voltage FET switching device, wherein the first bias signal is with respect to the voltage of the central node. Optionally, the drive circuitry is configured to output the first low voltage drive signal to a gate of the first low voltage FET switching device and to a gate of the second low voltage FET switching device. Optionally, the drive circuitry is configured to output: a second low voltage drive signal to a gate of the second low voltage FET switching device, wherein the second low voltage drive signal has a first level with respect to a voltage of the central node to turn on the second low voltage FET switching device and a second level with respect to a voltage of the central node to turn off the second low voltage FET switching device. Optionally, the drive circuitry is configured to output the first bias signal to a gate of the first high voltage FET switching device and to a gate of the second high voltage FET switching device. An aspect of the present invention provides a negative voltage conversion apparatus comprising: a first input and a second input for connecting to a source; a ground connection; a first DC output line; a first arm connected between the first input and the first DC output line, the first arm comprising a first switching unit; a second arm connected between the second input and the first DC output line, the second arm comprising a second switching unit; a third arm connected between the first input and the ground connection, the third arm comprising a third switching unit; a fourth arm connected between the second input and the ground connection, the fourth arm comprising a fourth switching unit; a control circuit configured to operate the conversion apparatus in: a first configuration, wherein the first switching unit is turned on to connect the first input to the first DC output line, the fourth switching unit is turned on to connect the second input to ground, and the second switching unit and the third switching unit are turned off; a second configuration, wherein the second switching unit is turned on to connect the second input to the first DC output line, the third switching unit is turned on to connect the first input to ground, and the first switching unit and the fourth switching unit are turned off; wherein: the third switching unit comprises a low voltage FET switching device and a high voltage FET switching device in a cascode configuration; and the fourth switching unit comprises a low voltage FET switching device and a high voltage FET switching device in a cascode configuration. This negative voltage conversion apparatus has an advantage of reduced energy requirements. For small signals, the high voltage FET switching devices remain on, or partially on, and there is only a requirement to turn the low voltage FET switching devices on and off. This allows the apparatus to accommodate a wide range of input signal amplitudes (e.g. up to 20 V), while only turning low voltage FET switching devices on and off when the apparatus is connected to a source with a small signal amplitude. An aspect of the present invention provides a negative voltage conversion apparatus comprising: a first input and a second input for connecting to a source; a ground connection; a first DC output line; a first arm connected between the first input and the first DC output line, the first arm comprising a first switching unit; a second arm connected between the second input and the first DC output line, the second arm comprising a second switching unit; a third arm connected between the first input and the ground connection, the third arm comprising a third switching unit; a fourth arm connected between the second input and the ground connection, the fourth arm comprising a fourth switching unit; a control circuit configured to operate the conversion apparatus in: a first configuration, wherein the first switching unit is turned on to connect the first input to the first DC output line, the fourth switching unit is turned on to connect the second input to ground, and the second switching unit and the third switching unit are turned off; a second configuration, wherein the second switching unit is turned on to connect the second input to the first DC output line, the third switching unit is turned on to connect the first input to ground, and the first switching unit and the fourth switching unit are turned off; wherein the first arm, the second arm, the third arm and the fourth arm form an outer converter, the third switching unit comprises an intermediate node and the fourth switching unit comprises an intermediate node, the conversion apparatus comprising an inner converter which is selectively connectable to the intermediate nodes to generate a constrained low voltage DC output. This negative voltage conversion apparatus has an advantage of generating a low voltage DC output. This is useful, for example, when the apparatus requires a constrained low voltage supply for starting up, such as a cold start. The low voltage DC output can be safely used by start-up circuitry, even when the apparatus is connected to an input which provides a much higher input signal (e.g. up to 20 V). BRIEF DESCRIPTION OF THE DRAWINGS One or more embodiments of the invention will now be described, by way of example only, with reference to the accompanying figures in which: FIGURE 1 shows an energy harvesting system including a power management apparatus; FIGURE 2 shows an overview of an input stage of the power management apparatus with DC and AC input signals; FIGURE 3 shows an input stage of the power management apparatus; FIGURE 4 shows operation of the input stage of the power management apparatus with DC and AC signals; FIGURE 5 shows a bridge rectifier circuit implemented with diodes; FIGURE 6 shows a negative voltage converter circuit implemented with switching devices; FIGURE 7 shows a negative voltage converter for use in an input stage of a power management apparatus; FIGURES 8A and 8B show operation of the negative voltage converter of FIGURE 7; FIGURE 9 shows a power management apparatus with a plurality of input stages connected in parallel; FIGURE 10 shows an example of a bi-directionally blocking switching unit; FIGURE 11 shows a switching unit for use in a negative voltage converter; FIGURE 12 shows a negative voltage converter with an additional output; FIGURE 13 schematically shows a negative voltage converter; FIGURE 14 shows a negative voltage converter with an inner negative voltage converter to provide a constrained output voltage; FIGURES 15A and 15B show one way of operating of the negative voltage converter of FIGURE 14; FIGURES 16A and 16B show another way of operating the negative voltage converter of FIGURE 14; FIGURE 17 shows a more detailed view of a negative voltage converter; FIGURE 18 shows a more detailed example of a bi-directionally blocking switching unit. DETAILED DESCRIPTION Figure 1 shows an energy harvesting system 10 comprising a power management apparatus 20. Other names for the power management apparatus are a power management unit (PMU) or a power management integrated circuit (PMIC). The power management apparatus 20 has a plurality of energy harvesting inputs or energy harvesting input channels 21-24. In this example there are four input channels but the number of input channels can be any suitable number. Each of the input channels 21-24 can connect to an energy harvesting source or an energy harvesting transducer 11-14. Examples of energy harvesting sources are: a photovoltaic (PV) cell which generates an electrical output in response to light; a thermoelectric generator (TEG) which generates an electrical output in response to a temperature difference; a piezoelectric transducer which generates an electrical output in response to mechanical strain across the transducer; and an electrodynamic transducer which generates an electrical output in response to vibrations. The input channels 21-24 may connect to different types of energy harvesting sources. One of the input channels 21-24 may connect to a type of energy harvesting source which is different to a type of energy harvesting source connected to another one of the input channels 21-24. For example, the input channels 21-24 may be connected to: (i) four PV sources; (ii) two PV sources and two TEG sources; (iii) one PV source, one TEG source and one piezo source. Each input channel 21-24 may receive electrical energy with a current in the range, for example, of 1 pA to 100 mA and a voltage in the range 20 mV to 20 V. An impedance of the energy harvesting source 11-14 may be in the range, for example, from single-digit ohms to tens of thousands of ohms. At least one of the input channels 21-24 is capable of receiving a direct current (DC) signal and an alternating current (AC) signal. Advantageously, and in the following description, each of the input channels 21-24 is capable of receiving a direct current (DC) signal and an alternating current (AC) signal. The power management apparatus 20 detects and adapts to whether the input signal is a DC signal or an AC signal. The power management apparatus 20 comprises an output 25 for connecting to an energy store 32. This will be called a main energy store as it is the main store of energy which is used to power a load and internal circuitry. The main energy store 32 may be provided on a same printed circuit board as the power management apparatus 20, or may be separate to the power management apparatus. Examples of devices suitable for use as the main energy store are: a capacitor, a super capacitor, a battery. The power management apparatus 20 may connect to a plurality of main energy stores. These may be of the same type, or different types (e.g. super-capacitor and battery). The power management apparatus 20 has an output 26 for connecting to a load 60. The load 60 can be any device requiring an electrical supply. There is a capacitor (not shown) between the output 26 and the load. Example loads are wireless devices which perform a sensing function (e.g. temperature sensing) and wirelessly report a measurement; Internet of Things (loT) devices; home automation devices; asset tracking devices. The power management apparatus 20 comprises an inductor connection 27 for connecting to an inductor 34. The inductor connection may comprise a pair of terminals or other electrical connection for electrically connecting to first and second ends of the inductor 34. The inductor 34 comprises a magnetic core and a coil. The power management apparatus 20 comprises a switching circuit 28 which can selectively connect the inputs 21-24 to the inductor 34. The switching circuit 28 can also selectively connect the inductor 34 to the energy store 32 via the output 25. The switching circuit 28 can also selectively connect the inductor 34 to a load 60 via the output 26. A controller 30 controls operation of the switching circuit 28. A plurality of loads 60 may be connected to the load output 26. The power management apparatus 20 comprises a plurality of input stages 41-44. Each of the input stages 41-44 connects to a respective input channel 21-24. Each of the input channels 21-24 is capable of receiving a direct current (DC) signal and an alternating current (AC) signal. One of these types of signal will be received at a particular time. At a particular time, each of the input channels 21-24: (i) receives a direct current (DC) signal; (ii) receives an alternating current (AC) signal; or (iii) does not receive any signal because the input channel is not connected to a source, or because the source is not active. The input stages 41-44 in cooperation with the controller 30 determine whether an input signal received at a particular time is a DC signal or an AC signal. In the case of an AC signal, the input stages 41-44 convert negative polarity portions of an AC signal to positive polarity (i.e. negative polarity AC half cycles are converted to positive polarity half cycles). The converted AC signal only has positive polarity half cycles. This has a similar effect to rectifying the input AC signal. Each of the input channels 21-24 has two input terminals. The input stages 41-44 provide a ground reference and clamp one of the input terminals to ground. The controller 30 determines and adapts operating parameters (energise time (tE) and harvesting cycle period (tP)) for the switching circuit 28 based on whether the input signal is DC or AC. In the case of a DC signal, ora quasi-DC signal, a positive polarity line may connect to either of the terminals of the input channels 21-24. The input stages 41-44 determine the relative polarity of the inputs and connect one of the inputs to the output and the other of the inputs to ground. This is particularly useful with quasi-DC sources such as TEG sources, where the relative polarity of the output depends on the thermal gradient. Figure 2 shows an overview of operation of one of the input stages 41-44. Input channel 21 has a pair of inputs IN(A), IN(B). The input signal can be a DC signal, a quasi-DC signal, or an AC signal. The top drawings show the case of a DC signal and a quasi-DC signal. Example (i) is a DC signal with a positive polarity line connected to IN(A). The input signal always has a positive voltage. The input stage 41 passes the DC input signal to the output OUT. Example (ii) is a DC signal with a positive polarity line connected to IN(B). The input stage 41 connects IN(B) to OUT to output a signal with positive polarity. The input stage 41 connects IN(A) to ground. While these drawings show a DC signal with a constant voltage, it will be understood that the DC signal may vary in voltage over a period of time. Example (iii) is a quasi-DC or bipolar DC signal. The input signal has a positive polarity (IN(A)>IN(B)) for a first period of time, and then reverses polarity (IN(B)>IN (A)) for a second period of time. The input stage 41 passes the DC input signal to the output OUT such that the output signal always has a positive polarity. The lower drawings show the case of an AC signal. The input signal is AC, i.e. the signal has a waveform which alternates between a period with positive voltage values (and current flow in a first direction) and a period with negative voltage values (and current flow in a second, opposite, direction). The input stage 41 converts the AC input signal such that the portions 45 of the AC signal with negative voltages are converted to positive voltages. This can be considered as a form of rectification although, as explained below, the input stage does not use diodes to convert the negative voltages. The output signal only has positive voltage values. The negative voltage half cycles 45 have been converted to positive voltage half cycles. In these drawings, the time scales of the quasi-DC signal and the AC signal are not intended to be the same. A quasi-DC signal typically remains in one polarity state ((1 N(A)>lN(B), IN(B)>IN(A)) for a much longer time than an AC signal. Figure 3 shows an example of one of the input stages 41-44. The input channel 21 has two inputs IN(A) and IN(B) which connect to input stage 41. The inputs IN(A), IN(B) are connected to a plurality of switches SW1-SW4 configured as a bridge 46. A first branch connects the input IN(A) to the input IN(B). The first branch comprises the switches SW1 and SW2 connected in series. A second branch connects the input IN(A) to the input IN(B). The second branch comprises the switches SW3 and SW4 connected in series. An output line OUT is connected to a mid-point of the first branch. The mid-point of the second branch is connected to ground. The switches SW1-SW4 are controlled 47 by the controller 30. A polarity detector 48 is connected to the inputs IN(A) and IN(B). The polarity detector 48 provides an output to the controller 30 indicative of the polarity of the input signal. In one example, the polarity detector 48 compares the signal on line IN(A) with the signal on line IN(B). For positive portions of an AC signal, there is a positive voltage difference between lines IN(A) and IN(B), i.e. IN(A) >IN(B). For negative portions of an AC signal, there is a negative voltage difference between lines IN(A) and IN(B), i.e. IN(A) <IN(B). The polarity detector 48 can operate continuously, or substantially continuously, by comparing analog signals on IN(A) and IN(B). Alternatively, the polarity detector 48 can operate on digital samples of the signals on IN(A) and IN(B). A source with a DC signal may connect to input channel 21 with: (i) the positive polarity on line IN(A), or (ii) the positive polarity on line IN(B). The polarity detector 48 detects which line (IN(A) or IN(B)) has positive polarity and the controller 30 connects the other line to ground. For a DC signal input, the polarity (once detected) remains the same. For a quasi-DC or bipolar DC signal, the polarity can change over a period of time. For example, a TEG source may output a DC electrical signal with a first polarity during a first part of a day and then output a DC electrical signal with a second (reversed) polarity during a second part of a day. Figure 4 shows operation of one of the input stages 41-44. The switches SW1-SW4 are operated in a first configuration and in a second configuration. In the first configuration switches SW1 and SW4 are closed. Switches SW2 and SW3 are open. Current flows along OUT. IN(B) is clamped to ground. In the second configuration switches SW2 and SW3 are closed. Switches SW1 and SW4 are open. Current flows along OUT. IN(A) is clamped to ground. The switches SW1-SW4 are operated in the first configuration during positive portions (half cycles) of an AC signal. The switches SW1-SW4 are operated in the second configuration during negative portions (half cycles) of an AC signal. The AC input signal is converted to a positive DC signal which is referenced to ground. The input stages 41-44 also provide flexibility with connecting to energy harvesting sources outputting a DC signal, or a quasi-DC or bipolar DC signal. The switches SW1-SW4 are operated in the first configuration when input IN(A) has positive polarity with respect to input IN(B). Input IN(A) is connected to OUT and input IN(B) is connected to ground. The switches SW1-SW4 are operated in the second configuration when input IN(B) has positive polarity with respect to input IN(A). Input IN(B) is connected to OUT and input IN(A) is connected to ground. This allows the power management apparatus 20 to be used with DC and quasi-DC energy harvesting sources, such as TEG sources, which output a DC signal where the output line having positive polarity can vary based on the quantity being sensed. Figures 5 and 6 show two possible types of apparatus which could possibly be used in each of the input stages 41-44. Figure 5 shows a bridge rectifier circuit implemented with diodes. The bridge rectifier comprises four arms 1-4, each having a diode. Figure 6 shows a similar circuit implemented with MOSFET switching devices called a negative voltage converter (NVC). The NVC has four arms 1-4. Arms 1 and 2 are PMOS devices. Arms 3 and 4 are NMOS devices. Operation of the circuits of Figures 5 and 6 is similar. During a positive half cycle, current flows via arms 1 and 4. During a negative half cycle, current flows via arms 2 and 3. The NVC circuit implemented with MOSFET switching devices has a higher efficiency than the bridge rectifier circuit implemented with diodes, but does not block reverse current flow. It is desirable to connect outputs of the plurality of input stages 41-44 in parallel. If multiple bridge rectifiers are connected in parallel, current will only flow from the source having the highest voltage, even if another one of the sources is required. If multiple NVCs are connected in parallel, current will flow between all sources; from the source with the highest voltage to all other sources. A means of selecting a required source is required. Figure 7 shows a first example of an NVC for use in each of the input stages 41-44. The NVC comprises: a first input Al and a second input Bl which connect to a source (i.e. an energy harvesting source 11, Figure 1); an output connection to a first DC output line +DC1; and a ground connection G. The NVC comprises four arms 1-4. A first arm 1 is connected between the first input Al and the first DC output line +DC1. The first arm comprises a first bi-directionally blocking switching unit SW1, driven by a control signal C_SW1. A second arm 2 is connected between the second input Bl and the first DC output line +DC1. The second arm comprises a second bi-directionally blocking switching unit SW2, driven by a control signal C_SW2. A third arm 3 is connected between the first input Al and the ground connection G. The third arm comprises a third switching unit SW3, driven by a control signal C_SW3. A fourth arm 4 is connected between the second input Bl and the ground connection G. The fourth arm comprises a fourth switching unit SW4, driven by a control signal C_SW4. Arms 1 and 2 will be called upper arms. Arms 3 and 4 will be called lower arms. Switching units SW1 and SW2 in the upper arms 1, 2 are bi-directionally blocking switching units. Each of the lower arms comprises a switching unit SW3, SW4. The bi-directionally blocking switching units SW1, SW2 are configured to operate in the following modes: in a first mode, current is not permitted to flow in either direction through the switching unit; in a second mode, current is permitted to flow in both directions through the switching unit. Figures 8A and 8B show operation of the NVC. When Al >Bl (e.g. during a positive half cycle of an AC signal), the switching units of the NVC operate in a first configuration. Switching units SW1 and SW4 are turned on and switching units SW2 and SW3 are turned off. Current flows via arms 1 and 4. Switching unit SW2 blocks current flow between the DC output line and Bl. Switching unit SW3 blocks current flow between Al and ground. When B1>A1 (e.g. during a negative half cycle of an AC signal), the switching units of the NVC operate in a second configuration. Switching units SW2 and SW3 are turned on and switching units SW1 and SW4 are turned off. Current flows via arms 2 and 3. Switching unit SW1 blocks current flow between the DC output line and Al. Switching unit SW4 blocks current flow between Bl and ground. Figures 8A and 8B show operation of the switching units SW1-SW4 when there is a need to transfer energy between an input source and the DC output line. When there is no requirement to transfer energy between an input source and the DC output line, there are two possible ways of operating the switching units SW3 and SW4. In a first option, the lower arm switching units the SW3 and SW4 are turned off. In a second option, one of the lower arm switching units SW3 and SW4 is turned on, depending on the source polarity. This ensures that the input source is connected to ground. This second option is shown in Figures 8C and 8D. Figure 8C shows the NVC with an input signal A1>B1. Switches SW1-SW3 are turned off. Switch SW4 is turned on. The bi-directionally blocking switching unit SW1 prevents current flow to and from the first DC output line +DC1. Figure 8D shows the NVC with an input signal B1>A1. Switches SW1, SW2 and SW4 are turned off. SW3 is turned on. The bi-directionally blocking switching unit SW2 prevents current flow to and from the first DC output line +DC1. If this bidirectionally blocking function of switches SW1, SW2 was not provided, current can flow from the input source connected to this inactive input stage to an input source connected to an active input stage with a lower source voltage. Operation of the switching units SW1-SW4 is controlled by control signals C_SW1 - C_SW4. These control signals may be output by a controller, such as controller 30, Figure 1. The controller 30 receives an input indicative of the polarity of the source connected to inputs Al, Bl, as shown in Figure 3. It is also possible for the control signals C_SW3 and C_SW4 of the switching units SW3 and SW4 in the lower arms to be generated by comparator-driven self-commutation, based on the polarity of Al and Bl. Figure 9 shows another view of the power management apparatus 20 of Figure 1. The input stages 41-44 are connected in parallel to an input of the switching circuit 28. Input stages 42-44 are the same as input stage 41. The switching circuit 28 also comprises connections to: the inductor 34; the store 32 and ground. The apparatus operates 28 as a DC-DC converter, transferring energy to the inductor 34, and from the inductor 34 to the store 32 by operating switches of the switching circuit 28 and the switches of the selected one of the input stages 41-44. The controller 30 is configured to turn on the switching units in a selected one of the input stages 41-44 to cause current to flow from the source connected to that input stage to the inductor 34. In Figure 9, the bi-directionally blocking switching units SW1 and SW2 are the only switches in the path between the source and the inductor 34. This avoids the need for a bi-directional blocking switch within the switching circuit 28. This reduces switching losses. The DC-DC converter may take a different form to the one shown here. Figure 10 shows one example of way of implementing the bi-directionally blocking switching unit SW1, SW2. This described in detail later in the specification. In summary, the switching unit comprises: a first group of switching devices LV1, HV1 in a cascode configuration between the central node and the first terminal A, the first group of switching devices comprising a first low voltage FET switching device and a first high voltage FET switching device, wherein the first low voltage switching device has the same or a lower operating voltage than the first high voltage switching device; a second group of switching devices LV2, HV2 in a cascode configuration between the central node and the second terminal B, the second group of switching devices comprising a second low voltage FET switching device and a second high voltage FET switching device, wherein the second low voltage switching device has the same or a lower operating voltage than the second high voltage switching device, wherein the first group of switching devices and the second group of switching devices are back-to-back about the central node. The use of a low voltage FET switching device and a high voltage FET switching device in a cascode configuration has an advantage of reducing switching energy requirements. This is because, for a lower range of voltages, the high voltage FET switching device remains on, or partially on, when the low voltage FET switching device is turned off. This is particularly useful with an apparatus which connects to input sources with a wide range of input voltages. LOWER ARMS CASCODE The switching units SW3, SW4 in the lower arms of the NVC can be implemented as single MOSFET devices (e.g. N-channel MOSFET devices), as shown in Figure 6. Figure 11 shows an alternative switching unit for use in each of the lower arms of the NVC. Terminals T1 and T2 are the terminals at each end of the switching unit SW3, SW4. Each switching unit comprises a group 81 of FET switching devices. In the example of Figure 11, the group of switches comprises a pair of switches: a low voltage MOSFET switch LV1 and a high voltage MOSFET switch HV1. The switches HV1 and LV1 are connected in series between T1 and T2 (ground). A drain D of HV1 is connected to terminal Tl. A source of HV1 is connected to the drain of LV1. A source of LV1 is connected to terminal T2 (ground). The terms "low voltage" and "high voltage" refer to the relative operating voltages of the switches. For example, the low voltage FET switch LV1 may have an operating voltage of around 2 Volts and the high voltage FET switch HV1 may have an operating voltage of around 20 Volts. This means that the low voltage FET switch LV1 is capable of switching a voltage of up to 2 Volts, and the high voltage FET switch HV1 is capable of switching a voltage of up to 20 Volts. Other voltages are possible. The low voltage switch LV1 is turned on / off by the low voltage control signal C_LV1. The control signal has values Vdrv and 0V. Depending on the voltage between terminals T1 and T2, the high voltage switch HV1 may turn off with the low voltage switch LV1, or it may remain on, or partially on. The ability to keep the high voltage switch HV1 on, or partially on, provides an energy saving from not needing to fully charge and discharge the larger gate capacitance of the high voltage switch HV1 at each switching event. The cascode configuration also has advantage of providing a constrained voltage at intermediate node N3. MULTIPLE UPPER ARMS Figure 12 shows a further example of an NVC which can be used as one of the input stages 41-44. A pair of NVCs NVC1, NVC2 are shown. The main differences are that each of the NVCs has a further pair of upper arms IB, 2B, and connects to a second DC output line +DC2. The upper arms 1 and 2 of Figures 7 and 9, between the inputs Al, Bl and the first DC output line +DC1 are labelled 1A, 2A. Upper arm IB is connected between the first input Al and the second DC output line +DC2. Arm IB comprises a fifth switching unit SW5, driven by a control signal C_SW5. Upper arm IB is connected between the second input Bl and the second DC output line +DC2. Arm IB comprises a sixth switching unit SW6, driven by a control signal C_SW6. Switching units SW5 and SW6 in the upper arms IB, 2B are bi-directionally blocking switching units. The NVC can be operated as before. To summarise: Output to the first DC output line +DC1 (Single source NVC1 selected). During a positive half cycle (i.e. when Al >Bl), switching units SW1 and SW4 are turned on. Switching units SW2, SW3, SW5 and SW6 are turned off. Current flows via arm 1A to the first DC output line +DC1. Current returns via arm 4. During a negative half cycle (Bl >Al), switching units SW2 and SW3 are turned on. Switching units SW1, SW4, SW5 and SW6 are turned off. Current flows via arm 2 to the first DC output line +DC1. Current returns via arm 3. Output to the first DC output line +DC1 (Single source connected in parallel to NVC1, NVC2). During a positive half cycle (i.e. when Al >Bl), switching units SW1 and SW4 in each of NVCl and NVC2 are turned on. Switching units SW2, SW3, SW5 and SW6 are turned off. Current flows via arms 1A (of NVCl and NVC2) to the first DC output line +DC1. Current returns via arms 4 (of NVCl and NVC2). During a negative half cycle (Bl >Al), switching units SW2 and SW3 in each of NVCl and NVC2 are turned on. Switching units SW1, SW4, SW5 and SW6 are turned off. Current flows via arms 2 (of NVCl and NVC2) to the first DC output line +DC1. Current returns via arms 3 (of NVCl and NVC2). The parallel connection of the single source to more than one NVC reduces l2R losses as current from the source flows via parallel paths to the inductor 34. Some further operating modes are: Output to the second DC output line +DC2. During a positive half cycle (i.e. when Al >Bl), switching units SW5 and SW4 are turned on. Switching units SW1, SW2, SW3, and SW6 are turned off. Current flows via arms IB and 4. During a negative half cycle (Bl >Al), switching units SW3 and SW6 are turned on. Switching units SW1, SW2, SW4 and SW5 are turned off. Current flows via arms 2B and 3. Bi-directionally blocking switching units SW5 and SW6 prevent current flow in both directions when they are not turned on. This prevents current flow from the source reaching other NVCs when the switching units are turned off. Output to the first DC output line +DC1 and to the second DC output line +DC2. During a positive half cycle (i.e. when Al >Bl), switching units SW1, SW5 and SW4 are turned on. Switching units SW2, SW3 and SW6 are turned off. Current flows via arm 1A to the first DC output line +DC1 and via arm IB to the second DC output line +DC2. Current returns via arm 4. During a negative half cycle (Bl >Al), switching units SW2, SW3 and SW6 are turned on. Switching units SW1, SW4 and SW5 are turned off. Current flows via arm 2A to the first DC output line +DC1 and via arm 2B to the second DC output line +DC2. Current returns via arm 3. When there is no requirement to transfer energy between an input source and the DC output lines +DC1, +DC2, the NVC is operated with all of the upper arm switching units SW1, SW2, SW5, SW6 turned off. The NVC is operated with either: (i) the lower arm switching units SW3 and SW4 turned off; or (ii) one of the lower arm switching units SW3 and SW4 turned on, depending on the source polarity. This ensures that the input source is connected to ground. This is the same as described above for the NVC with a single pair of upper arms. There are various possible uses for the two DC output lines +DC1, +DC2. Each DC output line may be connectable to a respective coil, or to different tap points on a single coil. INNER NVC - VOLTAGE CONSTRAINED OUTPUT Figure 13 shows the NVC as previously described, with the four arms 1-4 arranged in the form of a diamond. One requirement of the PMIC is for a constrained power supply at start up. Figure 14 shows an NVC which comprises a further inner NVC circuit 90 which provides a constrained low voltage output, +DC (LOW). For example, this may operate in the sub-threshold region to provide an output voltage range of between 150mV and 500mV from an input voltage range of + / -150mV to + / -20V. Other voltage ranges are possible. Arms 1 and 2 of the NVC are as previously described. Arms 3 and 4 comprise a pair of FET devices in a cascode configuration. These are shown as a high voltage FET device HV and a low voltage FET device LV. A node N3 is positioned in the arm 3 between the high voltage FET device HV and the low voltage FET device LV. A node N4 is positioned in the arm 4 between the high voltage FET device HV and the low voltage FET device LV. The cascode configuration also has advantage of providing a constrained voltage at node N3. The inner NVC circuit 90 comprises a DC output line +DC (LOW) and a ground connection G. The inner NVC circuit 90 comprises four arms. A first arm is connected between input node N1 and the first DC output line +DC (LOW). The first arm comprises a first switch 91. A second arm is connected between the input node N2 and the first DC output line +DC (LOW). The second arm comprises a second switch 92. A third arm is connected between the input node N1 and the ground connection G. The third arm comprises a third switch 93. A fourth arm is connected between the input node N2 and the ground connection G. The fourth arm comprises a fourth switch 94. In the example shown in Figure 17, each of the switches 91, 92 is a P-channel MOSFET device and each of the switches 93, 94 is an N-channel MOSFET device. The switches 91-94 are self-controlling. They do not require external control signals to operate. Switches 91, 92 form a first cross-coupled pair. A gate of switch 91 is connected to a source of switch 92, and a gate of switch 92 is connected to a source of switch 91. Switches 93, 94 form a second cross-coupled pair. A gate of switch 93 is connected to a drain of switch 94, and a gate of switch 94 is connected to a drain of switch 93. This configuration has an advantage that the switches operate at start up without the need for a controller to generate control signals, or sense input signals. In Figure 14, the inner NVC circuit 90 is selectively connectable to the outer NVC via switches SW7, SW8. When the switches SW7, SW8 are turned on, node N3 is connected to the input node N1 and node N4 is connected to the input node N2. When the switches SW7, SW8 are turned off, node N3 is disconnected from the input node N1 and node N4 is disconnected from the input node N2. In the example shown in Figure 17, the switches SW7, SW8 are depletion mode N-channel depletion mode MOSFET devices. This has an advantage that the switches SW7, SW8 turn on at start up, and so do not require a bias supply to operate. Switches SW7, SW8 of this type require a negative voltage to turn off, and thereby disconnect the inner NVC circuit 90. A suitable negative voltage is available once the main system controller (e.g. 30, Fig. 1) is operational. The switches SW7, SW8 also form part of a cascode. In arm 3, the cascode comprises: the high voltage FET device HV; switch SW7 and switch 93. In arm 4, the cascode comprises: the high voltage FET device HV; switch SW8 and switch 94. The switches SW7 / SW8 have the effect of constraining the voltage at node N1 / N2. This provides a voltage-constrained output across a wide range of input AC voltages. In the example shown in Figure 17, each of the switches SW7, SW8 is a 5V depletion mode N-channel MOSFET device and the voltage at nodes N1 / N2 is constrained to 0.5 V peak. Operation is shown in Figures 15 and 16. Firstly, operation of the outer NVC is shown in Figures 15A and 15B. This is the same as previously described. During a positive half cycle (i.e. when Al >Bl), current flows via arms 1 and 4. During a negative half cycle (Bl >Al), current flows via arms 2 and 3. Next, operation of the inner NVC 90 is shown in Figures 16A and 16B. During a positive half cycle (i.e. when Al >Bl), arms 1 and 2 are turned off. Switch 94 self-commutates to be on. This then turns on depletion mode devices SW8 and HV in arm 4. This forms the GND connection to Bl. Switch 93 self-commutates off. The cascode of HV in arm 3 and SW7 are at threshold (just off, but as current flows through the leg, just on), constraining the voltage at N3 and Nl. Switch 91 self-commutates to be on. This forms a current path from Al to the voltage constrained output +DC(LOW). Current flows from Al along the first part of arm 3, through the HV FET device, to node N3. Current passes via switch SW7 to node Nl. Current flows via the first switch 91 and exits on the DC output line +DC (LOW). Current returns via ground connection G, flows via the switch 94 to node N2, via switch SW8 to node N4 and along the upper part of arm 4 through the HV FET device to Bl. During a negative half cycle (Bl >Al), arms 1 and 2 are turned off. Switch 93 self-commutates to be on, which turns on depletion mode devices SW7 and HV in arm 3. This forms the GND connection to Al. Switch 94 is off. The cascode of HV in arm 4 and SW8 are at threshold, constraining the voltage at N4 and N2. Switch 92 self-commutates to be on. This forms a current path from Bl to the voltage constrained output +DC(LOW). Current flows from Bl along the first part of arm 4, through the HV FET device, to node N4. Current passes via switch SW8 to node N2. Current flows via the first switch 92 and exits on the DC output line +DC (LOW). Current returns via ground connection G, flows via the switch 93 to node Nl, via switch SW7 to node N3 along the upper part of arm 3 through the HV FET device to Al. BI-DIRECTIONALLY BLOCKING SWITCH Figure 18 shows an example of implementing a bi-directionally blocking switching unit. The first group of switching devices LV1, HV1 and the second group of switching devices LV2 HV2 are the same as shown in Figure 10. A MOSFET switch is controlled by the voltage between its gate and source. Drive circuitry 70 provides signals to drive the first pair 81 of switches and the second pair 82 of switches. Driver 75 has an output which is connected to a gate of the first low voltage switch LV1 and to a gate of the second low voltage switch LV2. Driver 75 is configured to output a low voltage drive signal C LV to drive the gate of the ••XI -x «x _ «x first low voltage switch LV1 and the gate of the second low voltage switch LV2. Driver 75 outputs a low voltage drive signal with respect to virtual ground, and can have a value of: 0V (with respect to virtual ground, turning LV1 and LV2 off) or Vdrv (with respect to virtual ground, turning LV1 and LV2 on). Driver 75 is a small low-output impedance driver. It receives the 0 / 1 logic control signal from the level shifter 74 and outputs a OV / Vdrv drive signal to the gates of the low voltage FET switches LV1, LV2. A switch control module 71 controls operation. The switch control module 71 outputs a control signal to turn the low voltage switches LV1, LV2 on or off. The control signal output by the switch control module 71 is translated, by the level shifter 74, to a voltage relative to virtual ground. This ensures that the "on" state of the low voltage drive signal C LV is a voltage Vdrv above the current voltage of the floating / virtual ground at node C. A local charge pump 73 generates two bias supplies with respect to the floating / virtual ground at node C: Vbias_cascode and Vdrv. Vbias_cascode is used to provide a fixed DC bias to the gate of the two high voltage switches HV1, HV2. Vdrv is used to provide power for a switch driver 75 and a level shifter 74. The central node C, also called virtual ground, is the source connection to both low voltage FET switches LV1, LV2. The voltage between the gate and source controls these FET switches LV1, LV2. Hence the output from driver 75 is referenced to virtual ground to control these FET switches LV1, LV2. Vbias_cascode and Vdrv are also both referenced to virtual ground. If the voltage on terminal A or terminal B changes, and as the switch is turned on / off, then virtual ground will move with respect to system ground. However, Vbias_cascode and Vdrv will always track virtual ground, and so keep the switch under control. The level shifter 74 generates an output signal to operate the low voltage switches LV1, LV2. The level shifter 74 receives an input from the controller 71, which is referenced to system ground. The level shifter 74 is connected to the virtual ground and generates the output signal with respect to the virtual ground. The level shifter 74 translates the system ground referenced control signal output by controller 71, to a virtual ground based drive signal, where 0=0V and l=Vdrv. As virtual ground moves with respect to system ground, the level-shifter ensures that a logical 0 / 1 output from controller 71 is always translated to a logical 0 / 1 output from level-shifter 74 and to drive signals OV / Vdrv from driver 75. A clock 72 is provided to drive the (floating) local charge-pump 73. Each pair of switches 81, 82 is in a cascode configuration. The low voltage switches LV1, LV2 are turned on / off by the low voltage drive signal. Depending on the voltage between terminals A and B, the high voltage switches HV1, HV2 may turn off with the low voltage switches LV1, LV2, or they may remain on, or partially on. The ability to keep the high voltage switches HV1, HV2 on, or partially on, provides an energy saving from not needing to fully charge and discharge the larger capacitance of the high voltage switches HV1, HV2 at each switching event. Referring again to Figure 10, operation of each of the pairs of cascoded switches will now be explained in more detail. This example uses N-channel MOSFET switches. Each switch is labelled to identify: gate G; source S and drain D. Node E is a node between the drain of the low voltage switch LV1 and the source of the high voltage switch HV1. Node F is a node between the drain of the low voltage switch LV2 and the source of the high voltage switch HV2. Switches LV1 and LV2 are controlled by the voltage on their gate G with respect to their source S, i.e. Vgs. Each of the switches LV1, LV2 has a respective threshold voltage to turn on, Vth_lvi, Vth_lv2. The source S of each of the switches LV1 and LV2 is connected to node C, virtual ground. Driver 75 generates a low voltage drive signal C_LV with respect to node C, virtual ground. A high output from driver 75 (= voltage Vdrv) will switch on LV1 and LV2. A low output (of zero voltage) will switch off LV1 and LV2. Switches HV1 and HV2 are controlled by the voltage on their gate G with respect to their source S, i.e. Vgs. A bias signal Vbias_cascode (with respect to node C, virtual ground) is applied to the gate G of HV1 and HV2. Each of the switches HV1, HV2 has a respective threshold voltage to turn on, Vth_hvi, Vth_hv2. Switch HV1 turns on when Vgs_hvi >Vth_hvi and switch HV2 turns on when Vgs_hv2 >Vth_hv2. Vbias_cascode is chosen such that, when switches LV1 and LV2 are on, switches HV1 and HV2 are also on. When switches LV1 and LV2 are off, the action of the (body) diodes associated with switches LV1, LV2, HV1 and HV2 will bias node C to the lowest voltage of node A or node B. For example, when node B is at a lower potential than node A, node C will be at a similar potential as node B. When node A is at a lower potential than node B, node C will be at a similar potential as node A. The behaviour of switch HV1 will depend on the voltage between nodes A and C, and the behaviour of switch HV2 will depend on the voltage between nodes B and C. The potential of node C "floats" according to the operating state of switches LV1, LV2 and the polarity of the potential difference between nodes A and B. Consider the case where the voltage at node A is greater than the voltage at node B. Firstly, consider the low voltage drive signal C_LV is switched to the high (Vdrv) value. Switches LV1 and LV2 are turned on, as Vgs_lvi >>Vth_lvi and Vgs_lv2 >>Vth_lv2. Switch HV1 will turn on as VEC = 0V and Vgs_hvi = Vbias_cascode. Switch HV2 will also turn on as VFC = 0V and Vgs_hv2 = Vbias_cascode. Switches LV1, HV1, LV2 and HV2 are now all on, and current can flow in either direction between nodes A and B. Nodes A, C and B will be at an equal voltage (ignoring resistive voltage drops). Now, consider the low voltage drive signal C_LV is switched to the low (0V) value. Switches LV1 and LV2 are turned off, as Vgs_lvi <<Vth_lvi and Vgs_lv2 <<Vth_lv2. At this time, switches HV1 and HV2 are still on. The voltage at node C will track the voltage at node B due to the body diodes of LV2 and HV2. Voltage at node E (relative to virtual ground node C, Vec) will start to rise (quickly) towards the voltage at node A. The voltage at node E (Vec) will continue to rise until it reaches the voltage at node A or reaches: Vgs_hvi = (Vbias_cascode - Vec). Below this voltage threshold switch HV1 remains on. At this threshold switch HV1 is (just) off because Vgs_hvi <Vth_hvi. As the voltage between A and C increases, switch HV1 will progressively switch off, constraining Vec at a constant voltage. Switch HV2 will remain on throughout as: Vbias_cascode - VFC >>Vth_hv2. This arrangement ensures the voltage between the source S and drain D of LV1 is always constrained. That is, the voltage will not exceed (Vbias_cascode -Vth_hvi), thus allowing a low operating voltage switch LV1, with a low gate-charge requirement, to be used. Vbias_cascode may have a voltage of Vdrv, or a different value than Vdrv. The value of Vbias_cascode is defined based on the operating voltage of the low voltage switches LV1, LV2, which determines the value of the constrained voltage between the source S and drain D of LV1. Consider the case where the voltage at node B is greater than the voltage at node A. Firstly, consider the low voltage drive signal C_LV is switched to the high (Vdrv) value. Switches LV1 and LV2 are turned on, as Vgs_lvi >>Vth_lvi and Vgs_lv2 >>Vth_lv2. Switch HV2 will turn on as VFC = 0V and Vgs_hv2 = Vbias_cascode. Switch HV1 will also turn on as VEC = 0V and Vgs_hvi = Vbias_cascode. Now consider that the low voltage drive signal C_LV is switched to the low (0V) value. Switches LV1 and LV2 are turned off, as Vgs_lvi « Vth_lvi and Vgs_lv2 <<VTH_LV2. At this time, switches HV1 and HV2 are still on. The voltage at node C will track the voltage at node A due to the body diodes of LV1 and HV1. Voltage at node F (relative to virtual ground node C, Vec) will start to rise (quickly) towards the voltage at node B. The voltage at node F (Vfc) will continue to rise until it reaches the voltage at node B or reaches: Vgs_hv2 = (Vbias_cascode - Vfc). Below this voltage threshold switch HV2 remains on. At this threshold switch HV2 is (just) off because Vgs_hv2 <Vth_hv2. As the voltage between B and C increases, switch HV2 will progressively switch off, constraining Vfc at a constant voltage. Switch HV1 will remain on throughout as: Vbias_cascode - VEC » VTH Hvi- This arrangement ensures the voltage between the source S and drain D of LV2 is also constrained. That is, the voltage will not exceed (Vbias_cascode - Vth_hv2), thus allowing a low operating voltage switch LV2, with a low gate-charge requirement, to be used. For small voltages between terminals A and B, the high voltage switches HV1, HV2 remain on (or partially on) when the low voltage switches LV1, LV2 are turned off. For larger positive voltages between terminals A and B, the high voltage switch HV1 is turned partially off, or fully off, when the low voltage switches LV1, LV2 are turned off. For larger positive voltages between terminals B and A, the high voltage switch HV2 is turned partially off, or fully off, when the low voltage switches LV1, LV2 are turned off. The high voltage switches HV1, HV2 are always on when the low voltage switches LV1, LV2 are turned on. The high voltage switches HV1, HV2 are always on when the low voltage switches LV1, LV2 are turned on. The energy cost of driving the smaller low voltage switch LV1 is significantly lower than that of driving the high voltage switch HV1. High voltage power switches have a higher gate charge requirement. There is an energy requirement associated with each time the high voltage switch is turned on (charge flows into the gate terminal of HV1) and each time the high voltage switch is turned off (charge flows out of the gate terminal of HV1). By reducing the number of times the high voltage switch HV1 is turned on and off, the overall energy requirement of the apparatus is reduced. The voltage (with respect to true ground) at node C varies, depending on the relative voltage of nodes A and B, i.e. A>B or B>A. The level shifter 74 ensures that the low voltage drive signal applied to the low voltage switches LV1, LV2 is always with respect to the voltage at node C. This allows the drive circuitry to turn the low voltage switches on and off, regardless of the relative voltage of A and B. Similarly, the drive circuitry outputs a bias signal Vbias_cascode which is always with respect to the voltage at node C. This allows the high voltage switches HV1, HV2 to operate along with LV1, LV2 in a cascode configuration. OTHER ALTERNATIVES Referring again to Figure 1, the energy harvesting system 10 comprises a plurality of input stages 41-44 connected in parallel. The NVC may also be used in an energy harvesting system 10 comprising a single input stage 41. One of the inputs to the switching circuit 28 is the energy store 32. Upper arms of the NVC in the input stage 41 have bi-directionally blocking switching units, as previously described. Additionally, a bi-directionally blocking switching unit is provided in the connection to the energy store 32. It is possible to selectively connect the input stage 41 or the energy store 32 to the inductor 34 by operating the bi-directionally blocking switching units. When the input stage 41 is not selected, it is isolated from the energy store 32. In another example, the bi-directionally blocking switching units SW1, SW2 are configured to operate in the following modes: in a first mode, current is not permitted to flow in either direction through the switching unit; in a second mode, current is permitted to flow in a single direction through the switching unit. This requires a more complex control of the switching units SW1, SW2. The functionality of the control circuit or controller described in this document can be implemented in hardware, software executed by a processing apparatus, or by a combination of hardware and software. The processing apparatus can comprise a computer, a processor, a state machine, a logic array or any other suitable processing apparatus. The processing apparatus can be a general-purpose processor which executes software to cause the general-purpose processor to perform the required tasks, or the processing apparatus can be dedicated to perform the required functions. Any features described in respect of an embodiment or example may be combined with any other embodiment or example.

Claims

1. A negative voltage conversion apparatus comprising:a first input and a second input for connecting to a source;a ground connection;a first DC output line;a first arm connected between the first input and the first DC output line, the first arm comprising a first switching unit;a second arm connected between the second input and the first DC output line, the second arm comprising a second switching unit, wherein each of the first switching unit and the second switching unit is each capable of bi-directionally blocking current flow when the switching units are turned off;a third arm connected between the first input and the ground connection, the third arm comprising a third switching unit;a fourth arm connected between the second input and the ground connection, the fourth arm comprising a fourth switching unit;a control circuit configured to operate the conversion apparatus in:a first configuration, wherein the first switching unit is turned on to connect the first input to the first DC output line, the fourth switching unit is turned on to connect the second input to ground, and the second switching unit and the third switching unit are turned off;a second configuration, wherein the second switching unit is turned on to connect the second input to the first DC output line, the third switching unit is turned on to connect the first input to ground, and the first switching unit and the fourth switching unit are turned off; anda third configuration, wherein at least the first switching unit and the second switching unit are turned off, and current is blocked from flowing to the first DC output line by the first switching unit and the second switching unit.

2. The conversion apparatus of claim 1 wherein, in the third configuration, the control circuit is configured to:turn off the first switching unit and the second switching unit; andturn on one of the third switching unit and the fourth switching unit.

3. The conversion apparatus of claim 2 wherein, in the third configuration, the control circuit is configured turn on one of the third switching unit and thefourth switching unit based on a relative polarity of the first input and the second input, wherein:the third switching unit is turned on when the second input is greater than the first input; andthe fourth switching unit is turned on when the first input is greater than the second input.

4. The conversion apparatus of claim 1 comprising:a second DC output line;an additional first arm connected between the first input and the second DC output line, the additional first arm comprising an additional first switching unit;an additional second arm connected between the second input and the second DC output line, the additional second arm comprising an additional second switching unit, wherein each of the first switching unit and the second switching unit is each capable of bi-directionally blocking current flow when the switching units are turned off; andthe control circuit is configured to operate the conversion apparatus in:a first configuration, wherein the additional first switching unit is turned on to connect the first input to the second DC output line, the fourth switching unit is turned on to connect the second input to ground, and the first switching unit, the second switching unit, the additional second switching unit and the third switching unit are turned off;a second configuration, wherein the additional second switching unit is turned on to connect the second input to the second DC output line, the third switching unit is turned on to connect the first input to ground, and the first switching unit, the additional first switching unit, the second switching unit, and the fourth switching unit are turned off; anda third configuration, wherein at least the first switching unit, the first additional switching unit, the second switching unit and the second additional switching unit are turned off, and current is blocked from flowing to the first DC output line by the first switching unit and the second switching unit and current is blocked from flowing to the second DC output line by the additional first switching unit and the additional second switching unit.

5. The conversion apparatus of any one of the preceding claims wherein:the third switching unit comprises a low voltage FET switching device and a high voltage FET switching device in a cascode configuration;the fourth switching unit comprises a low voltage FET switching device and a high voltage FET switching device in a cascode configuration.

6. The conversion apparatus of claim 5 wherein the control circuit is configured to:output a third switching unit control signal to control an operating state of the low voltage FET switching device in the third switching unit;output a fourth switching unit control signal to control an operating state of the low voltage FET switching device in the fourth switching unit;output a bias signal to the third switching unit and the fourth third switching unit.

7. The conversion apparatus of claim 6 wherein the bias signal is configured to turn on the high voltage FET switching device in the third switching unit when the third switching unit control signal turns on the low voltage FET switching device in the third switching unit and the bias signal is configured to turn on the high voltage FET switching device in the fourth switching unit when the fourth switching unit control signal turns on the low voltage FET switching device in the fourth switching unit.

8. The conversion apparatus of claim 6 or 7 wherein each of the third switching unit and the fourth switching unit is configured to receive a range of voltages, wherein the bias signal is configured to maintain the high voltage FET switching device at least partially on for a lower subset of the range of voltages when the low voltage FET switching device is turned off.

9. The conversion apparatus of any one of claims 5 to 8 wherein the first arm, the second arm, the third arm and the fourth arm form an outer converter, the third switching unit comprises an intermediate node and the fourth switching unit comprises an intermediate node,the conversion apparatus comprising an inner converter which is selectively connectable to the intermediate nodes to generate a low voltage DC output.

10. The conversion apparatus of claim 9 wherein the conversion apparatus is configured to start up in a configuration in which the inner converter is connected to the intermediate nodes to generate a low voltage DC output.

11. The conversion apparatus of claim 10 wherein the inner converter is connected to the intermediate nodes via a first connecting switch and a second connecting switch, and the first connecting switch and a second connecting switch are each configured to turn on with a zero voltage control signal.

12. The conversion apparatus of any one of claims 9 to 11 wherein the inner converter is connected to the intermediate nodes via a first connecting switch and a second connecting switch, wherein:the first connecting switch forms a cascode with the high voltage FET switching device of the third switching unit to provide a constrained low voltage at the first input node;the second connecting switch forms a cascode with the high voltage FET switching device of the fourth switching unit to provide a constrained low voltage at the second input node.

13. The conversion apparatus of any one of claims 9 to 12 wherein the inner converter comprises:a first input node and a second input node;a low voltage DC output line;a fifth arm connected between the first input node and the low voltage DC output line, the fifth arm comprising a fifth switching device;a sixth arm connected between the second input node and the low voltage DC output line, the sixth arm comprising a sixth switching device;a seventh arm connected between the first input node and the ground connection, the seventh arm comprising a seventh switching device;an eighth arm connected between the second input node and the ground connection, the eighth arm comprising an eighth switching device;wherein the apparatus is configured to selectively:operate a first configuration, wherein the fifth switching device is turned on to connect the first input node to the low voltage DC output line and the eighth switching device is turned on to connect the second input node to ground; andoperate the switching units in a second configuration, wherein the sixth switching device is closed to connect the second input node to the low voltage DC output line and the seventh switching device is turned on to connect the first input node to ground.

14. An energy harvesting power management apparatus comprising:a first input stage comprising a first negative voltage conversion apparatus according to any one of the preceding claims for connecting to a first electrical energy harvesting source;an energy storage element connection for connecting to an energy storage element;an inductor connection for connecting to an inductor; and a controller.

15. The energy harvesting power management apparatus of claim 14 wherein the controller is configured to selectively connect the first input stage to the inductor by operating the first switching unit and the second switching unit in the first negative voltage conversion apparatus.

16. The energy harvesting power management apparatus of claim 14 or 15 comprising:a second input stage comprising a second negative voltage conversion apparatus according to any one of the preceding claims, wherein the first negative voltage conversion apparatus and the second negative voltage conversion apparatus are connected in parallel.

17. The energy harvesting power management apparatus of claim 16 wherein the controller is configured to selectively connect the first input stage to the inductor by operating the first switching unit and the second switching unit in the first negative voltage conversion apparatus and to selectively connect the second input stage to the inductor by operating the first switching unit and the second switching unit in the second negative voltage conversion apparatus.

18. The energy harvesting power management apparatus of claim 16, wherein when the first input stage and the second input stage are connected to a single energy harvesting input source, the controller is configured to connect both thefirst input stage and the second input stage to the inductor by operating the first switching unit and the second switching unit in the first negative voltage conversion apparatus and by operating the first switching unit and the second switching unit in the second negative voltage conversion apparatus.

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