A semiconductor device and method of manufacture thereof

Abstract

A semiconductor device 200 comprising: a substrate having a patterned two-dimensional material layer structure 210’ thereon; a gold layer 215’’ on a portion of the two-dimensional material layer structure adjacent an edge thereof; and a contact-stack adjacent the edge of the two-dimensional material layer structure and overlapping the gold layer. The contact-stack comprises: (i) a first metal layer 230’ on a portion of the substrate and on the gold layer, wherein the first metal is selected from titanium and chromium; (ii) a second metal layer 235’ on the first metal layer, wherein the second metal is selected from aluminium, copper, gold, nickel and palladium; and (iii) a third metal layer 340’ on the second metal layer, wherein the third metal is selected from cobalt, chromium, iridium, iron, magnesium, niobium, platinum, ruthenium, silver, tantalum, titanium, titanium nitride, and tungsten. The semiconductor device may be a sensor, such as an electrochemical sensor. The two-dimensional material may be graphene.

Description

The present invention relates to a semiconductor device, more particularly a semiconductor device comprising a two-dimensional material layer structure, and a gold layer thereon providing electrical contact to the two-dimensional material layer structure. The present invention also relates to a method for the manufacture of such a device. The devices of the present invention are particularly suitable for use as sensors. Two-dimensional (2D) materials, in particular graphene, and their electronic devices are currently the focus of intense research and development worldwide. 2D-materials have been shown to have extraordinary properties, both in theory and in practice which has led to a deluge of products incorporating such materials which include coatings, batteries and sensors to name but a few. Graphene is most prominent and is being investigated for a range of potential applications. Most notable is the use of graphene in electronic devices and their constituent components which includes transistors, diodes, LEDs, photovoltaic cells, Hall-effect sensors, current sensors, biosensors, gas sensors and the like. Due to the exceptionally thin nature of two-dimensional materials, and their often minimal interaction with the underlying substrate / wafer generally being based essentially only on weak van der Waals interactions, the inventors have found that such materials are particularly susceptible to delamination. Such a problem can arise during manufacture and the deposition of various layers on and over two-dimensional materials. This problem is also especially pronounced under subsequent solution-based processing and other environments and occasions where the two-dimensional material is re-exposed to liquids and solutions (i.e. in both device manufacture and use of the final device). One such example of a device having an exposed surface of a two-dimensional material for receiving liquid samples is a biosensor. WO 2023 / 148149 relates to graphene sensors wherein the graphene layer structure has an exposed sample surface for receiving a sample for testing, particularly graphene biosensors. The sensor comprises first and second electrical contacts in contact with the graphene layer structure, and arranged on opposite sides of the sample surface, and each electrical contact being separated from the sample surface by a directly adjacent metal oxide layer which serves to isolate the electrical contact from the sample surface. The electrical contacts are made of metal, such as chromium, titanium, aluminium, nickel and / or gold. WO 2022 / 246261 relates to field effect transistor arrays, and more particularly relates to an integrated circuit with two dimensional field effect transistors for direct and indirect target signal measurement. US 2017 / 0365474 relates to creating wells on a graphene sheet by depositing a passivation layer on top of the graphene sheet. US 2017 / 0365477 discloses a method for providing a temporary layer on a graphene sheet comprising: transferring a graphene sheet to a selected wafer; depositing a metal layer to a first surface of the graphene sheet; and removing the metal layer. US 2017 / 0365562 discloses a method for patterning graphene comprising: placing a graphene sheet on a wafer; depositing a metal layer on the graphene sheet; depositing a photoresist layer on the metal layer; and etching a pattern on the photoresist layer to expose the metal layer. “Systematic Comparison of Metal Contacts on CVD Graphene” (45th European Solid State Device Research Conference (ESSDERC) 184-187 (IEEE, 2015)) details an experimental study for forming high quality ohmic contacts to graphene. Metal contacts of platinum / gold (Pt / Au), nickel / gold (Ni / Au), palladium (Pd), Ni, and Au to monolayer chemical vapor deposited graphene were studied. The experimental data reveal that pure Au and Ni / Au provide highly reproducible low resistance ohmic contacts. “Contact Resistance Study of Various Metal Electrodes with CVD Graphene” (Solid-State Electronics 2016, 125, 234-239) investigates the contact resistance of various metals to chemical vapour deposited monolayer graphene. Transfer length method (TLM) structures with varying widths and separation between contacts were fabricated and electrically characterized in ambient air and vacuum condition, wherein the electrical contacts are made with five metals: gold, nickel, nickel / gold, palladium and platinum / gold. “The role of contact resistance in graphene field-effect devices” (arXiv:1705.04025v1 [cond-mat.mes-hall] and Progress in Surface Science 2017, 92(3), 143-175) reviews the experimental and theoretical activity that has been focussing on the reduction of the contact resistance in graphene transistors, including by different metals, surface treatments or device architecture. “Recent Progress in 1D Contacts for 2D-Material-Based Devices” (Adv. Mater. 2023, 34, 2202408) provides a detailed review of the electrical characteristics of the 2D devices with 1D edge contacts fabricated using both top-down and bottom-up approaches. The present invention aims to overcome, or at least reduce, the aforementioned problems in the prior art, so as to improve the reliability of device manufacture, in particular sensors comprising exposed two-dimensional materials, as well as improve the manufacturing efficiency of integrating two-dimensional material and the required metal contacts into robust electronic devices, or to at least provide a commercially viable alternative thereto. The present disclosure will now be described further. In the following passages, different aspects / embodiments of the disclosure are defined in more detail. Each aspect / embodiment so defined may be combined with any other aspect / embodiment or aspects / embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous. Thus, a first aspect of the present invention provides a semiconductor device comprising: a substrate having a patterned two-dimensional material layer structure thereon; a gold layer on a portion of the two-dimensional material layer structure adjacent an edge thereof; and a contact-stack adjacent the edge of two-dimensional material layer structure and overlapping the gold layer, the contact-stack comprising: (i) a first metal layer on a portion of the substrate and on the gold layer, wherein the first metal is selected from the group consisting of titanium and chromium; (ii) a second metal layer on the first metal layer, wherein the second metal is selected from the group consisting of aluminium, copper, gold, nickel and palladium; and (iii) a third metal layer on the second metal layer, wherein the third metal is selected from the group consisting of cobalt, chromium, iridium, iron, magnesium, niobium, platinum, ruthenium, silver, tantalum, titanium, titanium nitride and tungsten. A second aspect of the present invention provides a method of forming the semiconductor device, the method comprising: (a) forming a precursor comprising: a substrate having a patterned two-dimensional material layer structure thereon; a precursor gold layer on the two-dimensional material layer structure; and a contact-stack adjacent the edge of two-dimensional material layer structure and overlapping the precursor gold layer, the contact-stack comprising: (i) a first metal layer on a portion of the substrate and on the precursor gold layer, wherein the first metal is selected from the group consisting of titanium and chromium; (ii) a second metal layer on the titanium and / or chromium layer, wherein the second metal is selected from the group consisting of aluminium, copper, gold, nickel and palladium; and (iii) a third metal layer on the second metal layer, wherein the third metal is selected from the group consisting of cobalt, chromium, iridium, iron, magnesium, niobium, platinum, ruthenium, silver, tantalum, titanium, titanium nitride and tungsten; and (b) etching the precursor gold layer with a gold etchant to form a device in accordance with the first aspect. The present invention provides a semiconductor device, preferably a sensor, more preferably an electrochemical sensor. The semiconductor device comprises a two-dimensional material layer structure as an electronic component, together with a unique metal contact formed of layers of gold and the first, second and third metals described herein. The device comprises a patterned two-dimensional material layer structure on a substrate. Two-dimensional materials per se are well-known, the most preferred for the present invention being graphene. Two-dimensional materials include mono-elemental two-dimensional materials such as graphene, silicene, phosphorene, borophene (whether doped or un-doped) as well as hetero-elemental two-dimensional materials such as h-BN and transition metal dichalcogenides (TMDCs), for example M0S2, WS2 and MoSe2 (a monolayer being known in the art to refer to a layer of MX2 stoichiometry). The device therefore comprises a semiconducting / semimetallic two-dimensional material, preferably graphene, phosphorene, or a TMDC due to the unique electronic properties of such materials being desirable for electronic devices, particularly for at least the uppermost layer of the layer structure. For many devices such as sensors, undoped (e.g. pristine or unintentionally doped) two-dimensional material is preferred. A two-dimensional material layer (which may be referred to herein as a two-dimensional material layer structure, for example a graphene layer structure) preferably has from 1 to 10 monolayers of two-dimensional material. Preferably the two-dimensional material layer is comprised of a single monolayer. A preferred multilayer structure would have 2 or 3 monolayers. In some embodiments, all of the monolayers are of the same two-dimensional material (e.g. bilayer graphene), though in some preferred embodiments, the multilayer structure may be a heterostructure. By way of example only, the two-dimensional material layer structure may be a sandwich of graphene between two layers of h-BN or a TMDC on graphene. A monolayer of graphene has a known thickness of about 0.34 nm, that of monolayer phosphorene is about 0.85 nm, and that of a monolayer of TMDC can be in the region of about 0.6 to about 0.7 nm. As described in greater detail herein, the combination of metals used to manufacture the electrical contacts provides a device that is advantageously resilient to delamination of such thin materials from the surface of the substrate. The two-dimensional material layer structure is patterned. Patterning is a well-known technique in the art of microfabrication and semiconductor manufacturing (i.e. semiconductor device fabrication). A patterned two-dimensional material layer structure has a shape with one or more edges, typically multiple straight edges defining a polygon (e.g. from four to six outer edges). The patterned two dimensional material layer structure typically is a “solid” or “filled” shape with only outer edges (that is, the layer structure does not have holes or the like similar to a ring). Quadrilaterals are preferred (i.e. four straight edges), and the patterned two-dimensional material layer structure may preferably be substantially rectangular, such a shape being simple in design and very suitable for many subsequent device applications, including sensors. Preferably, the corners of the patterned shape are about 90° (such as in a rectangle) or more. The two-dimensional material layer is provided on a substrate, preferably a non-metallic surface of a substrate, and in some embodiments an insulating surface. The nature of the substrate is not particularly limited. It is known in the art that such substrates or wafers provide a substantially flat upper surface for the fabrication of devices by the growth / deposition and patterning of further layers. Preferably, the non-metallic surface upon which the two-dimensional material layer is provided is silicon (Si), silicon carbide (SiC), silicon nitride (S13N4), silicon dioxide (S1O2), sapphire (AI2O3), aluminium gallium oxide (AGO), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgAhO^, yttrium orthoaluminate (YAIO3), strontium titanate (SrTiOs), cerium oxide (Ce2O3), scandium oxide (SC2O3), erbium oxide (Er2O3), magnesium difluoride (MgF2), calcium difluoride (CaF2), strontium difluoride (SrF2), barium difluoride (BaF2), scandium trifluoride (ScFs), germanium (Ge), cubic boron nitride (c-BN), hexagonal boron nitride (h-BN) and / or a 11l / V semiconductor such as aluminium nitride (AIN) and gallium nitride (GaN). In some embodiments, the substrate may consist of one such material. Preferably, the non-metallic surface is silicon, silicon nitride, silicon dioxide, sapphire, aluminium nitride, YSZ, scandium oxide, germanium, calcium difluoride and / or magnesium difluoride. Preferably, the non-metallic surface is sapphire, yttria-stabilised zirconia, scandium oxide, calcium difluoride or magnesium difluoride. In some preferred embodiments, the substrate comprises, or consists of, a first layer which provides the non-metallic surface and a “substrate support” layer, sapphire being a preferred example (such embodiments being particularly suitable for insulative substrates, i.e. typically the oxides, nitrides and fluorides described). In other preferred embodiments, the substrate support layer comprises silicon. A silicon support layer, includes a “pure” silicon wafer (essentially consisting of silicon, doped or undoped) or what may be referred to as a CMOS wafer which includes additional associated circuitry. First layers comprising or consisting of rare earth oxides (which include yttrium and scandium) are particularly preferably provided on a silicon substrate support. Scandium oxide, for example, is particularly preferred. Such substrates are preferred for devices such as gas sensors. A substrate may also comprise one or more layers (for example, regions or channels of embedded waveguide materials such as silicon nitride suitable for electro-optic modulators and photodetectors). The thickness of the substrate support layer is generally much thicker than the thickness of the first layer thereon. Typically, the substrate support layer has a thickness of 250 pm to 1.5 mm, for example from 400 pm to 1 mm. On the other hand, the thickness of the first layer of such a substrate is substantially thinner and may be formed on the substrate support by epitaxy such as molecular beam epitaxy (MBE) or high temperature sputtering. Preferably, the thickness is at least 2 nm, preferably at least 5 nm and / or less than 500 nm, preferably less than 100 nm. Suitable ranges for the thickness of the first layer are preferably 5 nm to 100 nm, preferably 10 to 50 nm. It is particularly preferred in the present invention that the two-dimensional material layer structure is provided on the surface of the substrate by directly forming the two-dimensional material layer on the surface by CVD (i.e. a CVD-grown two-dimensional material layer structure grown directly on the surface of the substrate). Forming the two-dimensional material directly on the substrate avoids steps such as physical transfer which can otherwise introduce impurities and / or defects which risks negating the benefit of the invention. For example, direct formation avoids using transfer polymers which are difficult to remove. Forming may be considered synonymous with synthesising, manufacturing, producing and growing. CVD is discussed in greater detail in respect of the method described herein. A person skilled in the art can readily ascertain whether the two-dimensional material is one has been grown directly on the substrate by CVD. This may be determined using conventional techniques in the art such as atomic force microscopy (AFM) and energy dispersive X-ray (EDX) spectroscopy. The two-dimensional material can be devoid of copper contamination and devoid of organic polymer residues by virtue of the complete absence of contacting these materials with the two-dimensional material in the process (graphene, for example, being commonly grown by CVD indirectly on a sacrificial catalytic copper substrate before transfer to a non-metallic surface). Furthermore, such transfer processes are generally not suitable for large scale manufacture (such as on silicon based substrates in fabrication plants), or at least are not economical. The device comprises a gold layer on a portion of the two-dimensional material layer structure adjacent an edge thereof. Preferably, particularly for sensors, a further surface portion of the two-dimensional layer structure is exposed. The exposed surface of the two-dimensional material layer structure may preferably be functionalised with an analyte-receptor. Suitable receptors for functionalising two-dimensional materials, including graphene, are well-known in the art. An analyte is chemical species of interest to be measured, for example to either detect its presence or more quantitively its concentration in the sample to be tested. A sensor is a device which generates a signal in response to a biological or chemical interaction with an analyte to be measured. A typical sensor comprises an analyte-receptor (for example a biosensor comprises a bioreceptor), transducer, electronics and a display, so as to measure the analyte. There are many different conventional configurations of such components. In some systems, they may be integrated within a single apparatus, or the biosensor might form part of a system which includes a separate reader that has the display and carries out the diagnosis. Alternatively, in other systems, a cloud-based service is for data analysis / diagnosis and a remote computer provides the diagnosis and display. A bioreceptor is a molecule or other biological element or species that serves to recognise the analyte. Bioreceptors include, though are not limited to, enzymes, cells, aptamers, DNA, RNA and antibodies. The interaction between the analyte and bioreceptor is also known as biorecognition and the biorecognition event (such as a change of light, heat, pH, charge or mass) is a form of energy which is then converted to a measurable signal by the transducer (i.e. the two-dimensional material layer structure). The electronics serve to process and prepare the transducer signal for display by the display to a user. For example, a processor or a signal processing unit can process a voltage signal generated by the transducer by signal conditioning, such as by amplification and conversion of signals from analogue into the digital form. The processed signals are then quantified by the display unit of the biosensor. Such processing can take place remotely. The user of the biosensor device may be different to the user who analyses the output. In other technical fields, sensors described herein may be used for gas sensing, pH sensing or ion sensing. As such, the devices find particular application in healthcare and diagnosis, environmental monitoring in agriculture for example, for testing foods, and the presence of heavy metals (and / or their ions). The sensor comprises first and second electrical contacts provided in contact with the two-dimensional material layer structure, typically arranged on opposite sides of the sample surface (e.g. adjacent opposite parallel edges). The electrical contacts are metallic contacts made of the stack of gold and first, second and third metals described herein. The relative arrangement of such contacts at opposite sides of the sample surface is well-known in the art and serves to define a sample-surface of the transducer for receiving an analyte composition therebetween the contacts. The sensor may also comprise a gate contact as is known for field-effect transistor based sensors. It is particularly preferred that the gate contact is formed on the substrate from the contact-stack described herein, such a gate contact may be used as a common gate contact for two or more sensors manufactured on a common underlying substrate. An electronic device may comprise two or more individual devices (where the individual devices may then be referred to as cells) which may then share common device features elsewhere on the substrate (e.g. the common gate contact). The following description will focus on an individual device or cell, though it will be appreciated an array of individual components may be manufactured simultaneously on a common substrate / wafer. The gold layer on the two-dimensional material layer structure may be referred to herein as the primary gold layer, for example to distinguish from any gold included in the second metal layer of the contact-stack (which itself may be referred to as a secondary gold layer). The gold layer is provided adjacent an edge of the two-dimensional material layer structure. The gold layer may comprise two portions each adjacent two opposite edges for providing electrical contacts. As described herein, the two dimensional material layer structure and the gold layer are patterned during manufacture simultaneously to form a co-patterned stack. This may be performed using conventional techniques such as photolithography and etching. As a result, the gold layer is not on the substrate and only on the two-dimensional material, and during device manufacture, etching after formation of the contact-stack, preferably after patterning a dielectric layer thereon, may further pattern the gold layer so as to expose a portion of the two-dimensional material (and form the two electrical contacts for example). Preferably, the gold layer has a thickness of 20 to 200 nm, preferably 80 to 120 nm. The device further comprises a contact-stack adjacent the edge of two-dimensional material layer structure and overlapping the gold layer. That is, the contact-stack is provided on the substrate adjacent the edge of two-dimensional material layer structure. Preferably, the contact-stack on the substrate further extends to form a connection-track for a circuit, for example to connect source and drain contacts. In a particularly preferred embodiment, the circuit further comprises a gate contact on the substrate surface, the gate contact therefore being formed of the contact-stack of metals. The contact-stack advantageously allows for the gate contact to be exposed during the gold etching step, thereby reducing the number of manufacturing steps in embodiments where a dielectric layer is patterned thereon. The contact-stack comprises a first metal layer on a portion of the substrate and on the gold layer, wherein the first metal is selected from the group consisting of titanium (Ti) and chromium (Cr). Preferably, the first metal layer has a thickness of less than 15 nm and / or more than 1 nm, such as from 3 to 10 nm. The first metal layer is an adhesion promoter facilitating adhesion of the second metal to the substrate surface, especially non-metallic surfaces such as silicon and metal oxides (e.g. sapphire and rare earth oxides). As such, only a relatively thin layer is required. The use of titanium and / or chromium in adhesion layers is well-known for the manufacture of contacts, these metals typically forming covalent interactions with the substrate to ensure good adhesion, and having good adhesion properties to metals suitable for the second layer. The contact-stack further comprises a second metal layer on the first metal layer, wherein the second metal is selected from the group consisting of aluminium (Al), copper (Cu), gold (Au), nickel (Ni) and palladium (Pd). Preferably, the second metal layer has a thickness of at least 50 nm and / or at most 100 nm, preferably 70 to 90 nm. The second metal layer is generally deposited directly after the first metal layer and therefore takes the same pattern as the first metal layer (so as to be on and across the first metal layer), as does the subsequent third metal layer. As is known in the art, a circuit pattern may be provided by a patterned photoresist using photolithography, which, following deposition of the various metal layers, may be removed in a lift-off step to leave the patterned contact-stack. Adhesion of the metals layers is required, at least to provide a desirably low contact resistance, as is generally the focus of the prior art. However, the inventors have also found that the mechanical properties of the layers are important for forming contacts to two-dimensional materials due to their relatively weak interaction with the substrate which makes them vulnerable to delamination. The thermal expansion between the various layers and the substrate can induce stress in microfabricated layers. Such stress can alter the adhesion properties, and the inventors have found that appropriate selection of the metals and their thickness can alleviate such a problem. Moreover, the inventors have also identified metals which provide the desired chemical properties so as to be able to protect the contact-stack during the gold etch. When selected from the metals described herein, the second metal layer is stress relieving, allowing the second metal layer to generally be the thickest layer of the contact-stack, providing the desired electrical conductivity for the contacts and associated circuitry. It is generally preferred that the second metal comprises or consists essentially of gold, though in some embodiments, combinations of the metals may be used. Exemplary combinations include gold on nickel or palladium. Nickel and palladium can act as a diffusion barrier to prevent diffusion of the first metal into the second metal layer and may be provided with a thickness of from 10 to 20 nm (e.g. about 15 nm Ni or Rd together with about 60 nm Au). The contact-stack further comprises a third metal layer on the second metal layer, wherein the third metal is selected from the group consisting of cobalt (Co), chromium (Cr), iridium (Ir), iron (Fe), magnesium (Mg), niobium (Nb), platinum (Pt), ruthenium (Ru), silver (Ag), tantalum (Ta), titanium (Ti), titanium nitride (TiN) and tungsten (W). The third metal layer preferably has a thickness sufficient to be conformal (i.e. a complete layer absent any pin-holes or the like). Preferably, the third metal layer has a thickness of less than 35 nm and / or more than 10 nm, preferably 15 to 30 nm. Preferably, the contact-stack has a thickness extending orthogonally from the substrate by a distance of 80 to 200 nm (that is the total thickness of the first, second and third metal layers). Thus, in one preferred embodiment, the first metal layer has a thickness of less than 15 nm, the second metal layer has a thickness of from 50 to 100 nm, and the third metal layer has a thickness of less than 35 nm. As described herein, it is also particularly preferred that the second metal is gold and the third metal is platinum. Consequently, another preferred embodiment is a semiconductor device comprising: a substrate having a patterned two-dimensional material layer structure thereon; a primary gold layer on a portion of the two-dimensional material layer structure adjacent an edge thereof; and a contact-stack adjacent the edge of two-dimensional material layer structure and overlapping the primary gold layer, the contact-stack comprising: (i) a titanium and / or chromium layer on a portion of the substrate and on the gold layer; (ii) a secondary gold layer on the titanium and / or chromium layer; and (iii) a platinum layer on the secondary gold layer, the platinum layer having a thickness of less than 35 nm. The third metal layer is resistant to gold etching solutions, in particular the preferred iodine / potassium iodide solutions, thereby protecting the underlying second metal layer which is vulnerable to etching with gold etchants. As with the second metal layer, the third metal layer may comprise two or more of such metals, or preferably consists essentially of one metal. Preferred metals are those which are particularly resistant to gold etchants as well as oxidation. As such, preferred metals include chromium, iridium, niobium, platinum, ruthenium, silver, tantalum, titanium and titanium nitride, more preferably platinum. Whilst a ceramic material, titanium nitride, particularly thin layers, is a known conductive ceramic nitride often referred to in the art as a barrier metal to chemically isolate semiconductors from soft metal interconnects whilst maintaining electrical connection between them. As such, a skilled person would readily recognise titanium nitride as a suitable metal in the context of a contact-stack. Platinum is also used as a reference in electrochemical applications and therefore provides a particularly suitable metal for the third metal layer as a protective layer of a gate contact. Due to the stress that can be imparted by the metals used in the third metal layer, the inventors have found that it is particularly desirable to use a layer thinner than the second metal layer, such as less than 35 nm. The layer typically has internal stresses at large thicknesses following metal deposition, which if too large can propagate through the layers. If this is greater than the adhesion of the two-dimensional material layer structure on the substrate surface, the inventors have found that this leads to delamination, including delamination of the entire device structure. The device may further comprise a patterned dielectric layer on and across the contact-stack, the dielectric layer being patterned to expose the gate contact and a portion of the two-dimensional material layer structure. That is, the dielectric layer is provided at least on and across the contacts on the two-dimensional material (e.g. source and drain) as well as the metal tracks. For sensors, the dielectric layer may be patterned to provide a window through to the exposed sample surface of the two-dimensional material layer structure. In some preferred embodiments, the window provided by the dielectric layer extends onto the surface of the two-dimensional material thereby encapsulating the edges of the two-dimensional material and isolating the sample surface from the electrical contacts. Consequently, during manufacture the dielectric layer may be patterned simultaneously to provide a window to the gold layer on the two-dimensional material and a window to the further metal stack (e.g. a gate contact), such that the gold layer may then be etched to expose the surface of the two-dimensional material layer structure with the gate contact having already been exposed improving manufacturing efficiency. The dielectric layer on the precursor gold layer can also help to encapsulate the edges of the second metal layer during the gold etch step, though some undercutting of the third metal layer in the absence of the dielectric layer would nevertheless still permit top-down etching of the gold layer to expose the two-dimensional material layer. The method described herein of forming the semiconductor device comprises: (a) forming a precursor comprising: a substrate having a patterned two-dimensional material layer structure thereon; a precursor gold layer on the two-dimensional material layer structure; and a contact-stack as described herein adjacent the edge of two-dimensional material layer structure and overlapping the precursor gold layer; and (b) etching the precursor gold layer with a gold etchant to form the device. The method therefore comprises partially etching the precursor gold layer thereby exposing a portion of the underlying two-dimensional material layer structure. The remaining portion of the precursor gold layer provides the (primary) gold layer of the product as an electrical contact on the surface of the two-dimensional material layer structure. The pattern of gold etching may be controlled by the pattern of the overlapping contact-stack which protects the underlying gold layer and optionally a patterned dielectric layer. As described herein, it is also particularly preferred that the method comprises directly forming the two-dimensional material layer structure on a growth surface of the substrate by CVD. CVD refers generally to a range of chemical vapour deposition techniques, each of which involve deposition to produce thin film materials such as two-dimensional crystalline materials like graphene, optionally under vacuum / reduced pressure. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. The description herein for the CVD of graphene may be modified accordingly to produce other two-dimensional materials. CVD as described herein is intended to refer to thermal CVD such that the formation of graphene from the decomposition of a carbon-containing precursor is the result of the thermal decomposition of said carbon-containing precursor. A CVD layer formed directly on a surface can be distinguished from one transferred, either due to impurities or other defects such as cracks and wrinkles. Preferably, the method involves forming graphene by thermal CVD such that decomposition is a result of heating the carbon-containing precursor. Preferably, the temperature of the growth surface during CVD is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. The inventors have found that such temperatures are particularly effective for providing graphene growth directly on the materials described herein by CVD. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber. In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm, between the surface of the substrate and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the substrate and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the substrate surface. Accordingly, such an embodiment involves a “vertical” arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the substrate surface (i.e. the growth surface). The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C. For the avoidance of doubt, the addition of precursor at a temperature above ambient does not constitute heating the chamber, since it would be a drain on the temperature in the chamber and is responsible in part for establishing a temperature gradient in the chamber. Preferably, a combination of a sufficiently small separation between the substrate surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the substrate to with a decomposition range of the precursor, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017 / 029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform two-dimensional material layers directly on non-metallic substrates, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® Turbo Disk reactor. Consequently, in a particularly preferred embodiment wherein the method of the present invention involves using a method as disclosed in WO 2017 / 029470, forming a graphene layer structure directly on a substrate by CVD comprises: providing the growth substrate on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; cooling the inlets to less than 100°C (i.e. so as to ensure that the precursor is cool as it enters the reaction chamber); introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the substrate surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm. The rotation rate of the heated susceptor in a close-coupled reaction chamber is typically less than 300 rpm, or even less than 200 rpm. In another particularly preferred embodiment wherein the method involves using a method as disclosed in WO 2019 / 138231, forming a graphene layer structure directly on a substrate by CVD comprises: providing the growth substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor; wherein the constant separation is at least 12 cm, preferably up to 20 cm. The most common carbon-containing precursor in the art for graphene growth is methane (CH4). The inventors have found that it is preferable that the carbon-containing precursor used to form graphene is an organic compound, that is, a chemical compound, or molecule, that contains a carbon-hydrogen covalent bond, which comprises two or more carbon atoms. The carbon-containing precursor is preferably a C3-C10 organic compound consisting of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and / or bromine, even more preferably a Ce-Cg organic compound. In a preferred embodiment, the precursor does not comprise a heteroatom, such that the precursor consists of carbon and hydrogen. In other words, preferably the carbon-containing precursor is a hydrocarbon, preferably an alkane. It is also preferable that the organic compound comprise at least two methyl groups (-CH3). Suitable precursors for other two-dimensional materials are known. TMDCs may be grown by a combination of metal precursor and chalcogenide precursor (introduced into the reaction chamber simultaneously or sequentially). The high quality material produced by such CVD methods also has fewer and weaker interactions with the substrate as a result of there being fewer defects in the two-dimensional material layer (in particular when compared to transferred materials or graphene grown by sublimation of silicon from silicon carbide). This is beneficial is terms of the unique electronic properties of the two-dimensional material, and as such, the directly grown material can be more susceptible to delamination. Therefore, there is a synergistic benefit associated with such combinations. Depositing the gold layer on and across the two-dimensional material layer structure may be achieved by conventional techniques, for example sputtering, thermal evaporation or e-beam evaporation. The gold layer is preferably deposited with a thickness of from 20 to 200 nm and is generally deposited across the whole surface. Preferably, one or more, and optionally all, of the precursor gold layer, the first metal layer, the second metal layer and the third metal layer are formed by e-beam, sputtering or vapour deposition techniques. Patterning the two dimensional material layer structure and the gold layer simultaneously to form a co-patterned stack may be performed using conventional techniques such as photolithography and etching. By co-patterned, it is meant that the gold layer and the two-dimensional material layer structure have coincident shapes with aligned edges. Typically, a mask is patterned onto the surface of the stack using a photoresist and both layers of the stack may be etched in a single step, or two steps with one for each layer. The patterned photoresist may be heated (which may be referred to as “curing” or “baking”) to improve adhesion to the gold layer prior to the etching step. Such a heating step to cure the photoresist is well-known in the art and can include heating up to about 180°C, or up to 160°C, for example from 80°C to 140°C and up 10 minutes, for example from 1 to 3 minutes. The cured photoresist may be washed away following etching using an appropriate solvent. The contact-stack may be deposited at this stage in contact with the gold layer and an edge of the two-dimensional material layer structure. The contact-stack can provide the desired circuitry for a final device. That is, the further metal may be used to provide circuit “tracks” and preferably, a gate contact on the substrate. The contact-stack may similarly be formed by photolithography using photoresist to pattern the metal through a lift-off process, having deposited the first, second and third metal layers to their desired thickness, sequentially. Etching the gold layer is preferably performed by a wet-etching method. Suitable methods for etching, and etching solutions for wet-etching of gold are well-known. Gold is particularly advantageous in this regard since gold may be etched with a relatively mild solution. Most common is a solution of potassium iodide and / or iodine, the metals of the third metal layers being resistant to etching by such a solution. Various commercial etchants (sometimes referred to as developing solutions) are also readily available. Preferably, the etching solution has a pH of greater than 5 and / or less than 9, such as about 7 to about 8, thereby avoiding undue damage to the two-dimensional material upon exposure. Etching time and temperature may be varied to control the degree of etching. Typically, a wet-etch may take up to 30 minutes, such as from 1 to 10 minutes, or even from 2 to 5 minutes. That is, wetetching may take place by submerging the entire substrate in an etchant solution for such time. The etching may be performed at room temperature (e.g. about 15°C to about 25°C), or may be gently heated, such as up to 50°C. The etching solution is then washed away and the device structure rinsed, such as with deionised water, and the structure is dried. Drying may be accelerated with gentle heating (e.g. up to 50°C) and / or a flow of dry inert gas such as nitrogen. Figures The present invention will now be described further with reference to the following non-limiting Figures, in which: Figures 1 to 3 illustrate, in cross-section, an embodiment of the method of the present invention. Figure 4 is an image of an example substrate in which device precursors manufactured thereon have delaminated. Figures 1 to 3 are schematics illustrating the present invention and the relative dimensions and shapes of some features / layers may be exaggerated and / or simplified and not presented to scale to improve the clarity of the drawing. The relative dimensions and sizes do not necessarily correspond to those of practical embodiments of the invention. Equivalent features have been given equivalent labels across the Figures. Figures 1 to 3 illustrate, in cross-section, an exemplary method in accordance with the present invention for the manufacture of device 200. A two-dimensional material layer structure such as a monolayer of graphene 210 is provided on and across the surface of a substrate 205 (for example, sapphire). The graphene monolayer 210 may be formed by CVD directly on the substrate 205 avoiding the need for physical transfer. In a first step 100, a primary gold metal layer 215 is deposited on and across the entire surface of the graphene 210, for example to a thickness of about 100 nm. A photoresist 220 is then coated on and across the gold layer 215 in step 105, before patterning into a patterned photoresist 220’ in step 110 and subsequently baking. Photoresist 220 can be patterned by conventional photolithography techniques thereby exposing portions of the underlying gold layer 215. In step 115, the exposed portion of the gold layer 215 and the corresponding underlying portion of the graphene 210 are then etched away to leave a co-patterned stack of the gold layer 215’ and the graphene 210’ having opposite edges (210a’, 210b’). Finally in Figure 1, the patterned photoresist 220’ is washed away in step 120 to leave the co-patterned stack (21 O’, 215’) whereby the patterned gold layer 215’ has the same shape with coincident edges as the patterned graphene 21 O’. As shown in Figure 2, the stack on the substrate 205 is then coated with a further photoresist 225 in step 125 which is then patterned in step 130 to expose portions of the underlying patterned gold layer 215’ adjacent the edges of the stack leaving a patterned further photoresist layer 225’. As shown in the specific cross-section of Figures 1 to 3, opposite edges of the stack comprising the patterned graphene 210’ are exposed. In step 135, a first metal 230 for the contact-stack is deposited, the first metal being formed of titanium and / or chromium to a thickness of about 10 nm for example. A second metal layer 235 comprising gold is then deposited in step 140 to a thickness of about 80 nm, followed by a platinum layer 240 having a thickness of about 30 nm. As shown in Figure 3, the patterned further photoresist layer 225’ is then removed in a conventional “lift-off” step 150 thereby removing the stack of first, second and third metals deposited on the patterned further photoresist layer 225’ so as to leave portions of the metal layers (230’, 235’, 240’) forming a contact-stack 230’. Each portion is in contact with opposite edges (210a’, 21 Ob’) of the graphene 210’ and on the substrate 205, via the first metal layer 230’, and may act as source and drain contacts. Elsewhere on the substrate 205, the stack of first, second and third metals (230’, 235’, 240’) provide the desired circuitry to integrating the structure into a larger device, including a gate contact (not shown). The lift-off exposes a window to the gold layer 215’ entirely above the graphene 21 O’. Finally, the patterned gold layer 215’ is etched in step 155 using a gold etching solution, such as one of potassium iodide and iodine in water. Etching step 155 exposes the upper surface 210c’ of the patterned graphene monolayer 21 O’, thereby forming device 200 which is suitable for use as a sensor. Figure 4 is an image of an example wafer in which precursor device precursors manufactured thereon have delaminated. The precursor devices include a patterned graphene monolayer 310’, co-patterned with a (primary) gold layer 315’ thereon, further including a contact-stack (330’, 335’, 340’) comprising a first titanium layer 330’, a second (or secondary) gold layer 335’, and a third platinum layer 340’ having a thickness of 40 nm. In this example, the thickness of the platinum layer is too large and introduces too much stress which overcomes the adhesion of the graphene monolayer 310’ to the substrate. Consequently, in two cells (approximately top-right and bottom-left in Figure 4), the graphene precursor devices have completely delaminated exposing the substrate 305 between two tracks of the contact-stack (330’, 335’, 340’), and in the other two cells (approximately top-left and bottom-right in Figure 4), the edges of the patterned graphene 310’ having a portion of the contactstack (330’, 335’, 340’) thereon have delaminated exposing the underlying substrate 305. As used herein, the singular form of “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. The use of the term “comprising” is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of “consisting essentially of” (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and “consisting of” (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise. It will be understood that, although the terms "first", "second", “primary” etc. may be used herein to describe, for example, various metals, layers and / or portions, the metals, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one metal, layer or portion from another, or a further, metal, layer or portion. It will be understood that the term “on” is intended to mean “directly on” such that there are no intervening layers between one material being said to be “on” another material. Spatially relative terms, such as “under”, "below", "beneath", "lower", “over”, "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device as described herein is turned over, elements described as "under” or “below" other elements or features would then be oriented “over” or "above" the other elements or features. Thus, the example term "under" can encompass both an orientation of over and under. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly. Numerical lower and upper limits of features described herein may preferably be combined to provide a closed range. The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents. For the avoidance of doubt, the entire contents of all documents acknowledged herein are incorporated herein by reference.

Claims

1. A semiconductor device comprising:a substrate having a patterned two-dimensional material layer structure thereon;a gold layer on a portion of the two-dimensional material layer structure adjacent an edge thereof; anda contact-stack adjacent the edge of two-dimensional material layer structure and overlapping the gold layer, the contact-stack comprising:(i) a first metal layer on a portion of the substrate and on the gold layer, wherein the first metal is selected from the group consisting of titanium and chromium;(ii) a second metal layer on the first metal layer, wherein the second metal is selected from the group consisting of aluminium, copper, gold, nickel and palladium; and(iii) a third metal layer on the second metal layer, wherein the third metal is selected from the group consisting of cobalt, chromium, iridium, iron, magnesium, niobium, platinum, ruthenium, silver, tantalum, titanium, titanium nitride, and tungsten.

2. The semiconductor device according to claim 1, wherein the third metal layer has a thickness of less than 35 nm, preferably 15 to 30 nm.

3. The semiconductor device according to claim 1 or claim 2, wherein the second metal layer has a thickness of at least 50 nm and / or at most 100 nm, preferably 70 to 90 nm.

4. The semiconductor device according to any preceding claim, wherein the gold layer has a thickness of 20 to 200 nm, preferably 80 to 120 nm.

5. The semiconductor device according to any preceding claim, wherein the first metal layer has a thickness of less than 15 nm, preferably 3 to 10 nm.

6. The semiconductor device according to any preceding claim, wherein the third metal is platinum.

7. The semiconductor device according to any preceding claim, wherein the second metal is gold.

8. The semiconductor device according to any preceding claim, wherein the third metal layer is conformal.

9. The semiconductor device according to any preceding claim, wherein the contact-stack on the substrate further extends to form a connection-track for a circuit.

10. The semiconductor device according to claim 9, wherein the circuit comprises a gate contact.

11. The semiconductor device according to any preceding claim, wherein the two-dimensionalmaterial is graphene.

12. The semiconductor device according to any preceding claim, wherein the two-dimensional material layer structure is CVD-grown on the substrate.

13. The semiconductor device according to any preceding claim, wherein the contact-stack has a thickness extending orthogonally from the substrate by a distance of 80 to 200 nm.

14. The semiconductor device according to any preceding claim, wherein the substrate is sapphire or a rare earth oxide on silicon.

15. A method of forming the semiconductor device, wherein the method comprises:(a) forming a precursor comprising:a substrate having a patterned two-dimensional material layer structure thereon;a precursor gold layer on the two-dimensional material layer structure; anda contact-stack adjacent the edge of two-dimensional material layer structure and overlapping the precursor gold layer, the contact-stack comprising:(i) a first metal layer on a portion of the substrate and on the precursor gold layer, wherein the first metal is selected from the group consisting of titanium and chromium;(ii) a second metal layer on the titanium and / or chromium layer, wherein the second metal is selected from the group consisting of aluminium, copper, gold, nickel and palladium; and(iii) a third metal layer on the second metal layer, wherein the third metal is selected from the group consisting of cobalt, chromium, iridium, iron, magnesium, niobium, platinum, ruthenium, silver, tantalum, titanium, titanium nitride and tungsten; and(b) etching the precursor gold layer with a gold etchant to form the device according to any preceding claim.

16. The method according to claim 15, wherein the semiconductor device has an exposed portion of the two-dimensional material layer structure.

17. The method according to claim 15 or claim 16, wherein one or more, preferably all, of the precursor gold layer, the first metal layer, the second metal layer and the third metal layer are formed by e-beam, sputtering or vapour deposition techniques.5 18. The method according to any of claims 15 to 17, wherein the gold etchant is an aqueoussolution comprising potassium iodide and / or iodine.

19. The method according to claim 18, wherein the etching solution has a pH of greater than 5 and / or less than 9.1020. The method according to any of claims 15 to 19, wherein the contact-stack on the substrate further extends to form a connection-track for a circuit comprising a gate contact, the precursor further comprising a patterned dielectric layer on and across the contact-stack and the precursor gold layer, the dielectric layer being patterned to expose the gate contact and a portion of the precursor gold15 layer.

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