Display panel and display apparatus

Abstract

A display panel, comprising: a substrate (10), a plurality of sub-pixels (PX) and a plurality of data lines (DL) located in a display area (AA), and a multiplexing circuit (30) located in a first frame area (B1). The plurality of data lines (DL) are connected to the plurality of sub-pixels (PX). The multiplexing circuit (30) comprises a plurality of multiplexing units (31, 32, 33). At least one multiplexing unit (31, 32, 33) comprises a plurality of multiplexing transistors. The multiplexing transistors of the plurality of multiplexing units (31, 32, 33) are arranged in a plurality of rows and columns, one row of multiplexing transistors comprises a plurality of multiplexing transistors arranged in a first direction (X), and one column of multiplexing transistors comprises a plurality of multiplexing transistors arranged in a second direction (Y). The first direction (X) intersects with the second direction (Y).

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on May 26, 2023, with application number 202310612612.5 and invention name “Display Panel and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, display devices using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display panel and a display device.

[0007] In one aspect, this embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, and a multiplexing circuit. The substrate includes a display area and a first frame area located on at least one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The multiplexing circuit is located in the first frame area and includes a plurality of multiplexing units. At least one of the plurality of multiplexing units includes a plurality of multiplexing transistors. The at least one multiplexing unit is electrically connected to a multiplexing data line, a plurality of multiplexing control lines, and a plurality of data lines, and is configured to provide data signals transmitted by the multiplexing data lines to the plurality of data lines via the control lines of the plurality of multiplexing control lines. The multiplexing transistors of the plurality of multiplexing units are arranged in multiple rows and columns. A row of multiplexing transistors includes a plurality of multiplexing transistors arranged along a first direction, and a column of multiplexing transistors includes a plurality of multiplexing transistors arranged along a second direction. The first direction and the second direction intersect.

[0008] In some example embodiments, a column of multiplexing transistors includes: a plurality of multiplexing transistors connected to the same multiplexing control line.

[0009] In some example embodiments, a column of multiplexing transistors includes a plurality of multiplexing transistors connected to a same multiplexing data line.

[0010] In some example embodiments, the multiplexing transistors of the multiplexing units are arranged in three rows.

[0011] In some exemplary embodiments, the at least one multiplexing unit includes two multiplexing transistors, the two multiplexing transistors are electrically connected to different multiplexing control lines and to the same multiplexing data line; and the two multiplexing transistors of the at least one multiplexing unit are arranged in the same row.

[0012] In some exemplary embodiments, the multiplexing units include at least a plurality of first multiplexing units, a plurality of second multiplexing units, and a plurality of third multiplexing units; the multiplexing transistors of the first multiplexing units are arranged in a first row, the multiplexing transistors of the second multiplexing units are arranged in a second row, and the multiplexing transistors of the third multiplexing units are arranged in a third row. The multiplexing transistors in the first, second, and third multiplexing units that are electrically connected to the same multiplexing control line are arranged in the same column.

[0013] In some exemplary embodiments, the plurality of sub-pixels include a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and a third sub-pixel that emits a third color light. The first multiplexing unit is configured to provide a data signal to the plurality of first sub-pixels, the second multiplexing unit is configured to provide a data signal to the plurality of second sub-pixels, and the third multiplexing unit is configured to provide a data signal to the plurality of third sub-pixels.

[0014] In some exemplary embodiments, the at least one multiplexing unit includes three multiplexing transistors, which are electrically connected to different multiplexing control lines and to the same multiplexing data line; the three multiplexing transistors of the at least one multiplexing unit are arranged in the same column.

[0015] In some exemplary embodiments, the plurality of sub-pixels include a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and a third sub-pixel that emits a third color light. The three multiplexing transistors of the at least one multiplexing unit are configured to provide data signals to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively.

[0016] In some exemplary embodiments, the three multiplexing transistors of the at least one multiplexing unit are a seventh multiplexing transistor, an eighth multiplexing transistor, and a ninth multiplexing transistor, and the seventh multiplexing transistor, the eighth multiplexing transistor, and the ninth multiplexing transistor located in the same column are staggered in the second direction.

[0017] In some exemplary embodiments, a plurality of the seventh multiplexing transistors are arranged in a first row, a plurality of the eighth multiplexing transistors are arranged in a second row, a plurality of the ninth multiplexing transistors are arranged in a third row, and the first row, the second row and the third row are arranged in sequence along a direction away from the display area.

[0018] In some example embodiments, the multiplexing transistors of the multiplexing units are arranged in two rows.

[0019] In some exemplary embodiments, the at least one multiplexing unit includes two multiplexing transistors, which are electrically connected to the first multiplexing control line and the second multiplexing control line, respectively, and are electrically connected to the same multiplexing data line; the two multiplexing transistors of the at least one multiplexing unit are arranged in different rows and different columns.

[0020] In some exemplary embodiments, the multiplexing transistors located in the i-th column are all electrically connected to the first multiplexing control line, the multiplexing transistors located in the i+1-th column are electrically connected to different multiplexing control lines, and the multiplexing transistors located in the i+2-th column are all electrically connected to the second multiplexing control line, where i is an integer greater than 0.

[0021] In some exemplary embodiments, the plurality of multiplexing units include at least: a plurality of first multiplexing units, a plurality of second multiplexing units, and a plurality of third multiplexing units. The plurality of sub-pixels include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. The first multiplexing unit is configured to provide data signals to the plurality of first sub-pixels, the second multiplexing unit is configured to provide data signals to the plurality of second sub-pixels, and the third multiplexing unit is configured to provide data signals to the plurality of third sub-pixels. The two multiplexing transistors of the first multiplexing unit are respectively located in the i-th column and the i+1-th column; the two multiplexing transistors of the second multiplexing unit are respectively located in the i-th column and the i+2-th column; and the two multiplexing transistors of the third multiplexing unit are respectively located in the i+1-th column and the i+2-th column.

[0022] In some exemplary embodiments, the first border region includes at least a first fan-out region and a bending region sequentially arranged away from the display region; the multiplexing circuit is located in the first fan-out region; the first fan-out region includes a plurality of data lead lines and a plurality of multiplexed data lines; and the bending region includes at least a plurality of data bending connection lines. The multiplexing circuit is electrically connected to the plurality of data lines in the display region via the plurality of data lead lines and to the plurality of multiplexed data lines, and the plurality of multiplexed data lines are electrically connected to the plurality of data bending connection lines.

[0023] In some exemplary embodiments, the first border region includes at least a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer disposed on the substrate. The multiplexed data lines are alternately arranged in the first conductive layer and the second conductive layer. The multiple data lead lines are alternately arranged in the first conductive layer and the second conductive layer.

[0024] In some exemplary embodiments, the first border region further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate; and the plurality of data bending connection lines are located in the fourth conductive layer.

[0025] On the other hand, this embodiment provides a display device including the display panel as described above.

[0026] On the other hand, this embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, and a multiplexing circuit. The substrate comprises a display area and a first frame area located on at least one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The multiplexing circuit is located in the first frame area and comprises a plurality of multiplexing units. At least one of the plurality of multiplexing units comprises a plurality of multiplexing transistors. At least one multiplexing unit is electrically connected to a multiplexing data line, a multiplexing control line and a plurality of data lines, and is configured to provide the data signals transmitted by the multiplexing data lines to the plurality of data lines under the control of the a multiplexing control line, wherein a is an integer greater than 1 and less than or equal to 3. The plurality of multiplexing transistors of the at least one multiplexing unit are located in the same row, or in the same column, or in different rows. A row of multiplexing transistors includes a plurality of multiplexing transistors arranged along a first direction, and a column of multiplexing transistors includes a plurality of multiplexing transistors arranged along a second direction, wherein the first direction intersects the second direction.

[0027] In some example embodiments, a column of multiplexing transistors includes: a plurality of multiplexing transistors connected to a same multiplexing control line; or a plurality of multiplexing transistors connected to a same multiplexing data line.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0029] Summary of the Figures

[0030] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0031] FIG1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0032] FIG2 is a schematic plan view of the structure of a display panel according to at least one embodiment of the present disclosure;

[0033] FIG3 is a partial cross-sectional schematic diagram of a display area of ​​a display panel according to at least one embodiment of the present disclosure;

[0034] FIG4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0035] FIG5 is a partial schematic plan view of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0036] FIG6 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG5 ;

[0037] FIG7A is a schematic diagram of the display panel after the first conductive layer is formed in FIG5 ;

[0038] FIG7B is a schematic plan view of the first conductive layer in FIG7A ;

[0039] FIG8A is a schematic diagram of the display panel after the second conductive layer is formed in FIG5 ;

[0040] FIG8B is a schematic plan view of the second conductive layer in FIG8A ;

[0041] FIG9 is a schematic diagram of the display panel after the third insulating layer is formed in FIG5 ;

[0042] FIG10 is a schematic plan view of the third conductive layer in FIG5 ;

[0043] FIG11 is a partial schematic plan view of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0044] FIG12 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG11;

[0045] FIG13 is a schematic diagram of the display panel after the first conductive layer is formed in FIG11;

[0046] FIG14 is a schematic diagram of the display panel after the second conductive layer is formed in FIG11;

[0047] FIG15 is a schematic diagram of the display panel after forming the third insulating layer in FIG11;

[0048] FIG16A is a schematic diagram of the display panel after the third conductive layer is formed in FIG11;

[0049] FIG16B is a schematic plan view of the third conductive layer in FIG16A ;

[0050] FIG17 is a schematic diagram of the display panel after the fifth insulating layer is formed in FIG11;

[0051] FIG18 is another partial schematic plan view of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0052] FIG19 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG18;

[0053] FIG20A is a schematic diagram of the display panel after the first conductive layer is formed in FIG18;

[0054] FIG20B is a schematic plan view of the first conductive layer in FIG20A ;

[0055] FIG21A is a schematic diagram of the display panel after the second conductive layer is formed in FIG18;

[0056] FIG21B is a schematic plan view of the second conductive layer in FIG21A ;

[0057] FIG22 is a schematic diagram of the display panel after forming the third insulating layer in FIG18;

[0058] FIG23A is a schematic diagram of the display panel after forming the third conductive layer in FIG18;

[0059] FIG23B is a schematic plan view of the third conductive layer in FIG23A ;

[0060] FIG24 is a schematic diagram of the display panel after the fifth insulating layer is formed in FIG18;

[0061] FIG25 is another equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0062] FIG26 is a partial schematic plan view of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0063] FIG27 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG26;

[0064] FIG28A is a schematic diagram of the display panel after the first conductive layer is formed in FIG26 ;

[0065] FIG28B is a schematic plan view of the first conductive layer in FIG28A ;

[0066] FIG29A is a schematic diagram of the display panel after the second conductive layer is formed in FIG26 ;

[0067] FIG29B is a schematic plan view of the second conductive layer in FIG29A ;

[0068] FIG30 is a schematic diagram of the display panel after the third insulating layer is formed in FIG26;

[0069] FIG31 is a plan view of the third conductive layer in FIG26;

[0070] FIG32 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0071] Details

[0072] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the methods and contents can be transformed into a variety of forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0073] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0074] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0075] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0076] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0077] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0078] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0079] In this specification, "connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0080] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0081] The terms “approximately” and “substantially” in the present disclosure do not strictly define the limits and allow for errors within the range of process and measurement errors.

[0082] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0083] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0084] With the development of display technology, increasing the screen-to-body ratio and reducing the size of the border is an important direction of improvement. Current display panels are usually equipped with a multiplexing circuit (MUX) to reduce the number of data lines, thereby reducing the space required for the data lead lines in the border area to reduce the border size. Usually, the multiplexing circuit can adopt a 1:6 design (that is, a single multiplexing unit provides data signals to multiple data lines under the control of six multiplexing control lines), and the border space of the display panel (such as the display panel of a wearable product) is limited, and the layout form of the multiplexing circuit is relatively fixed. However, for display products with higher refresh rate requirements, the conventional multiplexing circuit using a 1:6 design will affect the display effect of display products with high refresh rate requirements.

[0085] This embodiment provides a display panel and a display device, which can arrange a multiplexing circuit that meets the high refresh rate requirements of the display product on a display panel with limited frame space, thereby realizing a layout design of a multiplexing circuit suitable for high refresh rate requirements.

[0086] This embodiment provides a display panel comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, and a multiplexing circuit. The substrate includes a display area and a first frame area located on at least one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. The multiplexing circuit is located in the first frame area and includes a plurality of multiplexing units. At least one of the plurality of multiplexing units includes a plurality of multiplexing transistors. The at least one multiplexing unit is electrically connected to a multiplexing data line, a plurality of multiplexing control lines, and a plurality of data lines, and is configured to provide the data signals transmitted by the multiplexing data line to the plurality of data lines under the control of the plurality of multiplexing control lines. The multiplexing transistors of the plurality of multiplexing units are arranged in multiple rows and columns. A row of multiplexing transistors includes a plurality of multiplexing transistors arranged along a first direction, and a column of multiplexing transistors includes a plurality of multiplexing transistors arranged along a second direction. The first direction and the second direction intersect. For example, the first direction may be perpendicular to the second direction.

[0087] The display panel provided in this embodiment arranges the multiplexing transistors of the multiplexing circuit in an array, so that the multiplexing circuit suitable for high refresh rate requirements can be arranged in a frame area with limited space.

[0088] In some exemplary embodiments, a column of multiplexing transistors may include multiplexing transistors connected to the same multiplexing control line. This example arranges multiple multiplexing transistors connected to the same multiplexing control line in a column, thereby reducing the occupied space of the multiplexing circuit in the first direction.

[0089] In some exemplary embodiments, a column of multiplexing transistors may include multiple multiplexing transistors connected to the same multiplexing data line. This example facilitates reducing the space occupied by the multiplexing circuit in the first direction by arranging multiple multiplexing transistors connected to the same multiplexing data line in a column. For example, at least one multiplexing unit may include three multiplexing transistors, each electrically connected to different multiplexing control lines and to the same multiplexing data line. The three multiplexing transistors of the at least one multiplexing unit may be arranged in the same column.

[0090] In some exemplary embodiments, the multiplexing transistors of the multiplexing circuit may be arranged in three rows. This embodiment is not limited to this. In other examples, the multiplexing transistors of the multiplexing circuit may be arranged in two rows or more than three rows, such as six rows.

[0091] In some exemplary embodiments, at least one multiplexing unit includes two multiplexing transistors, the two multiplexing transistors being electrically connected to different multiplexing control lines and electrically connected to the same multiplexing data line. The two multiplexing transistors of the multiplexing unit can be arranged in the same row. In some examples, the multiplexing units can include at least: a plurality of first multiplexing units, a plurality of second multiplexing units, and a plurality of third multiplexing units. The multiplexing transistors of the plurality of first multiplexing units can be arranged in a first row, the multiplexing transistors of the plurality of second multiplexing units can be arranged in a second row, and the multiplexing transistors of the plurality of third multiplexing units can be arranged in a third row. The multiplexing transistors in the first, second, and third multiplexing units that are electrically connected to the same multiplexing control line can be arranged in the same column. For example, the gates of the plurality of multiplexing transistors in a column of multiplexing transistors can be interconnected as an integrated structure. The arrangement of this example helps reduce the space occupied by the multiplexing circuit in the first direction.

[0092] In some exemplary embodiments, the plurality of sub-pixels may include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. The first multiplexing unit may be configured to provide data signals to the plurality of first sub-pixels, the second multiplexing unit may be configured to provide data signals to the plurality of second sub-pixels, and the third multiplexing unit may be configured to provide data signals to the plurality of third sub-pixels. The multiplexing circuit of this example may adopt a 1:2 design to provide data signals to the plurality of sub-pixels, wherein a single multiplexing unit may provide data signals to adjacent sub-pixels of the same color, which not only reduces the load of the data signal but also facilitates achieving high refresh rate requirements.

[0093] The solution of this embodiment is illustrated below through multiple examples.

[0094] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display panel may include: a display area AA, a first border area B1 located on one side of the display area AA, and a second border area B2 located on the remaining sides of the display area AA. The first border area B1 may be connected to the second border area B2. For example, the first border area B1 may be the bottom border of the display panel, and the second border area B2 may include the remaining border area of ​​the display panel excluding the bottom border.

[0095] In some examples, as shown in FIG1 , the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic image or a still image. The display area AA may be referred to as an active area. In some examples, the display area AA may be circular or elliptical. However, this embodiment is not limited thereto. For example, the display area may be other shapes such as a rectangle. In some examples, the display panel may be a flexible panel, and thus the display panel may be deformable, such as being curled, bent, folded, or rolled up.

[0096] In some examples, as shown in FIG1 , the display area AA may include: a display structure layer provided on a substrate, or may include a display structure layer and a touch structure layer provided in sequence on a substrate. For example, the display panel may integrate a touch structure to form a structure in which the touch structure is on a thin film package (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The Touch on TFE structure mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0097] In some examples, the display structure layer may include a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions. One sub-pixel PX may be arranged in one sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate drive signals to the plurality of sub-pixels PX. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0098] In some examples, as shown in FIG1 , the first direction X may be an extending direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y may be an extending direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0099] Figure 2 is a schematic diagram of the planar structure of a display panel of at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, a pixel unit P in the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel P1 emitting a first color light (e.g., red light), a second sub-pixel P2 emitting a second color light (e.g., green light), and a third sub-pixel P3 emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0100] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0101] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0102] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel, that is, an LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0103] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0104] FIG3 is a partial cross-sectional schematic diagram of the display area of ​​a display panel according to at least one embodiment of the present disclosure. FIG3 illustrates the structure of a sub-pixel in the display area as an example. In this example, the multiple transistors in the pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors or oxide thin-film transistors.

[0105] In some examples, as shown in FIG3 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 10. The display structure layer may include at least the circuit structure layer 12 and the light-emitting structure layer 13. The circuit structure layer 12 may include at least pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least light-emitting elements for multiple sub-pixels.

[0106] In some examples, FIG3 illustrates a thin film transistor 21 and a capacitor 22 included in each sub-pixel as an example. In some examples, the circuit structure layer 12 of the display area may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer provided on the substrate 10. A first insulating layer 101 may be provided between the semiconductor layer and the first conductive layer, a second insulating layer 102 may be provided between the first conductive layer and the second conductive layer, a third insulating layer 103 may be provided between the second conductive layer and the third conductive layer, a fourth insulating layer 104 and a fifth insulating layer 105 may be provided between the third conductive layer and the fourth conductive layer, and a sixth insulating layer 106 may be provided on the side of the fourth conductive layer away from the substrate 10. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 may be inorganic insulating layers, and the fifth insulating layer 105 and the sixth insulating layer 106 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also improve the adhesion of the film layer in the display panel to the substrate. In other examples, the fourth insulating layer may be omitted between the third and fourth conductive layers, and only the fifth insulating layer may be provided. Alternatively, the fifth insulating layer may be omitted between the third and fourth conductive layers, and only the fourth insulating layer may be provided.

[0107] In some examples, as shown in FIG3 , the semiconductor layer in the display area may include at least an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first conductive layer may include at least a gate electrode 213 of the thin film transistor 21 and a first plate 221 of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin film transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 10. The second conductive layer may include at least a second plate 222 of the capacitor 22. The orthographic projections of the second plate 222 and the first plate 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, they may coincide. The third conductive layer may include at least a source electrode 211 and a drain electrode 212 of the thin film transistor 21. The third insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The fourth conductive layer may include at least an anode connection electrode 231. The anode connection electrode 231 can be electrically connected to the drain electrode 212 of the thin-film transistor 21 through the third pixel via defined in the sixth insulating layer 106. In some examples, the gate lines of the display area may be located in the first conductive layer, and the data lines and the high-potential power supply lines of the display area may be located in the third conductive layer or the fourth conductive layer.

[0108] In some examples, as shown in FIG3 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the sixth insulating layer 106 and electrically connected to the anode connection electrode 231 through a third pixel via provided in the sixth insulating layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 106. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0109] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0110] In some examples, the light-emitting layers of light-emitting elements emitting light of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0111] In some examples, as shown in FIG3 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of an inorganic material, and the second encapsulation layer 142 may be made of an organic material. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0112] In some examples, the touch structure layer 15 may include multiple touch units. At least one touch unit may include at least one touch electrode. The orthographic projection of at least one touch electrode on the substrate may include the orthographic projections of multiple sub-pixels on the substrate. When the touch unit includes multiple touch electrodes, the multiple touch electrodes may be arranged at intervals, and adjacent touch electrodes may be connected to each other through connecting portions. The touch electrodes and the connecting portions may be in the same layer structure. In some examples, the touch electrode may have a rhombus shape, for example, a regular rhombus, a horizontally long rhombus, or a vertically long rhombus. However, this embodiment is not limited to this. In some examples, the touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons.

[0113] In some examples, as shown in Figure 1, the first frame area B1 may include: a first fan-out area B11, a bending area B12, a second fan-out area B13, a first signal access area B14, and a second signal access area B15, which are arranged in sequence along a direction away from the display area AA. The first fan-out area B11 may be connected to the second frame area B2 and be located on one side of the display area AA. For example, the first fan-out area B11 may be provided with at least a first frame power line, a second frame power line, a plurality of display lead lines, and a plurality of touch lead lines. The first frame power line may be configured to connect the first power line (e.g., a high potential power line) of the display area AA. The second frame power line may be configured to connect the second power line (e.g., a low potential power line) in the second frame area B2. The multiple display lead lines may include a plurality of data lead lines and a plurality of drive lead lines. The multiple data lead lines may be electrically connected to the multiple data lines of the display area AA, for example, in a one-to-one electrical connection. Multiple drive lead lines can extend to the second border area B2 and be electrically connected to the gate drive circuit in the second border area B2. They can be configured to provide control signals to the gate drive circuit. For example, the control signals may include a start signal, a clock signal, etc. Multiple touch lead lines can extend from the second border area B2 to the first fan-out area B11 and can be located on the side of the multiple display lead lines away from the substrate.

[0114] In some examples, as shown in Figure 1, the bending area B12 can be connected to the first fan-out area B11 and the second fan-out area B13 and located on the side of the first fan-out area B11 away from the display area AA. The bending area B12 can be configured to bend the second fan-out area B13, the first signal access area B14, and the second signal access area B15 toward the back of the display area AA. The bending area B12 can be provided with multiple bending connection lines, such as multiple data bending connection lines, multiple touch bending connection lines, etc. For example, the multiple bending connection lines within the bending area B12 can be provided on the same layer, such as all located in the fourth conductive layer or the third conductive layer.

[0115] In some examples, as shown in FIG1 , the second fan-out region B13 may be located on a side of the bending region B12 away from the display region AA. For example, a plurality of test circuits may be provided in the second fan-out region B13.

[0116] In some examples, as shown in FIG1 , the first signal access area B14 may be located on a side of the second fan-out area B13 away from the display area AA. The first signal access area B14 may also be referred to as a driver chip setting area. The first signal access area B14 may be provided with a plurality of first contact pads (Bumps), which may be configured to be bound and connected to at least one driver chip (IC, Integrated Circuit). The driver chip may be configured to generate a drive signal required to drive the sub-pixel, for example, a data signal.

[0117] In some examples, as shown in Figure 1, the second signal access area B15 can be located on a side of the first signal access area B14 away from the display area AA. The second signal access area B15 can also be referred to as a circuit binding area. The second signal access area B15 can be provided with a plurality of second contact pads. The plurality of second contact pads can be configured to be bound and connected to at least one circuit board (e.g., a flexible printed circuit board (FPC)). For example, an external circuit board can be configured to generate a touch signal provided to the touch structure and receive a touch sensing signal.

[0118] In some examples, a multiplexing circuit may also be provided in the first fan-out area B11. For example, the multiplexing circuit may be adjacent to the bend area B12. The multiplexing circuit may be electrically connected to the multiple data lines in the display area AA via multiple data lead lines to be configured to transmit data signals to the multiple data lines. The multiplexing circuit may also be electrically connected to the multiple multiplexed data lines to be configured to receive data signals transmitted by a driver chip provided in the first signal access area B14. The multiplexed data lines may be electrically connected to the multiple data bend connection lines in the bend area. The second fan-out area may also be provided with multiple multiplexed data lead lines, which are electrically connected to the multiple data bend connection lines. The multiplexed data lead lines may be electrically connected to multiple first contact pads in the first signal access area B14 that transmit data signals. In some examples, the data signals provided by the driver chip may be sequentially transmitted to the data lines in the display area via the multiplexed data lead lines, the data bend connection lines, the multiplexed data lines, the multiplexing circuit, and the data lead lines. The multiplexing circuit can provide data signals transmitted by M multiplexed data lines to N data lines, where M and N are both integers, and M is less than N. The multiplexing circuit can reduce the number of data signal transmission lines, which helps reduce the size of the frame. It can also support situations where the driver chip has fewer data signal lines, allowing the driver chip to support providing data signals to all data lines in the display area.

[0119] FIG4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG4 , the multiplexing circuit 30 may include multiple multiplexing units. A multiplexing unit may be configured to provide a data signal provided by a multiplexed data line to multiple data lines (e.g., two data lines).

[0120] In some examples, as shown in FIG4 , a multiplexing unit can be electrically connected to two multiplexing control lines (e.g., a first multiplexing control line 51 and a second multiplexing control line 52), a multiplexing data line, and multiple data lines (e.g., two data lines). Each multiplexing unit can include two multiplexing transistors. The two data lines connected to a multiplexing unit can be electrically connected to sub-pixels that emit light of the same color. The connection method of the multiplexing unit in this example can effectively reduce the load of the data signal.

[0121] FIG4 illustrates six multiplexing units of multiplexing circuit 30 as an example. Three multiplexing units may form a group. Each group of multiplexing units is connected in a similar manner, and the following description uses a group of multiplexing units as an example. In some examples, as shown in FIG4 , a group of multiplexing units may include a first multiplexing unit 31, a second multiplexing unit 32, and a third multiplexing unit 33.

[0122] In some examples, as shown in FIG4 , the first multiplexing unit 31 may include a first multiplexing transistor T1 and a second multiplexing transistor T2. The gate of the first multiplexing transistor T1 is electrically connected to the first multiplexing control line 51, the first electrode of the first multiplexing transistor T1 is electrically connected to the first multiplexing data line 41, and the second electrode of the first multiplexing transistor T1 is electrically connected to the first data line 61. The first data line 61 may be electrically connected to a column of first sub-pixels R1. The gate of the second multiplexing transistor T2 is electrically connected to the second multiplexing control line 52, the first electrode of the second multiplexing transistor T2 is electrically connected to the first multiplexing data line 41, and the second electrode of the second multiplexing transistor T2 is electrically connected to the fourth data line 64. The fourth data line 64 may be electrically connected to a column of first sub-pixels R2. The column of first sub-pixels R1 and the column of first sub-pixels R2 may emit the same color light, for example, both emit red light.

[0123] In some examples, as shown in FIG4 , the second multiplexing unit 32 may include a third multiplexing transistor T3 and a fourth multiplexing transistor T4. The gate of the third multiplexing transistor T3 is electrically connected to the first multiplexing control line 51, the first electrode of the third multiplexing transistor T3 is electrically connected to the second multiplexing data line 42, and the second electrode of the third multiplexing transistor T3 is electrically connected to the second data line 62. The second data line 62 may be electrically connected to a column of second sub-pixels G1. The gate of the fourth multiplexing transistor T4 is electrically connected to the second multiplexing control line 52, the first electrode of the fourth multiplexing transistor T4 is electrically connected to the second multiplexing data line 42, and the second electrode of the fourth multiplexing transistor T4 is electrically connected to the fifth data line 65. The fifth data line 65 may be electrically connected to a column of second sub-pixels G2. The column of second sub-pixels G1 and the column of second sub-pixels G2 may emit light of the same color, for example, both emit green light.

[0124] In some examples, as shown in FIG4 , the third multiplexing unit 33 may include a fifth multiplexing transistor T5 and a sixth multiplexing transistor T6. The gate of the fifth multiplexing transistor T5 is electrically connected to the first multiplexing control line 51, the first electrode of the fifth multiplexing transistor T5 is electrically connected to the third multiplexing data line 43, and the second electrode of the fifth multiplexing transistor T5 is electrically connected to the third data line 63. The third data line 63 may be electrically connected to a column of third sub-pixels B1. The gate of the sixth multiplexing transistor T6 is electrically connected to the second multiplexing control line 52, the first electrode of the sixth multiplexing transistor T6 is electrically connected to the third multiplexing data line 43, and the second electrode of the sixth multiplexing transistor T6 is electrically connected to the sixth data line 66. The sixth data line 66 may be electrically connected to a column of third sub-pixels B2. The column of third sub-pixels B1 and the column of third sub-pixels B2 may emit the same color light, for example, both emit blue light.

[0125] In some examples, a column of first subpixels R1, a column of second subpixels G1, a column of third subpixels B1, a column of first subpixels R2, a column of second subpixels G2, and a column of third subpixels B2 may be sequentially arranged along the first direction.

[0126] In this example, the data signals received by adjacent monochrome sub-pixels are controlled by the same multiplexing unit, which can effectively reduce the load of the data signal and make the data voltage difference corresponding to the same color sub-pixels in the same row of sub-pixels smaller, thereby reducing power consumption; moreover, the multiplexing circuit adopts a 1:2 design (that is, a design in which one multiplexed data line provides data signals to two data lines), which can not only effectively reduce the load of the data signal, but also is conducive to achieving high refresh rate requirements.

[0127] Figure 5 is a partial plan view schematic diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 5 illustrates the partial plan view structure of a set of multiplexing units. In this example, the first connection end of the trace is the one close to the display area, and the second connection end is the one far from the display area.

[0128] In some examples, as shown in FIG5 , the first multiplexing unit 31 (including the first multiplexing transistor T1 and the second multiplexing transistor T2 ), the second multiplexing unit 32 (including the third multiplexing transistor T3 and the fourth multiplexing transistor T4 ), and the third multiplexing unit 33 (including the fifth multiplexing transistor T5 and the sixth multiplexing transistor T6 ) can be arranged sequentially along the second direction Y. For example, the third multiplexing unit 33 can be located on a side of the second multiplexing unit 32 away from the display area, and the second multiplexing unit 32 can be located on a side of the first multiplexing unit 31 away from the display area. The arrangement of the multiplexing circuits in this example can save space along the first direction X.

[0129] In some examples, as shown in FIG5 , multiple multiplexing units include multiple multiplexing transistors, and the multiple multiplexing transistors can be arranged in an array along a first direction X and a second direction Y. For example, the multiplexing transistors can be arranged in three rows. A row of multiplexing transistors can include multiple multiplexing transistors arranged in sequence along the first direction X, and a column of multiplexing transistors can include multiple multiplexing transistors arranged in sequence along the second direction Y. The first multiplexing transistor T1 and the second multiplexing transistor T2 of the first multiplexing unit 31 can be arranged in sequence along the first direction X. The first multiplexing transistor T1 and the second multiplexing transistor T2 can be arranged alternately in a row along the first direction X. The third multiplexing transistor T3 and the fourth multiplexing transistor T4 of the second multiplexing unit 32 can be arranged in sequence along the first direction X. The third multiplexing transistor T3 and the fourth multiplexing transistor T4 can be arranged alternately in a row along the first direction X. The fifth multiplexing transistor T5 and the sixth multiplexing transistor T6 of the third multiplexing unit 33 can be arranged in sequence along the first direction X. The fifth multiplexing transistors T5 and the sixth multiplexing transistors T6 may be alternately arranged in a row along the first direction X. In this example, a plurality of first multiplexing units 31 may be arranged in a row, a plurality of second multiplexing units 32 may be arranged in a row, and a plurality of third multiplexing units 33 may be arranged in a row; one first multiplexing unit 31, one second multiplexing unit 32, and one third multiplexing unit 33 may be arranged in a column.

[0130] In some examples, as shown in Figure 5, the first multiplexing transistor T1 of the first multiplexing unit 31, the third multiplexing transistor T3 of the second multiplexing unit 32, and the fifth multiplexing transistor T5 of the third multiplexing unit 33 can be arranged in a column along the second direction Y, and the second multiplexing transistor T2 of the first multiplexing unit 31, the fourth multiplexing transistor T4 of the second multiplexing unit 32, and the sixth multiplexing transistor T6 of the third multiplexing unit 33 can be arranged in a column along the second direction Y.

[0131] In some examples, as shown in FIG5 , in a direction perpendicular to the display panel, the first border region may include at least: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer disposed on the substrate. A first insulating layer may be disposed between the semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, and a third insulating layer may be disposed between the second conductive layer and the third conductive layer.

[0132] FIG6 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG5 . In some examples, as shown in FIG5 and FIG6A , the semiconductor layer in the first frame region may include at least active layers of multiplexing transistors of multiple multiplexing units of the multiplexing circuit, such as active layers T10 and T20 of the first multiplexing transistor T1 and the second multiplexing transistor T2 of the first multiplexing unit 31, active layers T30 and T40 of the third multiplexing transistor T3 and the fourth multiplexing transistor T4 of the second multiplexing unit 32, and active layers T50 and T60 of the fifth multiplexing transistor T5 and the sixth multiplexing transistor T6 of the third multiplexing unit 33.

[0133] In some examples, as shown in FIG6 , the active layer T10 of the first multiplexing transistor and the active layer T20 of the second multiplexing transistor of the first multiplexing unit, the active layer T30 of the third multiplexing transistor and the active layer T40 of the fourth multiplexing transistor of the second multiplexing unit, and the active layer T50 of the fifth multiplexing transistor and the active layer T60 of the sixth multiplexing transistor of the third multiplexing unit may have substantially the same shape and size of their orthographic projections on the substrate, for example, they may be substantially rectangles of the same size. However, this embodiment is not limited thereto.

[0134] In some examples, as shown in Figure 6, the active layer T10 of the first multiplexing transistor and the active layer T20 of the second multiplexing transistor can be aligned along the first direction X, the active layer T30 of the third multiplexing transistor and the active layer T40 of the fourth multiplexing transistor can be aligned along the first direction X, and the active layer T50 of the fifth multiplexing transistor and the active layer T60 of the sixth multiplexing transistor can be aligned along the first direction X.

[0135] In some examples, as shown in FIG6 , the active layer T10 of the first multiplexing transistor, the active layer T30 of the third multiplexing transistor, and the active layer T50 of the fifth multiplexing transistor may be arranged sequentially along the second direction Y. The active layer T10 of the first multiplexing transistor has a first center line O1, the active layer T30 of the third multiplexing transistor has a third center line O3, and the active layer T50 of the fifth multiplexing transistor has a fifth center line O5; the first center line O1, the third center line O3, and the fifth center line O5 may all be parallel to the second direction Y. The third center line O3 of the active layer T30 of the third multiplexing transistor may be located on one side of the first center line O1 of the active layer T10 of the first multiplexing transistor in the first direction X, and the fifth center line O5 of the active layer T50 of the fifth multiplexing transistor may be located on one side of the third center line O3 of the active layer T30 of the third multiplexing transistor in the first direction X. In the first direction X, the distance between the third center line O3 and the first center line O1 can be substantially the same as the distance between the third center line O3 and the fifth center line O5. However, this embodiment is not limited to this. For example, in the first direction X, the distance between the third center line O3 and the first center line O1 can be smaller than or larger than the distance between the third center line O3 and the fifth center line O5.

[0136] In some examples, as shown in FIG6 , the active layer T20 of the second multiplexing transistor, the active layer T40 of the fourth multiplexing transistor, and the active layer T60 of the sixth multiplexing transistor can be arranged sequentially along the second direction Y. The active layer T20 of the second multiplexing transistor can have a second centerline O2, the active layer T40 of the fourth multiplexing transistor can have a fourth centerline O4, and the active layer T60 of the sixth multiplexing transistor can have a sixth centerline O6. The second centerline O2, the fourth centerline O4, and the sixth centerline O6 can all be parallel to the second direction Y. The fourth centerline O4 can be located on one side of the second centerline O2 in the first direction X, and the sixth centerline O6 can be located on one side of the fourth centerline O4 in the first direction X. In the first direction X, the distance between the fourth centerline O4 and the second centerline O2 can be substantially the same as the distance between the fourth centerline O4 and the sixth centerline O6. The distance between the fourth centerline O4 and the second centerline O2 can be substantially the same as the distance between the third centerline O3 and the first centerline O1. However, this embodiment is not limited to this.

[0137] In some examples, as shown in FIG6 , in the first direction X, the distance between the fifth centerline O5 and the sixth centerline O6 can be smaller than the distance between the third centerline O3 and the fourth centerline O4, and the distance between the third centerline O3 and the fourth centerline O4 can be smaller than the distance between the first centerline O1 and the second centerline O2. However, this embodiment is not limited to this. For example, the distances between two adjacent centerlines along the first direction X can be substantially the same.

[0138] In some examples, the active layer of each multiplexing transistor may include a first region, a second region, and a channel region between the first region and the second region. The orthographic projection of the channel region of the active layer of the multiplexing transistor on the substrate may be covered by the orthographic projection of the corresponding gate on the substrate.

[0139] FIG7A is a schematic diagram of the display panel after the first conductive layer is formed in FIG5 . FIG7B is a planar schematic diagram of the first conductive layer in FIG7A . In some examples, as shown in FIG7A and FIG7B , the first conductive layer in the first border area may include at least: gates of multiple multiplexing transistors of multiple multiplexing units of the multiplexing circuit (for example, including the gate T13 of the first multiplexing transistor T1, the gate T23 of the second multiplexing transistor T2, the gate T33 of the third multiplexing transistor T3, the gate T43 of the fourth multiplexing transistor T4, the gate T53 of the fifth multiplexing transistor T5, and the gate T63 of the sixth multiplexing transistor T6), multiple data lead lines (for example, including the first data lead line 251, the third data lead line 253, and the fifth data lead line 255), the first multiplexing data line 41, the third multiplexing data line 43, the second multiplexing connection line 262, and the third multiplexing connection line 263.

[0140] In some examples, as shown in Figures 7A and 7B, the gate T13 of the first multiplexing transistor T1, the gate T33 of the third multiplexing transistor T3, and the gate T53 of the fifth multiplexing transistor T5 can all be substantially strip-shaped structures extending along the second direction Y. The gate T13 of the first multiplexing transistor T1, the gate T33 of the third multiplexing transistor T3, and the gate T53 of the fifth multiplexing transistor T5 can be interconnected integral structures. The gate T23 of the second multiplexing transistor T2, the gate T43 of the fourth multiplexing transistor T4, and the gate T63 of the sixth multiplexing transistor T6 can all be substantially strip-shaped structures extending along the second direction Y. The gate T23 of the second multiplexing transistor T2, the gate T43 of the fourth multiplexing transistor T4, and the gate T63 of the sixth multiplexing transistor T6 can be interconnected integral structures.

[0141] In some examples, the plurality of data lead lines may extend toward one side of the display area so as to be electrically connected to the plurality of data lines in the display area. As shown in FIG7B , the first data lead line 251 , the third data lead line 253 , and the fifth data lead line 255 may be arranged along the first direction X.

[0142] In some examples, as shown in Figures 7A and 7B, the first data lead line 251 can be located on a side of the active layer T10 of the first multiplexing transistor T1 away from the active layer T30 of the third multiplexing transistor T3 in the second direction Y. The third data lead line 253 can be located at least between the active layer T10 of the first multiplexing transistor T1 and the active layer T20 of the second multiplexing transistor T2, and between the active layer T30 of the third multiplexing transistor T3 and the active layer T40 of the fourth multiplexing transistor T4. One connection end of the third data lead line 253 can extend between the active layer T30 of the third multiplexing transistor T3 and the active layer T50 of the fifth multiplexing transistor T5, and close to the integrated structure of the gate T33 of the third multiplexing transistor T3 and the gate T53 of the fifth multiplexing transistor T5. The fifth data lead line 255 can be located on a side of the active layer T20 of the second multiplexing transistor T2 away from the third data lead line 253. One connection end of the fifth data lead line 255 may be located between the active layer T20 of the second multiplexing transistor T2 and the active layer T40 of the fourth multiplexing transistor T4 and close to the integrated structure of the gate T23 of the second multiplexing transistor T2 and the gate T43 of the fourth multiplexing transistor T4.

[0143] In some examples, as shown in Figures 7A and 7B, the first multiplexing data line 41 can be substantially in the shape of a zigzag line extending along the second direction Y. The first multiplexing data line 41 can be located on a side of the active layer T30 of the third multiplexing transistor T3 and the active layer T50 of the fifth multiplexing transistor T5 that is away from the third data lead-out line 253. The first connection end of the first multiplexing data line 41 can be located between the active layer T10 of the first multiplexing transistor T1 and the active layer T30 of the third multiplexing transistor T3, and close to the integrated structure of the gate T13 of the first multiplexing transistor T1 and the gate T33 of the third multiplexing transistor T3.

[0144] In some examples, the third multiplexing data line 43 may extend substantially along the second direction Y, and the first connection end of the third multiplexing data line 43 may be located on one side of the active layer T60 of the sixth multiplexing transistor T6 in the second direction Y.

[0145] In some examples, the third multiplexing connection line 263 may extend substantially along the second direction Y. A first connection end of the third multiplexing connection line 263 may be located on one side of the active layer T50 of the fifth multiplexing transistor T5 in the second direction Y.

[0146] In some examples, the second multiplexing connection line 262 can extend substantially along the second direction Y. The second multiplexing connection line 262 can be located between the active layer T50 of the fifth multiplexing transistor T5 and the active layer T60 of the sixth multiplexing transistor T6. The first connection end of the second multiplexing connection line 262 can be located between the active layer T40 of the fourth multiplexing transistor T4 and the active layer T60 of the sixth multiplexing transistor T6, and close to the integrated structure of the gate T43 of the fourth multiplexing transistor T4 and the gate T63 of the sixth multiplexing transistor T6. The second multiplexing connection line 262 can be adjacent to the third multiplexing data line 43.

[0147] FIG8A is a schematic diagram of the display panel after the second conductive layer is formed in FIG5 . FIG8B is a plan view schematic diagram of the second conductive layer in FIG8A . In some examples, as shown in FIG8A and FIG8B , the second conductive layer in the first border region may include at least: a plurality of data lead lines (e.g., including a second data lead line 252 , a fourth data lead line 254 , and a sixth data lead line 256 ), a second multiplexed data line 42 , and a first multiplexed connection line 261 .

[0148] In some examples, the first data lead line 251, the second data lead line 252, the third data lead line 253, the fourth data lead line 254, the fifth data lead line 255, and the sixth data lead line 256 can be arranged sequentially along the first direction X. The orthographic projections of the first data lead line 251, the second data lead line 252, the third data lead line 253, the fourth data lead line 254, the fifth data lead line 255, and the sixth data lead line 256 on the substrate may not overlap. In this example, the multiple data lead lines can be alternately arranged on the first conductive layer and the second conductive layer, which can reduce the spacing between adjacent data lead lines, thereby reducing the space occupied by the wiring and facilitating a narrower frame.

[0149] In some examples, the second data lead line 252 can be substantially in the shape of a zigzag line extending along the second direction Y. The second data lead line 252 can be located at least between the active layer T10 of the first multiplexing transistor T1 and the active layer T20 of the second multiplexing transistor T2. One connection end of the second data lead line 252 can be located between the active layer T10 of the first multiplexing transistor T1 and the active layer T30 of the third multiplexing transistor T3, and close to the integrated structure of the gate T13 of the first multiplexing transistor T1 and the gate T33 of the third multiplexing transistor T3. The fourth data lead line 254 can be located on a side of the active layer T20 of the second multiplexing transistor T2 that is opposite to the second direction Y. The sixth data lead line 256 can be substantially in the shape of a zigzag line extending along the second direction Y. The sixth data lead line 256 may be located at least on a side of the fifth data lead line 255 away from the active layer T20 of the second transistor T2, and on a side of the active layer T40 of the fourth multiplexing transistor T4 along the first direction X. One connection end of the sixth data lead line 256 may be located between the active layer T40 of the fourth multiplexing transistor T4 and the active layer T60 of the sixth multiplexing transistor T6, and close to the integrated structure of the gate T43 of the fourth multiplexing transistor T4 and the gate T63 of the sixth multiplexing transistor T6.

[0150] In some examples, the second multiplexing data line 42 may be substantially in the shape of a zigzag line extending along the second direction Y. The second multiplexing data line 42 may be located on a side of the first multiplexing data line 41 close to the active layer T50 of the fifth multiplexing transistor T5, and the second multiplexing data line 42 may be located between the first multiplexing data line 41 and the third multiplexing connection line 263. The first connection end of the second multiplexing data line 42 may be located between the active layer T30 of the third multiplexing transistor T3 and the active layer T50 of the fifth multiplexing transistor T5, and close to the integrated structure of the gate T33 of the third multiplexing transistor T3 and the gate T53 of the fifth multiplexing transistor T5.

[0151] In some examples, the first multiplexing connection line 261 can be roughly in the shape of a broken line extending along the second direction Y. The first multiplexing connection line 262 can be located at least between the active layer T50 of the fifth multiplexing transistor T5 and the active layer T60 of the sixth multiplexing transistor T6, and between the active layer T30 of the third multiplexing transistor T3 and the active layer T40 of the fourth multiplexing transistor T4. The first multiplexing connection line 261 can be located on a side of the third data lead-out line 253 close to the active layer T40 of the fourth multiplexing transistor T4, and the second multiplexing connection line 262 can be located on a side of the active layer T50 of the fifth multiplexing transistor T5. The first connection end of the first multiplexing connection line 261 can be located between the active layer T20 of the second multiplexing transistor T2 and the active layer T40 of the fourth multiplexing transistor T4, and close to the integrated structure of the gate T23 of the second multiplexing transistor T2 and the gate T43 of the fourth multiplexing transistor T4.

[0152] In some examples, the first multiplexed data line 41 can be connected to the first multiplexed connection line 261 and transmit a first data signal; the second multiplexed data line 42 can be connected to the second multiplexed connection line 262 and transmit a second data signal; and the third multiplexed data line 43 can be connected to the third multiplexed connection line 263 and transmit a third data signal. The first multiplexed data line 41 and the first multiplexed connection line 261 extend in substantially the same direction and are located in different film layers, which can save space. The second multiplexed data line 42 and the second multiplexed connection line 262 also extend in substantially the same direction and are located in different film layers, which helps save space.

[0153] FIG9 is a schematic diagram of the display panel after the third insulating layer is formed in FIG5 . In some examples, as shown in FIG9 , the third insulating layer in the first frame area may be provided with a plurality of vias, such as: the first via V1 to the twelfth via V12, the thirteenth via V13 to the twenty-first via V21, and the thirty-third via V33 to the thirty-ninth via V39. In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 to the twelfth via V12 may be removed to expose a portion of the surface of the semiconductor layer. The third insulating layer and the second insulating layer within the thirteenth via V13 to the twenty-first via V21 may be removed to expose a portion of the surface of the first conductive layer. The third insulating layer within the thirty-third via V33 to the thirty-ninth via V39 may be removed to expose a portion of the surface of the second conductive layer.

[0154] Figure 10 is a schematic plan view of the third conductive layer in Figure 5. In some examples, as shown in Figures 5 and 10, the third conductive layer in the first frame region may include at least: a plurality of connecting electrodes (eg, including the first connecting electrode 301 to the sixteenth connecting electrode 316).

[0155] In some examples, the first connection electrode 301 may be a substantially strip-shaped structure extending along the second direction Y. The first connection electrode 301 may be electrically connected to the first region of the active layer T10 of the first multiplexing transistor T1 through a plurality (e.g., four) vertically arranged first vias V1, and may also be electrically connected to the first multiplexing data line 41 through two vertically arranged sixteenth vias V16. In this example, vertical arrangement refers to arrangement along the second direction, and horizontal arrangement refers to arrangement along the first direction.

[0156] In some examples, the second connection electrode 302 may be substantially in the shape of a zigzag line extending along the second direction Y. The second connection electrode 302 may be connected to the second region of the active layer T10 of the first multiplexing transistor T1 through a plurality (e.g., four) vertically arranged second via holes V2, and may also be electrically connected to the first data lead line 251 through two vertically arranged thirteenth via holes V13.

[0157] In some examples, the third connection electrode 303 may be a substantially strip-shaped structure extending along the second direction Y. The third connection electrode 303 may be electrically connected to the first region of the active layer T20 of the second multiplexing transistor T2 through a plurality (e.g., four) vertically arranged third via holes V3, and may also be electrically connected to the first multiplexing connection line 261 through two vertically arranged thirty-seventh via holes V37. The first multiplexing connection line 261 may be electrically connected to the first multiplexing data line 41.

[0158] In some examples, the fourth connection electrode 304 may be substantially in the shape of a zigzag line extending along the second direction Y. The fourth connection electrode 304 may be electrically connected to the second region of the active layer T20 of the second multiplexing transistor T2 through a plurality (e.g., four) vertically arranged fourth via holes V4, and may also be electrically connected to the fourth data lead line 254 through two vertically arranged thirty-fourth via holes V34.

[0159] In some examples, the fifth connection electrode 305 may be a substantially strip-shaped structure extending along the second direction Y. The fifth connection electrode 305 may be electrically connected to the first region of the active layer T30 of the third multiplexing transistor T3 through a plurality (e.g., four) vertically arranged fifth via holes V5, and may also be electrically connected to the second multiplexing data line 42 through two vertically arranged thirty-eighth via holes V38.

[0160] In some examples, the sixth connection electrode 306 may be a substantially strip-shaped structure extending along the second direction Y. The sixth connection electrode 306 may be electrically connected to the second region of the active layer T30 of the third multiplexing transistor T3 through a plurality (e.g., four) vertically arranged sixth via holes V6, and may also be electrically connected to the second data lead line 252 through two vertically arranged thirty-sixth via holes V36.

[0161] In some examples, the seventh connection electrode 307 can be substantially a strip-shaped structure extending along the second direction Y. The seventh connection electrode 307 can be electrically connected to the first region of the active layer T40 of the fourth multiplexing transistor T4 through a plurality (e.g., four) of vertically arranged seventh via holes V7, and can also be electrically connected to the second multiplexing connection line 262 through two vertically arranged nineteenth via holes V19. The second multiplexing connection line 262 can be electrically connected to the second multiplexing data line 42.

[0162] In some examples, the eighth connection electrode 308 may be a substantially strip-shaped structure extending along the second direction Y. The eighth connection electrode 308 may be electrically connected to the second region of the active layer T40 of the fourth multiplexing transistor T4 through a plurality (e.g., four) of vertically arranged eighth via holes V8, and may also be electrically connected to the fifth data lead line 255 through two vertically arranged seventeenth via holes V17.

[0163] In some examples, the ninth connection electrode 309 may be a substantially strip-shaped structure extending along the second direction Y. The ninth connection electrode 309 may be electrically connected to the first region of the active layer T50 of the fifth multiplexing transistor T5 through a plurality (e.g., four) vertically arranged ninth via holes V9, and may also be electrically connected to the third multiplexing connection line 263 through two vertically arranged twentieth via holes V20. The third multiplexing connection line 263 may be electrically connected to the third multiplexing data line 43.

[0164] In some examples, the tenth connection electrode 310 may be a substantially strip-shaped structure extending along the second direction Y. The tenth connection electrode 310 may be electrically connected to the second region of the active layer T50 of the fifth multiplexing transistor T5 through a plurality (e.g., four) of vertically arranged tenth via holes V10, and may also be electrically connected to the third data lead line 253 through two vertically arranged eighteenth via holes V18.

[0165] In some examples, the eleventh connection electrode 311 may be substantially a strip-shaped structure extending along the second direction Y. The eleventh connection electrode 311 may be electrically connected to the first region of the active layer T60 of the sixth multiplexing transistor T6 through a plurality (e.g., four) vertically arranged eleventh via holes V11, and may also be electrically connected to the third multiplexing data line 43 through two vertically arranged twenty-first via holes V21.

[0166] In some examples, the twelfth connection electrode 312 may be a substantially strip-shaped structure extending along the second direction Y. The twelfth connection electrode 312 may be electrically connected to the second region of the active layer T60 of the sixth multiplexing transistor T6 through a plurality (e.g., four) of vertically arranged twelfth via holes V12, and may also be electrically connected to the sixth data lead line 256 through two vertically arranged thirty-ninth via holes V39.

[0167] In some examples, the thirteenth connection electrode 313 may be substantially rectangular. The thirteenth connection electrode 313 may be electrically connected to the second data lead line 252 via two vertically arranged thirty-third via holes V33. The fourteenth connection electrode 314 may be substantially rectangular. The fourteenth connection electrode 314 may be electrically connected to the third data lead line 253 via two vertically arranged fourteenth via holes V14. The fifteenth connection electrode 315 may be substantially rectangular. The fifteenth connection electrode 315 may be electrically connected to the fifth data lead line 255 via two vertically arranged fifteenth via holes V15. The sixteenth connection electrode 316 may be substantially rectangular. The sixteenth connection electrode 316 may be electrically connected to the sixth data lead line 256 via two vertically arranged thirty-fifth via holes V35.

[0168] In some examples, the first data lead line 251 is electrically connected to the multiplexing circuit through the second connecting electrode 302, and the fourth data lead line 254 is electrically connected to the multiplexing circuit through the fourth connecting electrode 304. By setting the thirteenth connecting electrode 313 to be electrically connected to the second data lead line 252, the fourteenth connecting electrode 314 to be electrically connected to the third data lead line 253, the fifteenth connecting electrode 315 to be electrically connected to the fifth data lead line 255, and the sixteenth connecting electrode 316 to be electrically connected to the sixth data lead line 256, the consistency of the film pattern of the third conductive layer can be ensured, and the uniformity of the via holes in the third insulating layer can be ensured, which is beneficial to the resistance uniformity of multiple data lead lines and ensures the uniformity of signal transmission.

[0169] Figure 11 is a partial schematic plan view of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 11 illustrates the planar structure of two sets of multiplexing units and their connection to the data zigzag connection lines in the zigzag region. The following description uses the structure of one set of multiplexing units and the data zigzag connection lines in Figure 11 as an example, in conjunction with Figures 5 to 10.

[0170] In some examples, as shown in FIG11 , a plurality of first multiplexing units 31 may be arranged in a row along a first direction X, a plurality of second multiplexing units 32 may be arranged in a row along the first direction X, and a plurality of third multiplexing units 33 may be arranged in a row along the first direction X. A column of multiplexing units may include the first multiplexing units 31, the second multiplexing units 32, and the third multiplexing units 33 arranged along a second direction Y.

[0171] In some examples, as shown in FIG11 , in a direction perpendicular to the display panel, the first border region may include at least: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate. A fourth insulating layer and a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer.

[0172] FIG12 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG11 . In some examples, as shown in FIG11 and FIG12 , the active layer T10 of the first multiplexing transistor T1 and the active layer T20 of the second multiplexing transistor T2 of the first multiplexing unit 31 can be arranged in a row with intervals along the first direction X. The active layer T30 of the third multiplexing transistor T3 and the active layer T40 of the fourth multiplexing transistor T4 of the second multiplexing unit 32 can be arranged in a row with intervals along the first direction X. The active layer T50 of the fifth multiplexing transistor T5 and the active layer T60 of the sixth multiplexing transistor T6 of the third multiplexing unit 33 can be arranged in a row with intervals along the first direction X.

[0173] FIG13 is a schematic diagram of the display panel after the first conductive layer is formed in FIG11 . In some examples, as shown in FIG13 , the second connection end of the first multiplexing data line 41 and the second connection end of the third multiplexing data line 43 can be aligned in the first direction X. The second connection end of the third multiplexing connection line 263 can be located on a side opposite to the second connection end of the third multiplexing data line 43 along the second direction Y. The second connection end of the second multiplexing connection line 262 can be located on a side opposite to the third multiplexing connection line 263 along the second direction Y.

[0174] FIG14 is a schematic diagram of the display panel after the second conductive layer is formed in FIG11 . In some examples, as shown in FIG14 , the second connection end of the second multiplexing data line 42 can be aligned with the second connection end of the first multiplexing data line 41 in the first direction X. The second connection end of the second multiplexing data line 42 can be located between the second connection end of the first multiplexing data line 41 and the second connection end of the third multiplexing data line 43 in the first direction X. The second connection end of the first multiplexing connection line 261 can be located on a side opposite to the second connection end of the second multiplexing connection line 262 in the second direction Y.

[0175] FIG15 is a schematic diagram of the display panel after the third insulating layer is formed in FIG11. In some examples, as shown in FIG15, the third insulating layer in the first border region may include, for example, first to twelfth via holes V1 to V12, thirteenth to twenty-ninth via holes V13 to V29, and thirtieth to thirty-ninth via holes V30 to V39.

[0176] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the first through twelfth vias V1 to V12 can be removed to expose a portion of the surface of the semiconductor layer. The third insulating layer and the second insulating layer within the thirteenth through twenty-ninth vias V13 to V29 can be removed to expose a portion of the surface of the first conductive layer. The third insulating layer within the thirtieth through thirty-ninth vias V30 to V39 can be removed to expose a portion of the surface of the second conductive layer.

[0177] FIG16A is a schematic diagram of the display panel after the third conductive layer is formed in FIG11. FIG16B is a planar schematic diagram of the third conductive layer in FIG16A. In some examples, as shown in FIG16A and FIG16B, the third conductive layer in the first frame area may include at least: a plurality of connection electrodes (for example, including the first connection electrode 301 to the sixteenth connection electrode 316), a first multiplexing control line 51, a second multiplexing control line 52, a plurality of transfer lines (for example, a first transfer line 361, a second transfer line 362, and a third transfer line 363), and a plurality of multiplexing connection electrodes (for example, including the first multiplexing connection electrode 351, the second multiplexing connection electrode 352, and the third multiplexing connection electrode 353).

[0178] In some examples, the first multiplexing control line 51 and the second multiplexing control line 52 may be at least linearly shaped and extend along the first direction X. The second multiplexing control line 52 may be located on one side of the first multiplexing control line 51 in the second direction Y. The first multiplexing control line 51 may be located on the same side of the ninth connection electrode 309, the tenth connection electrode 310, the eleventh connection electrode 311, and the twelfth connection electrode 312 in the second direction Y.

[0179] In some examples, the first multiplexing connection electrode 351, the second multiplexing connection electrode 352, and the third multiplexing connection electrode 353 may be located on one side of the second multiplexing control line 52 in the second direction Y. The first multiplexing connection electrode 351, the second multiplexing connection electrode 352, and the third multiplexing connection electrode 353 may be substantially strip-shaped structures extending along the first direction X. The second multiplexing connection electrode 352 may be located on one side of the first multiplexing connection electrode 351 in the second direction Y, and the third multiplexing connection electrode 353 may be located on one side of the second multiplexing connection electrode 352 in the second direction Y.

[0180] In some examples, the first patch line 361, the second patch line 362, and the third patch line 363 may be a bar-shaped structure extending along the second direction Y. The first patch line 361, the second patch line 362, and the third patch line 363 may be arranged sequentially along the first direction X. The first patch line 361, the second patch line 362, and the third patch line 363 may be located on one side of the third multiplexing connection electrode 353 in the second direction Y.

[0181] In some examples, the first multiplexing control line 51 can be electrically connected to the integrated structure of the gate T53 of the fifth multiplexing transistor, the gate T33 of the third multiplexing transistor, and the gate T13 of the first multiplexing transistor through two vertically arranged twenty-second vias V22. The second multiplexing control line 52 can be electrically connected to the integrated structure of the gate T63 of the sixth multiplexing transistor, the gate T43 of the fourth multiplexing transistor, and the gate T23 of the second multiplexing transistor through two vertically arranged twenty-third vias V23.

[0182] In some examples, the first multiplexing connection electrode 351 can be electrically connected to the first multiplexing data line 41 through the twenty-fourth via hole V24, and can also be electrically connected to the first multiplexing connection line 261 through two horizontally arranged thirty-first via holes V31. The second multiplexing connection electrode 352 can be electrically connected to the second multiplexing data line 42 through two vertically arranged thirty-second via holes V32, and can also be electrically connected to the second multiplexing connection line 262 through two horizontally arranged twenty-fifth via holes V25. The third multiplexing connection electrode 353 can be electrically connected to the third multiplexing connection line 263 through two horizontally arranged twenty-sixth via holes V26, and can also be electrically connected to the third multiplexing data line 43 through two horizontally arranged twenty-seventh via holes V27.

[0183] In some examples, the first patch line 361 can be electrically connected to the first multiplexed data line 41 through a plurality of 28th vias V28 arranged in an array. The second patch line 362 can be electrically connected to the second multiplexed data line 42 through a plurality of 30th vias V30 arranged in an array. The third patch line 363 can be electrically connected to the third multiplexed data line 43 through a plurality of 29th vias V29 arranged in an array.

[0184] Figure 17 is a schematic diagram of the display panel after the fifth insulating layer is formed in Figure 11. In some examples, as shown in Figure 17, the fourth insulating layer and the fifth insulating layer in the first border region may have multiple vias, such as vias 41 to 43. The fifth insulating layer and the fourth insulating layer within vias 41 to 43 may be removed to expose a portion of the surface of the third conductive layer.

[0185] In some examples, as shown in FIG11 , the fourth conductive layer of the first border region may include at least: a plurality of data bend connection lines (for example, a first data bend connection line 401, a second data bend connection line 402, and a third data bend connection line 403). The plurality of data bend connection lines may extend along the second direction Y and be arranged sequentially along the first direction X. The first data bend connection line 401 may be electrically connected to the first adapter line 361 through two vertically arranged forty-first vias V41, the second data bend connection line 402 may be electrically connected to the second adapter line 362 through two vertically arranged forty-second vias V42, and the third data bend connection line 403 may be electrically connected to the third adapter line 363 through two vertically arranged forty-third vias V43.

[0186] The structure and preparation process of the display panel of this example are described below by way of example. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire production process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0187] The phrase "A and B are arranged in the same layer" or "A and B are of the same layer structure" in the present disclosure means that A and B are formed simultaneously by the same patterning process. The phrase "A and B are of different layer structures" means that A and B are formed separately by two patterning processes. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display panel. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0188] In some examples, the preparation process of the display panel of this example may include the following operations.

[0189] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0190] (2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer disposed on the substrate. In some examples, as shown in FIG3 , FIG6 , and FIG12 , the semiconductor layer may include: an active layer of a thin film transistor of a pixel circuit located in a display area, and an active layer of a multiplexing transistor of a multiplexing circuit located in a first frame area.

[0191] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The first conductive film is patterned by a patterning process to form a first insulating layer disposed on the semiconductor layer and a first conductive layer disposed on the first insulating layer, as shown in FIG3 , FIG7A and FIG7B , and FIG13 . In some examples, the first conductive layer may also be referred to as a first gate metal layer. The first insulating layer may also be referred to as a first gate insulating layer.

[0192] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer, as shown in FIG3 , FIG8A and FIG8B , and FIG14 . In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0193] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate having the aforementioned pattern formed thereon, and the third insulating film is patterned by a patterning process to form a third insulating layer, as shown in FIG3 , FIG9 , and FIG15 . In some examples, the third insulating layer may have a plurality of vias. The third insulating layer may also be referred to as an interlayer insulating layer.

[0194] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the third conductive film is patterned by a patterning process to form a third conductive layer, as shown in FIG3 , FIG10 , FIG16A , and FIG16B . In some examples, the third conductive layer may also be referred to as a first source / drain metal layer.

[0195] (7) Forming a fourth insulating layer and a fifth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a fifth insulating film is coated. The fifth insulating film and the fourth insulating film are patterned in sequence using a patterning process to form the fourth insulating layer and the fifth insulating layer, as shown in FIG3 and FIG17. In some examples, the fourth insulating layer may also be referred to as a passivation layer, and the fifth insulating layer may also be referred to as a first planarization layer.

[0196] (8) Forming a fourth conductive layer. On the substrate having the aforementioned pattern, a fourth conductive film is deposited and patterned using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, as shown in FIG3 and FIG11. In some examples, the fourth conductive layer may also be referred to as a second source / drain metal layer.

[0197] Subsequently, a sixth insulating layer can be formed on the side of the fourth conductive layer away from the substrate. At this point, the circuit structure layer of this embodiment is completed on the substrate. In some examples, after the circuit structure layer of the display area is completed, a light-emitting structure layer, an encapsulation structure layer, and a touch structure layer can be sequentially formed on the circuit structure layer. This will not be described in detail here.

[0198] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. For example, the first conductive layer and the second conductive layer can be made of a single layer of molybdenum metal, and the third conductive layer and the fourth conductive layer can be made of a three-layer stacked structure of Ti / Al / Ti. The resistivity of the traces of the third conductive layer and the fourth conductive layer can be less than the resistivity of the traces of the first conductive layer and the second conductive layer.

[0199] In some examples, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103 and the fourth insulating layer 104 can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The fifth insulating layer 105 and the sixth insulating layer 106 can be made of organic materials, such as polyimide, acrylic or polyethylene terephthalate. The semiconductor layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0200] The structure of the display panel and its fabrication process in this embodiment are merely illustrative. In some examples, the corresponding structure can be modified and patterning processes can be added or removed based on actual needs. For example, the display panel can omit the second source / drain metal layer, the anode of the light-emitting element can be directly electrically connected to the drain of the thin-film transistor, and the data fold connection line can be located in the third conductive layer and electrically connected to the multiplexed data line located in the first conductive layer or the second conductive layer.

[0201] The preparation process of this example can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.

[0202] The multiplexing transistors of the multiplexing circuit in this example can be arranged in three rows, which is conducive to compressing the space of the multiplexing circuit along the first direction. Combined with the 1:2 design of the multiplexing circuit, it can meet the high refresh rate requirements of the display panel.

[0203] Figure 18 is another partial plan view of a multiplexing circuit according to at least one embodiment of the present disclosure, wherein Figure 18 takes a partial plan view of a group of multiplexing units as an example.

[0204] In some examples, as shown in FIG18 , the two multiplexing transistors of each multiplexing unit in a group of multiplexing units can be arranged in different rows and different columns. For example, the multiplexing transistors located in the i-th column (including the first multiplexing transistor T1 of the first multiplexing unit and the third multiplexing transistor T3 of the second multiplexing unit) are both electrically connected to the first multiplexing control line, the multiplexing transistors located in the i+1-th column (including the fifth multiplexing transistor T5 of the third multiplexing unit and the second multiplexing transistor T2 of the first multiplexing unit) are electrically connected to different multiplexing control lines, and the multiplexing transistors located in the i+2-th column (including the fourth multiplexing transistor T4 of the second multiplexing unit and the sixth multiplexing transistor T6 of the third multiplexing unit) are both electrically connected to the second multiplexing control line, where i is an integer greater than 0.

[0205] In some examples, as shown in FIG18 , six multiplexing transistors of a set of multiplexing units can be arrayed in two rows and three columns along a first direction X and a second direction Y. The first row of multiplexing transistors can include: a first multiplexing transistor T1 of the first multiplexing unit, a fifth multiplexing transistor T5 of the third multiplexing unit, and a fourth multiplexing transistor T4 of the second multiplexing unit. The first multiplexing transistor T1 of the first multiplexing unit, the fifth multiplexing transistor T5 of the third multiplexing unit, and the fourth multiplexing transistor T4 of the second multiplexing unit can be arranged sequentially along the first direction X. The second row of multiplexing transistors can include: a third multiplexing transistor T3 of the second multiplexing unit, a second multiplexing transistor T2 of the first multiplexing unit, and a sixth multiplexing transistor T6 of the third multiplexing unit. The third multiplexing transistor T3 of the second multiplexing unit, the second multiplexing transistor T2 of the first multiplexing unit, and the sixth multiplexing transistor T6 of the third multiplexing unit can be arranged sequentially along the first direction X. The second row of multiplexing transistors may be located on one side of the first row of multiplexing transistors in the second direction Y. The arrangement of the multiplexing circuit in this example can save installation space along the second direction Y. For example, the arrangement of the multiplexing circuit in this example can be suitable for a display panel with a narrow bottom bezel but a wide lateral area.

[0206] In some examples, as shown in FIG18 , the i-th column multiplexing transistors may include a first multiplexing transistor T1 and a third multiplexing transistor T3; the i+1-th column multiplexing transistors may include a fifth multiplexing transistor T5 and a second multiplexing transistor T2; and the i+2-th column multiplexing transistors may include a fourth multiplexing transistor T4 and a sixth multiplexing transistor T6. The i-th column multiplexing transistors, the i+1-th column multiplexing transistors, and the i+2-th column multiplexing transistors may be arranged sequentially along a first direction X.

[0207] FIG19 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG18. In some examples, as shown in FIG18 and FIG19, the semiconductor layer in the first frame region may include at least active layers of multiplexing transistors of multiple multiplexing units of the multiplexing circuit, for example, active layers T10 of the first multiplexing transistor T1 and T20 of the second multiplexing transistor T2 of the first multiplexing unit, active layers T30 of the third multiplexing transistor T3 and T40 of the fourth multiplexing transistor T4 of the second multiplexing unit, and active layers T50 of the fifth multiplexing transistor T5 and T60 of the sixth multiplexing transistor T6 of the third multiplexing unit.

[0208] In some examples, as shown in Figure 19, the shapes and sizes of the positive projections of the active layer T10 of the first multiplexing transistor and the active layer T20 of the second multiplexing transistor of the first multiplexing unit, the active layer T30 of the third multiplexing transistor and the active layer T40 of the fourth multiplexing transistor of the second multiplexing unit, and the active layer T50 of the fifth multiplexing transistor and the active layer T60 of the sixth multiplexing transistor of the third multiplexing unit on the substrate can be approximately the same, for example, they can be approximately rectangles of the same size.

[0209] In some examples, as shown in FIG19 , the active layer T10 of the first multiplexing transistor, the active layer T50 of the fifth multiplexing transistor, and the active layer T40 of the fourth multiplexing transistor can be aligned along the first direction X. The active layer T30 of the third multiplexing transistor, the active layer T20 of the second multiplexing transistor, and the active layer T60 of the sixth multiplexing transistor can be aligned along the first direction X. The active layer T10 of the first multiplexing transistor and the active layer T30 of the third multiplexing transistor can be arranged in sequence along the second direction Y, and there can be a misalignment between the two in the second direction Y. The active layer T50 of the fifth multiplexing transistor and the active layer T20 of the second multiplexing transistor can be arranged in sequence along the second direction Y, and there can be a misalignment between the two in the second direction Y. The active layer T40 of the fourth multiplexing transistor and the active layer T60 of the sixth multiplexing transistor can be arranged in sequence along the second direction Y, and there can be a misalignment between the two in the second direction Y.

[0210] FIG20A is a schematic diagram of the display panel after the first conductive layer is formed in FIG18 . FIG20B is a planar schematic diagram of the first conductive layer in FIG20A . In some examples, as shown in FIG20A and FIG20B , the first conductive layer in the first border area may include at least: gates of multiple multiplexing transistors of multiple multiplexing units of the multiplexing circuit (for example, including the gate T13 of the first multiplexing transistor T1, the gate T23 of the second multiplexing transistor T2, the gate T33 of the third multiplexing transistor T3, the gate T43 of the fourth multiplexing transistor T4, the gate T53 of the fifth multiplexing transistor T5, and the gate T63 of the sixth multiplexing transistor T6), multiple data lead lines (for example, including the second data lead line 252, the fourth data lead line 254, and the sixth data lead line 256), and the second multiplexed data line 42.

[0211] In some examples, as shown in Figures 20A and 20B, the gate T13 of the first multiplexing transistor T1 and the gate T33 of the third multiplexing transistor T3 can be an integrated structure connected to each other. The integrated structure of the gate T13 of the first multiplexing transistor T1 and the gate T33 of the third multiplexing transistor T3 can be roughly slot-shaped. The gate T43 of the fourth multiplexing transistor T4 and the gate T63 of the sixth multiplexing transistor T6 can be an integrated structure connected to each other. The integrated structure of the gate T43 of the fourth multiplexing transistor T4 and the gate T63 of the sixth multiplexing transistor T6 can be roughly slot-shaped.

[0212] In some examples, the second data lead line 252, the fourth data lead line 254, and the sixth data lead line 256 can be substantially in the shape of a zigzag line extending along the second direction Y. The second data lead line 252 can be located between the active layer T10 of the first multiplexing transistor T1 and the active layer T50 of the fifth multiplexing transistor T5, and one connection end of the second data lead line 252 can be located between the active layer T10 of the first multiplexing transistor and the active layer T30 of the third multiplexing transistor. The fourth data lead line 254 can be located between the active layer T40 of the fourth multiplexing transistor T4 and the active layer T50 of the fifth multiplexing transistor T5, and one connection end of the fourth data lead line 254 can be located between the active layer T40 of the fourth multiplexing transistor T4 and the active layer T50 of the fifth multiplexing transistor T5, and one connection end of the fourth data lead line 254 can be located between the active layer T20 of the fifth multiplexing transistor T5 and the active layer T20 of the second multiplexing transistor T2. The sixth data lead line 256 may be located on a side of the active layer T40 of the fourth multiplexing transistor T4 away from the fourth data lead line 254 , and one connection end of the sixth data lead line 256 may be located between the active layer T40 of the fourth multiplexing transistor T4 and the active layer T60 of the sixth multiplexing transistor T6 .

[0213] In some examples, the second multiplexing data line 42 may be substantially in the shape of a zigzag line extending along the second direction Y. A first connection end of the second multiplexing data line 42 may be located on one side of the active layer T30 of the third multiplexing transistor in the second direction Y, and a second connection end of the second multiplexing data line 42 may extend toward one side of the bending region.

[0214] FIG21A is a schematic diagram of the display panel after the second conductive layer is formed in FIG18 . FIG21B is a planar schematic diagram of the second conductive layer in FIG21A . In some examples, as shown in FIG21A and FIG21B , the second conductive layer in the first border region may include at least: a plurality of data lead lines (e.g., a first data lead line 251 , a third data lead line 253 , and a fifth data lead line 255 ), a first multiplexed data line 41 , a third multiplexed data line 43 , a first multiplexed connection line 261 , a second multiplexed connection line 262 , and a third multiplexed connection line 263 .

[0215] In some examples, as shown in Figures 21A and 21B, the first data lead line 251, the second data lead line 252, the third data lead line 253, the fourth data lead line 254, the fifth data lead line 255, and the sixth data lead line 256 can be arranged sequentially along the first direction X. The orthographic projections of the first data lead line 251, the second data lead line 252, the third data lead line 253, the fourth data lead line 254, the fifth data lead line 255, and the sixth data lead line 256 on the substrate may not overlap. The first data lead line 251, the third data lead line 253, and the fifth data lead line 255 can be located on the side of the first row of multiplexing transistors opposite to the second direction Y. In this example, the multiple data lead lines can be alternately arranged on the first conductive layer and the second conductive layer, which can reduce the spacing between adjacent data lead lines, thereby reducing the space occupied by the wiring and facilitating a narrower frame.

[0216] In some examples, the first multiplexing data line 41 can be substantially in the shape of a zigzag extending along the second direction Y. The first multiplexing data line 41 can be located on a side of the active layer T30 of the third multiplexing transistor T3 away from the third multiplexing connection line 263. The first connection end of the first multiplexing data line 41 can be located on a side of the active layer T10 of the first multiplexing transistor T1 in the second direction Y and adjacent to the gate T13 of the first multiplexing transistor T1. The second connection end of the first multiplexing data line 41 can be aligned with the second connection end of the second multiplexing data line 42 in the first direction X.

[0217] In some examples, the third multiplexing data line 43 may be substantially in the shape of a zigzag line extending along the second direction Y. A first connection end of the third multiplexing data line 43 may be located on one side of the active layer T60 of the sixth multiplexing transistor in the second direction Y and adjacent to the gate T63 of the sixth multiplexing transistor. A second connection end of the third multiplexing data line 43 may be aligned with a second connection end of the first multiplexing data line 41 and a second connection end of the second multiplexing data line 42 in the first direction X.

[0218] In some examples, the first multiplexing connection line 261 may be substantially in the shape of a zigzag line extending along the second direction Y. A first connection end of the first multiplexing connection line 261 may be located on one side of the active layer T20 of the second multiplexing transistor in the second direction Y, and a second connection end of the first multiplexing connection line 261 may be adjacent to the gate T23 of the second multiplexing transistor.

[0219] In some examples, the second multiplexing connection line 262 may be substantially straight and extend along the second direction Y. The second multiplexing connection line 262 may be located between the active layer T20 of the second multiplexing transistor and the gate T43 of the fourth multiplexing transistor. A first connection end of the second multiplexing connection line 262 may be located between the fourth data lead-out line 254 and the gate T43 of the fourth multiplexing transistor, and a second connection end of the second multiplexing connection line 262 may be located on one side of the second connection end of the first multiplexing connection line 261 along the second direction Y.

[0220] In some examples, the third multiplexing connection line 263 may be substantially in the shape of a zigzag line extending along the second direction Y. The third multiplexing connection line 263 may be located between the active layer T30 of the third multiplexing transistor and the gate T53 of the fifth multiplexing transistor. A first connection end of the third multiplexing connection line 263 may be located between the second data lead line 252 and the gate T53 of the fifth multiplexing transistor, and a second connection end of the third multiplexing connection line 263 may be located on one side of the second connection end of the second multiplexing connection line 262 in the second direction Y.

[0221] FIG22 is a schematic diagram of the display panel after the third insulating layer is formed in FIG18. In some examples, as shown in FIG22, the third insulating layer in the first frame region may have a plurality of via holes, such as the fifty-first via hole V51 to the sixty-second via hole V62, the sixty-third via hole V63 to the seventy-fifth via hole V75, and the seventy-sixth via hole V76 to the ninetieth via hole V90.

[0222] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the fifty-first through sixty-second vias V51 to V62 can be removed to expose a portion of the surface of the semiconductor layer. The third insulating layer and the second insulating layer within the sixty-third through seventy-fifth vias V63 to V75 can be removed to expose a portion of the surface of the first conductive layer. The third insulating layer within the seventy-sixth through ninety-second vias V76 to V90 can be removed to expose a portion of the surface of the second conductive layer.

[0223] FIG23A is a schematic diagram of the display panel after the third conductive layer is formed in FIG18 . FIG23B is a planar schematic diagram of the third conductive layer in FIG23A . In some examples, as shown in FIG23A and FIG23B , the third conductive layer in the first border region may include at least: a plurality of connection electrodes (e.g., including the twenty-first connection electrode 321 to the thirty-fifth connection electrode 335 ), a plurality of multiplexed connection electrodes (e.g., including the fourth multiplexed connection electrode 354 , the fifth multiplexed connection electrode 355 , and the sixth multiplexed connection electrode 356 ), and a plurality of transfer lines (e.g., including: a fourth transfer line 364 , a fifth transfer line 365 , and a sixth transfer line 366 ).

[0224] In some examples, the twenty-first connection electrode 321 may be substantially a strip-shaped structure extending along the second direction Y. The twenty-first connection electrode 321 may be electrically connected to the first region of the active layer T10 of the first multiplexing transistor through four fifty-first via holes V51 arranged vertically, and may also be electrically connected to the first multiplexing data line 43 through two eighty-sixth via holes V86 arranged vertically.

[0225] In some examples, the twenty-second connection electrode 322 may be substantially in the shape of a zigzag line extending along the second direction Y. The twenty-second connection electrode 322 may be electrically connected to the second region of the active layer T10 of the first multiplexing transistor through four fifty-second via holes V52 arranged vertically, and may also be electrically connected to the first data lead line 251 through two eighty-third via holes V83 arranged vertically.

[0226] In some examples, the twenty-third connection electrode 323 may be a substantially strip-shaped structure extending along the second direction Y. The twenty-third connection electrode 323 may be electrically connected to the first region of the active layer T50 of the fifth multiplexing transistor through four fifty-third via holes V53 arranged vertically, and may also be electrically connected to the third multiplexing connection line 263 through two eighty-seventh via holes V87 arranged vertically.

[0227] In some examples, the twenty-fourth connection electrode 324 may be substantially in the shape of a zigzag line extending along the second direction Y. The twenty-fourth connection electrode 324 may be electrically connected to the second region of the active layer T50 of the fifth multiplexing transistor through four fifty-fourth via holes V54 arranged vertically, and may also be electrically connected to the third data lead line 253 through two eighty-fourth via holes V84 arranged vertically.

[0228] In some examples, the twenty-fifth connection electrode 325 may be substantially a strip-shaped structure extending along the second direction Y. The twenty-fifth connection electrode 325 may be electrically connected to the first region of the active layer T40 of the fourth multiplexing transistor through four fifty-fifth via holes V55 arranged vertically, and may also be electrically connected to the second multiplexing connection line 262 through two eighty-eighth via holes V88 arranged vertically.

[0229] In some examples, the twenty-sixth connection electrode 326 may be substantially in the shape of a zigzag line extending along the second direction Y. The twenty-sixth connection electrode 326 may be electrically connected to the second region of the active layer T40 of the fourth multiplexing transistor through four fifty-sixth via holes V56 arranged vertically, and may also be electrically connected to the fifth data lead line 255 through two eighty-fifth via holes V85 arranged vertically.

[0230] In some examples, the twenty-seventh connection electrode 327 may be substantially in the shape of a zigzag line extending along the second direction Y. The twenty-seventh connection electrode 327 may be electrically connected to the first region of the active layer T30 of the third multiplexing transistor through four vertically arranged fifty-seventh via holes V57, and may also be electrically connected to the second data lead line 252 through two vertically arranged sixty-sixth via holes V66.

[0231] In some examples, the twenty-eighth connection electrode 328 may be substantially a strip-shaped structure extending along the second direction Y. The twenty-eighth connection electrode 328 may be electrically connected to the second region of the active layer T30 of the third multiplexing transistor through four fifty-eighth via holes V58 arranged vertically, and may also be electrically connected to the second multiplexing data line 42 through two seventieth via holes V70 arranged vertically.

[0232] In some examples, the twenty-ninth connection electrode 329 may be substantially in the shape of a zigzag line extending along the second direction Y. The twenty-ninth connection electrode 329 may be electrically connected to the first region of the active layer T20 of the second multiplexing transistor through four fifty-ninth via holes V59 arranged vertically, and may also be electrically connected to the fourth data lead line 254 through two sixty-seventh via holes V67 arranged vertically.

[0233] In some examples, the 30th connection electrode 330 may be a substantially strip-shaped structure extending along the second direction Y. The 30th connection electrode 330 may be electrically connected to the second region of the active layer T20 of the second multiplexing transistor through four 60th via holes V60 arranged vertically, and may also be electrically connected to the first multiplexing connection line 261 through two 80th via holes V80 arranged vertically.

[0234] In some examples, the thirty-first connection electrode 331 may be substantially in the shape of a zigzag line extending along the second direction Y. The thirty-first connection electrode 331 may be electrically connected to the first region of the active layer T60 of the sixth multiplexing transistor through four sixty-first via holes V61 arranged vertically, and may also be electrically connected to the sixth data lead line 256 through two sixty-eighth via holes V68 arranged vertically.

[0235] In some examples, the thirty-second connection electrode 332 may be a substantially strip-shaped structure extending along the second direction Y. The thirty-second connection electrode 332 may be electrically connected to the second region of the active layer T60 of the sixth multiplexing transistor through four vertically arranged sixty-second via holes V62, and may also be electrically connected to the third multiplexing data line 43 through two vertically arranged seventy-ninth via holes V79.

[0236] In some examples, the thirty-third connection electrode 333 can be electrically connected to the second data lead line 252 through two sixty-third via holes V63 arranged vertically. The thirty-fourth connection electrode 334 can be electrically connected to the fourth data lead line 254 through two sixty-fourth via holes V64 arranged vertically. The thirty-fifth connection electrode 335 can be electrically connected to the sixth data lead line 256 through two sixty-fifth via holes V65 arranged vertically. In this example, by providing the sixty-third, sixty-fourth, and sixty-fifth via holes, the uniformity of the openings can be ensured. By providing the thirty-third, thirty-fourth, and thirty-fifth connection electrodes, the resistance uniformity of multiple data lead lines can be ensured, thereby ensuring consistency in signal transmission.

[0237] In some examples, the first multiplexing control line 51 and the second multiplexing control line 52 may be at least linearly shaped and extend along the first direction X. The second multiplexing control line 52 may be located on one side of the first multiplexing control line 51 in the second direction Y. The first multiplexing control line 51 may be located on the same side of the twenty-eighth connection electrode 328, the thirtieth connection electrode 330, and the thirty-second connection electrode 332 in the second direction Y.

[0238] In some examples, the fourth multiplexing connection electrode 354, the fifth multiplexing connection electrode 355, and the sixth multiplexing connection electrode 356 may be located on one side of the second multiplexing control line 52 in the second direction Y. The fourth multiplexing connection electrode 354, the fifth multiplexing connection electrode 355, and the sixth multiplexing connection electrode 356 may be substantially strip-shaped structures extending along the first direction X. The fifth multiplexing connection electrode 355 may be located on one side of the fourth multiplexing connection electrode 354 in the second direction Y, and the sixth multiplexing connection electrode 356 may be located on one side of the fifth multiplexing connection electrode 355 in the second direction Y.

[0239] In some examples, the fourth patch line 364, the fifth patch line 365, and the sixth patch line 366 may be a bar-shaped structure extending along the second direction Y. The fourth patch line 364, the fifth patch line 365, and the sixth patch line 366 may be arranged sequentially along the first direction X. The fourth patch line 364, the fifth patch line 365, and the sixth patch line 366 may be located on one side of the sixth multiplexing connection electrode 356 in the second direction Y.

[0240] In some examples, the first multiplexing control line 51 can be electrically connected to the integrated structure of the gate T13 of the first multiplexing transistor and the gate T33 of the third multiplexing transistor through three horizontally arranged sixty-ninth vias V69, and can also be electrically connected to the gate T53 of the fifth multiplexing transistor through two horizontally arranged seventy-first vias V71. The second multiplexing control line 52 can be electrically connected to the gate T23 of the second multiplexing transistor through two horizontally arranged seventy-second vias V72, and can also be electrically connected to the integrated structure of the gate T43 of the fourth multiplexing transistor and the gate T63 of the sixth multiplexing transistor through three horizontally arranged seventy-third vias V73.

[0241] In some examples, the fourth multiplexing connection electrode 354 can be electrically connected to the first multiplexing data line 41 through two eighty-ninth via holes V89 arranged in a horizontal line, and can also be electrically connected to the first multiplexing connection line 261 through two eighty-first via holes V81 arranged in a horizontal line. The fifth multiplexing connection electrode 355 can be electrically connected to the second multiplexing data line 42 through two seventy-fourth via holes V74 arranged in a horizontal line, and can also be electrically connected to the second multiplexing connection line 262 through two eighty-second via holes V82 arranged in a horizontal line. The sixth multiplexing connection electrode 356 can be electrically connected to the third multiplexing connection line 263 through two ninetieth via holes V90 arranged in a horizontal line, and can also be electrically connected to the third multiplexing data line 43 through two seventy-eighth via holes V78 arranged in a horizontal line.

[0242] In some examples, the fourth patch line 364 can be electrically connected to the first multiplexed data line 41 through a plurality of seventy-sixth vias V76 arranged in an array. The fifth patch line 365 can be electrically connected to the second multiplexed data line 42 through a plurality of seventy-fifth vias V75 arranged in an array. The sixth patch line 366 can be electrically connected to the third multiplexed data line 43 through a plurality of seventy-seventh vias V77 arranged in an array.

[0243] FIG24 is a schematic diagram of the display panel after the fifth insulating layer is formed in FIG18 . In some examples, as shown in FIG24 , the fourth insulating layer and the fifth insulating layer in the first border region may have multiple vias, such as vias V91 through V93. The fifth insulating layer and the fourth insulating layer within vias V91 through V93 may be removed to expose a portion of the surface of the third conductive layer.

[0244] In some examples, as shown in FIG18 , the fourth conductive layer of the first border region may include at least: a plurality of data bend connection lines (for example, a first data bend connection line 401, a second data bend connection line 402, and a third data bend connection line 403). The plurality of data bend connection lines may extend along the second direction Y and be arranged sequentially along the first direction X. The first data bend connection line 401 may be electrically connected to the fourth transfer line 364 through two vertically arranged ninety-first vias V91, the second data bend connection line 402 may be electrically connected to the fifth transfer line 365 through two vertically arranged ninety-second vias V92, and the third data bend connection line 403 may be electrically connected to the sixth transfer line 366 through two vertically arranged ninety-third vias V93.

[0245] This example arranges the multiplexing transistors of the multiplexing circuit in two rows, thereby reducing the space occupied by the multiplexing circuit in the second direction, which is beneficial for compressing the space required for the multiplexing circuit. The preparation process of the display panel of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0246] In other examples, when there is enough space in the first border area, the multiplexing transistors of the multiplexing unit can be arranged in a row and arranged sequentially along the first direction.

[0247] In other examples, when the first border area of ​​the display panel is narrower along the first direction and larger along the second direction, the multiplexing transistors of the multiplexing unit can be arranged in four or more rows. For example, the multiplexing transistors of the multiplexing circuit can be arranged in six rows; the first to sixth multiplexing transistors can be arranged sequentially along the second direction, with multiple first multiplexing transistors arranged in a row, multiple second multiplexing transistors arranged in a row, multiple third multiplexing transistors arranged in a row, multiple fourth multiplexing transistors arranged in a row, multiple fifth multiplexing transistors arranged in a row, and multiple sixth multiplexing transistors arranged in a row. This embodiment is not limited to this.

[0248] FIG25 is another equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG25 , multiplexing circuit 30 may include multiple multiplexing units 34. One multiplexing unit 34 may be configured to provide a data signal provided by one multiplexed data line to multiple data lines (e.g., three data lines).

[0249] In some examples, as shown in FIG25 , a multiplexing unit 34 can be electrically connected to three multiplexing control lines (e.g., including a third multiplexing control line 53, a fourth multiplexing control line 54, and a fifth multiplexing control line 55), a multiplexing data line, and multiple data lines (e.g., three data lines). Each multiplexing unit 34 can include three multiplexing transistors. The three data lines connected to a multiplexing unit 34 can be electrically connected to sub-pixels that emit light of different colors. The connection method of the multiplexing unit in this example can effectively save the required data signals.

[0250] FIG25 illustrates four multiplexing units of a multiplexing circuit as an example. The connection method of each multiplexing unit is similar, and the following description uses one multiplexing unit as an example. In some examples, as shown in FIG25 , the multiplexing unit 34 may include: a seventh multiplexing transistor T7, an eighth multiplexing transistor T8, and a ninth multiplexing transistor T9. The gate of the seventh multiplexing transistor T7 is electrically connected to the third multiplexing control line 53, the first electrode of the seventh multiplexing transistor T7 is electrically connected to a multiplexing data line (e.g., the fourth multiplexing data line 44), and the second electrode of the seventh multiplexing transistor T7 is electrically connected to the first data line. The first data line can be electrically connected to a column of first sub-pixels R1. The gate of the eighth multiplexing transistor T8 is electrically connected to the fourth multiplexing control line 54, the first electrode of the eighth multiplexing transistor T8 is electrically connected to the fourth multiplexing data line 44, and the second electrode of the eighth multiplexing transistor T8 is electrically connected to the second data line. The second data line can be electrically connected to a column of second sub-pixels G1. The gate of the ninth multiplexing transistor T9 is electrically connected to the fifth multiplexing control line 55, the first electrode of the ninth multiplexing transistor T9 is electrically connected to the fourth multiplexing data line 44, and the second electrode of the ninth multiplexing transistor T9 is electrically connected to the third data line. The third data line can be electrically connected to a column of third subpixels B1. The column of first subpixels R1, the column of second subpixels G1, and the column of third subpixels B1 can be configured to emit light of different colors. For example, the column of first subpixels R1 can emit red light, the column of second subpixels G1 can emit green light, and the column of third subpixels B1 can emit blue light.

[0251] In this example, the data signals received by three adjacent sub-pixels emitting light of different colors can be controlled by the same multiplexing unit. A 1:3 design (i.e., a design in which one multiplexed data line provides data signals to three data lines) can be used to achieve high refresh rate requirements.

[0252] Figure 26 is a partial schematic plan view of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 26 illustrates the planar structure of three multiplexing units. The following description uses the planar structure of a multiplexing unit 34 as an example. In this example, the first connection end of the trace is the one closest to the display area, and the second connection end is the one farther from the display area.

[0253] In some examples, as shown in FIG26 , a plurality of multiplexing units 34 may be arranged sequentially along a first direction X. The three multiplexing transistors included in each multiplexing unit 34 may be arranged along a second direction Y. The multiplexing transistors of the multiplexing circuit of this example may be arranged in three rows. A plurality of seventh multiplexing transistors T7 may be arranged in a row, a plurality of eighth multiplexing transistors T8 may be arranged in a row, and a plurality of ninth multiplexing transistors T9 may be arranged in a row. A column of multiplexing transistors may include: a seventh multiplexing transistor T7, an eighth multiplexing transistor T8, and a ninth multiplexing transistor T9 arranged sequentially along the second direction Y.

[0254] In some examples, as shown in FIG. 26 , in a direction perpendicular to the display panel, the first border region may include at least: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer disposed on the substrate.

[0255] FIG27 is a schematic diagram of the display panel after the semiconductor layer is formed in FIG26. In some examples, as shown in FIG27, the semiconductor layer in the first frame region may include at least active layers of multiplexing transistors of multiple multiplexing units of the multiplexing circuit, such as active layers T70 of a seventh multiplexing transistor, T80 of an eighth multiplexing transistor, and T90 of a ninth multiplexing transistor.

[0256] In some examples, the shapes and sizes of the orthographic projections of the active layers T70, T80, and T90 of the seventh multiplexing transistor, respectively, on the substrate may be substantially the same, for example, rectangles of substantially the same size.

[0257] In some examples, the active layer T70 of the seventh multiplexing transistor has a seventh center line O7, the active layer T80 of the eighth multiplexing transistor has an eighth center line O8, and the active layer T90 of the ninth multiplexing transistor has a ninth center line O9. The seventh center line O7, the eighth center line O8, and the ninth center line O9 are all parallel to the second direction Y. The eighth center line O8 of the active layer T80 of the eighth multiplexing transistor can be located on one side of the ninth center line O9 of the active layer T90 of the ninth multiplexing transistor in the first direction X, and the seventh center line O7 of the active layer T70 of the seventh multiplexing transistor can be located on one side of the eighth center line O8 of the active layer T80 of the eighth multiplexing transistor in the first direction X. In the first direction X, the distance between the eighth center line O8 and the ninth center line O9 can be greater than the distance between the eighth center line O8 and the seventh center line O7. However, this embodiment is not limited to this.

[0258] FIG28A is a schematic diagram of the display panel after the first conductive layer is formed in FIG26 . FIG28B is a planar schematic diagram of the first conductive layer in FIG28A . In some examples, as shown in FIG28A and FIG28B , the first conductive layer in the first border region may include at least: gates of multiple multiplexing transistors of the multiplexing circuit (e.g., gate T73 of the seventh multiplexing transistor T7, gate T83 of the eighth multiplexing transistor T8, and gate T93 of the ninth multiplexing transistor T9), multiple data lead lines (e.g., first data lead line 251 and third data lead line 253), and multiple conductive connection blocks (e.g., first conductive connection block 271, second conductive connection block 272, and fourth conductive connection block 274).

[0259] In some examples, the gate T93 of the ninth multiplexing transistor T9 , the gate T83 of the eighth multiplexing transistor T8 , and the gate T73 of the seventh multiplexing transistor T7 may be sequentially arranged along the first direction X, and their lengths along the second direction Y may gradually decrease.

[0260] In some examples, the first data lead line 251 and the third data lead line 253 may be located on a side of the active layer T70 of the seventh multiplexing transistor in a direction opposite to the second direction Y. The first conductive connection block 271, the second conductive connection block 272, and the fourth conductive connection block 274 may be located on a side of the active layer T90 of the ninth multiplexing transistor in the second direction Y. The first conductive connection block 271 is aligned with one end of the gate T93 of the ninth multiplexing transistor in the second direction Y, and the second conductive connection block 272 is aligned with one end of the gate T83 of the eighth multiplexing transistor in the second direction Y. The fourth conductive connection block 274 may be located between the gate T93 of the ninth multiplexing transistor and the second conductive connection block 272.

[0261] FIG29A is a schematic diagram of the display panel after the second conductive layer is formed in FIG26 . FIG29B is a planar schematic diagram of the second conductive layer in FIG29A . In some examples, as shown in FIG29A and FIG29B , the second conductive layer in the first border region may include at least: a plurality of data lead lines (e.g., including second data lead lines 252 ), a plurality of conductive connection blocks (e.g., including third conductive connection blocks 273 ), and a multiplexed data line (e.g., fourth multiplexed data line 44 ).

[0262] In some examples, the second data lead line 252 may be located between the first data lead line 251 and the third data lead line 253. The third conductive connection block 273 may be located on one side of the gate T73 of the seventh multiplexing transistor in the second direction Y and aligned with one end of the gate T73 of the seventh multiplexing transistor in the second direction Y. The fourth multiplexing data line 44 may be located on one side of the fourth conductive connection block 274 in the second direction Y and aligned with the fourth conductive connection block 274 in the second direction Y.

[0263] FIG30 is a schematic diagram of the display panel after the third insulating layer is formed in FIG26. In some examples, as shown in FIG30, the third insulating layer in the first border region may have a plurality of via holes, such as the 101st to 106th via holes V106, the 107th to 116th via holes V107, and the 121st to 124th via holes V121.

[0264] In some examples, the third insulating layer, the second insulating layer, and the first insulating layer within the one hundred and first vias V101 to the one hundred and sixth vias V106 can be removed to expose a portion of the surface of the semiconductor layer; the third insulating layer and the second insulating layer within the one hundred and seventh vias V107 to the one hundred and sixteenth vias V116 can be removed to expose a portion of the surface of the first conductive layer; and the third insulating layer within the one hundred and twenty-first vias V121 to the one hundred and twenty-fourth vias V124 can be removed to expose a portion of the surface of the second conductive layer.

[0265] FIG31 is a plan view schematic diagram of the third conductive layer in FIG26. In some examples, as shown in FIG26 and FIG31, the third conductive layer in the first border region may include at least: a plurality of connection electrodes (for example, including the forty-first connection electrode 341 to the forty-seventh connection electrode 347), a third multiplexing control line 53, a fourth multiplexing control line 54, and a fifth multiplexing control line 55.

[0266] In some examples, the forty-first connection electrode 341 may be substantially in the shape of a zigzag line extending along the second direction Y. The forty-first connection electrode 341 may be connected to the first region of the active layer T70 of the seventh multiplexing transistor through four vertically arranged via holes V101 (one hundred and first), may be connected to the first region of the active layer T80 of the eighth multiplexing transistor through four vertically arranged via holes V104 (one hundred and fourth), may be connected to the first region of the active layer T90 of the ninth multiplexing transistor through four vertically arranged via holes V106 (one hundred and sixth), may be electrically connected to the fourth conductive connection block 274 through two vertically arranged via holes V111, and may be electrically connected to the fourth multiplexing data line 44 through two vertically arranged via holes V122 (one hundred and second).

[0267] In some examples, the 42nd connection electrode 342 may be a substantially strip-shaped structure extending along the second direction Y. The 42nd connection electrode 342 may be connected to the second region of the active layer T70 of the seventh multiplexing transistor through four 102nd via holes V102 arranged vertically, and may also be electrically connected to the third data lead line 253 through two 108th via holes V108 arranged vertically.

[0268] In some examples, the forty-third connection electrode 343 may be substantially in the shape of a zigzag line extending along the second direction Y. The forty-third connection electrode 343 may be connected to the second region of the active layer T80 of the eighth multiplexing transistor through four 103rd via holes V103 arranged vertically, and may also be electrically connected to the second data lead line 252 through two 121st via holes V121 arranged horizontally.

[0269] In some examples, the forty-fourth connection electrode 344 may be substantially in the shape of a straight line extending along the second direction Y. The forty-fourth connection electrode 344 may be connected to the second region of the active layer T90 of the ninth multiplexing transistor through four vertically arranged via holes V105, and may also be electrically connected to the first data lead line 251 through two horizontally arranged via holes V107.

[0270] In some examples, the forty-fifth connection electrode 345 may be a substantially strip-shaped structure extending along the second direction Y. The forty-fifth connection electrode 345 may be electrically connected to the gate T93 of the ninth multiplexing transistor through two vertically arranged 109th via holes V109, and may also be electrically connected to the first conductive connection block 271 through two vertically arranged 100th via holes V110.

[0271] In some examples, the forty-sixth connection electrode 346 may be a substantially strip-shaped structure extending along the second direction Y. The forty-sixth connection electrode 346 may be electrically connected to the gate T83 of the eighth multiplexing transistor through two vertically arranged 112th via holes V112 , and may also be electrically connected to the second conductive connection block 272 through two vertically arranged 113th via holes V113 .

[0272] In some examples, the forty-seventh connecting electrode 347 has a strip-shaped structure extending along the second direction Y. The forty-seventh connecting electrode 347 can be electrically connected to the gate T73 of the seventh multiplexing transistor through two vertically arranged 116th via holes V116, and can also be electrically connected to the third conductive connecting block 273 through two vertically arranged 123rd via holes V123.

[0273] In some examples, the third multiplexing control line 53, the fourth multiplexing control line 54, and the fifth multiplexing control line 55 may be at least linearly shaped and extend along the first direction X. The fourth multiplexing control line 54 may be located on one side of the fifth multiplexing control line 55 in the second direction Y, and the third multiplexing control line 53 may be located on one side of the fourth multiplexing control line 54 in the second direction Y. The fifth multiplexing control line 55 may be located on one side of the forty-seventh connection electrode 347 in the second direction Y.

[0274] In some examples, the fifth multiplexing control line 55 can be electrically connected to the first conductive connection block 271 through two horizontally arranged 114th via holes V114, thereby being electrically connected to the gate T93 of the ninth multiplexing transistor. The fourth multiplexing control line 54 can be electrically connected to the second conductive connection block 272 through two horizontally arranged 115th via holes V115, thereby being electrically connected to the gate T83 of the eighth multiplexing transistor. The third multiplexing control line 53 can be electrically connected to the third conductive connection block 273 through two horizontally arranged 124th via holes V124, thereby being electrically connected to the gate T73 of the seventh multiplexing transistor.

[0275] In some examples, the fourth multiplexed data line 44 may extend toward one side of the bending region and be electrically connected to the data bending connection line in the bending region.

[0276] In this example, three multiplexing transistors electrically connected to the same multiplexing data line are arranged in a column and are misaligned in the second direction. The gates of the three multiplexing transistors are connected to different multiplexing control lines. The arrangement of the multiplexing transistors in this example can reduce the arrangement space required in the horizontal and vertical directions, improve space utilization, and is suitable for display panels with narrow first frame areas. Moreover, combined with the 1:3 design of the multiplexing circuit, the high refresh rate requirements of the display panel can be met. The method for preparing the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0277] This embodiment also provides a display panel, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, and a multiplexing circuit. The substrate includes a display area and a first frame area located on at least one side of the display area. A plurality of sub-pixels and a plurality of data lines are located in the display area, and the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. The multiplexing circuit is located in the first frame area and includes a plurality of multiplexing units, at least one of the plurality of multiplexing units includes a plurality of multiplexing transistors, and the at least one multiplexing unit is electrically connected to a multiplexed data line, a multiplexed control lines and a plurality of data lines, and is configured to provide the data signals transmitted by the multiplexed data lines to the plurality of data lines under the control of the a multiplexed control lines, wherein a is an integer greater than 1 and less than or equal to 3. For example, a can be 2 or 3. The multiple multiplexing transistors of the at least one multiplexing unit are located in the same row, or in the same column, or in different rows; wherein, a row of multiplexing transistors includes a plurality of multiplexing transistors arranged along a first direction, and a column of multiplexing transistors includes a plurality of multiplexing transistors arranged along a second direction, and the first direction intersects the second direction.

[0278] In some examples, the multiplexing transistors of at least one multiplexing unit may be located in the same row, such as the embodiment shown in Figure 5. In other examples, the multiplexing transistors of at least one multiplexing unit may be located in the same column, such as the embodiment shown in Figure 26. In other examples, the multiplexing transistors of at least one multiplexing unit may be located in different rows, such as the embodiment shown in Figure 18.

[0279] In some example embodiments, a column of multiplexing transistors includes: a plurality of multiplexing transistors connected to a same multiplexing control line; or a plurality of multiplexing transistors connected to a same multiplexing data line.

[0280] For the description of the display panel of this embodiment, reference can be made to the description of the aforementioned embodiment, and thus no further details will be given here.

[0281] Figure 32 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 32, this embodiment provides a display device 91 comprising a display panel 910 according to the aforementioned embodiment. In some examples, display panel 910 may be an OLED display panel, such as an OLED display panel with an integrated touchscreen structure. Display device 91 may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, or may be a product or component with both touchscreen and display functions.

[0282] In some examples, the display device 91 may be a wearable display device, for example, a display device that can be worn on a human body in some manner. For example, the display device 91 may be a smart watch, a smart bracelet, etc. However, this embodiment is not limited to this.

[0283] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display panel, comprising: A substrate, comprising a display area and a first frame area located on at least one side of the display area; A plurality of sub-pixels and a plurality of data lines are located in the display area, the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; A multiplexing circuit, located in the first frame area, comprising a plurality of multiplexing units; at least one of the plurality of multiplexing units comprises a plurality of multiplexing transistors, the at least one multiplexing unit is electrically connected to a multiplexing data line, a plurality of multiplexing control lines and a plurality of data lines, and is configured to provide the plurality of data lines with data signals transmitted by the multiplexing data lines under the control of the plurality of multiplexing control lines; The multiplexing transistors of the multiple multiplexing units are arranged in multiple rows and columns, a row of multiplexing transistors includes multiple multiplexing transistors arranged along a first direction, and a column of multiplexing transistors includes multiple multiplexing transistors arranged along a second direction; wherein the first direction intersects the second direction.

2. The display panel according to claim 1, wherein: A column of multiplexing transistors includes: a plurality of multiplexing transistors connected to the same multiplexing control line.

3. The display panel according to claim 1, wherein: A column of multiplexing transistors includes: a plurality of multiplexing transistors connected to the same multiplexing data line.

4. The display panel according to any one of claims 1 to 3, wherein: The multiplexing transistors of the multiplexing units are arranged in three rows.

5. The display panel according to claim 4, wherein: The at least one multiplexing unit comprises two multiplexing transistors, the two multiplexing transistors are electrically connected to different multiplexing control lines and to the same multiplexing data line; the two multiplexing transistors of the at least one multiplexing unit are arranged in the same row.

6. The display panel according to claim 5, wherein: The multiple multiplexing units at least include: a plurality of first multiplexing units, a plurality of second multiplexing units and a plurality of third multiplexing units; the multiplexing transistors of the plurality of first multiplexing units are arranged in a first row, the multiplexing transistors of the plurality of second multiplexing units are arranged in a second row, and the multiplexing transistors of the plurality of third multiplexing units are arranged in a third row; The multiplexing transistors in the first multiplexing unit, the second multiplexing unit and the third multiplexing unit that are electrically connected to the same multiplexing control line are arranged in the same column.

7. The display panel according to claim 6, wherein: The plurality of sub-pixels include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light; The first multiplexing unit is configured to provide data signals to a plurality of first sub-pixels, the second multiplexing unit is configured to provide data signals to a plurality of second sub-pixels, and the third multiplexing unit is configured to provide data signals to a plurality of third sub-pixels.

8. The display panel according to claim 4, wherein: The at least one multiplexing unit comprises three multiplexing transistors, the three multiplexing transistors are electrically connected to different multiplexing control lines and to the same multiplexing data line; the three multiplexing transistors of the at least one multiplexing unit are arranged in the same column.

9. The display panel according to claim 8, wherein: The plurality of sub-pixels include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light; The three multiplexing transistors of the at least one multiplexing unit are configured to provide data signals to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively.

10. The display panel according to claim 9, wherein: The three multiplexing transistors of the at least one multiplexing unit are a seventh multiplexing transistor, an eighth multiplexing transistor and a ninth multiplexing transistor; The seventh multiplexing transistor, the eighth multiplexing transistor and the ninth multiplexing transistor located in the same column are staggered in the second direction.

11. The display panel according to claim 10, wherein: The plurality of the seventh multiplexing transistors are arranged in a first row, the plurality of the eighth multiplexing transistors are arranged in a second row, the plurality of the ninth multiplexing transistors are arranged in a third row, and the first row, the second row and the third row are arranged in sequence in a direction away from the display area.

12. The display panel according to any one of claims 1 to 3, wherein: The multiplexing transistors of the multiplexing units are arranged in two rows.

13. The display panel according to claim 12, wherein: The at least one multiplexing unit includes two multiplexing transistors, which are electrically connected to a first multiplexing control line and a second multiplexing control line, respectively, and are electrically connected to the same multiplexing data line; the two multiplexing transistors of the at least one multiplexing unit are arranged in different rows and columns.

14. The display panel according to claim 13, wherein: The multiplexing transistors located in the i-th column are all electrically connected to the first multiplexing control line, the multiplexing transistors located in the i+1-th column are electrically connected to different multiplexing control lines, and the multiplexing transistors located in the i+2-th column are all electrically connected to the second multiplexing control line, where i is an integer greater than 0.

15. The display panel according to claim 13 or 14, wherein: The multiple multiplexing units at least include: a plurality of first multiplexing units, a plurality of second multiplexing units and a plurality of third multiplexing units; the plurality of sub-pixels include: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light and a third sub-pixel emitting a third color light; The first multiplexing unit is configured to provide data signals to a plurality of first sub-pixels, the second multiplexing unit is configured to provide data signals to a plurality of second sub-pixels, and the third multiplexing unit is configured to provide data signals to a plurality of third sub-pixels; The two multiplexing transistors of the first multiplexing unit are respectively located in the i-th column and the i+1-th column; The two multiplexing transistors of the second multiplexing unit are respectively located in the i-th column and the i+2-th column; The two multiplexing transistors of the third multiplexing unit are respectively located in the i+1th column and the i+2th column.

16. The display panel according to any one of claims 1 to 15, wherein: The first frame area at least includes: a first fan-out area and a bending area arranged in sequence along a direction away from the display area; the multiplexing circuit is located in the first fan-out area; the first fan-out area includes: a plurality of data lead-out lines and a plurality of multiplexed data lines; the bending area at least includes: a plurality of data bending connection lines; The multiplexing circuit is electrically connected to the plurality of data lines in the display area through the plurality of data lead-out lines and is electrically connected to the plurality of multiplexed data lines, and the plurality of multiplexed data lines are electrically connected to the plurality of data bending connection lines.

17. The display panel according to claim 16, wherein: The first frame region at least includes: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer arranged on the substrate; The multiplexed data lines are alternately arranged in the first conductive layer and the second conductive layer; The plurality of data lead lines are alternately arranged in the first conductive layer and the second conductive layer.

18. The display panel according to claim 17, wherein: The first frame region further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate; and the plurality of data bending connection lines are located in the fourth conductive layer.

19. A display device comprising the display panel according to any one of claims 1 to 18.

20. A display panel, comprising: A substrate, comprising a display area and a first frame area located on at least one side of the display area; A plurality of sub-pixels and a plurality of data lines are located in the display area, the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; a multiplexing circuit, located in the first frame area, comprising a plurality of multiplexing units, at least one of the plurality of multiplexing units comprising a plurality of multiplexing transistors, the at least one multiplexing unit being electrically connected to a multiplexing data line, a multiplexing control lines and a plurality of data lines, and being configured to provide the plurality of data lines with data signals transmitted by the multiplexing data lines under the control of the a multiplexing control lines, wherein a is an integer greater than 1 and less than or equal to 3; The multiple multiplexing transistors of the at least one multiplexing unit are located in the same row, or in the same column, or in different rows; wherein a row of multiplexing transistors includes a plurality of multiplexing transistors arranged along a first direction, and a column of multiplexing transistors includes a plurality of multiplexing transistors arranged along a second direction, and the first direction intersects with the second direction.

21. The display panel according to claim 20, wherein: A column of multiplexing transistors includes: a plurality of multiplexing transistors connected to the same multiplexing control line; or, a plurality of multiplexing transistors connected to the same multiplexing data line.

Images