Superconducting structures and methods of manufacture

Abstract

A superconducting structure (e.g., via) extending at least part-way through a substrate 101. The substrate comprises a first surface 102, a second surface 104 opposed to the first surface, and a reces

Description

FIELD OF THE INVENTION This invention relates to a superconducting structure in which a superconductive pathway extends between a surface of a substrate (such as a semiconductor wafer) and the side wall of a recess (such as a via) formed in the substrate. Superconducting structures manufactured by methods in accordance with the invention find particular application in the manufacture of electronic devices for quantum applications, such as quantum computing and superconducting nanowire single photon detectors, since they can be employed to realise 3D integration of quantum circuits. BACKGROUND TO THE INVENTION In many quantum processors, the quantum computing components (e.g. the devices that implement and manipulate the quantum mechanical systems on which computations are performed) are typically arranged on one side of a substrate (e.g. a semiconductor wafer) and are in communication with other devices arranged on the opposite side of the substrate, or to other areas on the same side of the wafer, or to devices on a separate substrate. Such communication can be achieved by forming one or more electrical connections through the wafer by the provision of “through-substrate vias” (TSVs) (often referred to as “through-silicon vias”, where the substrate is silicon) extending through the wafer and forming a conductive pathway between its two sides. This is important for increasing the scalability of electronics for quantum computing and other quantum applications. Because quantum processors of the kind just described operate at cryogenic temperatures (e.g. below 10 Kelvin (K)), the vias must be superconducting to ensure that they do not experience resistive heating and thereby raise the temperature of the quantum computing components. Moreover, the transition temperature (also sometimes referred to as “critical temperature”), Tc, of the via (above which it ceases to be superconductive and acquires a non-zero resistance) must be sufficiently high that the via is superconductive across the temperature range at which the quantum processor operates. A high transition temperature is desirable for many quantum applications. A high critical temperature enables a higher range of currents to be supported in the quantum circuit and also allows the working temperature of the quantum circuit to be achieved using less sophisticated cryogenic systems. It also enables the quantum circuit to tolerate potential suppression of superconductivity in superconducting parts of the circuit such as TSVs. Previous superconducting TSV designs have encountered difficulties in reliably producing vias that exhibit superconductivity and have a suitably high transition temperature. For example, attempts have been made to produce superconducting vias by lining the wall of a via through the substrate with a deposited superconductor material such as titanium nitride, but these approaches have generally either failed altogether to demonstrate superconductivity reliably or, where they have done so, exhibited transition temperatures that are below the range at which most quantum processors preferably operate. For example, many attempts have produced vias with transition temperatures of about 2 K, whereas, as mentioned above, a transition temperature of at least 10 K is desirable for many quantum applications. An aim of the present invention is to provide superconducting structures that exhibit high transition temperatures. SUMMARY OF THE INVENTION A first aspect of the invention provides a superconducting structure extending at least part-way through a substrate, the substrate comprising: a planar first surface and a planar second surface opposed to the first surface; and a recess formed in the substrate, the recess having a side wall extending from the first surface at least part-way through the substrate towards the second surface; and the superconducting structure comprising: a superconductor material coating extending continuously across a region comprising part of the first surface and at least part of the side wall of the recess, the superconductor material coating comprising, on at least one of the side wall and the first surface: a plurality of layers overlapping one another, the plurality of overlapping layers comprising at least one higher-crystallinity layer of the superconductor material and at least one lower-crystallinity layer of the superconductor material, one or more of the higher-crystallinity layers contacting the superconductor material on the other of the side wall and the first surface such that said one or more higher-crystallinity layers and the superconductor material on the other of the side wall and the first surface together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess. Superconducting structures of the construction defined enable the achievement of high transition temperatures. The inventors have realised that the quality (i.e. crystallinity) of superconductor material produced by conventional deposition processes varies in quality between the surfaces on which it is deposited: for example, a set of process parameters that form good quality, relatively high-crystallinity superconductor material on the first surface of the substrate (the normal of which is typically substantially aligned with the deposition direction, or makes a low angle with the deposition direction - e.g. 60 degrees or less) would form worse quality, relatively low-crystallinity superconductor material on other surfaces such as the side wall of a recess (the normal of which typically makes a higher angle with the deposition direction, e.g. more than 60 degrees and in many cases around 90 degrees). Consequently, whichever parameters the superconductor material is deposited under, there will typically be poor quality material somewhere along the conductive pathway and consequently the behaviour of the pathway as a whole will be limited (e.g. in terms of its transition temperature, Tc). The design defined above enables the formation of an electrical pathway which has good quality superconductor material extending continuously along its entire length. Since a process that deposits good quality material in one location generally produces worse material elsewhere, the invention provides a structure in which at least one of the surfaces on which the coating is present has multiple overlapping layers of the superconductor material, including lower-crystallinity layers which may be present as a result of performing depositions optimised for other locations on the substrate. Provided that at least one higher-crystallinity crystallinity layer is also present on that surface and in direct electrical contact with material on the other surface, a continuous conductive pathway formed by good quality material along its entire length can be produced. Examples of preferred techniques for forming this structure will be described below. A “superconductor material” is a material that exhibits superconductivity (i.e. substantially or exactly zero resistance) below a critical temperature, the exact value of which depends on the superconductor material and the structure of the particular sample in question. Niobium nitride (NbN) is an example of such a material, and samples of this material can exhibit critical temperatures of up to about 17 K. Here, “crystallinity” means the proportion (as a percentage) of the material that has crystal structure, rather than being amorphous. Therefore, in the or each “higher-crystallinity layer”, a greater proportion of the superconductor material is crystalline than in the or each “lower-crystallinity layer”. It will be understood that the terms “higher-crystallinity” and “lower-crystallinity" define the crystallinity of layers within each stack relative to one another, rather than relative to layers in other stacks. This means that, for example, the higher-crystallinity layer(s) on the side wall of the recess are of higher crystallinity than the lower-crystallinity layer(s) on the side wall of the recess and the higher-crystallinity layer(s) on the first surface of the substrate are of higher crystallinity than the lower-crystallinity layer(s) on the first surface of the substrate. Where this specification makes reference to one piece superconductor material being of a higher (or lower) “quality” than another, what is meant is that its crystallinity, as defined above, is higher (or lower) than that of the other piece of superconductor material. It should be understood that each of the plurality of layers referred to above is of the same material, i.e. has substantially the same chemical composition, but that material varies in crystallinity between the layers in the manner described, “Coating” here means a conformal deposition of material, which may be composed of one layer or more than one layer of the material, across the region concerned. The number of layers forming the coating may be the same at all locations across the region, or may vary. It will be appreciated that the coating is not required to cover all parts of the surfaces on which it is present because the region defined above (across which the coating extends continuously) does not necessarily encompass the entirety of each of the surfaces concerned. For example, in many embodiments, the purpose of the superconductor material on the first surface of the substrate is to electrically connect a component (e.g. an electronic component) on the first surface to the side wall of the recess. For this purpose, the superconductor material on the first surface need only cover enough of the first surface to form this electrical connection. For brevity, the term “stack” will be used in places herein to refer to the “plurality of overlapping layers” defined above. Since there may be a plurality of overlapping layers on each of the first surface of the substrate and the side wall of the recess, each of these surfaces may carry a respective “stack” of layers forming the part of the coating that extends across that surface (or part of that surface). In preferred implementations, the superconductor material coating comprises, on each of the side wall and the first surface, a respective plurality of layers overlapping one another, each plurality of overlapping layers comprising at least one higher-crystallinity layer of the superconductor material and at least one lower-crystallinity layer of the superconductor material, wherein one or more of the higher-crystallinity layers on the side wall each directly contact one or more of the higher-crystallinity layers on the first surface. In these embodiments, each of the first surface of the substrate and the side wall of the recess carries a respective stack of layers, which comprises higher-crystallinity and lower-crystallinity layers, forming the part of the superconductor material coating that covers that surface. The lower-crystallinity layer(s) on each surface may be the result of performing a deposition process optimised for forming the higher-crystallinity layer(s) in the stack on the other surface. Preferably, on the first surface of the substrate and / or the side wall of the recess, the overlapping higher-crystallinity layers and lower-crystallinity layers are layered in an alternating manner. In other words, the order of the layers within each stack is such that if the first layer (the layer nearest the substrate) is a higher-crystallinity layer, then the next is lower-crystallinity, then higher-crystallinity, and so on. Alternatively, if the first layer in the stack is a lower-crystallinity layer, the next is higher-crystallinity, then lower-crystallinity, and so on. Most preferably, the overlapping higher-crystallinity layers and lower-crystallinity layers are layered in an alternating manner on each of the first surface of the substrate and the side wall of the recess, and the order of the higher-crystallinity layers and lower-crystallinity layers on the first surface is inverted relative to the order of the higher-crystallinity layers and lower-crystallinity layers on the side wall of the recess. In this scenario, if the first layer of the stack on one of the first surface of the substrate and the side wall of the recess is higher-crystallinity, the first layer of the other stack is lower-crystallinity. The next layer in the stack on the one surface will be lower-crystallinity and the next in the other stack will be higher-crystallinity, and so on. Advantageously, on the first surface of the substrate and / or the side wall of the recess, the respective plurality of layers (stack) may comprise at least three layers. Preferably the superconductor material is niobium nitride (NbN), titanium nitride (TiN), tantalum nitride (TaN), or a mixture thereof. These materials have been found to achieve good transition temperatures in the construction defined above. As noted above, if the superconductor material is NbN (for example) then each of the layers will be composed of NbN. However, the crystallinity of the NbN will vary between layers in the matter described. In preferred implementations, the transition temperature, Tc, of the superconductive pathway is at least 3 K. To say that the superconductive pathway exhibits this critical temperature means that the superconductive pathway as a whole exhibits no resistance below 3 K. Preferably the substrate is a wafer. The substrate may also be referred to as an “interposer” since in many applications it will ultimately be located between two circuits (one on each side of the substrate). The substrate preferably comprises (or consists of) any one or more of the following materials: • Semiconductor material(s), preferably silicon. Doped (p-type or n-type) silicon or undoped (i.e. ‘intrinsic’) silicon can be used. • Glass material(s), such as SiO2. Glass substrates can offer high electrical insulation, low signal loss, and excellent thermal stability. • Organic material(s), for instance polymer(s), such as epoxy resin-based laminates (e.g., Bismaleimide-Triazine resin). Organic substrates such as these may be less expensive and more flexible than silicon and glass. They are widely used in conventional PCB manufacturing, making them a cost-effective option. • Ceramic material(s), such as aluminium oxide (AI2O3, also known as sapphire) or aluminium nitride (AIN). Ceramic substrates can provide excellent thermal conductivity and mechanical strength. They can also be good electrical insulators. Advantageously the thickness of the superconductor material coating may be at all points less than 5 pm, preferably less than 1 pm, preferably less than 500 nm, more preferably less than 200 nm. Advantageously, the recess is a via extending all the way through the substrate from the first surface to the second surface. “Via” here means an aperture (i.e. a gap in the substrate, which may optionally be filled or partially filled with a different material such as the superconductor material) extending through the full thickness of the substrate from the first surface to the second surface. In these embodiments, it is preferred that the superconductive pathway extends all the way along the side wall of the via and preferably onto the second surface. The superconductive pathway thus provides an electrical connection between the two surfaces of the substrate, which can enable electrical communication between components on the two surfaces. The via preferably has a smallest lateral dimension in the range of 0.2 pm to 5000 pm, preferably 60-80 pm. Preferably, the ratio of the thickness of the substrate to the smallest lateral dimension of the etched via is in the range of 1:1 to 70:1, preferably 3:1 to 20:1, more preferably in the range of 4:1 to 10:1. By “smallest lateral dimension” we mean the smallest dimension that the via has in any lateral direction (i.e. any direction parallel to the plane of the substrate). For example, in the case of a via with a circular crosssection, this smallest dimension is the diameter. In the case of a rectangular cross-section, this smallest dimension is the length of the shorter side of the rectangle. The thickness of the substrate corresponds to the depth of the manufactured via, and if the depth of the via is too great relative to its lateral dimensions, it can become difficult to achieve uniform deposition of superconductor material across the side wall. The aspect ratios defined above have been found to enable suitably uniform deposition and formation of high-quality crystal structure in the deposited material. Particularly where the thickness of the substrate is large in relation to the lateral dimensions of the via, atomic layer deposition is preferred for depositing the superconductor material because this process is particularly effective at forming layers of a uniform thickness and quality over large distances and the amount of material deposited is (thanks to the selflimiting nature of the deposition) relatively unaffected by differences in the exposure of different parts of the via wall to plasma. Methods of manufacturing superconducting structures in accordance with the invention will now be introduced. Each of the methods below may be employed to produce superconducting structures as described above. A second aspect of the invention provides a method of manufacturing a superconducting structure extending at least part-way through a substrate, the substrate having a planar first surface, a planar second surface opposed to the first surface, and a recess formed in the substrate, the recess having a side wall extending from the first surface at least part-way through the substrate towards the second surface, the method comprising: depositing a superconductor material coating extending continuously across a region comprising part of the first surface and at least part of the side wall of the recess, the deposition comprising depositing on at least one of the side wall and the first surface: a plurality of sublayers overlapping one another, the plurality of overlapping sublayers comprising at least one higher-crystallinity sublayer of the superconductor material and at least one lower-crystallinity sublayer of the superconductor material, one or more of the higher-crystallinity sublayers contacting the superconductor material on the other of the side wall and the first surface such that said one or more higher-crystallinity sublayers and the superconductor material on the other of the side wall and the first surface together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess. Any or all of the preferred features described above with reference to the first aspect may be provided in superconducting structures manufactured in accordance with this second aspect of the invention. A third aspect of the invention provides a method of manufacturing a superconducting structure extending at least part-way through a substrate, the substrate having opposed first and second surfaces and a recess extending from the first surface at least part-way through the substrate towards the second surface, the method comprising, in any order: (a) using a lower-plasma-dose plasma deposition process, depositing a layer of a superconductor material on the first surface of the substrate at least adjacent to an edge of the recess on the first surface; (b) using a higher-plasma-dose plasma deposition process, depositing a layer of the superconductor material on at least part of a side wall of the recess; wherein the process parameters of the deposition processes used in steps (a) and (b) are different from one another, the plasma dose delivered to the substrate in the lower-plasma-dose plasma deposition process of step (a) being lower than the plasma dose delivered to the substrate in the higher-plasma-dose plasma deposition process of step (b); whereby the layer of the superconductor material deposited on the first surface of the substrate in step (a) and the layer of the superconductor material deposited on the side wall of the recess in step (b) contact one another and together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess. This method employs a “lower-plasma-dose” plasma deposition process for depositing the superconductor material onto at least the first surface of the substrate and a “higher-plasma-dose” plasma deposition process for depositing the superconductor material onto at least the side wall of the recess. Each process delivers to the substrate a “plasma dose”, which is higher in the higher-plasma-dose process than in the lower-plasma-dose process. The “plasma dose” here is defined as the product of the average particle energy in the plasma, the flux of particles impinging on the substrate, and the time for which the substrate is exposed to the plasma. In most embodiments, the plasma dose will be controlled principally by controlling factors that influence the average ion energy, such as the power supplied to the plasma source from which the plasma is generated and the bias applied (if any) to the surface on which the substate is supported during the deposition. It has been found that formation of the best quality superconductor material is formed by plasma doses that are optimised to remove defect and impurities while avoiding damage to the deposited material. Relative to the first surface of the substrate, the side walls of recesses are to a degree shielded from the plasma. Therefore, the side wall typically exhibits better quality material when supplied with a greater plasma dose than the first surface. It is believed that for this reason, the optimum plasma dose for the side wall of the recess is generally higher than the optimum for the first surface. As noted above, the plasma dose is defined as the product of the average particle energy in the plasma, the flux of particles impinging on the substrate, and the time for which the substrate is exposed to the plasma. The plasma dose increases when any of the following factors is increased: • the plasma pressure, because increased plasma pressure raises the average ion energy; • the plasma source power, because increased plasma source power raises the density of ions and hence raises the flux of particles impinging on the substrate; • the plasma temperature, because increased temperature raises the average ion energy; and • the bias power applied to the substrate or substrate table, because increasing the bias power applied to the substrate increases the energy of ions colliding with the substrate. The flux of particles impinging on the substrate increases when any of the factors influencing average particle energy is increased (because more energetic particles will collide more frequently with the substrate) but also increases when the number density of particles in the plasma is increased (for example by increasing the flow rates of any of the compounds from which the plasma is generated). One example of a way of achieving a higher plasma dose in the higher-plasma-dose plasma deposition process relative to the lower-plasma-dose deposition process is to set one or more of the following parameters to a higher value in the higher-plasma-dose deposition process while holding the others constant between the higher-plasma-dose and lower-plasma-dose processes: the flow rates of any of the gases from which the plasma is generated, the plasma pressure, the plasma source power, the bias power applied to the substrate table or substrate, and the plasma exposure time. For example, the higher-plasma-dose deposition process may employ a higher plasma temperature while holding every other one of the listed factors constant, or employ a higher exposure time while holding every other one of the listed factors constant. In this approach (where one or more parameters are increased in the higher-plasma-dose process relative to the lower-plasma-dose process while the others are held constant), preferably the or each factor that is increased in the higher-plasma-dose process relative to the lower-plasma-dose process is increased by at least a factor of two. For example, the higher-plasma-dose process could employ a substrate bias and / or plasma exposure time that is twice that used in the lower-plasma-dose process while every other one of the factors listed above is held constant. In this third aspect of the invention, (a) and (b) may be performed in any order with respect to one another. While steps (a) and (b) require depositing material on at least the first surface of the substrate and the side wall of the recess respectively, the material deposited may extend to other parts of the substrate. In particular, it may be the case that material is deposited onto both the side wall of the recess and the first surface of the substrate in each of steps (a) and (b), thereby forming, in each of steps (a) and (b) a layer of material extending along the entire superconductive pathway. In some preferred embodiments, the method comprises before step (a), forming the recess. The recess may be formed by etching into the substrate using one or more plasma etching processes, for example. Alternatively the substrate may be provided with the recess already formed. In particularly preferred embodiments, forming the recess comprises: (i) forming, at least partly, the recess by etching into the first surface of the semiconductor wafer using a first plasma etching process, such that the recess extends from the first surface of the substrate, at least part-way through the substrate towards the second surface of the substrate; and then: (ii) using a second plasma etching process different from the first plasma etching process, etching the side wall of the recess so as to reduce its surface roughness. This is advantageous as smoothing the side wall improves the uniformity of the deposited material and hence also increases its crystallinity, leading to higher-quality superconductor material being formed on the side wall of the recess. The first plasma etching process could be a Bosch process, which is particularly suitable for forming deep, highly vertical features such as vias that extend some or all of the way through the substrate, but impart significant roughness to the surface (one example of which is ‘scalloping’, in the case of the Bosch process). The second plasma etching process could be a reactive ion etching process. Techniques for manufacturing vias, which are suitable for forming the recess in embodiments of all aspects of this invention, are described in United Kingdom patent application no. 2300559.8. A fourth aspect of the invention provides a method of manufacturing a superconducting structure extending at least part-way through a substrate, the substrate having opposed first and second surfaces, the method comprising, in this order: (a) using a lower-plasma-dose plasma deposition process, depositing a layer of superconductor material on at least part of the first surface of the substrate; (a’) forming a recess extending, from the first surface of the substrate, at least part-way through the substrate towards the second surface of the substrate, an edge of the via on the first surface being adjacent to the layer of superconductor material deposited on the first surface; (b) using a higher-plasma-dose plasma deposition process, depositing a layer of superconductor material on at least part of a side wall of the recess; wherein the process parameters of the deposition processes used in steps (a) and (b) are different from one another, the plasma dose delivered to the substrate in the lower-plasma-dose plasma deposition process of step (a) being lower than the plasma dose delivered to the substrate in the higher-plasma-dose plasma deposition process of step (b); whereby the layer of superconductor material deposited on the first surface of the substrate in step (a) and the layer of superconductor material deposited on the side wall of the recess in step (b) contact one another and together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess. This method differs from that provided by the third aspect of the invention in that steps (a) and (b) are required to be performed in the specific order defined above. In addition, after depositing the superconductor material on the first surface in step (a), the recess is formed in step (a’) (e.g. by etching into the substrate using a plasma etching process). The recess could be formed directly adjacent to the material deposited in step (a), or could be formed inside the area covered by the material deposited in step (a), in which case forming the recess may involve etching through the superconductor material deposited in step (a) and then into the underlying substrate material. Preferably, forming the recess in step (a’) comprises: (i) forming, at least partly, the recess by etching into the first surface of the semiconductor wafer using a first plasma etching process, such that the recess extends from the first surface of the substrate, at least part-way through the substrate towards the second surface of the substrate; and then: (ii) using a second plasma etching process different from the first plasma etching process, etching the side wall of the recess so as to reduce its surface roughness. As discussed above with reference to preferred implementations of the third aspect, this is particularly advantageous as smoothing the side wall improves the uniformity of the deposited material and hence also increases its crystallinity, leading to higher-quality superconductor material being formed on the side wall of the recess. The first plasma etching process could be a Bosch process, which is particularly suitable for forming deep, highly vertical features such as vias that extend some or all of the way through the substrate. The second plasma etching process could be a reactive ion etching process. Techniques for manufacturing vias, which are suitable for forming the recess in embodiments of all aspects of this invention, are described in United Kingdom patent application no. 2300559.8. Preferred features of methods in accordance with the third and fourth aspects of the inventions will now be introduced. In preferred embodiments: the higher-plasma-dose plasma deposition process in step (a) is a first plasma-enhanced atomic layer deposition, PEALD, process; and / or the lower-plasma-dose plasma deposition process in step (b) is a second PEALD process. Atomic layer deposition processes, including PEALD, are a class of processes in which the deposition takes place by a cycle of self-limiting steps, with each cycle forming a single atomic or molecular layer of the deposited material. The self-limiting nature of this process enables layers of extremely uniform thickness to be deposited, which is particularly beneficial for depositing material on the side walls of features such as recesses, where the rate of deposition would otherwise vary significantly across the surface in question. (For the avoidance of doubt, the “layers” of superconductor material referred to above, such as the higher-crystallinity layers and lower-crystallinity layers and the layers deposited in steps (a) and (b) described with respect to the third and fourth aspects, do not correspond to the atomic layers which are formed by a PEALD process. Each “layer” in the sense used above will typically comprise several atomic layers and so each layer could be deposited by performing several PEALD cycles under one set of process conditions.) Typically, the first PEALD process and the second PEALD process each comprise depositing the superconductor material using a plasma generated from a gas mixture comprising the superconductor material and / or a precursor thereof. In this case, the gas mixture preferably further comprises hydrogen, H2, wherein the concentration of H2 in the gas mixture may be lower in the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process. The gas mixture also preferably further comprises a noble gas, preferably argon, Ar, wherein the concentration of the noble gas in the gas mixture may be higher in the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process. Gas mixtures comprising H2 and / or a noble gas such as Ar in addition to the superconductor material have been shown to produce superconductive pathways demonstrating good superconductive properties. Alternatives to PEALD may be employed to perform the deposition in some embodiments, in particular for deposition onto the first surface of the substrate. Suitable alternative deposition processes include chemical vapour deposition (CVD) and physical vapour deposition (PVD). The substrate may be exposed to the plasma for a greater period of time during the higher-plasma-dose plasma deposition process than during the lower-plasma-dose plasma deposition process. Since the plasma dose depends on the time to which the substrate is exposed to the plasma, the plasma dose delivered in the higher-plasma-dose plasma deposition process relative to the lower-plasma-dose plasma deposition process can be increased by increasing its duration. Preferably, the substrate is disposed on a substrate table during step (a) and (b) and wherein a bias voltage is applied to the substrate table during step (a) and / or step (b). Applying a bias voltage is advantageous as this enables a further degree of control over the energy of the ions incident on the surfaces of the substrate, thereby providing improved control over the density of the deposited material. The power of the bias voltage may be higher in the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process. As discussed above, the energy of ions in the plasma (and hence the plasma dose) can be controlled by adjusting the power supplied to the plasma source with which the plasma is generated. Therefore, preferably, in each of the higher-plasma-dose plasma deposition process and the lower-plasma-dose plasma deposition process, the superconductor material is deposited using a plasma generated using plasma source, wherein the plasma source may be supplied with a higher power during the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process. The plasma source may be an inductively-coupled plasma source (ICP), but other high-density plasma sources may also be used. In some preferred embodiments, the superconductor material deposited in step (b) extends onto the first surface of the substrate and overlaps the superconductor material deposited on the first surface of the substrate in step (a), wherein preferably the method further comprises, after step (b), etching into the superconductor material on the first surface of the substrate so as to remove some, preferably all, of the superconductor material deposited on the first surface of the substrate in step (b). As discussed previously, steps (a) and (b) may each be performed such that the material deposited in each of these steps extends onto both of the side wall of the recess and the first surface of the substrate. Material deposited on the first surface of the substrate in step (b) (which will typically form a lower-crystallinity layer of the layer stack on the first surface) can be removed in the manner described above (e.g. using a plasma etching process) to reduce the thickness of the superconductor material coating on the first surface without losing the higher-quality superconductor material on that surface. In some preferred embodiments, the superconductor material deposited in step (a) extends onto the sidewall of the recess and overlaps the superconductor material deposited on the side wall of the via in step (b). Preferably, the method further comprises: performing one or more repetitions of the higher-plasma-dose plasma deposition process so as to form, on at least the sidewall of the recess, a corresponding number of additional layers of the superconductor material; and / or performing one or more repetitions of the lower- plasma-dose plasma deposition process so as to form, on at least the first surface of the substrate, a corresponding number of additional layers of the superconductor material. Most preferably: the additional layer or layers of the superconductor material deposited by the one or more repetitions of the higher-plasma-dose plasma deposition process extend onto the first surface of the substrate and overlap the superconductor material deposited on the first surface of the substrate in step (a); and / or the additional layer or layers of the superconductor material deposited by the one or more repetitions of the lower-plasma-dose plasma deposition process extend onto the sidewall of the recess and overlap the superconductor material deposited on the sidewall of the recess in step (b). In this way, stacks of higher-crystallinity and lower-crystallinity layers as described above with reference to the first aspect may be formed. Preferably, the order of the layers in any such layer stacks produced in embodiments of the third and fourth aspects is alternating, and if such stacks are present on both the first surface and the side wall, preferably the orders of the stacks are inverted with respect to one another. BRIEF DESCRIPTION OF THE DRAWINGS Examples of superconducting structures and methods in accordance with embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows an example of a superconducting structure in accordance with an embodiment of the first aspect of the invention; Figure 2 is a flow diagram showing an example of a method in accordance with the second aspect of the invention; Figure 3 is a flow diagram showing an example of a method in accordance with the third aspect of the invention; Figure 4 is a flow diagram showing an example of a method in accordance with the fourth aspect of the invention; Figures 5Ato 5D shows a substrate during steps of the method illustrated in Figure 4; Figures 6 and 7 are scanning electron microscope images showing parts of a superconducting structure manufactured in accordance with an embodiment of the second and third aspects of the invention; Figure 8 shows measurements of the resistivity and stress of layers of superconductor material; Figure 9 shows x-ray diffraction measurements of a sample of superconductor material; and Figure 10 is the electron diffraction pattern of a sample of superconductor material. DETAILED DESCRIPTION Figure 1 shows an example of a superconducting structure 100 in accordance with an embodiment of the invention. Shown in Figure 1 is a cross-sectional view of a substrate 101 through which the superconducting structure extends. The substrate 101 in this example is a silicon (or other semiconductor) wafer having the general form of a disc that lies in the plane of the X and Y directions shown in Figure 1 (and therefore oriented perpendicular to the Z direction). In other embodiments, the substrate 101 could be formed of one or more other materials, such as ceramics (e.g. AI2O3 (sapphire)), glass (e.g. SiO2) or organic materials (e.g. a polymer such as an epoxy resin-based laminate). The disc has a first surface 102 and a second surface 104 opposed to the first surface 102. Extending through the wafer 101 along the Z direction, from the first surface 102 to the second surface 104, is a via 103 (a kind of recess), which has a side wall 105. The via 103 has the general form of a cylinder with its axis aligned with the Z direction. A superconductor material coating covers at least part of the first surface 102 and the side wall 105 of the via 103. Typically the superconductor material has been deposited along a deposition direction substantially parallel to the z-axis shown in Figure 1 (or within a low angle of that axis, e.g. within 60 degrees of the z-axis). The coating comprises a first plurality (or “stack”) of layers 110, which are deposited on the first surface of the wafer 101 and include two higher-crystallinity layers 111,113 and a lower-crystallinity layer 112 ordered in an alternating fashion. The coating also includes a second plurality (or stack) of layers 120, which is deposited on the side wall 105 of the via 103 and comprises two lower-crystallinity layers 121 and 123 and one higher-crystallinity layer 122. It can be seen that the higher-crystallinity layers 111, 113 of the first stack 110 are in direct contact with the higher-crystallinity layer 122 of the second stack 120. The higher-crystallinity layers of the two stacks 110,120 thus form a continuous superconductive pathway extending from the first surface 102 along the side wall 105 of the via 103. In this example, the superconductive pathway extends along the full extent of the via 103. Inaddition, a(optional) Iayer131 ofthe superconductor material is deposited on the second surface 104 ofthe wafer 101, and the higher-crystallinity layer 122 on the side wall 105 is in contact with this layer 131. The superconductive pathway thus extends onto the second surface 104 of the wafer 101 in this example. In this example, the superconductor material layer 131 on the second surface 104 was deposited using a plasma deposition process optimised for the second surface 104 such that the crystallinity of this material is comparable to that ofthe higher-crystallinity layers 111, 113 of the first stack 110. If the layer 131 is deposited after the via 103 is formed, this will typically result in a further lower-crystallinity layer (not shown) being deposited on the sidewall of the via. The orders of the alternating sequences of layers in the first stack 110 and the second stack 120 are “inverted” with respect to one another, meaning that the first layer in the first stack 110 is a higher-crystallinity layer while the first layer in the second stack 120 is a lower-crystallinity layer 121, the next layer 112 in the first stack 110 is lower-crystallinity and the next layer 122 in the second stack 120 is higher-crystallinity, and so on. It should be appreciated that in other examples each stack 110, 120 could have a (plural) number of layers other than three, and the number of layers in each respective stack may or may not be the same. Figure 2 is a flow diagram illustrating an example of a method manufacturing a superconducting structure in accordance with an embodiment of the second aspect of the invention. At step 201, a substrate having a first surface and an opposing second surface (such as the wafer 101 shown in Figure 1) is provided. The substrate may at this point have a recess already formed in it, but if the recess that is to form part of the superconducting structure is not yet formed, the method may optionally (as indicated by dashed lines) include a step 202 of forming a recess in the substrate, the recess extending from the first surface at least partway through the substrate towards the second surface. Then, in step 203, a superconductor material coating with the structure described above with reference to Figure 1 is deposited. The superconductor material is thus deposited such that the coating extends continuously across a region comprising part of the first surface and at least part of the side wall of the recess. The deposition comprises depositing on each of the side wall and the first surface: a respective plurality (stack) of layers overlapping one another, the plurality of overlapping layers comprising at least one higher-crystallinity layer of the superconductor material and at least one lower-crystallinity layer of the superconductor material, one or more of the higher-crystallinity layers contacting the superconductor material on the other of the side wall and the first surface such that said one or more higher-crystallinity layers and the superconductor material on the other of the side wall and the first surface together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess. Figure 3 is a flowchart showing an example of a method in accordance with an embodiment of the third aspect of the invention, which will be described with reference to the structure shown in Figure 1. At step 301, a substrate 101 having a first surface and an opposing second surface (such as the wafer 101 shown in Figure 1) is provided. The substrate may at this point have a recess such as the via 103 already formed in it, but if the recess that is to form part of the superconducting structure is not yet formed, the method may optionally (as indicated by dashed lines) include a step 302 of forming a recess in the substrate, the recess extending from the first surface at least part-way through the substrate towards the second surface. After steps 301 and 302, a lower-dose plasma deposition process and a higher-plasma-dose plasma deposition process are performed in steps 303 and 304. It should be noted that, while step 303 takes place before step 304 in this example, these steps may be performed in any order with respect to one another. In general, in step 303, the lower-plasma-dose plasma deposition process is performed such that the superconducting material is deposited on at least the first surface of the substrate 101. In this example, however, the lower-plasma dose plasma deposition step is performed such that the superconductor material is deposited on the side wall 105 of the via 103 in addition to the first surface 102. Typically the deposition steps 303, 304 will be using a plasma processing tool in which the substrate 101 is placed on a substrate table (with the second surface 104 facing towards the substrate table and the first surface 102 facing away from the substrate table and towards the plasma). Thus, as noted above, the deposition direction may typically be approximately parallel to the normal of the substrate 101 (the z-axis). Typically, each of the lower-plasma-dose and higher-plasma-dose plasma deposition processes will deposit material onto both the first surface 102 and the side wall 105 unless the deposition is controlled and / or the substrate arranged in such a way that prevents material being deposited onto both surfaces (e.g. by provision of a mask preventing deposition onto some regions). In this example, the lower-plasma-dose plasma deposition process performed in step 303, which is optimised for depositing material onto the first surface 102, deposits the first higher-crystallinity layer 111 on the first surface 102 and the first lower-crystallinity layer on the side wall 103. The higher-plasma-dose plasma deposition process then deposits the higher-crystallinity layer 122 of the second stack 120 and the lower-crystallinity layer 112 of the first stack on top of the layers formed previously. This results in the higher-crystallinity layers 111 and 122 being in direct contact with one another and thus forming a superconductive electrical pathway extending along the side wall 103 and onto the first surface 102. Optionally, each of the higher-plasma-dose plasma deposition process and lower-plasma-dose plasma deposition process may be performed more than once. Where this is the case, the two processes are preferably performed in an alternating manner so that the stacks of layers on each of the first surface 102 and side wall 105 have the alternating sequences described above (and are preferably inverted in order relative to one another, as was also described above). For example, in the example shown in Figure 1, each of the layer stacks 110, 120 includes a third layer formed by repeating the lower-plasma-dose plasma deposition process, thereby forming a second higher-crystallinity layer 113 in the first stack 110 and a second lower-crystallinity layer 123 in the second stack 120. Figure 4 is a flowchart showing an example of a method in accordance with an embodiment of the fourth aspect of the invention. Like the previous embodiments, the first step 401 in this method is providing the substrate 501. Unlike the methods of Figures 2 and 3, however, in this method, the recess which will form part of the superconducting structure is always not present in this initial step 401. The substrate during step 501 is shown in Figure 5A: the substrate here has a first surface 502 and an opposing second surface 504, but the recess has not yet been formed. At step 402, while the recess is still not yet formed, the lower-plasma-dose plasma deposition process is performed so as to form a layer 511 of the superconductor material on the first surface 102 of the substrate 101. Figure 5B shows the substrate 501 after performing the lower-plasma-dose plasma deposition process in step 402. After step 402, in step 403, the recess is formed, for example by plasma etching into the substrate through the layer of superconductor material that was deposited in step 402. The resulting structure is shown in Figure 5C: it can be seen that the superconductor material 511 extends to the edges of the recess 503. After forming the recess in step 403, in step 404, the higher-plasma-dose plasma deposition process is performed so as to deposit a layer of the superconductor material 521 on at least the side wall 505 of the recess 503 - and in this case also on the first surface 502, resulting in a layer 512 on the first surface overlapping the layer 511 formed prior to forming the via 503. This is shown in Figure 5D. The layer 512 that overlaps the first layer 511 on the first surface 502 is of lower crystallinity than the first layer 511 because it was deposited by the higher-plasma-dose plasma deposition process, which is optimised for deposition onto the side wall 505 rather than the first surface 502. The layers 511 and 521 thus form a superconductive pathway extending from the first surface 502 along the side wall 505. Optionally, the second layer 512 could be removed (e.g. by etching) after being deposited, leaving only the layers 511 and 521 on the first surface 502 and side wall 505 respectively. It will be noted that the resulting structure has only one “stack”, i.e. that formed by layers 511 and 512, rather than two. The superconducting coating is formed by that stack together with the single layer 505. A specific example of a method which was performed in accordance with an embodiment of the second and third aspects of the invention will now be described and the results that were obtained will be presented. A silicon wafer with opposed first and second surfaces was provided. Formed in the silicon wafer was a via extending from the first surface, in the direction perpendicular to the first surface, part-way through the wafer towards the second surface. Three plasma-enhanced atomic layer deposition (PEALD) processes were performed in sequence to form a coating of niobium nitride (NbN) extending from the first surface along the side wall of the via, in the following order. Each PEALD process deposited material across the same continuous region, which comprised part of the first surface and the side wall of the via. The first PEALD process was controlled so as to deliver a first plasma dose, the parameters of which were chosen to optimise deposition onto the side wall of the via. Next, a second PEALD process was performed to deliver a lower plasma dose than the first PEALD process. After the second PEALD process, the third PEALD process was performed so as to deliver approximately the same plasma dose as the first PEALD process. Therefore, the first and third PEALD processes were higher-plasma-dose plasma deposition processes and the second PEALD process was a lower-plasma-dose plasma deposition process. During each PEALD process, several ALD cycles were performed such that each PEALD process formed a layer of superconductor material several atoms thick and extending continuously across the region defined above. The parameters used during the three PEALD processes are listed in Table 1 below. In these PEALD processes, the NbN was deposited from a precursor compound, which in this example was (T-Butylimido)tris(diethylamino)niobium(V), (TBTDEN). The precursor compound was delivered in a plasma generated from 5 a gas mixture that also included H2 and Ar. The plasma was generated and sustained using an inductively coupled plasma source (ICP). The wafer was placed on a substrate table to which a radio frequency (RF) bias was applied during the deposition. To achieve a higher plasma dose in the higher-plasma-dose PEALD processes, the plasma source power, RF bias power and exposure 10 time were used in these processes were higher than the corresponding parameters in the lower-plasma-dose PEALD process. The difference in plasma dose between the lower-plasma-dose and higher-plasma-dose processes in this example was further enhanced by the use of higher flow rates of H2 and Ar and increased pressure in the higher-plasma-dose process. 15 Parameter Lower-plasma-dose PEALD process Higher-plasma-dose PEALD processes H2 flow rate (seem) 40 100 Ar flow rate (seem) 10 100 Pressure (millitorr, mTorr) 20 500 Plasma source power (Watts, W) 100 600 Temperature (degrees Celsius, °C) 250 250 RF bias power (W) 25 50 Plasma exposure time (seconds, s) 5 10 TABLE 1 As discussed above, in general, a higher plasma dose in the higher-plasma-dose process can be ensured by making any one of the parameters that influence the average particle energy or particle density, or the exposure time, greater while 5 holding all other factors constant. Therefore, in an alternative approach to the process detailed in Table 1, the higher-plasma-dose process could be configured such that all but one of the parameters listed in Table 1 are the same in both the higher-plasma-dose process and the lower-plasma-dose process - for example such that the higher-plasma-dose process involves a plasma exposure time of 10s 10 while the plasma exposure time in the lower-plasma-dose deposition process is 5s. Figure 6 is a scanning electron microscope (SEM) image showing the side wall 605 of the via after performing the three PEALD processes described above, with the material of the silicon wafer 601 being visible in the lower part of the image. The structure was cut away before producing this image to reveal the layer structure of the deposited superconductor material. Since the first and third PEALD process was a higher-plasma-dose plasma deposition process configured to form highly crystalline material on the side wall 605 of the via, the first and third layers 621, 623 in this stack 620 are of higher crystallinity than the second layer 622, which was deposited by the lower-plasma-dose PEALD process. Figure 7 is an SEM image showing another part of the superconducting structure shown in Figure 6. This image shows a region of the first surface 602 of the wafer adjacent to the opening of the via, with part of the via side wall 605 and the superconductor material deposited thereon being visible in the right-hand region of the image. Like that on the side wall 605, the superconductor material on the first surface 602 is composed of a stack 610 of three layers 611,612, 613 formed by the three PEALD processes. The first and third layers 611, 613 contain the material deposited by the first and third higher-plasma-dose PEALD processes, so these layers are of lower crystallinity than the second layer 612, which was formed by the lower-plasma-dose PEALD process configured to favour the formation of good quality material on the first surface 602. In the region shown, the higher-crystallinity layers 621, 623 on the side wall 605 contact the higher-crystallinity layer on the first surface 602. This results in the higher-crystallinity layers 621, 623, 612 forming a superconductive pathway that extends from the first surface 602 along the side wall 605 of the via. An example of a way in which the optimum plasma dose for depositing the superconductor material onto any given surface, such as the first surface of a substrate or the side wall of a recess formed in the substrate, will now be described. As has been explained above, the quality (i.e. crystallinity) of superconductor material deposited on the surfaces of the substrate by methods in accordance with the invention depends on the plasma dose that is delivered during the deposition process, and the optimum plasma dose differs between the main, ‘horizontal’ surfaces of the wafer (i.e. its first and second surfaces) and the side walls of recesses (e.g. the side wall of a via extending through the substrate). The plasma dose depends, among other things, on the energy of the ions incident no the surface in question, and one way in which this energy (and hence the plasma dose) can be controlled is by selecting the RF bias power applied to the substrate table during the deposition. To identify the RF bias power value that optimised deposition onto the first surface of a silicon wafer, depositions of NbN onto the surfaces of several wafers were carried out using a PEALD process in which the NbN was delivered using a plasma generated from a gas mixture comprising H2 and Ar, like the depositions that formed the superconductor material coating shown in Figures 6 and 7. A different RF bias power was applied to the substrate table in each deposition, but all other process parameters (those listed in the first column on Table 1, excluding RF bias power) were held constant. For each wafer, the resistivity of the resulting layer of superconductor material at room temperature (in units of micro-ohm cm, pQ cm) and the residual stress of the film (in units of megapascal, MPa) were measured. The results of these measurements are shown in Figure 8. It can be seen that the variation of resistivity and residual stress with different bias power exhibited a good correlation. Both achieved extremum at a bias power of about 13 W. These measurements were taken as an indication that the optimum quality (i.e. crystallinity) for a surface with its normal approximately parallel to the deposition direction (or within a small of it, e.g. less than 60 degrees) was achieved by the plasma dose corresponding about 13 W RF bias power under the set of process parameters that was used. To confirm this, an x-ray diffraction (XRD) analysis was performed for a sample of NbN deposited under these conditions, the results of which are shown in Figure 9. The XRD data show sharp, narrow peaks, indicating a highly crystalline structure in the deposited NbN, and are in good agreement with reference data available for high-Tc NbN with a lattice parameter of 0.446 nm. Rietvald refinement carried out on these data indicated the presence of a small amount of NbC formed during the deposition, though the level was sufficiently low that it did not significantly degrade the film quality. The example just described with reference to Figure 8 identified the optimum bias power for deposition onto a ‘horizontal’ surface (i.e. the first surface of the substrate). The same approach could be used to identify the optimum for deposition onto the side wall of a recess - i.e. by repeating the process described above, but by depositing layers of superconductor material onto the sidewalls of a set of recess (e.g. vias) under different bias powers and determining which bias power produced the lowest-resistivity material. Alternatively, having identified the optimum bias power for deposition onto the horizontal surface, the bias power for deposition onto the side wall could be selected simply by choosing a higher bias power than that which is to be used for the horizontal deposition (thereby increasing the plasma dose of the side wall deposition process relative to that used for deposition onto the first surface). To confirm further the quality of the NbN deposited under these conditions, electron diffraction measurements of a film deposited under the same conditions were taken. The measured diffraction pattern in shown in Figure 10. The presence of bright, distinct spots again indicates a highly uniform crystalline structure. Further measurements of higher-crystallinity layers (specifically, layers deposited on the first surfaces of wafers using the lower-plasma-dose process of Table 1, which is optimised for deposition onto the first surface) and lower-crystallinity layers (specifically, layers deposited on the first surfaces of wafers using the higher-plasma-dose process of Table 1, which is optimsed for deposition onto the side walls of recesses rather than onto the first surface) were taken to further characterise the differences between these layers. It was found that the stress, room temperature resistivity, and transition temperatures, Tc, of these layers typically fell into the ranges presented in Table 2. The higher-crystallinity layers exhibited high transition temperatures and lower room temperature resistivity than the lower-crystallinity layers. Property Higher-crystallinity Lower-crystallinity Stress (gigapascals, GPa) 2-3 <1 Resistivity (micro-ohm centimetres, pQ cm) <200 >250 TC(K) > 10 < 3 TABLE 2 While it is preferred that PEALD is for depositing all of the superconductor material in embodiments of the invention, alternative processes may be used, particularly for deposition onto the first and second surfaces of the substrate, such as in the 5 lower-plasma-dose plasma deposition process. An example of a plasma-enhanced chemical vapor deposition (PECVD) process suitable for implementing the lower-plasma-dose plasma deposition process deposits NbN using a precursor from the family of compounds NbClx, for example NbCIs, evaporated and delivered to the substrate in a plasma generated from NH3 10 or a mixture of H2 and N2. This process may be implemented using the following parameters: • NbCIs precursor evaporated at 65°C. • Pressure in the range of 0.1-5 Torr, preferably 1-5 Torr. • RF bias in the range of 200-500W, preferably about 300 W. 15 • Plasma temperature in the range of 250-600°C, preferably about 400°C. An example of a physical vapour deposition process suitable for implementing the lower-plasma-dose plasma deposition process deposits NbN sputtered, using a magnetron, from a solid target and delivered to the substrate in a plasma generated from a mixture of Ar and N2. The process may be implemented using the following parameters: • Pressure in the range of 1-10 mTorr, preferably 3-5 mTorr. • N2 flowed at a rate of 0.1-10 seem, preferably 0.5-1 seem, with the Ar flow rate adjusted to maintain the desired pressure. • Magnetron power in the range of 100-3000 Wcontinuous wave (CW), DC or RF, preferably DC or RF in the range 100-300 W. • Temperature in the range of 0-300°C, preferably about room temperature. As discussed above, some embodiments of the invention involve forming the recess, which in many scenarios will be a via extending part-way or fully through the wafer. As has already been noted, the via or other recess in such embodiment may be formed by a two-step process comprising: (i) forming, at least partly, the recess by etching into the first surface of the semiconductor wafer using a first plasma etching process, such that the recess extends from the first surface of the substrate, at least part-way through the substrate towards the second surface of the substrate; and then: (ii) using a second plasma etching process different from the first plasma etching process, etching the side wall of the recess so as to reduce its surface roughness. Examples of such processes, which are suitable for implementing all embodiments of the invention in which forming the via constitutes a step, will now be discussed. These features, their advantages and detailed embodiments thereof are also discussed in United Kingdom patent application no. 2300559.8. The method further comprise: before step (i), providing the substrate, the substrate having a deposited layer (which may be an epitaxial layer but could be some other kind of deposited layer, for example a layer of an amorphous compound) on the second surface thereof, and wherein the deposited layer is present on the second surface of the substrate during step (i), preferably also in step (ii); and after step (i), if the deposited layer is not a superconducting deposited layer, removing the deposited layer from the second surface of the substrate. The deposited layer here is on the second surface of the substrate - i.e. the surface opposite the first surface, into which the via is etched in step (i). The presence of this deposited layer during step (i) can be beneficial for two main reasons: firstly, a cooling gas such as helium can be applied to the underside of this layer during the etching in step (i) to control the temperature of the wafer (thereby enabling improved control over the etching) and, secondly, it helps to prevent the material of the wafer rupturing when the via breaks through the second surface. The deposited layer may remain in place for step (ii), in which case it may again be used for cooling the wafer by application of a cooling gas. The deposited layer will however ultimately be removed (at any time after step (i), or, if it is present in step (ii), any time after step (ii)). In embodiments in which the deposited layer just described is present, the method preferably further comprises comprising applying a cooling gas, preferably helium, to the deposited layer during the etching in step (i), preferably also in step (ii). The deposited layer may advantageously be formed of silicon dioxide (SiO2) (which may be deposited on the second surface of the substrate). This material is suitable for cooling the substrate by application of a cooling gas and can easily be removed, e.g. by reactive ion etching. It also has a high selectivity to Si etching - in other words, a process used to etch a via through a substrate made of Si will etch the SiO2 layer much more slowly, which helps to ensure that the etching stops at the SiO2 layer. Other materials with high selectivity to Si etching could also be used for forming this deposited layer. The via may be formed completely in step (i). However, in some preferred embodiments, the via is formed partly in step (i), and the formation of the via is completed in a further step (iii). Completing the formation of the via in step (iii) may comprise removing material from the second surface of the substrate. The formation of the via is thus completed once material has been removed from the second surface of the substrate, in step (iii), such that the via opens onto the second surface (from which the material has been removed). For example, in step (i), the via may be etched such that it extends only part-way through the substrate (and therefore opens onto the first surface, but not onto the second surface, immediately after step (i)). Preferably the removal of material in step (iii) is substantially uniform across the second surface of the substrate, thereby thinning the substrate. In these embodiments, the formation of the via is completed in step (iii) when the substrate has been thinned to the point at which the second surface meets the base of the etched via. Where material is removed from the second surface in step (iii), preferably the removal of material in step (iii) is performed by plasma etching. For example, where the substrate is thinned in the manner just described, the etch could be an all-over etch (or ‘blanket etch’). Alternatively, material could be removed by chemical mechanical polishing (CMP) or wet etching. The method may further comprise, after partly forming the via in step (i) and before completing the formation of the via in step (iii), bonding a support substrate onto the first surface of the substrate. Most preferably, the support substrate is bonded to the substrate after any deposition of superconductor material onto the side wall of the recess that is required has been completed. The support substrate could be another substrate, for example. Bonding a support substrate to the substrate in this manner can be advantageous as it allows the second side of the substrate to be processed (e.g. by etching) while protecting the first surface (and the deposited superconductor material, if present). For example, advantageously, step (iii) may be performed while the substrate is bonded to the support substrate; in which case the method preferably further comprises separating the support substrate from the substrate after step (iii). It will be appreciated that the support substrate is not necessarily in direct contact with the second surface of the substrate when bonded to it - for example, there could be other structures and / or layers on the second surface (e.g. additional superconductor material on the second surface surrounding the opening of the via onto that surface), which will be between the support substrate and the substrate when the two are bonded together. In some preferred embodiments, the first plasma etching process is a Bosch process or a cryo etching process. The Bosch process is particularly preferred since it allows rapid etching of deep vias with highly vertical side walls. Cryo etching processes are particularly effective for etching vias in comparatively thin substrates, e.g. those with a thickness of 300 pm or less. By “cryo etching” we mean plasma etching in which the substrate being etched is cooled to cryogenic temperatures during the etching. Preferably the second plasma etching process is a reactive ion etching process. Reactive ion etching processes are particularly suitable for smoothing vertical features such as the walls of the via etched in step (i). Alternative processes suitable for this step include ion beam etching or ion beam milling. Advantageously, the second plasma etching process may comprise etching the wall of the substrate using a plasma generated from a gas mixture that comprises: at least one fluorine-bearing gas, more preferably at least one of CF4, SF6 and NF3; and / or at least one of Ar, 02 and H2. By “fluorine-bearing gas” we mean a compound that releases fluorine radicals when present in a plasma, and CF4, SF6 and NF3 are examples of compounds that exhibit this property. CF4 is particularly preferred for this purpose, particularly where the second plasma etching process is a reactive ion etching process. Preferably the second plasma etching process is performed at a pressure in the range of 1 mTorr to 500 mTorr, preferably about 10 mTorr. These values have been found to achieve good smoothing of the wall of the via. Preferably, in step (ii), the substrate is arranged on a substrate table while the second plasma etching process is being performed. A bias voltage can be applied to such a table to increase the energy of ions colliding with the substrate, thereby affording improved control over the etching. Hence, preferably, an RF bias is applied to the substrate table during the second plasma etching process, wherein preferably: the RF bias has a value (in other words, generates a DC offset) in the range of 5 V to 1500 V, preferably about 400 V; and / or the power of the applied RF bias is in the range of 5 W to 1500 W, preferably about 100 W These values of bias voltage and bias voltage power (particularly when applied in combination) have been found to achieve good results in reasonable time. Preferably in the second plasma etching process, the plasma used to etch the wall of the substrate is generated using an inductively-coupled plasma source (ICR also sometimes referred to as a transformer couple plasma source, TCP) or an electron cyclotron resonance (ECR) plasma source, preferably at a power in the range of 100 W to 5000 W. The plasma could alternatively be generated using a capacitively-coupled plasma source, however.

Claims

1. A superconducting structure extending at least part-way through a substrate, the substrate comprising:a planar first surface and a planar second surface opposed to the first surface; anda recess formed in the substrate, the recess having a side wall extending from the first surface at least part-way through the substrate towards the second surface; and the superconducting structure comprising:a superconductor material coating extending continuously across a region comprising part of the first surface and at least part of the side wall of the recess, the superconductor material coating comprising, on at least one of the side wall and the first surface:a plurality of layers overlapping one another, the plurality of overlapping layers comprising at least one higher-crystallinity layer of the superconductor material and at least one lower-crystallinity layer of the superconductor material, one or more of the higher-crystallinity layers contacting the superconductor material on the other of the side wall and the first surface such that said one or more higher-crystallinity layers and the superconductor material on the other of the side wall and the first surface together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess.

2. The superconducting structure of claim 1, wherein the superconductor material coating comprises, on each of the side wall and the first surface, a respective plurality of layers overlapping one another, each plurality of overlapping layers comprising at least one higher-crystallinity layer of the superconductor material and at least one lower-crystallinity layer of the superconductor material, wherein one or more of the higher-crystallinity layers on the side wall each contact one or more of the higher-crystallinity layers on the first surface.

3. The superconducting structure of any preceding claim, wherein, on the first surface of the substrate and / or the side wall of the recess, the overlappinghigher-crystallinity layers and lower-crystallinity layers are layered in an alternating manner.

4. The superconducting structure of claim 3, wherein the overlapping higher-crystallinity layers and lower-crystallinity layers are layered in an alternating manner on each of the first surface of the substrate and the side wall of the recess, and the order of the higher-crystallinity layers and lower-crystallinity layers on the first surface is inverted relative to the order of the higher-crystallinity layers and lower-crystallinity layers on the side wall of the recess.

5. The superconducting structure of any preceding claim, wherein on the first surface of the substrate and / or the side wall of the recess, the plurality of layers comprises at least three layers.

6. The superconducting structure of any preceding claim, wherein the superconductor material is NbN, TiN, TaN, or a mixture thereof.

7. The superconducting structure of any preceding claim, wherein the transition temperature, Tc, of the superconductive pathway is at least 3 K.

8. The superconducting structure of any preceding claim, wherein the substrate comprises or consists of any one or more of:semiconductor material(s), preferably silicon;glass material(s), preferably SiO2;organic material(s), preferably a polymer; and ceramic material(s), preferably AI2O3 or AIN.

9. The superconducting structure of any preceding claim, wherein the thickness of the superconductor material coating is at all points less than 5 pm, preferably less than 1 pm, more preferably less than 500 nm, more preferably less than 200 nm.

10. The superconducting structure of any preceding claim, wherein the recess is a via extending all the way through the substrate from the first surface to the second surface.

11. The superconducting structure of claim 10, wherein the superconductive pathway extends all the way along the side wall of the via and preferably onto the second surface.

12. A method of manufacturing a superconducting structure extending at least part-way through a substrate, the substrate having a planar first surface, a planar second surface opposed to the first surface, and a recess formed in the substrate, the recess having a side wall extending from the first surface at least part-way through the substrate towards the second surface, the method comprising:depositing a superconductor material coating extending continuously across a region comprising part of the first surface and at least part of the side wall of the recess, the deposition comprising depositing on at least one of the side wall and the first surface:a plurality of layers overlapping one another, the plurality of overlapping layers comprising at least one higher-crystallinity layer of the superconductor material and at least one lower-crystallinity layer of the superconductor material, one or more of the higher-crystallinity layers contacting the superconductor material on the other of the side wall and the first surface such that said one or more higher-crystallinity layers and the superconductor material on the other of the side wall and the first surface together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess.

13. A method of manufacturing a superconducting structure extending at least part-way through a substrate, the substrate having opposed first and second surfaces and a recess extending from the first surface at least part-way through the substrate towards the second surface, the method comprising, in any order:(a) using a lower-plasma-dose plasma deposition process, depositing a layer of a superconductor material on the first surface of the substrate at least adjacent to an edge of the recess on the first surface;(b) using a higher-plasma-dose plasma deposition process, depositing a layer of the superconductor material on at least part of a side wall of the recess;wherein the process parameters of the deposition processes used in steps (a) and (b) are different from one another, the plasma dose delivered to the substrate in the lower-plasma-dose plasma deposition process of step (a) being lower than the plasma dose delivered to the substrate in the higher-plasma-dose plasma deposition process of step (b);whereby the layer of the superconductor material deposited on the first surface of the substrate in step (a) and the layer of the superconductor material deposited on the side wall of the recess in step (b) contact one another and together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess.

14. The method of claim 13, further comprising, before step (a), forming the recess.

15. The method of claim 14, wherein forming the recess comprises:(i) forming, at least partly, the recess by etching into the first surface of the semiconductor wafer using a first plasma etching process, such that the recess extends from the first surface of the substrate, at least part-way through the substrate towards the second surface of the substrate; and then:(ii) using a second plasma etching process different from the first plasma etching process, etching the side wall of the recess so as to reduce its surface roughness.

16. A method of manufacturing a superconducting structure extending at least part-way through a substrate, the substrate having opposed first and second surfaces, the method comprising, in this order:(a) using a lower-plasma-dose plasma deposition process, depositing a layer of superconductor material on at least part of the first surface of the substrate;(a’) forming a recess extending, from the first surface of the substrate, at least part-way through the substrate towards the second surface of the substrate, an edge of the via on the first surface being adjacent to the layer of superconductor material deposited on the first surface;(b) using a higher-plasma-dose plasma deposition process, depositing a layer of superconductor material on at least part of a side wall of the recess;wherein the process parameters of the deposition processes used in steps (a) and (b) are different from one another, the plasma dose delivered to the substrate in the lower-plasma-dose plasma deposition process of step (a) being lower than the plasma dose delivered to the substrate in the higher-plasma-dose plasma deposition process of step (b); whereby the layer of superconductor material deposited on the first surface of the substrate in step (a) and the layer of superconductor material deposited on the side wall of the recess in step (b) contact one another and together form a superconductive pathway electrically connecting the first surface of the substrate and the side wall of the recess.

17. The method of claim 16, wherein forming the recess in step (a’) comprises:(i) forming, at least partly, the recess by etching into the first surface of the semiconductor wafer using a first plasma etching process, such that the recess extends from the first surface of the substrate, at least part-way through the substrate towards the second surface of the substrate; and then:(ii) using a second plasma etching process different from the first plasma etching process, etching the side wall of the recess so as to reduce its surface roughness.

18. The method of any of claims 13 to 17, wherein the higher-plasma-dose plasma deposition process and the lower-plasma-dose plasma deposition process each comprise using a plasma generated from a gas mixture comprising the superconductor material and / or a precursor thereof, wherein a greater quantity of one or more, preferably all, of the gases in the gas mixture is supplied during the higher-plasma-dose plasma deposition process than during the lower-plasma-dose plasma deposition process.

19. The method of any of claims 13 to 18 wherein:the higher-plasma-dose plasma deposition process in step (a) is a first plasma-enhanced atomic layer deposition, PEALD, process; and / orthe lower-plasma-dose plasma deposition process in step (b) is a second PEALD process.

20. The method of claim 19, wherein the first PEALD process and the second PEALD process each comprise depositing the superconductor material using a plasma generated from a gas mixture comprising the superconductor material and / or a precursor thereof.

21. The method of claim 20, wherein the gas mixture further comprises hydrogen, H2, wherein optionally the concentration of H2 in the gas mixture is lower in the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process.

22. The method of claim 20 or 21, wherein the gas mixture further comprises a noble gas, preferably argon, Ar, wherein optionally the concentration of the noble gas in the gas mixture is higher in the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process.

23. The method of any of claims 13 to 22, wherein the substrate is exposed to plasma for a greater period of time during the higher-plasma-dose plasma deposition process than during the lower-plasma-dose plasma deposition process.

24. The method of any of claims 13 to 23, wherein the substrate is disposed on a substrate table during step (a) and (b) and wherein a bias voltage is applied to the substrate table during step (a) and / or step (b).

25. The method of claim 24, wherein the power of the bias voltage is higher in the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process.

26. The method of any of claims 13 to 25, wherein in each of the higher-plasma-dose plasma deposition process and the lower-plasma-dose plasma deposition process, the superconductor material is deposited using a plasma generated using plasma source, wherein preferably the plasma source is suppliedwith a higher power during the higher-plasma-dose plasma deposition process than in the lower-plasma-dose plasma deposition process.

27. The method of claim 26, wherein the plasma source is an inductively-coupled plasma source.

28. The method of any of claims 13 to 27, wherein the superconductor material deposited in step (b) extends onto the first surface of the substrate and overlaps the superconductor material deposited on the first surface of the substrate in step (a), and wherein preferably the method further comprises, after step (b), etching into the superconductor material on the first surface of the substrate so as to remove some, preferably all, of the superconductor material deposited on the first surface of the substrate in step (b).

29. The method of any of claims 13 to 28, wherein the superconductor material deposited in step (a) extends onto the sidewall of the recess and overlaps the superconductor material deposited on the side wall of the via in step (b).

30. The method of any of claims 13 to 29, further comprising:performing one or more repetitions of the higher-plasma-dose plasma deposition process so as to form, on at least the sidewall of the recess, a corresponding number of additional layers of the superconductor material; and / or performing one or more repetitions of the lower-plasma-dose plasma deposition process so as to form, on at least the first surface of the substrate, a corresponding number of additional layers of the superconductor material.

31. The method of claim 30, wherein:the additional layer or layers of the superconductor material deposited by the one or more repetitions of the higher-plasma-dose plasma deposition process extend onto the first surface of the substrate and overlap the superconductor material deposited on the first surface of the substrate in step (a); and / orthe additional layer or layers of the superconductor material deposited by the one or more repetitions of the lower-plasma-dose plasma deposition process extend onto the sidewall of the recess and overlap the superconductor material deposited on the sidewall of the recess in step (b).

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