An optical switching network

Abstract

An optical switching network 1000 includes a plurality of switch devices 100 and a plurality of hosts 200 each comprising at least one network interface controller (NIC). A network data plane and a ne

Description

Technical Field The present disclosure relates to an optical switching network. Background Optical circuit switching (OCS) permits exchange of data in an optical form between a source host and a destination host. Compared with electrical switching networks, the optical counterpart benefits from a broader bandwidth and lower power consumption. As such, they may be considered for many applications. For instance, a nanosecond optical switching and control system has been reported to enable an optically switched data center network (See Xue, X., Calabretta, N. Nanosecond optical switching and control system for data center networks. Nat Commun 13, 2257 (2022) https: / / doi.org / 10.1038 / s41467-022-29913-ll. OCS networks are often designed for use with a specific network protocol or targeted at packet-based networks. This prevents flexibility of use and a wider deployment of the technology. It is an object of the disclosure to address one or more of the above mentioned limitations. Summary According to a first aspect of the disclosure, there is provided an optical switching network comprising a plurality of switch devices; a plurality of hosts, wherein each host comprises at least one network interface controller; a network data plane and a network control plane distributed among the plurality of hosts and the plurality of switch devices forming the network; wherein the said at least one network interface controller is configured to provide network protocol information to the network data plane and control information to the network control plane for routing optical data to be transmitted between a source host and a destination host among the plurality of hosts. Optionally, each switch device is configured to receive the control information and pass the optical data to be transmitted. For instance, the optical data may be passed directly, that is without check or alteration of the optical data. Optionally, each network interface controller (NIC) comprises a NIC data plane and a NIC control plane coupled to an optical physical medium dependent layer. For instance, the network interface controller may comprise an electrical to optical and optical to electrical converter. The network interface controller may be provided in a plugin card. Alternatively, the network interface controller may be integrated into a system on chip. Optionally, the NIC data plane comprises a data physical coding sublayer, coupled to a data physical sublayer. Optionally, the NIC control plane comprises a set of buffers, a control physical coding sublayer, a control physical sublayer, a protocol circuit, and a phase locked loop and clock distribution circuit. Optionally, the optical switching network comprises one or more bridge devices, wherein each bridge device comprises at least two ports. For instance, at least one bridge device may be configured to perform electrical to optical and optical to electrical conversion. Optionally, each bridge device comprises at least one of a buffer and a routing table circuit. Optionally, one or more bridge devices comprise an optical amplifier and / or an optical bypass connection. Optionally, each bridge device is arranged between two switch devices. Optionally, wherein each switch device comprises an optical switch matrix coupled to a plurality of ports on a switch data plane; and a switch control plane configured to identify a destination information of the optical data and to configure the optical switch matrix to route the optical data to a destination port among the plurality of ports, based on the destination information. Optionally, wherein the switch data plane is all optical. Optionally, wherein at least one switch device is configured to amplify an amplitude of the optical data transmitted through the optical switch matrix upon detection of a decrease in data signal quality. For instance, the switch device may be configured to receive error information from the hosts that are attached to it. Optionally, wherein the optical switching network is implemented as a meta network compatible with different kinds of hosts. Optionally, wherein the network data plane establishes an optical point-to-point connection between two given hosts and wherein the network control plane is multi-hop such that all connections between two switch devices or between a host and a switch device are established point-to-point, either electrical or optical, between two adjacent devices. Optionally, wherein when a route cannot be immediately acknowledged by the switch device, the switch device is configured to communicate a time of availability of a path to a requested destination and report it back to the host making the request. For instance, the control physical coding sublayer of the host may be configured to wait for an acknowledged (ACK) signal or a not-acknowledged (NACK) signal or a delayed ACK signal from the switch device control plane. Optionally, wherein the optical switching network is configured to enable unidirectional flow of optical data on the network data plane by sending data on the control plane in the opposite direction to the flow of optical data on the data plane. Optionally, the optical switching network is configured to enable broadcast communication on the network data plane; wherein during broadcast communication a host transfers data to multiple other hosts. Optionally, wherein the network control plane is configured to transmit flow control information. For instance, flow control information may comprise an indicator of data transmission success. Optionally, wherein when a host on the network does not have a communication partner on the data plane and becomes a disconnected host, the optical output of the disconnected host is redirected through the switch matrix to its own optical input to form a loopback on the data plane. Optionally, wherein the switch control plane comprises a reference oscillator for generating a reference clock, and a phase locked loop circuit configured to generate a plurality of PLL clock outputs locked to the reference clock; and wherein the reference clock is embedded in a control plane protocol. Optionally, wherein the switch control plane comprises a plurality of transmitters for communicating the control plane protocol to one or more hosts attached to a given switch port; and wherein the plurality of transmitters are coupled to multiplex circuitry, the PLL clock outputs being configured to drive the multiplex circuitry. Optionally, wherein at least one host comprises an equalization circuit adapted to cache equalizer settings for a pair of transmitter / receiver on each side of a physical link associated with a specific connection in the network, and to recall such settings when the same connection is established. For instance, the equalization circuit may be provided in the data plane of the host, for instance as part of the transceiver of the host. The host may include a register to store the equalizer settings. For instance the register may be provided in the transceiver or in the physical medium dependent PMD layer. Optionally, wherein the NIC control plane comprises a transmitter, receiver and a clock data recovery circuit adapted to recover a clock embedded in a data stream that originates from the switch device it is connected to. Optionally, the data physical sublayer comprises a transmitter, receiver and clock data recovery circuit, and wherein the NIC control plane is configured to store phase accumulator states of the clock data recovery circuit of the data physical sublayer for a plurality of hosts. Optionally, wherein the phase locked loops and clock distribution circuit comprises a first phase locked loop configured to lock to a local reference oscillator from a host, and a second phase locked loop circuit configured to lock to the recovered clock; wherein the transmitter, receiver and clock data recovery circuit of the NIC control plane is driven by the first phase locked loop; and wherein the transmitter, receiver and clock data recovery circuit of the NIC data plane is driven by the second phase locked loop circuit For instance, this may be used to implement a clock coherent data plane. Description of the drawings The disclosure is described in further detail below by way of example and with reference to the accompanying drawings, in which: figure 1A is a schematic diagram of an optical switching network according to the disclosure; figure IB shows various layers that may be implemented in the optical switching network of figure 1A; figure 2A is a diagram of a switch device for use in the optical switching network of figure 1; figure 2B is a diagram of another switch device for use in the optical switching network of figure 1; figure 3A is a partial diagram of a host NIC for use in the optical switching network of figure 1; figure 3B is a diagram of an exemplary implementation of a transceiver for use in the circuit of figure 3A; figure 3C is a diagram of an example implementation of a PLLs and clock distribution circuit for use in figure 3A; figure 4 is a modified version of the optical switching network of figure 1; figure 5 is a diagram of an exemplary bridge device for use in the network of figure 4; figure 6 is a schematic diagram illustrating signal flow in an optical switching network; figure 7 is a diagram illustrating signal exchange in an exemplary optical switching network. Description Various acronyms and abbreviations are used in this application and listed in the following glossary. Host - a host node (source and sink of application data) attached to the network via a network interface controller (NIC). NIC - network interface controller containing the MAC / PCS / PHYs for data and control plane. Network protocol - The protocol (stack) implemented on the data plane. The switch devices described in the application are agnostic to these protocols, however the network interface controllers (NICs) are network protocol aware, at least to some degree. In practice this means that the NIC is designed to implement a procedure for embedding or de-embedding data into the packet layer (L3) of the network protocol. PCS - Physical coding sublayer, contains protocol flit / package detection, lane to lane deskew, line code embeddings (e.g. 64 / 66 or 128 / 130b), data de- / scrambling and error correction (Forward error correction FEC) and depending on protocol, the flow control. MAC - Medium access control sublayer. Although this is a term customarily used in Ethernet, in the context of this application MAC is used to denote a layer with the following properties: i) Seen from the point of higher layers (towards OS and software) the first to potentially establish hardware-based flow control, unless the PCS takes care of this functionality. For Ethernet, this means the Reconciliation sublayer (RS) is attributed to the MAC layer. ii) Seen from the point of higher layers, the last layer to have plain and well-defined access to the destination host ID on the network. PHY - Physical sublayer (connecting to the medium of transmission), comprising clocking (PLL), serialization, deserialization, equalization, driver and receiver amplifiers, clock data recovery circuits. Ethernet often separate PHY into physical medium attach (PMA) and physical medium dependent (PMD). Link - established bidirectional serial data transmission over one or many physical connections (lanes) or optical channels between a specific host and a specific switch device, attached to a single port on either side. Optical channels may be provided on a same fiber or may be distributed over multiple fibers. Each optical channel may carry a signal (for instance data) at a specific wavelength A. Lane - a physical electrical connection from one point to another. In case of differential signalling, the connection is made using two physical conductors. Channel - the optical equivalent to a lane. A wavelength (lambda) of specific polarization with associated, dedicated bandwidth around it, onto which the information can be encoded. Channels of different wavelength, polarization and modes may also be encoded onto physically separated fibers. Port - taken to be bidirectional and including physical data and control plane connection (lanes / channels). The number of ports of a switch is called the radix. The terms transceiver, SerDes and Serializer are used interchangeably throughout the description. They signify the union of one transmitter with data serialization path, analog signal equalization as well as (electrical and optical) driver circuitry, one receiver with data deserializer, analog frontend (TIA, equalization stages such as FFE) and the clock data recovery (CDR) circuit as well as the clock distribution circuitry required to operate all circuits. For clarity, the phase locked loop (PLL) circuits are excluded. The PLL circuits are customarily deployed in these systems to generate high frequency, low jitter clock signals for the transceiver circuit. Other common abbreviations include: FFE - Feed forward equalization; FIR - Finite impulse response filter; FEC - Forward error correction; DFE -Decision feedback equalization; CDR - Clock data recovery circuit; PLL -Phase locked loop (clock generation); AFE - Analog front end; TIA -Transimpedance amplifier; DSP - Digital signal processor. Figure 1A illustrates an optical switching network according to the disclosure. The optical switching network 1000 includes a plurality of switch devices 100 coupled to a plurality of hosts 200. Each switch device 100 is configured to receive the control information and pass the optical data to be transmitted. The switch devices 100 are arranged in a cascaded fashion to form a scalable network. The number of switch devices and hosts may vary. In this example three switch devices 100a, 100b, 100c and three hosts 200a, 200b and 200c are represented. Each host includes at least one network interface controller (NIC). For example, a host may contain one or more processors such as one or more processing units. Various processing units could be considered including one or more of a graphics processing unit (GPU), a central processing unit (CPU) an optical processing unit (OPU), and a Tensor Processing Unit (TPU), to name a few. In addition, the host may include a memory. In this specific example the switch device 1, 100a is directly connected to the host 1 200a and host 2 200b, and switch device 3 is directly connected to host 3 200c. It will be appreciated that the connections between individual switch devices and individual hosts may vary. For instance, the switch device 2 may be connected to additional hosts; the switch device 1 may be connected to all three hosts 2001, 200b and 200c, etc.... A given host may also be connected to several switch devices. For example, the host 200a may be connected to all three switch devices 100a, 100b and 100c. A switch device may be connected to multiple other switch devices with single or multiple links. In figure 1A the switch device 100b is connected to both the switch devices 100a and 100c. The optical switching network 1000 has a network data plane and a network control plane distributed among the plurality of host and the plurality of switch devices forming the network. Stated another way the network data plane is formed by the host data planes and the switch data planes of all host and switch devices present in the network. Similarly, the network control plane is formed by the host control planes and the switch control planes of all hosts and switch devices present in the network. The network control plane is realized through point-to-point connections between two given devices on the network (i.e. host to switch or switch to switch) and thus forms a multi-hop network. A "hop" refers to an opticelectric-optic conversion on a device. These conversions happen on the control plane only. The network data plane remains point-to-point between two distinct hosts only since the switch devices on the network will not inspect the data plane traffic. The data plane is all-optical and just enables two hosts on either end to form a point-to-point direct optical link. The network interface controllers are configured to provide network protocol information to the network data plane and control information to the network control plane for routing and flow control of optical data to be transmitted between a source host and a destination host among the plurality of hosts. The network protocol information may vary depending on the specific use case. For instance, when using optical switching network 1000 in conjunction with an Ethernet environment then, the network protocol information would be the L3 data (IP packets] to be sent through the network 1000. The optical switching network 1000 may be referred to as an optical circuit switching OCS network, or smartOCS network. The optical switching network 1000 may be implemented as a so-called meta network, that is as a physical network added to an existing network. For this reason, the OCS 1000 may also be referred to as OCS meta network or smartOCS meta network (SMN]. Such a meta network is compatible with different kinds of network stacks on layer L2 and above. Examples of protocols that shall be supported by the proposed network include Ethernet, Ultra Ethernet, CXl / PCIe, NVLink or UALink, to name a few. The commonality of these protocols lies in the fact that they are based on point-to-point SerDes enabled PHY layers. These PHY layers can be directly used as data plane PHYs on the host systems with relatively small modifications as described further in this application. In operation the control flow takes place on the control plane of the network, while the data flow takes place on the data plane. The control plane and its control plane protocol are responsible for establishing routes through the network on the protocol agnostic, all optical data plane. The data plane may be built using optical circuit switch technology. Connections are established between source and destination through their respective PHYs as a physical point to point link through the optical switch matrices of the switches that have to be traversed by the light originating from the transmitter of one host to the receiver of the other host. All connections on the data plane are taken to be bidirectional in nature throughout this document. An option is also presented, describing how the data plane connections can be used unidirectionally. Since the optical circuit switch technology is protocol agnostic, the bidirectional connection may be established on several channels (lambdas). It is assumed that the number of wavelengths (lambdas) will be the same in either direction. The control plane can be built based on varying point to point physical interconnect technology. Here, each host of the network is attached to one or more switches of the network through a link. In contrast to the data plane, the control plane will never be interrupted or disconnected. Switch events of the switch will only ever affect the physical connection of a host with another host on the data plane. More specifically, if the control plane connection between a host and a switch device malfunctions or becomes disconnected, the host is considered non-operational. The optical switching network of the present disclosure permits fast routing reconfiguration. For instance, the network may reconfigure routing in less than about a microsecond. Figure IB shows the network layer definition as put forward by the Open Systems Interconnection (OSI) model. The optical switching network 1000 of figure 1A (the meta network portion) implements the physical and parts of the coding sublayers. This allows it to be used with the network protocols mentioned above which implement the packet and transport layers and any layers required beyond them. Figure 2A is a diagram of a switch device for use in the optical switching network of figure 1. The switch device 100, also referred to as smart optical circuit switching (smartOCS) device, includes an optical switch matrix 140 coupled to a plurality of ports 110i-n. For instance, the number of ports may be an integer N, usually but not limited to a power of two. All ports 110 are implemented in the same way and therefore identical to each other. It will be appreciated that the ports 110i-n maybe arranged in different ways in the switch device. Figure 2A shows a possible connection between a specific port 110k and another specific port 110j. The optical switch matrix 140 provides an optical input and an optical output for each one of the N ports. Several optical multiplexers MUX 170i-n and demultiplexers DEMUX 130i-n are provided. One MUX and one DEMUX are provided per port 110 of the optical switch 100. An electronic control plane 160 and a reference oscillator 180 are also provided. The electronic control plane 160 includes N control path circuits 1611-n, whose fundamental operation clock is provided by one or more PLLs 162; and a control network layer 163. The control network layer 163 includes an arbitration functionality, routing tables and usage statistics, monitoring and failure recovery functionalities. The electronic plane 160 of the switch device is part of the control plane of the network. A port 110 may be implemented as the combination of an optical input 111 with an optical output 112. There are at least two distinct optical channels encoded onto the fibre which connects to a port, one for data and one for control. Alternatively, a port 110 may be implemented as the combination of an optical input, an optical output, an electrical input and an electrical output (In this case, the electrical input may be directly connected to RX and TX of port control path 161 for port K). There can be a single or multiple optical data channels encoded onto the fibre / waveguides passing through the optical switch matrix 140. The control and data channel(s) enter the switch device 100 through the port 110, the optical input is connected to an optical demultiplexer 130 which separates the control channel from the data channel(s). The data channel(s) is / are routed through the switch matrix 140 (in this example and without loss of generality, to port 110j). The optical control channel signal is converted to the electronic domain via one of the N photodiodes 150i-n or via one of the N optical pattern recognition circuits 120i-n. The control channel signal is then directed to the electronic control plane 160, more precisely to the control path 161 assigned to the given port. After passing through the switch matrix 140, the optical data are combined with control information from the control path 16lj at the multiplexer 170j. Figure 2B is a diagram of another switch device for use in the optical switching network of figure 1. The switch device 100’ of figure 2B is similar to the switch device 100 of figure 2A with some modifications, and corresponding components are represented with the same reference numerals. In this implementation the ports 110i-n include the optical output 112, the optical input 111, as well as the electrical input 113 and the electrical output 114. For each port 110, the optical input 111 and the optical output 112 are connected to the optical switch matrix 140 via an optical connection. Similarly, the electrical input 113 and the electrical output 114 are connected to the electronic control plane 160 via an electrical connection. In both figures 2A or 2B, the electronic control plane 160 could be either an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or a system on chip (SoC). The switch matrix 140 and ports on the data plane are all optical without buffering so that communication through the network happens all-optical or regenerated-optical from the source host to the destination host. The buffering is delegated to the hosts connected to the switch device. The procedure of establishing a path through the network on the data plane is handled by the control plane. The control plane ensures appropriate signal flow control through the data plane. All connections on the control plane within the network are point-to-point communication paths. Possible connection scenarios are host-to-switch or switch-to-switch. The electronic control plane 160 may be adapted to generate a clock reference based on a reference oscillator 180. The clock distribution to other devices in the network happens by embedding this clock in the control plane point-to-point link protocol. An appropriate number of transitions will be guaranteed by choice of datalink layer protocol encoding on the control path. A switch device 100, 100’ can be either a clock generator or a clock follower. Every network has a single clock generator. The clock generator is determined during network initialization. All other devices are clock followers. The hosts 200 connected to the network are always clock followers. If a switch device 100 is a clock generator, it uses its high precision, internal quartz-based reference oscillator to drive the phase locked loops (PLLs) 162 of all its control plane PHYs 161i-n. In turn these PHYs are all connected to the control plane PHYs of the attached host systems through the control channel. The switch reference oscillator 180 becomes the timing reference for the attached hosts as follows. The switch PLLs 162 are all locked to the local reference oscillator 180. The PLL clock outputs are used to drive the multiplexer circuitry of all PHY transmitters of the switch. The PHY transmitters are responsible for serially communicating the control plane protocol contents originating from the switch control plane to the hosts attached to a given switch port. In this way, the data stream sent on the control plane from the switch to each host also contains phase and frequency information that is locked onto the switch devices’ own reference oscillator. How this information is used to form a source synchronous link on the data plane is described in the sections which describe the host device architecture. Figure 3A is a partial diagram of a host NIC for use in the optical switching network of figure 1. Figure 3B illustrates an exemplary implementation of a transceiver for use in the circuit of figure 3A. Figure 3C shows an example implementation of a PLLs and clock distribution circuit for use in figure 3A. Among other entities, the NIC contains a MAC, the network PCS and PHY (205) and a PMD. The PHY 205 is made of a NIC data plane 210 and a NIC control plane 220, also referred to as smart NIC data plane SDP and as smart NIC control plane SCP. The NIC data and control planes 210 and 220 are coupled to an optical physical medium dependent PMD layer 230. The PMD layer 230 is configured to convert a signal from electrical to optical on TX and vice versa for RX. On the data plane, this is always true. On the control plane, conversion between optical and electrical domain may also be omitted, if the host is electrically connected to a switch device on the control plane. The NIC data plane 210 contains a physical coding sublayer PCS 211, coupled to a data physical sublayer, data PHY 212. The NIC control plane 220 contains a set of buffers 221, a control PCS 222, a control PHY 223, an address translation table 224, and a PLLs and clock distribution circuit 225. The address translation table 224 is used to translate between the higher level L3 protocol address and the SMN (L2) address. Therefore, the NIC control plane 220 has both the control plane PHY 223 and the control plane PCS 222. The control plane PCS 222 is responsible to provide the control information to 223 with the appropriate line coding and packaged into information characters such that this information can be readily decoded by the PCS layer within the switch device attached to the other end of the control path (i.e. PCS of 161 in Figure 2A). The control plane PCS 222 is coupled with the data plane PCS 211 and the MAC layer to process network routing information and carry it through the control plane network. This allows the optical switching network to never have to evaluate information contained in the packet data stream on the data plane. Thus, irrespective of the transformations within the data plane PCS 211 demanded by a given standard (such as scrambling or recoding), the control plane always has unhindered access to all routing and packet information required to perform its routing tasks. The hosts 200 which are part of the optical switching network 1000 (also labelled smartOCS network) use a NIC dedicated to both the switch devices 100 (also labeled smartOCS devices), and the desired network protocol such as Ethernet, CXL, among others. This is achieved in the implementation of the NIC software layers (beyond the hardware) and the MAC layer (L3) which is part of the NIC hardware. In this document, only the technical details of the network protocol agnostic functionality of the switch devices are discussed. Wherever required for clarity, a potential Ethernet implementation is described. It will be appreciated that Ethernet is just one example of a network protocol to be supported by the switch devices and the optical switching network they form. The NIC (smartNIC) of a host 200 is configured to provide the network protocol information to the data plane of the optical switching network 1000 and the control information for routing and flow control of the data to be transmitted to the control plane of the optical switching network 1000. The NIC could be physically located in a dedicated plugin card (Peripheral Component Interconnect Express PCI-E CEM) or be fully integrated into a SoC. Irrespective of its location, the smartNIC implements the full stack required by the given network protocol down to the layer of packetization. In Ethernet, this would be the medium access (MAC) layer. The smartNIC may also be compliant with layers below the protocol layer, such as the coding layer (again, in Ethernet terms: the PCS). However, if a network protocol defines a clear-cut interface between layers of packetization and coding, the smartOCS NIC may opt to implement a coding sublayer deemed optimal for the optical engine it needs to support. In Ethernet language, the optical engine would be represented by the physical medium dependent (PMD) layer. Data entering the host NIC and arriving at the interface from packet layer to coding layer will still be in its native binary form, unscrambled and unencoded. Instead of the plain PCS and physical sublayer (in Ethernet terms called physical medium attach - PMA), the smartOCS NIC possesses two PCS layers 211, 222 and two PHY layers 212 and 223. One for the data plane and one for the control plane. The host NIC control plane 220 is configured to perform one or more of the following tasks: i) establish flow control, ii) perform arbitration through the optical switching network, iii) perform network address translation if not done through the packet layer, iv) perform fast relock operation upon smartOCS switch events. The data physical sublayer (212) includes a clock data recovery circuit, and the NIC control plane (220) is configured to store phase accumulator states of the clock data recovery circuit of the data physical sublayer (212) for a plurality of hosts. The control PCS circuit 222 may perform flow control by creating backpressure upstream towards the packet layer by not accepting data at the smart NIC control plane SCP interface and not providing valid data towards the MAC. Arbitration through the optical switch network 1000 is performed within the switch devices 100 by the arbitration module of the control network layer 163. Specific control characters are sent to the switch device(s) 100 attached to the host 200. These characters inform the switch device of a particular connection on the data plane that the host wants to establish (a request). In turn, switch 100 informs a host about the availability or unavailability of a requested connection through switch matrix 140 by sending acknowledge characters or non-acknowledge characters on the control network layer. If a path through 140 is requested by one of the hosts 200 connected to a switch device 100 which is already in use, the process known as "arbitration" is performed inside of the control network layer 163 to decide, in what order and at what time pending request are to be served (i.e. acknowledged). The protocol circuit 224 is configured to perform network address translation. The destination ID information, which may also be referred to as label, can be provided by the MAC layer or be extracted from the packet header before scrambling / encoding in the data plane PCS 211 if the network protocol layout is known and documented. When the destination ID information is provided by the MAC layer, a dedicated interface provides a target host ID in a format common to the network protocol. This host ID is then translated to a network specific label which is then used to route through the control network layer 163 of the switch device 100, to set up the path through the data plane. The label may be a global label or a sequence of local labels. A global label is valid throughout the network and used to find the correct physical path through the network in each and every switch device 100 of the network using switch device local routing tables. This approach scales well but requires appropriate network initialization through a network management instance. In the sequence of local labels, every label is valid for finding the path through the next switch device. This is a global routing scheme, and all hosts 200 need a view of the network topology and associated host IDs. This is mostly suitable for small networks and keeps the complexity of routing tables very low within the switches. In order to perform fast relock on the SCP, the NIC control plane 220 and the control plane 160 of each switch devices in the network leverage fast SerDes relock times upon reconfiguration of optical links on the data plane through multiple different features on transmitting and receiving side. The control path between a switch device 100 and a host 200 connected to it, is always active and constantly exchanging control and / or idle characters. This allows the transceivers on either side of the control link to maintain lock at all times and have a recoverable reference clock at their disposal. The clock data recovery (CDR) of the receiver in the NIC control plane 220 locks onto the clock embedded in the data stream that originates from the switch device 100 it is connected to. The CDR then outputs both the recovered data (going towards 222) and a recovered clock. The recovered clock is used as a reference to PLLs and clock distribution circuit (225) which performs some jitter cleaning on the clock and provides reference clocks to all circuits present in the Data PHY 212. This switch device may either be a clock follower or a clock generator. In any case, the clock embedded in the control channel data stream will be frequency locked to the network base reference oscillator. As shown in figure 3C the PLLs and clock distribution circuit 225 may be implemented with two PLLs. The first PLL (PLL_1) locks to a local reference oscillator on the host. The second PLL (PLL_2) locks to the CDR recovered clock of the control channel, which then drives the data plane transmitter and receiver. This arrangement makes the data plane transceiver source synchronous. Clock coherency refers to a situation in which a transmitter and a receiver which form the two ends of an optical link operate based on a same timing reference (reference oscillator). This means that transmitter and receiver will never experience a difference in momentary frequency (frequency as measured over a finite time interval) but will only differ in relative phase. Extrapolated to an entire data plane, this means that _any combination of transmitter / receiver pair is clock coherent. The transmitter, receiver and CDR circuit of the NIC control plane 220 (see CDR in Control PHY 223) is clocked by (or driven by) the first PLL (PLL_1). As such, the control channel is not source synchronous and requires both frequency and phase tracking in the CDR. The recovered clock of the CDR (of 223) is passed on to a jitter cleaning PLL (second PLL, PLL_2) which drives the transmitter, receiver and CDR circuit of the NIC data plane SDP 210 (See arrow between circuit 225 and CDR of Data PHY 212 in figure 3). Since the same is true for any other host 200 in the optical switching network 1000, any established data channel through the network between two hosts will be a source synchronous serial link and will not require frequency acquisition. As a result, the phase and frequency accumulators in the CDR circuits on either end of the data channel will not have to recover frequency when their receivers lock onto the data stream of the opposing sides transmitter after a switch operation thereby decreasing overall relock time. Equalization caching is performed on the data plane of the network. At least one host 200 in the network (or possibly all the hosts) may be provided with an equalization circuit adapted to cache equalizer settings for a pair of transmitter / receiver on each side of a physical link associated with a specific connection in the network, and to recall such settings when the same connection is established. The Data PHY 212 of the host 200 has a transceiver circuit. When two transceiver circuits form a physical link, their equalization circuits try to remove as many physical signal distortions as possible. The equalizer setting that a transmitter(tx) / receiver(rx) pair on each side of a physical link will train to are specific to that particular pair of tx / rx. This equalizer training process occurs inside of the tx / rx circuitry and may be relatively time consuming. The host 200 is provided with a register that stores equalization states or settings. For instance, the register may be located in the PMD 230 or the data PHY 212. The host caches the last known equalizer settings for a pair of tx / rx, (that is already trained or "good" settings) and can recall them the next time the same connection is established. As a result, equalizer training can be skipped thus saving reconnection time. The NIC control plane 220 receives regular notifications from the switch device 100 it is connected to. These include information on when a reconfiguration will take place and to which other host on the network the NIC control planes will be reconnected to. By storing the last known phase accumulator states for all hosts of the system a particular host has been connected to in the past, this phase information can be restored prior to the actual reconfiguration taking place and the CDR of the SCP can be frozen (disabled phase updates). Upon physical reconnection due to a switch event in the switch devices 100, the number of required phase updates to arrive at the optimal sampling location will at most be a few steps (the number of required steps usually is not zero due to inevitable temperature and voltage drifts in all devices of the network). In any case, time is saved for reestablishing a connection. The same procedure described above for caching and recalling the phase accumulator state of the CDR can also be applied for the equalization state in transmitter FIR and receiver FFE / DSP for optimal bit error rate. In multichannel / lane data plane systems (wave division multiplexing, polarization multiplexing and mode multiplexing), in addition the host specific intra-channel / lane skew can be cached and recalled. The optical switching network may also be configured to perform loopback on disconnect. Time constants in a transceiver based serial link are usually on the order of THz (optical bandwidth), GHz (analog bandwidth) or hundreds of MHz (CDR, DSP, line coding). Yet, disconnecting an optical link and reconnecting it is reported to take a long time, sometimes in the order of milliseconds (kHz). A likely candidate for long down times if PLLs are not powered down are the baseline wander effects due to inactive, AC coupled links and the slow current sources in analog frontends that are required to calibrate a receiver to the optimal DC biasing points. To avoid this behavior if a host needs to be disconnected from the network data plane (because at this point in time the host has no communication partner on the data plane), the smartOCS will direct a host without current communication partner to be put into a loopback configuration through the switch devices optical switch matrix. In this context "disconnected” simply means that a particular host on the network does not have a communication partner on the data_ plane, however its point to point connection to the switch device always stays active and alive. The optical output of the host is redirected through the switch matrix to its own optical input thus forming a loopback on the data plane. In this way, the biasing sensitive circuitries inside the Optical PDM 230 will always see an active link, even if only idle characters are transmitted across that (loopback) link. Note that the point-to-point connection between the host control PHY and the electronic control plane of the switch device it is connected to always stays alive. Turning to data flow control, when data is available for transmission at the MAC layer, the optical communication switching network 1000 considers this interface the last interface at which on-chip flow control is realized. The serial links on the data and control planes transmit regularly changing symbols at every unit (limited run length). This is to maintain the CDRs of the receivers in lock and limit the magnitude of baseline wander. To this end, in addition to scrambling the data to be transmitted (by manipulating the data stream before transmitting), the coding layers of data and control planes will introduce idle characters into their data streams whenever there is no valid data available from the packet layer (SDP) or no control information needs to be transmitted (SCP). On the receiving side of the data plane, these idle characters are used by the coding sublayer to monitor the health state (absence of errors) of the link but are not passed on to the packet layer. They are dropped from the data stream and thus, there is a clear mechanism to indicate the availability of useful data at the interface between coding to packet layer. The NIC control plane 220 can interfere and override the way in which the coding sublayer reports data availability to or readiness to accept data from the packet layer. In this way, the NIC control planes 220 in the two hosts forming a direct link across the data plane establish the flow control with the packet layer. Additionally, the NIC control plane 220 conceals the actual physical link availability during switching operations. Usually, if an optical circuit switch breaks the connection between two hosts A and B and establishes a new connection from host A to C, the physical layer in host A would, for a certain period, indicate a loss of link to the coding sublayer and the coding sublayer in turn would then report a link unavailability to the packet layer. This unavailability indication would then propagate all the way to the operating system which would consequently free all packet buffers in memory associated with the network link. Upon successfully establishing the physical connection between hosts A and C, the physical layer would indicate the presence of a valid signal to the coding sublayer which would then again try to reestablish lane deskew, descrambling lock and FEC lock. Once this has been accomplished, the coding sublayer would then report link availability to packet layers and above. As a result, the operating system would reinitialize all transmission and reception buffers in memory and make the network link available to applications again. This process can easily take several milliseconds and would render all link re-establishment speedups implemented by the NIC control plane 220 and the NIC data plane 210 superfluous. The optical switching network 1000 may be configured to avoid operation system (OS) interaction altogether and perform a switching operation on layers at and below the physical coding layer only. This can be achieved through network protocol dependent tweaks to all network layers above the coding layer combined with the ability of the NIC control plane to hide the fact that a physical link is actually "lost” during a smartOCS switching operation. This may be accomplished by not passing link status updates to the upper layers. Only in cases when the NIC control plane or the NCI data plane run into irrecoverable hardware errors will layers at and above the packet layer be involved and made aware of a link outage. To improve performance, the NIC control plane 220 may be provided with a a set of buffers (221), also referred to as per-destination-host packet buffers to collate a set of smaller transactions if necessary. This is because the network efficiency depends on the duration of data transmission to and from a given host. If data sizes and thus duration of transmission is large, the time to reconfigure to connect from one host to another decreases in importance. The network efficiency Neff is calculated as: Neff = t_dtran / (t_dtran + t_overhead) in which t_dtran is the data transmission time interval, and t_overhead is the overhead time that includes the time elapsed for all tasks required to form a new connection between two hosts on the data plane. To keep the number of host packet buffers manageable, a least recently used (LRU) algorithm may be used to reassign packet buffer space to new host IDs. Since the optical switching communication network 1000 is primarily targeted at applications with regular traffic patterns, it is expected that an upper bound for the number of required buffers can be determined for a given cluster and workload size. Data presented to the NIC data plane 210 at the MAC / PCS interface is indicated via a valid signal. For protocol stacks where this is not customary (such as Ethernet, although more recent standards now employ the reconciliation layer (RS) between MAC and PCS), the MAC layer needs to be adapted accordingly. Standards like Ethernet define a physical interface standard such as 10 gigabit media-independent interface (XGMII) to connect lower-level network layers. An Ethernet example would be the connection of a MAC with PCS in one physical chip connecting to another PCS / PMA / PMD in another chip such as a transceiver chip on an XSFP module. Interfaces like these would need to be amended to be compatible with the switch devices 100. This is not only because of the requirement of flow control at the MAC / PCS interface but also because the MAC layer may need to present the network host ID to the NIC control protocol directly. This is because the propagation of routing information may happen according to multiple different scenarios. For Ethernet like protocol - the physical interface presents data that may already be scrambled to the NIC data protocol. In this case, the header and thus the routing information of a packet cannot be extracted without descrambling. This would make the NCI data protocol very network protocol dependent and optical switching communication network 1000 seeks to keep the NIC control and data planes as network protocol agnostic as possible. For modified Ethernet like protocol, several cases may be considered. In a first case, the MAC does not perform IP network address to network destination ID translation. The routing tables in IP based networks are kept in the network switches and are updated through various protocols (e.g. ARP). The optical switching communication network 1000 cannot rely on mechanisms like these as the underlying data plane is a circuit switched network which only establishes point to point connections between hosts. As such, the destination ID must be known at the initiating host side already. In a second case, the MAC is modified to perform IP address to network destination ID translation. It must then present this destination ID to the NIC control protocol, thus altering the way in which the MAC / PCS interface in network stacks like these are defined (and also how XGM11 based interfaces work). In a third case, memory semantic fabrics (like CXL / PC1-E or NVLink) - here, the base memory address of an address range is used either directly or hashed as the destination ID. In resemblance to the second case, this translation may either happen on the protocol layer or within the NIC control protocol. Figure 4 is a modified version of the optical switching network of figure 1. In this case the optical switching network 4000 includes several bridge devices 300a, 300b provided between the switch devices 100. The bridge devices may be used for optical signal regeneration, buffering and head of line blocking mitigation. Figure 5 is a diagram of an exemplary bridge device for use in the network of figure 4. The bridge device 300 has two ports (P0 311 and Pl 313) coupled to a buffer 320, such as a per-egress (per destination host ID) buffer, and a routing table circuit 330. Only one direction of data flow is illustrated. The first port 311 has a data plane PO SDP 311a and a control plane PO SCP 311b. Similarly, the second port 313 has a data plane PO SDP 313a and a control plane PO SCP 313b. Optionally, an additional optical bypass connection may be provided (not shown) may be provided between the two ports P0 311 and Pl 313. In operation, data are received through the data plane of port P0 SDP 311a once a link has been established by aide of the control plane of port PO SCP 311b. Instead of passing the data on to a packet layer for stripping and application processing, the data is optionally buffered in the egress buffer 320 based on the destination ID (label). Additional optical PMDs (not shown) are provided in the bridge device 300 to perform the optical to electronic data conversion for data received at 311a, and the electronic to optical conversion for the data arising from 313a. Optionally, the bridge device 300 can perform network address translation to provide flexibility in setting up multiple independent address domains within a single physical network (SMN). If the control plane of port Pl 313b receives an acknowledgement (ACK) to indicate data plane route availability, then the data plane of port Pl 313a can pass on the data from the egress buffer 320 to the destination host through the network data plane. A passthrough mode without buffering is also supported in cases where long-lasting route configurations can be beneficial. A unidirectional mode of operation on the data plane can also be supported by bridge devices. Bridge devices may be implemented in different ways. For instance, a host device having more than one network port can also operate as a bridge device. A bridge device operates like any other host device in the system up to the PCS layer. It thus performs opto-electro-optic (OEO) conversions. This is done to achieve: i) optical signal cleaning in multi-hop scenarios; and ii) head-of-line blocking reduction and more efficient routing path reservation through electronic buffering. A key aspect of the bridge device is that the data on the data plane is never touched or inspected. Reception, buffering and forwarding solely take place based on the information communicated on the control plane. The amplitude of the data signal transmitted between switch devices decreases slightly at each hop. For large optical switching networks this may result in a significant loss of signal-to-noise ratio (SNR). The bridge devices may be used to "clean" the signal between switch devices, hence improving the reliability of the optical switching network. The opto-electro-optic (OEO) conversion "cleans" the signal by restoring its original digital meaning in the process. Optionally, further amplification of the signal may also be implemented. Figure 6 is a schematic diagram illustrating signal flow in an optical switching network through the data plane and the control plane. The optical switching network as illustrated in figures 1 or 4 performs its operation through the interplay between the control plane and the data plane. Links on the data plane are formed in a point-to-point manner between two hosts of the network. The switch devices 100 between these two hosts 200 are set up such that their optical switching matrices will allow two direct optical paths between two hosts A and B. The SDP transmitters of hosts A and B drive their respective modulators to alter the intensity of the light originating from the laser and travelling towards the outgoing fibre attached between host and switch. The SDP receivers receive the intensity modulated light on the incoming fibre attached between switch and host and convert the light into electrical information through a photodetector to then perform electrical processing and detection. As such, the data plane establishes bidirectional and direct connections between the PHYs of two hosts connected to the network. Optical multiplexing or demultiplexing circuitry is not shown here for brevity but multiple different channels ( for carrying different wavelengths A) can be added to the fibre or fibres and will thus increase the available bandwidth of the data plane. A transceiver could use multiple fibres to increase bandwidth. It will be appreciated that optical signal generation may be implemented in different ways. For instance, the transceiver of host A could modulate the laser directly. Similarly different techniques may be used to convert optical to electronic signal. The optical switching network does not impose any restriction on the modulation techniques used on the data plane. As such intensity modulation is just one possible example, and other modulation techniques may be used. It is agnostic to the optical aspects of a given network protocol and the interaction between control plane and the data plane does not depend on it. In contrast, the control plane forms point to point connections between switches devices and switch devices, and between switch devices and host devices. In figure 6, the nature of the bidirectional connection between these devices is omitted. Two scenarios are covered: i) an all-electrical network control plane with bidirectional electrical cables connecting the transceivers of two connected devices (that is a host device and a switch device], and ii) an optoelectrical network control plane which either shares the fibre with the data plane but uses a different wavelength onto which the control data is encoded, or which is carried over a separate fibre. In both cases, the control plane of a switch device 100 will transform and propagate switch requests that are issued by a host control plane. The mechanics of this process and how a route is established through the network is covered as an example implementation in the following sections. It will be appreciated various implementations may deviate from the approach described below in several aspects. Without loss of generality, let host A be connected to switch device 1. Further, let switch device 1 be connected to switch device 2 which has two hosts B and C connected to it. Initially, the switches 1 and 2 are set up such that hosts A and B have formed an operational link on the data plane. Either because the MAC presents enough data directed at host C to the SDP 220 and SCP 210 or because the per-host buffer for target host C on the SCP of host A has collected enough data, irrespective of whether the datapath link is in use or idle, the control PCS 222 will send a request to switch device 1. The request contains the host ID and the amount of data which needs to be communicated. The default behaviour of the host control PCS 222 is to wait for an acknowledged (ACK) signal or a not-acknowledged NACK signal or a delayed ACK signal from the switch control plane. The delayed ACK is an acknowledge but with a timer value computed by the switch device to instruct the requesting host to delay transmission until that point in time. In case of a NACK, the control PCS 222 has to resend requests until either an ACK or a delayed ACK is received or until a timeout timer has expired (in which case the link is considered physically disconnected and the NIC informs higher software layers about this incident while commencing with the transmission and reception to and from other destination IDs). In a network including many switch devices 100, it is the last switch device in the chain of switch devices whose ACK needs to propagate back to the initiating host device so that the link on the data plane can be safely established. Upon reception of an ACK, the control PCS 222 immediately instructs the data PCS 211 to start sending data. In the special case where a path is already established to the host ID requested by a host, the control PCS 222 may grant the data PCS 211 to immediately send the data, even prior to requesting a new ACK from the switch devices of the network. The data PCS 211 keeps a copy of all data sent during that time of uncertainty until the SCP receives the corresponding ACK for the transaction. If the switch device responds with a NACK or a delayed ACK, all data sent up until this point is considered lost and the data PCS 211 stops accepting data from the MAC (if the buffer associated with the specific destination ID is also full). The SDP 210 will restart sending the data as soon as indicated by the control PCS 222 depending on the timing information contained in the delayed ACK. Once all data has been sent, the transmitter will keep on sending idle characters for the reason mentioned above. The switch device will keep track time and can thus determine when the allotted time of communication between the two connected hosts has expired. Update notifications are sent to both hosts participating in a connection if a host on either side of the existing connection has issued a new request to a different host id and the connection window has expired. It does however not send any update notifications otherwise so that the existing connection between the two hosts can be used by succeeding packet streams. In this case the SCP 220 of a host which uses an existing path through the network will still have to issue requests so that switch devices will be notified and will not redirect the optical datapath until the new time window of transmission has expired. This is accomplished through the delayed ACK mechanism. If a route through the network can be maintained and has not been reprogrammed ever since the host request was seen by the last switch device of a switch path, an ACK will inform the host that its speculative data transmission attempt on the data plane was successful. Otherwise, the host will receive a delayed ACK which informs it that all data sent ever since the last request will need to be retransmitted once the link to the requested host is reestablished. In this way, the network control plane (or more specifically, the switch control planes) will keep the SCP 220 of each host informed about which host they are supposed to connect next and which cached transceiver settings to recall in order to speed up the serial link relock process on the data plane. If the host is to be disconnected (i.e. not reconnected to another host of the network), the switch device to which the host is connected will put it into loopback mode via the appropriate control channel update notification and by appropriately reprogramming the optical switch matrix state. The receiver will store the last known information on CDR phase, equalization state, intra-channel skew and internal FEC state for the host it is currently connected to for later restoration and will recall the information stored for its loopback connection. This will allow the Transimpedance amplifier (TIA), biasing circuitry and voltages across potential decoupling capacitors in the signal path of the receiver to stay in an operational state. The control plane of each switch device 100 and host device 200 is, depending on physical implementation, reconfigurable. This allows multiple routing and flow control schemes to be implemented. The control plane may for example implement a scheme of reservation-based routing throughout the data plane. Figure 7 is a diagram illustrating signal exchange in an exemplary optical switching network. Three examples are shown labelled Ml, M2 and M3, respectively. Each switch device 100 has a local routing table (see control network layer 163 in figures 2A and 2B). The host enumeration during network initialization (through a management network) assigns host IDs in a contiguous fashion such that the routing tables in each switch device can be strictly local. For example, a computer cluster may have a management network that the data center uses for out-of-band health and availability control of all components. The management network is centrally managed by the system administrator and usually, all hosts, switches, power supplies and thermal management equipment is attached to it for monitoring and setup. Ranges of host IDs map to a specific output port or set of output ports. As an example from figure 6, host A connects to switch device 1 on port K. The switch device 1 is connected to switch device 2 via port L. The local routing table of the switch device 1 thus has port L assigned to path setup requests with destination label B. More specifically, in this example, the host ID enumeration would be created such that contiguous ranges of destination labels map to the same output port at a given switch (B through F map to port L in the example given here). In memory semantic based fabrics but also in static high-performance computing networks such as Infiniband, such enumerations can always be found at setup time and programmed into the local routing tables of all switch devices. This scheme of localized routing tables allows for better overall scalability of the network and does not require the construction of complex composite labels. Furthermore, the host devices 200 do not need a global view of the entire network. Such a view can be constrained to exist in the management network responsible for programming and monitoring all switch devices. The request propagates through the network control plane to the last switch device in the chain (see example Ml in figure 7). Passing through each switch device 100, it either receives an immediate ACK or a delayed ACK - a pending reservation. Upon reception in the final switch device right before the destination host, it will, based on the ACK information of the previous switch devices, either receive an immediate ACK or a delayed ACK. This information propagates back through the control plane of all switch devices. As it passes each switch device on the way back to the initiator host, the reservation is fixed. The final ACK or delayed ACK is reported back to the control PCS of the initiator host and to all switch devices participating in the route to the destination host. If a route between hosts A and B has already been established and host A has not received any link update notifications from the switch control plane in the meantime, it can, together with a new REQ message on the control plane, keep on sending data towards B. The REQ indicates the intended size of the new transaction so that appropriate reservations can be made in the switches on the path from host A to host B. If successful (see example M2), the host A will receive an ACK at some later point in time which indicates that its "speculative” transmission is successful. If on the other hand (see example M3) one of the switches had to reconfigure the associated path due to other requests, its delayed NACK will propagate back to the other switch devices involved in the routing process and to host A to indicate when the next available timeslot for transmission to B is going to be available. This scenario allows completely unscheduled operation but may not be necessary or optimal in many situations. Therefore, the optical switching network 1000, 4000 may be configured to also allow fully and semi scheduled operation in which the hosts perform scheduled requests that require no ACK by the switch devices 100. In this case, it is assumed that contention free operation is guaranteed by software (i.e. compilation or optimization) procedures beforehand on a network global scale and that hosts 200 can simply assume at all times that the requests they issue to the control planes of the switch devices 100 can always be considered granted and perform the appropriate physical switch operation on the optical switch matrix of the data plane. The control plane may furthermore support link quality update control characters. These quality update characters report the bit error rate (BER) state of host receivers on the data plane to the switch device the host is directly attached to. In response to poor BER scenarios at the data plane receiver within a host 200, the switch electronic control plane 160 may be configured to increase the signal strength through optical amplification elements. These amplification elements may be integrated with the optical switch matrix 140 and their gain can be controlled by the electronic control plane 160 of the switch device 100. In this way, a feedback loop is formed that allows the switch device 100 to determine the optimal switch device output power towards the host receiver so that the BER is within safe limits and the power required to achieve this scenario is minimized. The optical switching network may be configured to enable unidirectional communication on the network data plane. Recent developments in computer architecture may lead to an asymmetrical utilization of bidirectional network links. A prime example is the ring-based communication that is often utilized to implement collective operations for a group of devices. In this scenario, the bulk of the data is transmitted from one device in the ring to the succeeding device with only very little data communicated in the opposite direction - mainly flow control, error state and retransmission information. In such asymmetrical cases, the optical switching network can use the control channel as a backchannel for tasks of low data intensity. This means that data information is propagating on the control plane in the opposite direction to the flow of data on the data plane. The control plane "tunnels” the data plane information through the point-to-point control network (here "tunnels" signifies that the control plane is used as some sort slow "tunnel" to get from host B to host A without using the data plane]. The control network is not designed to have high throughput and control information always takes precedence over tunnelled data transmission. However, for cases in which the asymmetry is very large, the advantage of being able to dedicate the other half of the full-duplex datapath link of a host system to another communication partner with a unidirectional communication design improves overall network utilization considerably. The optical switching network may be configured to enable broadcast communication on the network data plane. To implement al!2all(v] collective operations more efficiently, smartOCS can support broadcast operation during which a host A can transfer its data to multiple other hosts. Because the bidirectionality of any existing network protocol would very likely break operation, the control plane of smartOCS can make sure that flow control information is communicated through the control plane to indicate transmission success. 5 A skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the disclosure. Accordingly, the above description of the specific embodiments is made by way of example only and not for the purposes of limitation. It will be clear to 10 the skilled person that minor modifications may be made without significant changes to the operation described.

Claims

1. An optical switching network comprisinga plurality of switch devices;a plurality of hosts, wherein each host comprises at least one network interface controller;a network data plane and a network control plane distributed among the plurality of hosts and the plurality of switch devices forming the network;wherein the said at least one network interface controller is configured to provide network protocol information to the network data plane and control information to the network control plane for routing optical data to be transmitted between a source host and a destination host among the plurality of hosts.

2. The optical switching network as claimed in claim 1, wherein each switch device is configured to receive the control information and pass the optical data to be transmitted.

3. The optical switching network as claimed in claim 1 or 2, wherein each network interface controller (NIC) comprises a NIC data plane and a NIC control plane coupled to an optical physical medium dependent layer.

4. The optical switching network as claimed in claim 3, wherein the NIC data plane comprises a data physical coding sublayer, coupled to a data physical sublayer.

5. The optical switching network as claimed in claim 4, wherein the NIC control plane comprises a set of buffers, a control physical coding sublayer, a control physical sublayer, a protocol circuit, and a phase locked loops and clock distribution circuit.

6. The optical switching network as claimed in any preceding claims, comprising one or more bridge devices; wherein each bridge device comprises at least two ports.

7. The optical switching network as claimed in claim 6, wherein eachbridge device comprises at least one of a buffer and a routing table circuit.

8. The optical switching network as claimed in claim 6 or 7, wherein one or more bridge devices comprise an optical amplifier and / or an optical bypass connection.

9. The optical switching network as claimed in any one of the claims 6 or 8, wherein each bridge device is arranged between two switch devices.

10. The optical switching network as claimed in any of the preceding claims, wherein each switch device comprisesan optical switch matrix coupled to a plurality of ports on a switch data plane; anda switch control plane configured to identify a destination information of the optical data and to configure the optical switch matrix to route the optical data to a destination port among the plurality of ports, based on the destination information.

11. The optical switching network as claimed in claim 10, wherein the switch data plane is all optical.

12. The optical switching network as claimed in any of the preceding claims, wherein at least one switch device is configured to amplifyan amplitude of the optical data transmitted through the optical switch matrix upon detection of a decrease in data signal quality.

13. The optical switching network as claimed in any one of the preceding claims, wherein the optical switching network is implemented as a meta network compatible with different kinds of hosts.

14. The optical switching network as claimed in any one of the preceding claims, wherein the network data plane establishes an optical point-to-point connection between two given hosts and wherein the network control plane is multi-hop such that all connections between two switch devices or between a host and a switch device are established point-to-point, either electrical or optical, between two adjacent devices.

15. The optical switching network as claimed in any one of the preceding claims, wherein when a route cannot be immediately acknowledged by the switch device, the switch device is configured to communicate a time of availability of a path to a requested destination and report it back to the host making the request.

16. The optical switching network as claimed in any one of the preceding claims, wherein the optical switching network is configured to enable unidirectional flow of optical data on the network data plane by sending data on the control plane in the opposite direction to the flow of optical data on the data plane.

17. The optical switching network as claimed in any one of the preceding claims, wherein the optical switching network is configured to enable broadcast communication on the networkdata plane; wherein during broadcast communication a host transfers data to multiple other hosts.

18. The optical switching network as claimed in any preceding claims, wherein the network control plane is configured to transmit flow control information.

19. The optical switching network as claimed in any of the preceding claims, wherein when a host on the network does not have a communication partner on the data plane and becomes a disconnected host, the optical output of the disconnected host is redirected through the switch matrix to its own optical input to form a loopback on the data plane.

20. The optical switching network as claimed in claim 10, wherein the switch control plane comprises a reference oscillator for generating a reference clock, and a phase locked loop (PLL) circuit configured to generate a plurality of PLL clock outputs locked to the reference clock; and wherein the reference clock is embedded in a control plane protocol.

21. The optical switching network as claimed in claim 20, wherein the switch control plane comprises a plurality of transmitters for communicating the control plane protocol to one or more hosts attached to a given switch port; and wherein the plurality of transmitters are coupled to multiplex circuitry, the PLL clock outputs being configured to drive the multiplex circuitry.

22. The optical switching network as claimed in any of the preceding claims, wherein at least one host comprises an equalization circuit adapted to cache equalizer settings for a pair of transmitter / receiver on each side of a physical link associated witha specific connection in the network, and to recall such settings when the same connection is established.

23. The optical switching network as claimed in any one of the claims 4 to 22, wherein the NIC control plane comprises a transmitter, receiver and a clock data recovery circuit (CDR) adapted to recover a clock embedded in a data stream that originates from the switch device it is connected to.

24. The optical switching network as claimed in claim 23 , wherein the data physical sublayer comprises a transmitter, receiver and clock data recovery circuit, and wherein the NIC control plane is configured to store phase accumulator states of the clock data recovery circuit of the data physical sublayer for a plurality of hosts.

25. The optical switching network as claimed in claim 24, wherein the phase locked loops and clock distribution circuit comprises a first phase locked loop configured to lock to a local reference oscillator from a host, and a second phase locked loop circuit configured to lock to the recovered clock; wherein the transmitter, receiver and clock data recovery circuit of the NIC control plane is driven by the first phase locked loop; and wherein the transmitter, receiver and clock data recovery circuit of the NIC data plane is driven by the second phase locked loop circuit.

Images