Shift register unit, display panel, display device and driving method

Abstract

Provided in the embodiments of the present disclosure are a shift register unit, a display panel, a display device and a driving method. The shift register unit comprises: a shift register, which is configured to output a cascade signal by means of a cascade output end; and an output circuit, which is electrically connected to the shift register and is configured to control a driving output end to output a gate scanning signal on the basis of a signal of an output control signal end and a signal of a reference signal end.

Description

Shift register unit, display panel, display device and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a display panel, a display device, and a driving method. Background Art

[0002] With the rapid development of display technology, display panels are showing a trend toward high integration and low cost. Among these technologies, Gate Driver on Array (GOA) technology integrates drive control circuitry onto the array substrate of a display panel to provide scan drive for the display panel. Currently, these drive control circuits typically consist of multiple cascaded shift register units.

[0003] Summary of the Invention

[0004] Some embodiments of the present disclosure provide a shift register unit comprising:

[0005] The shift register is configured to output a cascade signal through a cascade output terminal;

[0006] an output circuit electrically connected to the shift register, wherein the output circuit is configured to control the driving output terminal to output a gate scanning signal according to a signal at the first voltage signal terminal and a signal at the reference signal terminal;

[0007] Wherein, the shift register comprises: a first control subcircuit;

[0008] The first control sub-circuit is electrically connected to the first node, the second node, the second voltage signal terminal, and the first clock signal terminal in the shift register; the first control circuit is configured to control the voltage of the second node according to the voltage of the first node and the signal of the first clock signal terminal.

[0009] In some possible implementations provided by the present disclosure, the shift register includes:

[0010] The input sub-circuit is configured to provide a signal at the input signal terminal to the first node in response to a signal at the second clock signal terminal.

[0011] In some possible implementations provided by the present disclosure, the input sub-circuit includes: a first transistor;

[0012] A first electrode of the first transistor is electrically connected to the input signal terminal, a second electrode of the first transistor is electrically connected to the first node, and a third electrode of the first transistor is electrically connected to the second clock signal terminal.

[0013] In some possible implementations provided by the present disclosure, the first control subcircuit includes: a second transistor, a third transistor, a fourth transistor, and a first capacitor;

[0014] A first electrode of the second transistor is electrically connected to the first clock signal terminal, a second electrode of the second transistor is electrically connected to the second node, and a third electrode of the second transistor is electrically connected to the third node;

[0015] The first electrode of the third transistor is electrically connected to the second voltage signal terminal, the second electrode of the third transistor is electrically connected to the third node, and the third electrode of the third transistor is electrically connected to the first node;

[0016] A first electrode of the fourth transistor is electrically connected to the second voltage signal terminal, a second electrode of the fourth transistor is electrically connected to the second node, and a third electrode of the fourth transistor is electrically connected to the first node;

[0017] A first electrode of the first capacitor is electrically connected to the first clock signal terminal, and a second electrode of the first capacitor is electrically connected to the third node.

[0018] In some possible implementations provided by the present disclosure, the shift register includes:

[0019] The second control subcircuit is electrically connected to the first node, the second node, the second voltage signal terminal and the first clock signal terminal; the second control subcircuit is configured to transmit the signal from the second voltage signal terminal to the first node based on the voltage of the second node and the signal of the first clock signal terminal.

[0020] In some possible implementations provided by the present disclosure, the second control subcircuit includes: a fifth transistor and a sixth transistor;

[0021] a first electrode of the fifth transistor is electrically connected to the second voltage signal terminal, a second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, and a third electrode of the fifth transistor is electrically connected to the second node;

[0022] A second electrode of the sixth transistor is electrically connected to the first node, and a third electrode of the sixth transistor is electrically connected to the first clock signal terminal.

[0023] In some possible implementations provided by the present disclosure, the shift register includes:

[0024] A voltage stabilization subcircuit is electrically connected to the first node, the fourth node and the first voltage signal terminal. The voltage stabilization circuit is configured to transmit the voltage from the first node to the fourth node according to the signal of the first voltage signal terminal.

[0025] In some possible implementations provided by the present disclosure, the voltage stabilization subcircuit includes: a seventh transistor;

[0026] A first electrode of the seventh transistor is electrically connected to the first node, a second electrode of the seventh transistor is electrically connected to the fourth node, and a third electrode of the seventh transistor is electrically connected to the first voltage signal terminal.

[0027] In some possible implementations provided by the present disclosure, the shift register includes:

[0028] The cascade sub-circuit is electrically connected to the second node, the fourth node, the first clock signal terminal and the second voltage signal terminal. The cascade sub-circuit is configured to cause the cascade output terminal to output the cascade signal in response to the voltages of the second node and the fourth node.

[0029] In some possible implementations provided by the present disclosure, the cascade sub-circuit includes: an eighth transistor, a ninth transistor, and a second capacitor;

[0030] A first electrode of the eighth transistor is electrically connected to the first clock signal terminal, a second electrode of the eighth transistor is electrically connected to the cascade output terminal, and a third electrode of the eighth transistor is electrically connected to the fourth node;

[0031] a first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, a second electrode of the ninth transistor is electrically connected to the cascade output terminal, and a third electrode of the ninth transistor is electrically connected to the second node;

[0032] A first electrode of the second capacitor is electrically connected to the fourth node, and a second electrode of the second capacitor is electrically connected to the cascade output terminal.

[0033] In some possible implementations provided by the present disclosure, the cascade sub-circuit includes: a third capacitor;

[0034] A first electrode of the third capacitor is electrically connected to the second voltage signal terminal, and a second electrode of the third capacitor is electrically connected to the cascade output terminal.

[0035] In some possible implementations provided by the present disclosure, the shift register includes:

[0036] The pull-down sub-circuit is electrically connected to the third voltage signal terminal and the first node, and is configured to transmit a signal from the third voltage signal terminal to the first node.

[0037] In some possible implementations provided by the present disclosure, the amplitude of the voltage signal at the third voltage signal terminal is greater than the amplitude of the voltage signal at the first voltage signal terminal.

[0038] In some possible implementations provided by the present disclosure, the pull-down sub-circuit includes: a twelfth transistor;

[0039] The first electrode of the twelfth transistor is electrically connected to the third voltage signal terminal, the second electrode of the twelfth transistor is electrically connected to the first node, and the third electrode of the twelfth transistor is electrically connected to the fourth node.

[0040] In some possible implementations provided by the present disclosure, the pull-down sub-circuit includes: a twelfth transistor;

[0041] A first electrode of the twelfth transistor is electrically connected to the third voltage signal terminal, a second electrode of the twelfth transistor is electrically connected to the first node, and a third electrode of the twelfth transistor is electrically connected to the first node.

[0042] In some possible implementations provided by the present disclosure, the output circuit includes: a tenth transistor and an eleventh transistor;

[0043] A first electrode of the tenth transistor is electrically connected to the reference signal terminal, a second electrode of the tenth transistor is electrically connected to the driving output terminal, and a third electrode of the tenth transistor is electrically connected to the first node;

[0044] A first electrode of the eleventh transistor is electrically connected to the first voltage signal terminal, a second electrode of the eleventh transistor is electrically connected to the driving output terminal, and a third electrode of the eleventh transistor is electrically connected to the second node.

[0045] In some possible implementations provided by the present disclosure, the output circuit includes: a tenth transistor, an eleventh transistor, and a thirteenth transistor;

[0046] a first electrode of the tenth transistor is electrically connected to the reference signal terminal, a second electrode of the tenth transistor is electrically connected to the driving output terminal, and a third electrode of the tenth transistor is electrically connected to the second electrode of the thirteenth transistor;

[0047] A first electrode of the eleventh transistor is electrically connected to the first voltage signal terminal, a second electrode of the eleventh transistor is electrically connected to the driving output terminal, and a third electrode of the eleventh transistor is electrically connected to the second node.

[0048] A first electrode of the thirteenth transistor is electrically connected to the first node, and a third electrode of the thirteenth transistor is electrically connected to the first voltage signal terminal.

[0049] In some possible implementations provided by the present disclosure, the output circuit further includes: a fourth capacitor;

[0050] A first electrode of the fourth capacitor is electrically connected to the first voltage signal terminal, and a second electrode of the fourth capacitor is electrically connected to the second node.

[0051] In some possible implementations provided by the present disclosure, the signal at the reference signal terminal and the signal at the first clock signal terminal are inverted signals of each other.

[0052] In some possible implementations provided by the present disclosure, the signal at the first clock signal terminal and the signal at the second clock signal terminal are not valid level signals at the same time.

[0053] Some embodiments of the present disclosure provide a display panel including:

[0054] A base substrate, comprising a display area and a non-display area;

[0055] The display area includes:

[0056] multiple sub-pixels;

[0057] a plurality of scan lines, wherein a row of the sub-pixels in the plurality of sub-pixels is electrically connected to at least one of the scan lines;

[0058] The non-display area includes:

[0059] The gate driving circuit includes a plurality of the above-mentioned shift register units, wherein the driving output end of each of the plurality of shift register units is electrically connected to at least one of the plurality of scan lines.

[0060] In some possible implementations provided by the present disclosure, the further comprising: an input signal line electrically connected to the gate driving circuit and disposed in the non-display area, a first voltage signal line away from the display area, a first clock signal line, and a second clock signal line;

[0061] Any one of the input signal line, the first voltage signal line away from the display area, the first clock signal line and the second clock signal line extends along a first direction, the gate line extends along a second direction, and the first direction intersects the second direction.

[0062] In some possible implementations provided in the present disclosure, the input signal line, the first clock signal line, the second clock signal line and the first voltage signal line away from the display area are arranged in sequence on the substrate substrate along a direction close to the display area, and are located on the side of the shift register unit away from the display area.

[0063] In some possible implementations provided by the present disclosure, the input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line away from the display area are arranged on the same layer.

[0064] In some possible embodiments provided in the present disclosure, the input signal line, the first voltage signal line away from the display area, the first clock signal line and the second clock signal line are arranged in sequence along the direction close to the display area, and are arranged on the side of the shift register unit away from the display area.

[0065] In some possible implementations provided by the present disclosure, the input signal line and the first voltage signal line away from the display area are arranged on the same layer, the first clock signal line and the second clock signal line are arranged on the same layer, and the input signal line, the first voltage signal line away from the display area and the first clock signal line, the second clock signal line are arranged on different layers.

[0066] In some possible implementations provided by the present disclosure, the present invention further includes: a second voltage signal line electrically connected to the gate driving circuit and disposed in the non-display area, wherein the second voltage signal line extends along the first direction.

[0067] In some possible implementations provided by the present disclosure, the second voltage signal line is arranged on a side of the first voltage signal line that is away from the display area and close to the display area.

[0068] In some possible implementations provided by the present disclosure, the present invention further includes: a third voltage signal line electrically connected to the gate driving circuit and disposed in the non-display area, wherein the third voltage signal line extends along the first direction.

[0069] In some possible implementations provided by the present disclosure, the third voltage signal line is disposed on a side of the second voltage signal line close to the display area.

[0070] In some possible implementations provided by the present disclosure, it also includes: a third clock signal line, a fourth clock signal line, and a first voltage signal line close to the display area, which are electrically connected to the gate drive circuit and arranged in the non-display area, and the third clock signal line, the fourth clock signal line, and the first voltage signal line close to the display area extend along the first direction.

[0071] In some possible implementations provided by the present disclosure, any one of the third clock signal line and the fourth clock signal line is disposed on a side of the third voltage signal line close to the display area;

[0072] The first voltage signal line close to the display area is located on a side of any one of the third clock signal line and the fourth clock signal line close to the display area.

[0073] In some possible implementations provided in the present disclosure, the reference signal end of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the reference signal end of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

[0074] In some possible implementations provided by the present disclosure, the first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line;

[0075] The first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.

[0076] In some possible implementations provided in the present disclosure, the width of any one of the input signal line, the first voltage signal line, the second voltage signal line, and the third voltage signal line along the second direction is smaller than the width of any one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line along the second direction.

[0077] In some possible implementations provided by the present disclosure, the shift register unit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor, and a first capacitor;

[0078] At least a portion of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor and the first capacitor is located between the first voltage signal line and the second voltage signal line.

[0079] In some possible implementations provided by the present disclosure, the shift register unit includes: a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a twelfth transistor, and a second capacitor;

[0080] At least a portion of any one of the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the twelfth transistor and the second capacitor is located between the second voltage signal line and the third voltage signal line.

[0081] In some possible implementations provided by the present disclosure, the active layer of the twelfth transistor extends along the first direction, at least a portion of either the first electrode or the second electrode of the twelfth transistor extends along the second direction, and the third electrode of the twelfth transistor extends along the second direction.

[0082] In some possible implementations provided by the present disclosure, the shift register unit includes: a tenth transistor, an eleventh transistor, and a third capacitor;

[0083] At least a portion of any one of the tenth transistor, the eleventh transistor and the third capacitor is located on a side of the first voltage signal line close to the display area close to the display area;

[0084] An orthographic projection of the first voltage signal line close to the display area on the base substrate partially overlaps with an orthographic projection of the third capacitor on the base substrate.

[0085] In some possible implementations provided by the present disclosure, a channel width of the active layer of the tenth transistor is greater than a channel width of the active layer of the eighth transistor.

[0086] In some possible implementations provided by the present disclosure, a channel width of the active layer of the tenth transistor is not less than 90 micrometers.

[0087] In some possible implementations provided by the present disclosure, a channel width of the active layer of the eighth transistor is no greater than 50 micrometers.

[0088] In some possible implementations provided by the present disclosure, a channel width of the active layer of the eleventh transistor is greater than a channel width of the active layer of the ninth transistor.

[0089] In some possible implementations provided by the present disclosure, a channel width of the active layer of the eleventh transistor is not less than 90 micrometers.

[0090] In some possible implementations provided by the present disclosure, a channel width of the active layer of the ninth transistor is no greater than 50 micrometers.

[0091] Some embodiments of the present disclosure provide a display device including: the above-mentioned display panel.

[0092] Some embodiments of the present disclosure provide a driving method, including:

[0093] The input sub-circuit provides the signal of the input signal terminal to the first node under the control of the signal of the second clock signal terminal;

[0094] a first control subcircuit, controlling the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal;

[0095] a second control subcircuit, under the control of the voltage of the second node and the signal of the first clock signal terminal, providing a signal of a second voltage signal terminal to the first node;

[0096] a voltage stabilization subcircuit, under control of a signal from the first voltage signal terminal, providing the voltage of the first node to a fourth node;

[0097] a cascade sub-circuit, under the control of the voltages of the second node and the fourth node, providing a signal from the second voltage signal terminal or the first clock signal terminal to the cascade output terminal;

[0098] The output circuit provides a signal from a reference signal terminal or a first voltage signal terminal to a driving output terminal under the control of the voltages of the first node and the second node.

[0099] In some possible implementations provided by the present disclosure, the shift register unit further includes: a pull-down sub-circuit;

[0100] The method further includes: the pull-down sub-circuit providing a signal from a third voltage signal terminal to the first node under control of the voltage of the first node or the fourth node.

[0101] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0103] FIG1 is a schematic diagram of some structures of a shift register unit provided by an embodiment of the present disclosure;

[0104] FIG2 is another schematic diagram of the structure of the shift register unit provided by the embodiment of the present disclosure;

[0105] FIG3 is one of the equivalent circuit diagrams of the shift register unit provided in an embodiment of the present disclosure;

[0106] FIG4 is a schematic diagram of some further structures of the shift register unit provided by an embodiment of the present disclosure;

[0107] FIG5 is a second equivalent circuit diagram of the shift register unit provided in an embodiment of the present disclosure;

[0108] FIG6 is a third equivalent circuit diagram of the shift register unit provided in an embodiment of the present disclosure;

[0109] FIG7 is a fourth equivalent circuit diagram of the shift register unit provided in an embodiment of the present disclosure;

[0110] FIG8 is a fifth equivalent circuit diagram of the shift register unit provided in an embodiment of the present disclosure;

[0111] FIG9 is a sixth equivalent circuit diagram of the shift register unit provided in an embodiment of the present disclosure;

[0112] FIG10 is a signal timing simulation diagram of the shift register unit provided in FIG3 and FIG5 to FIG9;

[0113] FIG11 is a comparison diagram of signals at the driving output ends of different shift register units;

[0114] FIG12 is a schematic structural diagram of a display device;

[0115] FIG13 is a schematic diagram of a planar structure of a display substrate;

[0116] FIG14 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0117] FIG15 is an operation timing diagram of the pixel driving circuit corresponding to FIG14 ;

[0118] FIG16 is a schematic diagram of a cascade connection of a gate driving circuit of a display device;

[0119] FIG17 is a schematic diagram of the layout structure of a shift register unit provided in an embodiment of the present disclosure;

[0120] FIG18 is a schematic diagram of the structure of FIG17 after the semiconductor layer pattern is formed;

[0121] FIG19 is a schematic structural diagram of the first conductive layer pattern in FIG17 ;

[0122] FIG20 is a schematic diagram of the structure of FIG17 after the first conductive layer pattern is formed;

[0123] FIG21 is a schematic structural diagram of the second conductive layer pattern in FIG17;

[0124] FIG22 is a schematic diagram of the structure of FIG17 after forming a second conductive layer pattern;

[0125] FIG23 is a schematic structural diagram of the third insulating layer pattern in FIG17;

[0126] FIG24 is a schematic diagram of the structure of FIG17 after forming a third insulating layer pattern;

[0127] FIG25 is a schematic structural diagram of the third conductive layer pattern in FIG17;

[0128] FIG26 is a schematic diagram of the structure of FIG17 after forming a third conductive layer pattern;

[0129] FIG27 is a schematic structural diagram of the fourth insulating layer pattern in FIG17;

[0130] FIG28 is a schematic diagram of the structure of FIG17 after forming a fourth insulating layer pattern;

[0131] FIG29 is a schematic structural diagram of the fourth conductive layer pattern in FIG17;

[0132] FIG30 is a schematic diagram of the structure of FIG17 after forming a fourth conductive layer pattern;

[0133] FIG31 is a schematic diagram of the layout structure of another shift register unit provided in an embodiment of the present disclosure;

[0134] FIG32 is a schematic structural diagram of the first conductive layer pattern in FIG31;

[0135] FIG33 is a schematic diagram of the structure of FIG31 after the first conductive layer pattern is formed;

[0136] FIG34 is a schematic structural diagram of the second conductive layer pattern in FIG31;

[0137] FIG35 is a schematic diagram of the structure of FIG31 after forming a second conductive layer pattern;

[0138] FIG36 is a schematic structural diagram of the third insulating layer pattern in FIG31;

[0139] FIG37 is a schematic diagram of the structure of FIG31 after forming a third insulating layer pattern;

[0140] FIG38 is a schematic structural diagram of the third conductive layer pattern in FIG31;

[0141] FIG39 is a schematic diagram of the structure of FIG31 after forming a third conductive layer pattern;

[0142] FIG40 is a schematic structural diagram of the fourth insulating layer pattern in FIG31;

[0143] FIG41 is a schematic diagram of the structure of FIG31 after forming a fourth insulating layer pattern;

[0144] FIG42 is a schematic structural diagram of the fourth conductive layer pattern in FIG31;

[0145] FIG43 is a schematic diagram of the structure of FIG31 after the fourth conductive layer pattern is formed. DETAILED DESCRIPTION

[0146] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0147] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "electrically connected" or "connected" are not limited to physical or mechanical electrical connections, but may include electrical connections, whether direct or indirect.

[0148] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0149] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0150] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0151] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0152] The display substrate includes a pixel driver circuit, a light-emitting element, and a gate driver circuit. The gate driver circuit is configured to provide a third-pole signal to the pixel driver circuit, enabling the pixel driver circuit to drive the light-emitting element to emit light. The display substrate utilizes low-temperature polysilicon (LTPS) technology, which boasts advantages such as high resolution, high response speed, high brightness, and a high aperture ratio. While popular in the market, LTPS technology also has drawbacks, such as high production costs and high power consumption. This is why low-temperature polycrystalline oxide (LTPO) technology has emerged. Compared to LTPS technology, the pixel driver circuit includes low-temperature polysilicon transistors. In LTPO technology, the pixel driver circuit includes both low-temperature polysilicon transistors and metal oxide transistors. Metal oxide transistors have lower leakage current, resulting in faster pixel response. The display substrate incorporates an additional oxide layer, which reduces the energy required to activate the pixels, thereby reducing power consumption during screen display. The development of LTPO technology requires the gate driver circuit to provide a third-pole signal that meets the required potential.

[0153] The present disclosure provides a shift register unit, as shown in FIG1 , comprising:

[0154] The shift register 100 is configured to output a cascade signal through a cascade output terminal OUT1;

[0155] The output circuit 200 is electrically connected to the shift register 100 . The output circuit 200 is configured to control the driving output terminal OUT2 to output a gate scanning signal according to the signal of the reference signal terminal VREF and the signal of the first voltage signal terminal V1 .

[0156] In some embodiments of the present disclosure, as shown in FIG2 , the shift register 100 includes:

[0157] The input sub-circuit 110 is configured to provide a signal from the input signal terminal IN to the first node N1 according to a signal from the second clock signal terminal CK2;

[0158] A first control subcircuit 120, wherein the first control subcircuit 120 is electrically connected to the first clock signal terminal CK1, the second voltage signal terminal V2, the first node N1, and the second node N2, and is configured to control the voltage of the second node N2 according to the voltage of the first node N1 and the signal of the first clock signal terminal CK1;

[0159] The second control sub-circuit 130 is configured to transmit the signal from the second voltage signal terminal V2 to the first node N1 according to the voltage of the second node N2 and the signal of the first clock signal terminal CK1;

[0160] The potential stabilization circuit 140 is configured to transmit the voltage from the first node N1 to the fourth node N4 according to the signal of the first voltage signal terminal V1;

[0161] The cascade sub-circuit 150 is configured to control the cascade output terminal OUT1 to output a cascade signal according to the voltages of the second node N2 and the fourth node N4.

[0162] In some embodiments of the present disclosure, as shown in Figure 3, the input sub-circuit 110 includes: a first transistor T1; wherein the first electrode of the first transistor T1 is electrically connected to the input signal terminal IN, the second electrode of the first transistor T1 is electrically connected to the first node N1, and the third electrode of the first transistor T1 is electrically connected to the second clock signal terminal CK2.

[0163] In some embodiments of the present disclosure, as shown in FIG3 , the first control subcircuit 120 includes: a second transistor T2 , a third transistor T3 , a fourth transistor T4 , and a first capacitor C1 ;

[0164] A first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, a second electrode of the second transistor T2 is electrically connected to the second node N2, and a third electrode of the second transistor T2 is electrically connected to the third node N3; a first electrode of the third transistor T3 is electrically connected to the second voltage signal terminal V2, a second electrode of the third transistor T3 is electrically connected to the third node N3, and a third electrode of the third transistor T3 is electrically connected to the first node N1; a first electrode of the fourth transistor T4 is electrically connected to the second voltage signal terminal V2, a second electrode of the fourth transistor T4 is electrically connected to the second node N2, and a third electrode of the fourth transistor T4 is electrically connected to the first node N1; a first electrode of the first capacitor C1 is electrically connected to the third node N3, and a second electrode of the first capacitor C1 is electrically connected to the first clock signal terminal CK1.

[0165] In some embodiments of the present disclosure, the first capacitor C1 may couple the signal at the first clock signal terminal to the third node N3 .

[0166] In some embodiments of the present disclosure, as shown in FIG3 , the second control subcircuit 130 includes: a fifth transistor T5 and a sixth transistor T6 ;

[0167] A first electrode of the fifth transistor T5 is electrically connected to the second voltage signal terminal V2, a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6, and a third electrode of the fifth transistor T5 is electrically connected to the second node N2; a second electrode of the sixth transistor T6 is electrically connected to the first node N1, and a third electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal CK1.

[0168] In some embodiments of the present disclosure, as shown in FIG3 , the voltage stabilization sub-circuit 140 includes: a seventh transistor T7 ; wherein a first electrode of the seventh transistor T7 is electrically connected to the first node N1 , a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4 , and a third electrode of the seventh transistor T7 is electrically connected to the first voltage signal terminal V1 .

[0169] In some embodiments of the present disclosure, as shown in FIG3 , the cascade sub-circuit 150 includes: an eighth transistor T8 , a ninth transistor T9 , and a second capacitor C2 ;

[0170] A first electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CK1, a second electrode of the eighth transistor T8 is electrically connected to the cascade output terminal OUT1, and a third electrode of the eighth transistor T8 is electrically connected to the fourth node N1; a first electrode of the ninth transistor T9 is electrically connected to the second voltage signal terminal V2, a second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal OUT1, and a third electrode of the ninth transistor T9 is electrically connected to the second node N2; a first electrode of the second capacitor C2 is electrically connected to the fourth node N4, and a second electrode of the second capacitor C2 is electrically connected to the cascade output terminal OUT1.

[0171] In some embodiments of the present disclosure, the second capacitor C2 can maintain a voltage difference between the fourth node N4 and the signal at the cascade output terminal OUT1 .

[0172] In some embodiments of the present disclosure, as shown in FIG3 , the output circuit 200 includes: a tenth transistor T10 and an eleventh transistor T11 ;

[0173] A first electrode of the tenth transistor T10 is electrically connected to the reference signal terminal VREF, a second electrode of the tenth transistor T10 is electrically connected to the driving output terminal OUT2, and a third electrode of the tenth transistor T10 is electrically connected to the first node N1; a first electrode of the eleventh transistor T11 is electrically connected to the first voltage signal terminal V1, a second electrode of the eleventh transistor T11 is electrically connected to the driving output terminal OUT2, and a third electrode of the eleventh transistor T11 is electrically connected to the second node N2.

[0174] In some embodiments of the present disclosure, as shown in FIG4 , the shift register 100 further includes a pull-down sub-circuit 160 configured to transmit a signal from the third voltage signal terminal V3 to the first node N1. The amplitude of the voltage signal at the third voltage signal terminal V3 is greater than the amplitude of the voltage signal at the first voltage signal terminal V1. That is, the absolute value of the voltage of the signal at the third voltage signal terminal V3 is greater than the absolute value of the voltage of the signal at the first voltage signal terminal V1.

[0175] In some embodiments of the present disclosure, as shown in Figure 5, the pull-down sub-circuit 160 includes: a twelfth transistor T12; wherein, the first electrode of the twelfth transistor T12 is electrically connected to the third voltage signal terminal V3, the second electrode of the twelfth transistor T12 is electrically connected to the first node N1, and the third electrode of the twelfth transistor T12 is electrically connected to the fourth node N4.

[0176] In some embodiments of the present disclosure, as shown in Figure 6, the pull-down sub-circuit 160 includes: a twelfth transistor T12; wherein, the first electrode of the twelfth transistor T12 is electrically connected to the third voltage signal terminal V3, the second electrode of the twelfth transistor T12 is electrically connected to the first node N1, and the third electrode of the twelfth transistor T12 is electrically connected to the first node N1.

[0177] The shift register unit provided in the present disclosure can pull down the signal of the first node N1 to a low-level signal with a lower voltage value by setting a pull-down sub-circuit 160, so that some transistors in the shift register unit can be fully turned on, and thus the voltage of the output signal of the shift register unit can reach a predetermined voltage, thereby improving the driving capability of the shift register unit, and can ensure the conduction capability of the transistors in the pixel driving circuit, thereby improving the performance of the pixel driving circuit and the display effect of the display substrate.

[0178] In some embodiments of the present disclosure, as shown in FIG7 , the cascade sub-circuit 150 further includes: a third capacitor C3 ; wherein a first electrode of the third capacitor C3 is electrically connected to the second voltage signal terminal V2 , and a second electrode of the third capacitor C3 is electrically connected to the cascade output terminal OUT1 .

[0179] In the present disclosure, since the signal output by the cascade output terminal OUT1 is a cascade signal, that is, the signal line connected to the cascade output terminal OUT1 does not flow through the display area where the pixel driving circuit is located, that is, the load on the signal line connected to the cascade output terminal OUT1 is small and is easily affected by the parasitic capacitance of some transistors in the output circuit, thereby causing the signal at the cascade output terminal OUT1 to fluctuate. In the present disclosure, by providing a third capacitor C3, the signal output by the cascade output terminal OUT1 can be made more stable, thereby improving the performance of the shift register unit.

[0180] In some embodiments of the present disclosure, as shown in FIG8 , the output circuit 200 may further include: a fourth capacitor C4 ; wherein a first electrode of the fourth capacitor C4 is electrically connected to the second node N2 , and a second electrode of the fourth capacitor C4 is electrically connected to the first voltage signal terminal V1 .

[0181] In some embodiments of the present disclosure, the fourth capacitor C4 can ensure the stability of the signal at the second node N2.

[0182] In some embodiments of the present disclosure, as shown in Figure 9, the output circuit 200 further includes: a thirteenth transistor T13; wherein, the first electrode of the thirteenth transistor T13 is electrically connected to the first node N1, the second electrode of the thirteenth transistor T13 is electrically connected to the third electrode of the tenth transistor T10, and the third electrode of the thirteenth transistor T13 is electrically connected to the first voltage signal terminal V1.

[0183] In some embodiments of the present disclosure, the thirteenth transistor T13 is a continuously conducting transistor, which can ensure the stability of the signal at the third electrode of the tenth transistor T10, avoid large deviation of the output signal of the shift register unit, and ensure the stability of the output signal of the shift register unit.

[0184] In some embodiments of the present disclosure, transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0185] In some embodiments of the present disclosure, the first to thirteenth transistors T1 to T13 may all be P-type transistors.

[0186] In some embodiments of the present disclosure, the first voltage signal terminal V1 and the third voltage signal terminal V3 continuously provide low-level signals, and the second voltage signal terminal V2 continuously provides a high-level signal.

[0187] In some embodiments of the present disclosure, the amplitude of the voltage signal at the third voltage signal terminal V3 is greater than the amplitude of the voltage signal at the first voltage signal terminal V1 .

[0188] In some embodiments of the present disclosure, a signal at any one of the reference signal terminal VREF, the first clock signal terminal CK1 and the second clock signal terminal CK2 may be a periodic pulse signal.

[0189] In some embodiments of the present disclosure, a signal at any one of the reference signal terminal VREF, the first clock signal terminal CK1 and the second clock signal terminal CK2 may be a clock signal.

[0190] In some embodiments of the present disclosure, the signal at the reference signal terminal VREF and the signal at the first clock signal terminal CK1 are inverted signals, or they may not be inverted signals. When the signal at the reference signal terminal VREF and the signal at the first clock signal terminal CK1 are inverted signals, when the signal at the reference signal terminal VREF is a valid level signal, the signal at the first clock signal terminal CK1 is an inactive level signal; when the signal at the reference signal terminal VREF is an inactive level signal, the signal at the first clock signal terminal CK1 is a valid level signal.

[0191] In some embodiments of the present disclosure, the signal at the first clock signal terminal CK1 and the signal at the second clock signal terminal CK2 are not simultaneously active level signals. For example, when the signal at the first clock signal terminal CK1 is active level signal, the signal at the second clock signal terminal CK2 is inactive level signal; and when the signal at the second clock signal terminal CK2 is active level signal, the signal at the first clock signal terminal CK1 is inactive level signal.

[0192] In some embodiments of the present disclosure, the signals of the cascade output terminal OUT1 and the driving output terminal OUT2 can be single pulse signals, and the signal of the cascade output terminal OUT1 and the signal of the driving output terminal OUT2 can be mutually inverted signals, that is, when the signal of the cascade output terminal OUT1 is a high-level signal, the signal of the driving output terminal OUT2 is a low-level signal; when the signal of the cascade output terminal OUT1 is a low-level signal, the signal of the driving output terminal OUT2 is a high-level signal.

[0193] In some embodiments of the present disclosure, the cascade output terminal OUT1 is configured to output a cascade signal, which may be a low-level signal, and the drive output terminal OUT2 is configured to output a gate scan signal, which may be a high-level signal.

[0194] Figure 10 is a signal timing simulation diagram for the shift register unit provided in Figures 3 and 5 through 9. Figure 10 is illustrated using the example of a shift register unit in which all transistors are P-type transistors. It is understood that, in this case, the first voltage signal terminal V1 provides a first low-level signal VGL1, the second voltage signal terminal V2 provides a high-level signal VGH, and the third voltage signal terminal V3 provides a second low-level signal VGL2. At this point, the second low-level signal VGL2 provided by the third voltage signal terminal V3 is lower than the first low-level signal VGL1 provided by the first voltage signal terminal V1.

[0195] In some embodiments of the present disclosure, for the shift register units provided in FIG. 3 and FIG. 5 to FIG. 9 , since the third electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1 , the seventh transistor T7 is continuously turned on.

[0196] 5 and 10 , the operation process of the control shift register unit provided in FIG5 includes the following stages:

[0197] During the first phase t1, i.e., the input phase, the input signal terminal IN, the reference signal terminal VREF, and the second clock signal terminal CK2 provide low-level signals, while the first clock signal terminal CK1 provides a high-level signal. At this point, the first transistor T1 is turned on, and the low-level signal provided by the input signal terminal IN is written to the first node N1. Since the first voltage signal terminal V1 continuously provides the low-level signal VGL1, the seventh transistor T7 remains turned on. At this point, the low-level signal at the first node N1 is written to the fourth node N4 via the seventh transistor T7. The eighth transistor T8 is turned on, and the high-level signal provided by the first clock signal terminal CK1 is written to the cascade output terminal OUT1. The low-level signal at the first node N1 is written to the third electrode of the tenth transistor T10 via the thirteenth transistor T13. The tenth transistor T10 is turned on, and the low-level signal provided by the reference signal terminal VREF is written to the driver output terminal OUT2. Simultaneously, the twelfth transistor T12 is turned on, and the second low-level signal VGL2 provided by the third voltage signal terminal V3 is written to the first node N1, maintaining the signal at the first node N1 at a low level. The third transistor T3 and the fourth transistor T4 are turned on, and the high-level signal VGH provided by the second voltage signal terminal V2 is written to the second node N2 and the third node N3, respectively. At this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are all turned off. The first clock signal terminal CK1 provides a high-level signal, and the sixth transistor T6 is turned off. The first capacitor C1 can couple the high-level signal provided by the first clock signal terminal CK1 to the third node N3, and the second capacitor C2 can maintain the voltage difference between the fourth node N4 and the cascade output terminal OUT1. At this time, the cascade output terminal OUT1 outputs the high-level signal provided by the first clock signal terminal CK1, driving the output terminal OUT2 to output the low-level signal provided by the reference signal terminal VREF.

[0198] During the second phase t2, or output phase, the first clock signal terminal CK1 provides a low-level signal, while the input signal terminal IN, the reference signal terminal VREF, and the second clock signal terminal CK2 provide high-level signals. At this point, the first transistor T1 is turned off, allowing the second capacitor C2 to discharge, and the voltage at the first node N1 remains low. Because the first voltage signal terminal V1 continues to provide the low-level signal VGL1, the seventh transistor T7 remains on. At this point, the low-level signal at the first node N1 is written to the fourth node N4 via the seventh transistor T7, the eighth transistor T8 turns on, and the low-level signal provided by the first clock signal terminal CK1 is written to the cascade output terminal OUT1. The low-level signal at the first node N1 is written to the third electrode of the tenth transistor T10, which turns on, and the high-level signal provided by the reference signal terminal VREF is written to the driver output terminal OUT2. Simultaneously, the twelfth transistor T12 turns on, and the second low-level signal VGL2 provided by the third voltage signal terminal V3 is written to the first node N1. This further lowers the voltage at the first node N1, causing the eighth and tenth transistors T8 and T10 to fully turn on. The third and fourth transistors T3 and T4 are turned on, and the high-level signal VGH provided by the second voltage signal terminal V2 is written to the second and third nodes N2 and N3, respectively. At this time, the second, fifth, ninth, and eleventh transistors T2 and T11 are all turned off. The third transistor T3 is turned on, and the high-level signal VGH provided by the second voltage signal terminal V2 is written to the third node N3. At this time, the first clock signal terminal CK1 is still coupled to the third node N3 via the first capacitor C1, but the voltage of the third node N3 is still controlled by the second voltage signal terminal V2. In the output phase, the cascade output terminal OUT1 outputs the low-level signal provided by the first clock signal terminal CK1, driving the output terminal OUT2 to output the high-level signal provided by the reference signal terminal VREF.

[0199] In the third phase t3, the input signal terminal IN and the first clock signal terminal CK1 provide high-level signals, the reference signal terminal VREF provides a low-level signal, and the second clock signal terminal CK2 initially maintains a high-level signal before switching to a low-level signal. While the second clock signal terminal CK2 maintains a high-level signal, the first transistor T1 is turned off, the first node N1 is in a floating state, and the voltage at the first node N1 is low. The low-level signal is written to the fourth node N4 via the continuously conductive seventh transistor T7. The eighth and tenth transistors T8 and T10 are turned on, the high-level signal provided by the first clock signal terminal CK1 is written to the cascade output terminal OUT1, and the low-level signal provided by the reference signal terminal VREF is written to the driver output terminal OUT2. The third and fourth transistors T3 and T4 are turned on, and the high-level VGH signal provided by the second voltage signal terminal V2 is written to the second and third nodes N2 and N3, respectively. At this time, the second transistor T2, the fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are all turned off. The first clock signal terminal CK1 provides a high-level signal, and the sixth transistor T6 is turned off. Therefore, when the second clock signal terminal CK2 maintains a high-level signal, the cascade output terminal OUT1 outputs the high-level signal provided by the first clock signal terminal CK1, and the driver output terminal OUT2 outputs the low-level signal provided by the reference signal terminal VREF. When the second clock signal terminal CK2 transitions to a low-level signal, the first transistor T1 turns on, and the high-level signal provided by the input signal terminal IN is written to the first node N1. At this time, the third transistor T3 and the fourth transistor T4 turn off, and the high-level signal at the first node N1 is written to the fourth node N4 via the continuously conductive seventh transistor T7. The eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 turn off. Because the first clock signal terminal CK1 transitions from a low-level signal to a high-level signal, and due to the coupling effect of the first capacitor C1, the voltage at the third node N3 remains high, and the second transistor T2 turns off. The second node N2 is in a floating state, and the voltage at the second node N2 is high at this time. The fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 turn off. Therefore, when the second clock signal terminal CK2 jumps to a low level signal, the cascade output terminal OUT1 and the driver output terminal OUT2 are both in a floating state. At this time, the cascade output terminal OUT1 outputs a high level signal and the driver output terminal OUT2 outputs a low level signal.

[0200] In the fourth phase t4, the input signal terminal IN, the reference signal terminal VREF, and the second clock signal terminal CK2 provide high-level signals, while the first clock signal terminal CK1 provides a low-level signal. At this point, the first transistor T1 is turned off, the first node N1 is in a floating state, and the voltage at the first node N1 is high. The third transistor T3 and the fourth transistor T4 are turned off. The high-level signal at the first node N1 is written to the fourth node N4 via the continuously turned-on seventh transistor T7. The eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 are turned off. Due to the transition of the first clock signal terminal CK1 from a high level to a low level, and due to the coupling effect of the first capacitor C1, the voltage at the third node N3 is low, and the second transistor T2 is turned on. The low-level signal provided by the first clock signal terminal CK1 is written to the second node N2 via the second transistor T2. The fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 are turned on, and the sixth transistor T6 is also turned on. The high-level signal VGH provided by the second voltage signal terminal V2 is written to the first node N1 via the fifth transistor T5 and the sixth transistor T6, and is then written to the cascade output terminal OUT1 via the ninth transistor T9. The low-level signal VGL1 provided by the first voltage signal terminal V1 is written to the driver output terminal OUT2 via the eleventh transistor T11. At this stage, the cascade output terminal OUT1 outputs the high-level signal provided by the second voltage signal terminal V2, and the driver output terminal OUT2 outputs the low-level signal provided by the first voltage signal terminal V1.

[0201] The working process of the shift register unit includes: a plurality of third phases t3 and fourth phases t4, and the third phases t3 and the fourth phase t4 work alternately.

[0202] The difference between the shift register unit provided in FIG3 and the shift register unit provided in FIG5 is that the shift register unit provided in FIG5 includes a twelfth transistor T12, while the shift register unit provided in FIG3 does not have the twelfth transistor T12. Apart from this, the operation process of the shift register unit provided in FIG3 is the same as that of the shift register unit provided in FIG5.

[0203] The setting of the twelfth transistor T12 in the present disclosure can pull the first node N1 down to the signal of the third voltage signal terminal V3 with a lower voltage value, thereby improving the conduction degree of the eighth transistor T8 and the tenth transistor T10, so that the eighth transistor T8 and the tenth transistor T10 can be fully turned on.

[0204] The shift register unit provided in FIG6 differs from the shift register unit provided in FIG5 in that the third electrode of the twelfth transistor T12 is connected to a different node. FIG5 illustrates the connection between the third electrode of the twelfth transistor T12 and the fourth node N4, while FIG6 illustrates the connection between the third electrode of the twelfth transistor T12 and the first node N1. Because the signals at the first node N1 and the fourth node N4 are both high-level signals or both low-level signals, the twelfth transistors T12 in the shift register units provided in FIG5 and FIG6 are both turned on or turned off at the same time. Therefore, the operation process of the shift register unit provided in FIG5 is the same as the operation process of the shift register unit provided in FIG6.

[0205] The shift register unit provided in FIG7 differs from the shift register unit provided in FIG5 in that the shift register unit provided in FIG7 further includes a third capacitor C3. The third capacitor C3 can be used to maintain the stability of the signal at the cascade output terminal OUT1 and does not affect the operation of the shift register unit. Therefore, the operation of the shift register unit provided in FIG5 is the same as the operation of the shift register unit provided in FIG7.

[0206] The shift register unit provided in FIG8 differs from the shift register unit provided in FIG5 in that the shift register unit provided in FIG8 further includes a fourth capacitor C4. The fourth capacitor C4 can be used to maintain the stability of the voltage of the second node N2 and does not have any other impact on the operation process of the shift register unit. Therefore, the operation process of the shift register unit provided in FIG8 is the same as the operation process of the shift register unit provided in FIG7.

[0207] The shift register unit provided in FIG9 differs from the shift register unit provided in FIG8 in that the shift register unit provided in FIG9 further includes a thirteenth transistor T13. Because the third electrode of the thirteenth transistor T13 is electrically connected to the first voltage signal terminal V1, the thirteenth transistor T13 is continuously turned on. Therefore, the thirteenth transistor T13 can be equivalent to a section of wire and will not affect the operation process of other transistors in the shift register unit. Therefore, the operation process of the shift register unit provided in FIG9 is the same as the operation process of the shift register unit provided in FIG5.

[0208] It is understood that in some embodiments of the present disclosure, the shift register unit may include: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; or may include: a first capacitor C1 and a second capacitor C2; or may include: a first capacitor C1, a second capacitor C2, and a third capacitor C3; or may include: a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. Those skilled in the art may make configurations based on actual needs.

[0209] In FIG11 , OUT2-0 refers to the signal output by the driver output terminal of the shift register unit provided in FIG3 of the present application, and OUT2-M refers to the signal output by the driver output terminal of any of the shift register units provided in FIG5 to FIG9 of the present application. As shown in FIG11 , in operating phases other than the output phase, the voltage value of the OUT2-M signal is lower than the voltage value of the OUT2-0 signal, and in the output phase, the duration of the rising edge of the OUT2-M signal is shorter than the duration of the rising edge of the OUT2-0 signal. That is, the shift register unit provided in some embodiments of the present disclosure can lower the voltage value of the signal output by the driver output terminal, thereby improving the performance of the shift register unit.

[0210] The embodiment of the present disclosure further provides a driving method of a shift register unit, which is configured to drive the shift register unit. The driving method of the shift register unit may include the following steps:

[0211] Step 100: The input sub-circuit provides a signal from an input signal terminal to a first node under control of a signal from a second clock signal terminal.

[0212] Step 200: The first control subcircuit controls the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal.

[0213] Step 300: The second control sub-circuit provides a signal from a second voltage signal terminal to the first node under the control of the voltage of the second node and the signal from the first clock signal terminal.

[0214] Step 400: The voltage stabilization sub-circuit provides the voltage of the first node to a fourth node under the control of a signal from the first voltage signal terminal.

[0215] Step 500: The cascade sub-circuit provides a signal from a second voltage signal terminal or a first clock signal terminal to a cascade output terminal under the control of the voltages of the second node and the fourth node.

[0216] Step 600: The output circuit provides a signal from a reference signal terminal or a first voltage signal terminal to a driving output terminal under the control of the voltages of the first node and the second node.

[0217] The shift register unit is the shift register unit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be described in detail here.

[0218] In some embodiments of the present disclosure, the shift register unit may further include a pull-down sub-circuit; the driving method of the shift register unit may further include: the pull-down sub-circuit provides a signal of the third voltage signal terminal to the first node under the control of the voltage of the first node or the fourth node.

[0219] The embodiment of the present disclosure also provides a display device. Figure 12 is a schematic structural diagram of a display device. As shown in Figure 12, the display device may include a timing controller, a data signal driver, a scan signal driver, a light-emitting signal driver and a display substrate. The display substrate includes: pixels arranged in an array, the timing controller is respectively connected to the data signal driver, the scan signal driver and the light-emitting signal driver, the data signal driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting signal driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pij, i and j may be natural numbers, at least one sub-pixel Pij may include a circuit unit and a light-emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively electrically connected to the scan signal line, the light-emitting signal line and the data signal line. In some embodiments of the present disclosure, a timing controller may provide grayscale values ​​and control signals suitable for the specifications of a data signal driver to the data signal driver; may provide clock signals, scan start signals, etc. suitable for the specifications of a scan signal driver to the scan signal driver; and may provide clock signals, emission stop signals, etc. suitable for the specifications of a light emitting signal driver to the light emitting signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn. For example, the data signal driver may sample grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan signal driver may generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan signal driver may sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be constructed in the form of a shift register unit and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next level circuit under the control of a clock signal, and m can be a natural number. The light-emitting signal driver can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting signal driver can sequentially provide an emission signal with an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting signal driver can be constructed in the form of a shift register unit and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next level circuit under the control of a clock signal, and o can be a natural number.

[0220] In some embodiments of the present disclosure, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be any product or component with a display function, such as an LCD panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0221] Figure 13 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 13, the display substrate may include a plurality of pixel units P arranged in a matrix. The plurality of pixel units P include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and at least one third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are electrically connected to scan signal lines, data signal lines, and light-emitting signal lines, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and the light-emitting signal lines, and control the pixel driving circuits to output a corresponding current. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are electrically connected to the pixel driving circuits of their respective subpixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of their respective subpixels.

[0222] In some embodiments of the present disclosure, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light. In some embodiments of the present disclosure, the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern, which is not limited in this disclosure.

[0223] In some embodiments of the present disclosure, a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in the present disclosure. FIG13 illustrates the arrangement in a horizontal parallel pattern as an example.

[0224] In some embodiments of the present disclosure, a pixel unit may further include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in the present disclosure.

[0225] In some embodiments of the present disclosure, the light emitting device may be an organic light emitting diode (OLED), including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0226] In some embodiments of the present disclosure, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some embodiments of the present disclosure, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

[0227] In some embodiments of the present disclosure, the display substrate is an LTPO display substrate.

[0228] FIG14 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In some embodiments of the present disclosure, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG14 , the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7) and one capacitor C.

[0229] As shown in Figure 14, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, the second electrode of the first transistor M1 is electrically connected to the first node Q1, and the third electrode of the first transistor M1 is electrically connected to the reset signal line Reset; the first electrode of the second transistor M2 is electrically connected to the first node Q1, the second electrode of the second transistor M2 is electrically connected to the third node Q3, and the third electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2; the first electrode of the third transistor M3 is electrically connected to the second node Q2, the second electrode of the third transistor M3 is electrically connected to the third node Q3, and the third electrode of the third transistor M3 is electrically connected to the first node Q1; the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data, the second electrode of the fourth transistor M4 is electrically connected to the second node Q2, and the The third electrode is electrically connected to the first scanning signal line Gate1; the first electrode of the fifth transistor M5 is electrically connected to the high-level power line VDD, the second electrode of the fifth transistor M5 is electrically connected to the second node Q2, and the third electrode of the fifth transistor M5 is electrically connected to the light-emitting signal line EM; the first electrode of the sixth transistor M6 is electrically connected to the third node Q3, the second electrode of the sixth transistor M6 is electrically connected to the fourth node Q4, and the third electrode of the sixth transistor M6 is electrically connected to the light-emitting signal line EM; the first electrode of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is electrically connected to the fourth node Q4, and the third electrode of the seventh transistor M7 is electrically connected to the first scanning signal line Gate1; the first plate of the capacitor C is electrically connected to the first node Q1, and the second plate of the capacitor C is electrically connected to the high-level power line VDD.

[0230] In some embodiments of the present disclosure, the first transistor M1 to the seventh transistor M7 in the pixel driving circuit may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or both a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form an LTPO display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0231] In some embodiments of the present disclosure, the first transistor M1 and the second transistor M2 are of opposite transistor types to the third transistor M3 to the seventh transistor M7. For example, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

[0232] In some embodiments of the present disclosure, the first transistor M1 and the second transistor M2 may be oxide transistors, and the third transistor M3 to the seventh transistor M7 may be low-temperature polysilicon transistors.

[0233] In some embodiments of the present disclosure, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0234] In some embodiments of the present disclosure, the voltage value of the signal on the second initial signal line INIT2 is constant and is a DC signal. The voltage value of the signal on the second initial signal line INIT2 may be 0V.

[0235] In some embodiments of the present disclosure, the light emitting device L′ may be electrically connected to the fourth node Q4 and the low-level power line VSS, respectively.

[0236] In some embodiments of the present disclosure, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0237] FIG15 is a timing diagram of the operation of the pixel driving circuit corresponding to FIG14 . The following illustrates an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG14 during the display phase. FIG15 is illustrated by taking the first transistor M1 and the second transistor M2 as N-type transistors and the third transistor M3 to the seventh transistor M7 as P-type transistors as an example. The pixel driving circuit in FIG26 includes the first transistor M1 to the seventh transistor M7, a capacitor C, and 8 signal lines (data signal line Data, a first scanning signal line Gate1, a second scanning signal line Gate2, a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, an emitting signal line EM, and a high-level power line VDD).

[0238] With reference to FIG14 and FIG15 , the operation process of the pixel driving circuit may include:

[0239] The first stage P1 is called the initialization stage. The signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node Q1 through the turned-on first transistor M1, initializing (i.e., resetting) the first node Q1, clearing the pre-stored voltage inside it, and completing the initialization.

[0240] In the second phase P2, called the data writing phase or threshold compensation phase, the first scanning signal line Gate1 is a low-level signal, the second scanning signal line Gate2 is a high-level signal, and the data signal line Data outputs the data voltage. During this phase, since the first node Q1 is a low-level signal, the third transistor M3 is turned on. The signal of the first scan signal line Gate1 is a low-level signal, the fourth transistor M4 is turned on, and the seventh transistor M7 is turned on. The signal of the second scan signal line Gate2 is a high-level signal, and the second transistor M2 is turned on. The data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node Q2, the turned-on third transistor M3, the third node Q3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node Q1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node Q4 through the turned-on seventh transistor M7, thereby initializing (i.e., resetting) the first electrode of the light-emitting device L, clearing the pre-stored voltage therein, and completing the initialization.

[0241] In the third stage P3, referred to as the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0242] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the third electrode and the first electrode of the third transistor M3. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0243] I=K*(Vgs-Vth)2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*(Vdd-Vd)2

[0244] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the third electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0245] The display substrate provided by the embodiments of the present disclosure may include: a substrate substrate, and sub-pixels, gate lines, and a gate driving circuit disposed on the substrate substrate. The substrate substrate is provided with a display area and a non-display area. The gate driving circuit is located in the non-display area, and the sub-pixels and the gate lines are located in the display area. The gate lines are electrically connected to the sub-pixels and the gate driving circuit respectively.

[0246] In some embodiments of the present disclosure, the sub-pixel includes: a pixel driving circuit and a light-emitting device. When the pixel driving circuit is the pixel driving circuit provided in FIG. 14, the gate line may include: at least one of a reset signal line, a first scan signal line, a second scan signal line, and a light-emitting signal line.

[0247] FIG. 16 is a schematic diagram of the cascading of the gate driving circuit. As shown in FIG. 16, the cascading output terminal OUT1 of the i-th stage shift register unit GOA(i) is connected to the signal input terminal IN of the i + 1-th stage shift register unit GOA(i + 1), where 1 ≤ i < N, and N is the total number of stages of the shift register unit.

[0248] In some embodiments of the present disclosure, as shown in FIG. 16, the clock signal is respectively input into the second clock signal terminal CK2 and the first clock signal terminal CK1 of multiple shift register units through the first clock signal line CLK1 and the second clock signal line CLK2.

[0249] In some embodiments of the present disclosure, as shown in FIG. 16, the clock signal is respectively input into the reference signal terminal VREF of multiple shift register units through the third clock signal line CLK3 and the fourth clock signal line CLK4.

[0250] In some embodiments of the present disclosure, as shown in FIG. 16, the driving output terminal OUT2 of the shift register unit may be electrically connected to the gate line.

[0251] In some embodiments of the present disclosure, as shown in Figure 16, the second clock signal terminal CK2 of the i-th stage shift register unit is electrically connected to one of the first clock signal line CLK1 and the second clock signal line CLK2, and the first clock signal terminal CK1 of the i-th stage shift register unit is electrically connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2; the second clock signal terminals of adjacent shift register units are connected to different signal lines, and the first clock signal terminals of adjacent shift register units are connected to different signal lines. Exemplarily, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2, and the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1, or, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1, and the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2. Figure 16 is explained by taking the example that the second clock signal terminal CK2 of the odd-numbered shift register unit is electrically connected to the first clock signal line CLK1, the first clock signal terminal CK1 of the odd-numbered shift register unit is electrically connected to the second clock signal line CLK2, the second clock signal terminal CK2 of the even-numbered shift register unit is electrically connected to the second clock signal line CLK2, and the first clock signal terminal CK1 of the even-numbered shift register unit is electrically connected to the first clock signal line CLK1.

[0252] In some embodiments of the present disclosure, as shown in FIG16 , the reference signal terminal VREF of the i-th shift register unit is electrically connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4, and the reference signal terminal VREF of the i+1-th shift register unit is electrically connected to the other of the third clock signal line CLK3 and the fourth clock signal line CLK4. For example, the reference signal terminal VREF of the odd-numbered shift register unit is electrically connected to the third clock signal line CLK3, and the reference signal terminal VREF of the even-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, or the reference signal terminal VREF of the odd-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, and the reference signal terminal VREF of the even-numbered shift register unit is electrically connected to the third clock signal line CLK3. 16 illustrates an example in which the reference signal terminal VREF of the odd-numbered shift register units is electrically connected to the third clock signal line CLK3 and the reference signal terminal VREF of the even-numbered shift register units is electrically connected to the fourth clock signal line CLK4.

[0253] In some embodiments of the present disclosure, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0254] In some embodiments of the present disclosure, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the semiconductor layer may be made of amorphous silicon (a-Si). In some embodiments of the present disclosure, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0255] In some embodiments of the present disclosure, FIG17 is a schematic diagram of the structure of a display substrate. FIG17 illustrates the shift register unit shown in FIG8 as an example. As shown in FIG16 and FIG17 , the display substrate may further include: an input signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first voltage signal line VGL1, a second voltage signal line VGH, and a third voltage signal line VGL2, disposed on the base substrate and located in the non-display area. There is at least one first voltage signal line VGL1.

[0256] In some embodiments of the present disclosure, the input signal terminal IN of the first-stage shift register unit GOA(1) is electrically connected to the input signal line STV, the first voltage signal terminal V1 of the i-th stage shift register unit is electrically connected to the first voltage signal line VGL1, the second voltage signal terminal V2 of the i-th stage shift register unit is electrically connected to the second voltage signal line VGH, and the third voltage signal terminal V3 of the i-th stage shift register unit is electrically connected to the third voltage signal line VGL2.

[0257] In some embodiments of the present disclosure, any one of the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1, the second voltage signal line VGH and the third voltage signal line VGL2 extends along the first direction D1, the gate line extends along the second direction D2, and the first direction D1 intersects with the second direction D2.

[0258] In some embodiments of the present disclosure, as shown in Figure 17, the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2 and the first voltage signal line VGL1 are arranged in sequence along the direction close to the display area and are located on the side of the shift register unit away from the display area.

[0259] In some embodiments of the present disclosure, as shown in FIG17 , the shift register unit includes: a plurality of transistors, and the second voltage signal line VGH is located on a side of the first voltage signal line VGL1 close to the display area and between the plurality of transistors of the shift register unit.

[0260] In some embodiments of the present disclosure, as shown in FIG17 , the third voltage signal line VGL2 is located on a side of the second voltage signal line VGH close to the display area, and its orthographic projection on the base substrate partially overlaps with the orthographic projection of the shift register unit on the base substrate.

[0261] In some embodiments of the present disclosure, as shown in FIG17 , a shift register unit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1. At least a portion of any one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the first capacitor C1 is located between a first voltage signal line VGL1 and a second voltage signal line VGH.

[0262] In some embodiments of the present disclosure, as shown in FIG17 , the shift register unit includes: a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a twelfth transistor T12, and a second capacitor C2. At least a portion of any one of the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the second capacitor C2 is located on a side of the second voltage signal line VGH close to the display area.

[0263] In some embodiments of the present disclosure, as shown in FIG. 17 , the orthographic projection of the third voltage signal line VGL2 on the substrate partially overlaps with the orthographic projections of the eighth transistor T8 , the ninth transistor T9 , and the second capacitor C2 on the substrate.

[0264] In some embodiments of the present disclosure, as shown in Figure 17, the display substrate may further include: a third clock signal line CLK3 and a fourth clock signal line CLK4 arranged on the base substrate and located in the non-display area, and either the third clock signal line CLK3 and the fourth clock signal line CLK4 extends along the first direction D1.

[0265] In some embodiments of the present disclosure, as shown in Figure 17, the number of the first voltage signal lines VGL1 is two, and the first voltage signal line VGL1 close to the display area is located on a side of any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 close to the display area; the first voltage signal line VGL1 away from the display area is located on a side of any one of the first clock signal line CLK1 and the second clock signal line CLK2 close to the display area, and is located on a side of the second voltage signal line VGH away from the display area.

[0266] In some embodiments of the present disclosure, as shown in FIG17 , the shift register unit further includes a tenth transistor T10, an eleventh transistor T11, and a fourth capacitor C4. At least a portion of any one of the tenth transistor T10, the eleventh transistor T11, and the fourth capacitor C4 is located on a side of the first voltage signal line VGL1 close to the display area.

[0267] In some embodiments of the present disclosure, as shown in FIG. 17 , the orthographic projection of the first voltage signal line VGL1 close to the display area on the base substrate partially overlaps with the orthographic projection of the fourth capacitor C4 on the base substrate.

[0268] In some embodiments of the present disclosure, as shown in Figure 17, the active layer T121 of the twelfth transistor T12 extends along the first direction D1, any electrode of the first electrode and the second electrode of the twelfth transistor T12 extends along the second direction D2, and the third electrode T82 of the twelfth transistor T12 at least partially extends along the second direction D2.

[0269] In some embodiments of the present disclosure, as shown in Figure 17, the width of any one of the two first voltage signal lines VGL1, the second voltage signal line VGH and the third voltage signal line VGL2 along the second direction D2 is smaller than the width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2.

[0270] In some embodiments of the present disclosure, since the signals of the clock signal lines are AC signals, the width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2 is wider, which can effectively reduce the load of the signal line.

[0271] In some embodiments of the present disclosure, the channel width of the active layer of the tenth transistor T10 is greater than the channel width of the active layer of the eighth transistor T8 .

[0272] In some embodiments of the present disclosure, the channel width of the active layer of the tenth transistor T10 is not less than 90 micrometers. For example, the channel width of the active layer of the tenth transistor T10 may be about 100 micrometers.

[0273] In some embodiments of the present disclosure, the channel length of the active layer of the tenth transistor T10 may be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the tenth transistor T10 may be approximately 100 / 3.5.

[0274] In some embodiments of the present disclosure, the channel width of the active layer of the eighth transistor T8 is no greater than 50 micrometers. For example, the channel width of the active layer of the eighth transistor T8 may be approximately 25 micrometers.

[0275] In some embodiments of the present disclosure, the channel length of the active layer of the eighth transistor T8 may be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the eighth transistor T8 may be approximately 25 / 3.5.

[0276] In some embodiments of the present disclosure, the channel width of the active layer of the eleventh transistor T11 is greater than the channel width of the active layer of the fifth transistor.

[0277] In some embodiments of the present disclosure, the channel width of the active layer of the eleventh transistor T11 is not less than 90 micrometers. For example, the channel width of the active layer of the eleventh transistor T11 may be approximately 100 micrometers.

[0278] In some embodiments of the present disclosure, the channel length of the active layer of the eleventh transistor T11 may be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the eleventh transistor T11 may be approximately 100 / 3.5.

[0279] In some embodiments of the present disclosure, the channel width of the active layer of the ninth transistor T9 is no greater than 50 micrometers. For example, the channel width of the active layer of the ninth transistor T9 may be approximately 25 micrometers.

[0280] In some embodiments of the present disclosure, the channel length of the active layer of the ninth transistor T9 may be approximately 3.5 micrometers, and the channel width-to-length ratio of the active layer of the ninth transistor T9 may be approximately 25 / 3.5.

[0281] In some embodiments of the present disclosure, the display substrate may further include: a driving structure layer disposed on a base substrate; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the base substrate; the shift register unit includes: a plurality of transistors and a plurality of capacitors, each capacitor including: a first plate and a second plate;

[0282] The semiconductor layer includes at least: an active layer of a plurality of transistors located in at least one shift register unit;

[0283] The first conductive layer at least includes: third electrodes of a plurality of transistors located in at least one shift register unit and first electrodes of a plurality of capacitors;

[0284] The second conductive layer includes at least: second plates of a plurality of capacitors located in at least one shift register unit;

[0285] The third conductive layer at least includes: an initial signal line, a first clock signal line, a second clock signal line, a first power line, a second power line, a third clock signal line, a fourth clock signal line, and first electrodes and second electrodes of a plurality of transistors located in at least one shift register unit;

[0286] The fourth conductive layer at least includes: a third power line.

[0287] In some embodiments of the present disclosure, the driving structure layer may further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a flat layer, wherein the first insulating layer is located between the semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, the fourth insulating layer is located between the third conductive layer and the fourth conductive layer, the fifth insulating layer is located on the side of the fourth conductive layer away from the substrate, and the flat layer is located on the side of the fifth insulating layer away from the substrate.

[0288] The following is an illustrative explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0289] The first step is to form a semiconductor pattern on the substrate, including depositing a semiconductor film on the substrate and patterning the semiconductor film through a patterning process to form a semiconductor layer pattern. As shown in Figure 18, Figure 18 is a schematic diagram of the semiconductor layer pattern after the semiconductor layer pattern is formed in Figure 17.

[0290] In some embodiments of the present disclosure, as shown in FIG. 18 , the semiconductor layer may include: active layers T1 a of first transistor to T12 a of twelfth transistor of at least one shift register unit.

[0291] In some embodiments of the present disclosure, as shown in FIG18 , the active layer T1a of the first transistor and the active layer T7a of the seventh crystal are integrally formed; the active layer T2a of the second transistor and the active layer T4a of the fourth crystal are integrally formed; the active layer T5a of the fifth transistor and the active layer T6a of the sixth crystal are integrally formed; the active layer T10a of the tenth transistor and the active layer T11a of the eleventh crystal are integrally formed. The active layer T3a of the third transistor, the active layer T8a of the eighth transistor, the active layer T9a of the ninth transistor, and the active layer T12a of the twelfth transistor can be provided separately.

[0292] In some embodiments of the present disclosure, as shown in FIG18 , the active layer T1a of the first transistor (also the active layer T7a of the seventh crystal) is located on a side away from the display area, the active layer T2a of the second transistor (also the active layer T4a of the fourth crystal) is located on a side of the active layer T1a of the first transistor close to the display area, the active layer T3a of the third transistor is located on a side of the active layer T1a of the first transistor close to the display area, and the active layer T3a of the third transistor is located on a side of the active layer T2a of the second transistor (also the active layer T4a of the fourth crystal) of the current-stage shift register unit close to the next-stage shift register unit. The active layer T5a of the fifth transistor (also the active layer T6a of the sixth crystal) and the active layer T12a of the twelfth transistor are arranged along the first direction D1 and are located on a side of the active layer T2a of the second transistor (also the active layer T4a of the fourth crystal) close to the display area. The active layer T9a of the ninth transistor and the active layer T8a of the eighth transistor are arranged along the first direction D1 and are located on the side of the active layer T5a of the fifth transistor (also the active layer T6a of the sixth crystal) that is closer to the display area. The active layer T9a of the ninth transistor of the current shift register unit is located on the side of the active layer T8a of the eighth transistor of the current shift register unit that is closer to the previous shift register unit. The active layer T10a of the tenth transistor (also the active layer T11a of the eleventh crystal) is located on the side of the active layer T8a of the eighth transistor that is closer to the display area.

[0293] In some embodiments of the present disclosure, as shown in FIG18 , the active layer T1a of the first transistor (also the active layer T7a of the seventh crystal), the active layer T5a of the fifth transistor (also the active layer T6a of the sixth crystal), the active layer T12a of the twelfth transistor, the active layer T8a of the eighth transistor, the active layer T9a of the ninth transistor, and the active layer T10a of the tenth transistor (also the active layer T11a of the eleventh crystal) are all strip-shaped and extend along the first direction D1. The active layer T2a of the second transistor (also the active layer T4a of the fourth crystal) and the active layer T3a of the third transistor are all strip-shaped and extend along the second direction D2.

[0294] In some embodiments of the present disclosure, as shown in FIG18 , the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. The first region and the second region will be conductorized after the subsequent formation of the first conductive layer, and therefore, are also referred to as conductive regions. In some embodiments of the present disclosure, the second region T1a-2 of the active layer T1a of the first transistor can simultaneously serve as the first region T7a-1 of the active layer T7a of the seventh crystal, the second region T2a-2 of the active layer T2a of the second transistor can simultaneously serve as the second region T4a-2 of the active layer T4a of the fourth crystal, the second region T5a-2 of the active layer T5a of the fifth transistor can simultaneously serve as the first region T6a-1 of the active layer T6a of the sixth crystal, and the second region T10a-2 of the active layer T10a of the tenth transistor can simultaneously serve as the second region T11a-2 of the active layer T11a of the eleventh crystal. The first region T1a-1 of the active layer T1a of the first transistor, the first region T2a-1 of the active layer T2a of the second transistor, the first region T3a-1 of the active layer T3a of the third transistor, the second region T3a-2 of the active layer T3a of the third transistor, the first region T4a-1 of the active layer T4a of the fourth transistor, the first region T5a-1 of the active layer T5a of the fifth transistor, the second region T6a-2 of the active layer T6a of the sixth transistor, the second region T7a-2 of the active layer T7a of the seventh transistor, the first region T8a-1 of the active layer T8a of the eighth transistor, the second region T8a-2 of the active layer T8a of the eighth transistor, the first region T9a-1 of the active layer T9a of the ninth transistor, the second region T9a-2 of the active layer T9a of the ninth transistor, the first region T10a-1 of the active layer T10a of the tenth transistor, and the first region T11a-1 of the active layer T11a of the eleventh transistor may be separately provided.

[0295] The second step, forming a first conductive pattern, includes depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the first insulating film and the first conductive film through a patterning process to form a first insulating layer pattern and a first conductive pattern disposed on the first insulating layer pattern, as shown in Figures 19 and 20. Figure 19 is a schematic diagram of the first conductive layer pattern in Figure 17, and Figure 20 is a schematic diagram of Figure 17 after the first conductive layer pattern is formed. In some embodiments of the present disclosure, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0296] In some embodiments of the present disclosure, as shown in Figures 19 and 20, the first conductive layer pattern may include: the third electrode T1b of the first transistor to the third electrode T12b of the twelfth transistor located in at least one stage of the shift register unit, the first electrode C1-1 of the first capacitor, the first electrode C2-1 of the second capacitor, the first electrode C4-1 of the fourth capacitor and the first connecting portion L1.

[0297] In some embodiments of the present disclosure, as shown in Figures 19 and 20, the third electrode T2b of the second transistor and the first electrode plate C1-1 of the first capacitor are integrally formed. The third electrode T3b of the third transistor, the third electrode T4b of the fourth transistor, and the third electrode T10b of the tenth transistor are integrally formed. The third electrode T5b of the fifth transistor, the third electrode T9b of the ninth transistor, the third electrode T11b of the eleventh transistor, and the first electrode plate C4-1 of the fourth capacitor are integrally formed. The third electrode T8b of the eighth transistor, the third electrode T12b of the twelfth transistor, and the first electrode plate C2-1 of the second capacitor are integrally formed. The third electrode T1b of the first transistor, the third electrode T6b of the sixth transistor, the third electrode T7b of the seventh transistor, and the first connecting portion L1 can be provided separately.

[0298] In some embodiments of the present disclosure, as shown in FIG19 and FIG20 , the third electrode T1b of the first transistor includes: a first third electrode portion T1b-1 and a second third electrode portion T1b-2. The first third electrode portion T1b-1 of the first transistor is The second and third electrodes T1b-2 of the first transistor extend along the second direction D2, and the first and third electrodes T1b-1 of the first transistor are connected to the middle of the second and third electrodes T1b-2 of the first transistor.

[0299] In some embodiments of the present disclosure, as shown in Figures 19 and 20, the first electrode C1-1 of the first capacitor can be square in shape, and the third electrode T2b of the second transistor can be strip-shaped and extend along the first direction D1. The third electrode T2b of the second transistor is located on a side of the first electrode C1-1 of the first capacitor that is close to the previous shift register unit.

[0300] In some embodiments of the present disclosure, as shown in FIG. 19 and FIG. 20 , the shape of the first plate C2-1 of the second capacitor can be The third electrode T8b of the eighth transistor and the third electrode T12b of the twelfth transistor may be in the shape of a strip and extend along the second direction D2, an end of the third electrode T8b of the eighth transistor is connected to the middle of the first electrode C2-1 of the second capacitor extending along the first direction D1, and the third electrode T12b of the twelfth transistor is located on a side of the third electrode T8b of the eighth transistor away from the display area.

[0301] In some embodiments of the present disclosure, as shown in Figures 19 and 20, the first electrode C4-1 of the fourth capacitor can be square in shape and extend along the first direction D1. The third electrode T11b of the eleventh transistor includes: a plurality of first branch segments T11b-1, the plurality of first branch segments T11b-1 extending along the second direction D2, and the plurality of first branch segments T11b-1 arranged along the first direction D1. The third electrode T9b of the ninth transistor is located on a side of the first electrode C4-1 of the fourth capacitor away from the display area, and the third electrode T5b of the fifth transistor is located on a side of the third electrode T9b of the ninth transistor away from the display area. Figures 19 and 20 illustrate an example in which the third electrode T11b of the eleventh transistor includes two first branch segments T11b-1.

[0302] In some embodiments of the present disclosure, as shown in Figures 19 and 20, the third electrode T10b of the tenth transistor includes a first connecting segment T10b-1 and a plurality of second branch segments T10b-2. The first connecting segment T10b-1 extends along a first direction D1, and the plurality of second branch segments T10b-2 extend along a second direction D2. The plurality of second branch segments T10b-2 are arranged along the first direction D1. The first connecting segment T10b-1 is equivalent to the "back of a comb," and the plurality of second branch segments T10b-2 are equivalent to the "teeth of a comb." Figures 19 and 20 illustrate the example of the third electrode T10b of the tenth transistor including four second branch segments T10b-2. The third electrode T3b of the third transistor and the third electrode T4b of the fourth transistor are located on a side of the third electrode T10b of the tenth transistor away from the display area, and the third electrode T3b of the third transistor is located on a side of the third electrode T4b of the fourth transistor close to the next-stage shift register unit, and the third electrode T3b of the third transistor and the third electrode T4b of the fourth transistor at least partially extend along the first direction D1.

[0303] In some embodiments of the present disclosure, as shown in FIG. 19 and FIG. 20 , the third electrode T6 b of the sixth transistor, the third electrode T7 b of the seventh transistor, and the first connection portion L1 may be strip-shaped and at least partially extend along the second direction D2 .

[0304] In some embodiments of the present disclosure, as shown in FIG19 and FIG20, the first third electrode portion T1b-1 and the second third electrode portion T1b-2 of the third electrode T1b of the first transistor are respectively arranged across the active layer T1a of the first transistor; the third electrode T2b of the second transistor is arranged across the active layer T2a of the second transistor; the third electrode T3b of the third transistor is arranged across the active layer T3a of the third transistor; the third electrode T4b of the fourth transistor is arranged across the active layer T4a of the fourth transistor; the third electrode T5b of the fifth transistor is arranged across the active layer T5a of the fifth transistor; and the third electrode T6b of the sixth transistor is arranged across the active layer T6a of the fifth transistor. The triode T6b is arranged across the active layer T6a of the sixth transistor; the third electrode T7b of the seventh transistor is arranged across the active layer T7a of the seventh transistor; the third electrode T8b of the eighth transistor is arranged across the active layer T8a of the eighth transistor; the third electrode T9b of the ninth transistor is arranged across the active layer T9a of the ninth transistor; the multiple second branch segments T10b-2 of the third electrode T10b of the tenth transistor are arranged across the active layer T10a of the tenth transistor; and the multiple first branch segments T11b-1 of the third electrode T11b of the eleventh transistor are arranged across the active layer T11a of the eleventh transistor. In other words, the extension direction of the third electrode of at least one transistor intersects with the extension direction of the active layer (they are mutually perpendicular).

[0305] In some embodiments of the present disclosure, this process also includes a conductorization process. After forming the first conductive layer, the conductorization process utilizes the semiconductor layer corresponding to the third-pole blocking region of multiple transistors (i.e., the region where the semiconductor layer and the third pole overlap) as the channel region of the transistor. The semiconductor layer not blocked by the first conductive layer is processed into a conductorization layer to form the electrode connection portion of the transistor.

[0306] The third step is to form a second conductive layer pattern, including: depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern, and patterning the second insulating film and the second conductive film through a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer pattern. As shown in Figures 21 and 22, Figure 21 is a schematic diagram of the second conductive layer pattern in Figure 17, and Figure 22 is a schematic diagram of Figure 17 after the second conductive layer pattern is formed. In some embodiments of the present disclosure, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0307] In some embodiments of the present disclosure, as shown in Figures 21 and 22, the second conductive layer pattern may include: a second plate C1-2 of a first capacitor located in at least one level of shift register unit, a second plate C2-2 of a second capacitor, a second plate C4-2 of a fourth capacitor, a second connection part L2, a third connection part L3, a fourth connection part L4, a fifth connection part L5 and a sixth connection part L6.

[0308] In some embodiments of the present disclosure, as shown in Figures 21 and 22, the second electrode plate C1-2, third connection portion L3, fourth connection portion L4, and fifth connection portion L5 of the first capacitor can be an integrally formed structure. The second electrode plate C2-2 of the second capacitor, the second electrode plate C4-2 of the fourth capacitor, the second connection portion L2, and the sixth connection portion L6 can be provided separately.

[0309] In some embodiments of the present disclosure, as shown in Figures 21 and 22, the second plate C1-2 of the first capacitor can be square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate C1-1 of the first capacitor on the substrate.

[0310] In some embodiments of the present disclosure, as shown in FIG. 21 and FIG. 22 , the shape of the second plate C2-2 of the second capacitor can be The orthographic projection of the first electrode plate C2-1 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C2-1 of the second capacitor on the substrate.

[0311] In some embodiments of the present disclosure, as shown in Figures 21 and 22, the second plate C4-2 of the fourth capacitor can be square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate C4-1 of the fourth capacitor on the substrate.

[0312] In some embodiments of the present disclosure, as shown in Figures 21 and 22, the second connection portion L2, the fourth connection portion L4, and the fifth connection portion L5 may be strip-shaped and extend at least partially along the second direction D2. The third connection portion L3 and the sixth connection portion L6 may be strip-shaped and extend at least partially along the first direction D1.

[0313] The fourth step is to form a third insulating layer pattern, including: depositing a third insulating film on the base substrate on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in Figures 23 and 24, Figure 23 is a schematic diagram of the first via pattern in Figure 17, and Figure 24 is a schematic diagram of Figure 17 after the third insulating layer pattern is formed.

[0314] In some embodiments of the present disclosure, as shown in FIG. 23 and FIG. 24 , the plurality of via hole patterns may include: a first via hole V1 to a thirty-seventh via hole V37 .

[0315] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the third electrode of the first transistor on the substrate. The second insulating layer below the first via V1 is etched away, exposing the surface of the third electrode of the first transistor. The first via V1 is configured to electrically connect one of the first clock signal line and the second clock signal line formed in a subsequent process to the third electrode of the first transistor.

[0316] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the second via V2 on the substrate is located within the orthographic projection of the first region of the active layer of the first transistor on the substrate. The first and second insulating layers below the second via V2 are etched away, exposing the surface of the first region of the active layer of the first transistor. The second via V2 is configured to electrically connect the first electrode of the first transistor formed in a subsequent process to the first region of the active layer of the first transistor through the via.

[0317] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the third via V3 on the base substrate is located within the range of the orthographic projection of the second connection portion L2 on the base substrate, and the third via V3 exposes the surface of the second connection portion L2. The third via V3 is configured to electrically connect the first electrode of the first transistor of the shift register unit of this stage formed in a subsequent process to the second connection portion L2.

[0318] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the fourth via V4 on the base substrate is located within the range of the orthographic projection of the second connection portion L2 on the base substrate, and the fourth via V4 exposes the surface of the second connection portion L2. The fourth via V4 is configured to electrically connect the second electrode of the eighth transistor (also the second electrode of the ninth transistor) of the previous-stage shift register unit formed in a subsequent process to the second connection portion L2 through the via.

[0319] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the fifth via V2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, and the first and second insulating layers below the fifth via V2 are etched away, exposing the surface of the second region of the active layer of the first transistor. The fifth via V5 is configured to electrically connect the second electrode of the first transistor (also the first electrode of the seventh transistor) formed in a subsequent process to the second region of the active layer of the first transistor through the via.

[0320] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the sixth via V6 on the substrate is located within the orthographic projection of the third electrode of the seventh transistor on the substrate. The second insulating layer below the sixth via V6 is etched away, exposing the surface of the third electrode of the seventh transistor. The sixth via V6 is configured to electrically connect a first voltage signal line formed in a subsequent process to the third electrode of the seventh transistor.

[0321] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the second region of the active layer of the seventh transistor on the substrate. The first and second insulating layers below the seventh via V7 are etched away, exposing the surface of the second region of the active layer of the seventh transistor. The seventh via V7 is configured to electrically connect the second electrode of the seventh transistor formed in a subsequent process to the second region of the active layer of the seventh transistor through the via.

[0322] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the fifth connection portion L5 on the substrate, and the eighth via V8 exposes the surface of the fifth connection portion L5. The eighth via V8 is configured to electrically connect the other of the first clock signal line and the second clock signal line formed in a subsequent process to the second plate of the first capacitor.

[0323] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the ninth via V9 on the substrate is located within the orthographic projection of the third connection portion L3 on the substrate, and the ninth via V9 exposes the surface of the third connection portion L3. The ninth via V9 is configured to electrically connect the first electrode of the second transistor formed in a subsequent process to the second plate of the first capacitor.

[0324] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the second transistor on the substrate. The first insulating layer and the second insulating layer below the tenth via hole V10 are etched away, exposing the surface of the first region of the active layer of the second transistor. The tenth via hole V10 is configured to electrically connect the first electrode of the second transistor formed in a subsequent process to the first region of the active layer of the second transistor through the via hole.

[0325] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second transistor on the substrate. The first insulating layer and the second insulating layer below the eleventh via hole V11 are etched away, exposing the surface of the second region of the active layer of the second transistor. The eleventh via hole V11 is configured to electrically connect the second electrode of the second transistor (also the second electrode of the fourth transistor) formed in a subsequent process to the second region of the active layer of the second transistor through the via hole.

[0326] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the third electrode of the second transistor on the substrate, and the second insulating layer below the twelfth via V12 is etched away, exposing the surface of the third electrode of the second transistor. The twelfth via V12 is configured to electrically connect the second electrode of the third transistor formed in a subsequent process to the third electrode of the second transistor (which is also the first plate of the first capacitor).

[0327] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the orthographic projection of the second region of the active layer of the third transistor on the substrate. The first and second insulating layers below the thirteenth via hole V13 are etched away, exposing the surface of the second region of the active layer of the third transistor. The thirteenth via hole V13 is configured to electrically connect the second electrode of the third transistor formed in a subsequent process to the second region of the active layer of the third transistor through the via hole.

[0328] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the third transistor on the substrate. The first insulating layer and the second insulating layer below the fourteenth via hole V14 are etched away, exposing the surface of the first region of the active layer of the third transistor. The fourteenth via hole V14 is configured to electrically connect the first electrode of the third transistor formed in a subsequent process to the first region of the active layer of the third transistor through the via hole.

[0329] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the third electrode of the third transistor on the substrate, and the second insulating layer below the fifteenth via hole V15 is etched away, exposing the surface of the third electrode of the third transistor. The fifteenth via hole V15 is configured to electrically connect the first electrode of the seventh transistor formed in a subsequent process to the third electrode of the third transistor (which is also the third electrode of the fourth transistor) through the via hole.

[0330] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the third pole of the third transistor on the substrate, and the second insulating layer below the sixteenth via V16 is etched away, exposing the surface of the third pole of the third transistor. The sixteenth via V16 is configured to electrically connect the second pole of the sixth transistor formed in a subsequent process to the third pole of the third transistor (also the third pole of the fourth transistor) through the via. At the same time, the sixteenth via V16 is also configured to electrically connect the second pole of the twelfth transistor formed in a subsequent process to the third pole of the third transistor (also the third pole of the fourth transistor) through the via.

[0331] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the orthographic projection of the second region of the active layer of the sixth transistor on the substrate. The first and second insulating layers below the seventeenth via hole V17 are etched away, exposing the surface of the second region of the active layer of the sixth transistor. The seventeenth via hole V17 is configured to electrically connect the second electrode of the sixth transistor formed in a subsequent process to the second region of the active layer of the sixth transistor through the via hole.

[0332] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the third electrode of the sixth transistor on the substrate. The second insulating layer below the eighteenth via V18 is etched away, exposing the surface of the third electrode of the sixth transistor. The eighteenth via V18 is configured to electrically connect the first electrode of the eighth transistor formed in a subsequent process to the third electrode of the sixth transistor.

[0333] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fifth transistor on the substrate. The first insulating layer and the second insulating layer below the nineteenth via hole V19 are etched away, exposing the surface of the first region of the active layer of the fifth transistor. The nineteenth via hole V19 is configured to electrically connect the first electrode of the fifth transistor formed in a subsequent process to the first region of the active layer of the fifth transistor through the via hole.

[0334] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twentieth via hole V20 on the substrate is located within the orthographic projection of the second region of the active layer of the eighth transistor on the substrate. The first and second insulating layers below the twentieth via hole V20 are etched away, exposing the surface of the second region of the active layer of the eighth transistor. The twentieth via hole V20 is configured to electrically connect the second electrode of the eighth transistor formed in a subsequent process to the second region of the active layer of the eighth transistor through the via hole.

[0335] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the eighth transistor on the substrate. The first insulating layer and the second insulating layer below the twenty-first via hole V21 are etched away, exposing the surface of the first region of the active layer of the eighth transistor. The twenty-first via hole V21 is configured to electrically connect the first electrode of the eighth transistor formed in a subsequent process to the first region of the active layer of the eighth transistor through the via hole.

[0336] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connection portion L4 on the substrate, and the twenty-second via hole V22 exposes the surface of the fourth connection portion L4. The twenty-second via hole V22 is configured to electrically connect the first electrode of the eighth transistor formed in a subsequent process to the second plate of the first capacitor through the via hole.

[0337] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the third electrode of the twelfth transistor on the substrate, and the second insulating layer below the twenty-third via hole V23 is etched away, exposing the surface of the third electrode of the twelfth transistor. The twenty-third via hole V23 is configured to electrically connect the second electrode of the seventh transistor formed in a subsequent process to the third electrode of the twelfth transistor through the via hole.

[0338] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the ninth transistor on the substrate. The first insulating layer and the second insulating layer below the twenty-fourth via hole V24 are etched away, exposing the surface of the first region of the active layer of the ninth transistor. The twenty-fourth via hole V24 is configured to electrically connect the first electrode of the ninth transistor formed in a subsequent process to the first region of the active layer of the ninth transistor through the via hole.

[0339] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-fifth via hole V25 on the base substrate is located within the range of the orthographic projection of the second region of the active layer of the ninth transistor on the base substrate. The first insulating layer and the second insulating layer below the twenty-fifth via hole V25 are etched away, exposing the surface of the second region of the active layer of the ninth transistor. The twenty-fifth via hole V25 is configured to electrically connect the second electrode of the ninth transistor formed in a subsequent process to the second region of the active layer of the ninth transistor through the via hole.

[0340] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, and the twenty-sixth via V26 exposes the surface of the second plate of the second capacitor. The twenty-sixth via V26 is configured to electrically connect the second electrode of the eighth transistor (also the second electrode of the ninth transistor) formed in a subsequent process to the second plate of the second capacitor.

[0341] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the twelfth transistor on the substrate. The first insulating layer and the second insulating layer below the twenty-seventh via hole V27 are etched away, exposing the surface of the second region of the active layer of the twelfth transistor. The twenty-seventh via hole V27 is configured to electrically connect the second electrode of the active layer of the twelfth transistor formed in a subsequent process to the second region of the active layer of the twelfth transistor through the via hole.

[0342] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the twelfth transistor on the substrate. The first insulating layer and the second insulating layer below the twenty-eighth via hole V28 are etched away, exposing the surface of the first region of the active layer of the twelfth transistor. The twenty-eighth via hole V28 is configured to electrically connect the first electrode of the twelfth transistor formed in a subsequent process to the first region of the active layer of the twelfth transistor through the via hole.

[0343] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthographic projection of the third electrode of the fifth transistor on the substrate, and the second insulating layer below the twenty-ninth via hole V29 is etched away, exposing the surface of the third electrode of the fifth transistor. The twenty-ninth via hole V29 is configured to electrically connect the second electrode of the second transistor (which is also the second electrode of the fourth transistor) formed in a subsequent process to the third electrode of the fifth transistor through the via hole.

[0344] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the 30th via hole V30 on the substrate is located within the orthographic projection of the first region of the active layer of the 11th transistor on the substrate. The first insulating layer and the second insulating layer below the 30th via hole V30 are etched away, exposing the surface of the first region of the active layer of the 11th transistor. The 30th via hole V30 is configured to electrically connect the first electrode of the 11th transistor, which will be formed in a subsequent process, to the first region of the active layer of the 11th transistor through the via hole.

[0345] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eleventh transistor on the substrate. The first insulating layer and the second insulating layer below the thirty-first via hole V31 are etched away, exposing the surface of the second region of the active layer of the eleventh transistor. The thirty-first via hole V31 is configured to electrically connect the second electrode of the eleventh transistor (also the second electrode of the tenth transistor) formed in a subsequent process to the second region of the active layer of the eleventh transistor (also the second region of the active layer of the tenth transistor) through the via hole.

[0346] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirty-second via V32 on the substrate is located within the orthographic projection of the first region of the active layer of the tenth transistor on the substrate. The first and second insulating layers below the thirty-second via V32 are etched away, exposing the surface of the first region of the active layer of the tenth transistor. The thirty-second via V32 is configured to electrically connect the first electrode of the tenth transistor, which will be formed in a subsequent process, to the first region of the active layer of the tenth transistor through the via.

[0347] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the first connection portion L1 on the substrate. The second insulating layer below the thirty-third via V33 is etched away, exposing the surface of the first connection portion L1. The thirty-third via V33 is configured to electrically connect one of the third and fourth clock signal lines formed in subsequent processes to the first connection portion L1.

[0348] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirty-fourth via hole V34 on the substrate is located within the range of the orthographic projection of the first connection portion L1 on the substrate. The second insulating layer below the thirty-fourth via hole V34 is etched away, exposing the surface of the first connection portion L1. The thirty-fourth via hole V34 is configured to electrically connect the first electrode of the tenth transistor formed in a subsequent process to the first connection portion L1.

[0349] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirty-fifth via hole V35 on the substrate is located within the range of the orthographic projection of the sixth connection portion L6 on the substrate, and the thirty-fifth via hole V35 exposes the surface of the sixth connection portion L6. The thirty-fifth via hole V35 is configured to electrically connect the second electrode of the tenth transistor (also the second electrode of the eleventh transistor) formed in a subsequent process to the sixth connection portion L6.

[0350] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirty-sixth via V36 on the substrate is located within the orthographic projection of the second plate of the fourth capacitor on the substrate, and the thirty-sixth via V36 exposes the surface of the second plate of the fourth capacitor. The thirty-sixth via V36 is configured to electrically connect a first voltage signal line formed in a subsequent process to the second plate of the fourth capacitor.

[0351] In some embodiments of the present disclosure, as shown in Figures 23 and 24, the orthographic projection of the thirty-seventh via hole V37 on the substrate is located within the orthographic projection of the first region of the active layer of the fourth transistor on the substrate. The first and second insulating layers below the thirty-seventh via hole V37 are etched away, exposing the surface of the first region of the fourth transistor. The thirty-seventh via hole V37 is configured to electrically connect the first electrode of the fourth transistor formed in a subsequent process to the first region of the active layer of the fourth transistor through the via hole.

[0352] The fifth step, forming a third conductive pattern, includes depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to form a third conductive layer pattern, as shown in Figures 25 and 26 . Figure 25 is a schematic diagram of the third conductive layer pattern in Figure 17 , and Figure 29 is a schematic diagram of Figure 17 after the third conductive pattern is formed. In some embodiments of the present disclosure, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0353] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the third conductive layer pattern may include: an input signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, two first voltage signal lines VGL1, a second voltage signal line VGH, a third clock signal line CLK3, a fourth clock signal line CLK4, and the first electrode T1c-1 and the second electrode T1c-2 of the first transistor to the first electrode T12c-1 and the second electrode T12c-2 of the twelfth transistor located in the shift register unit of this level.

[0354] In some embodiments of the present disclosure, as shown in FIG. 25 and FIG. 26 , the input signal line, the first clock signal line, the second clock signal line, and the first voltage signal line away from the display area are arranged on the same layer.

[0355] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T1c-2 of the first transistor and the first electrode T7c-1 of the seventh transistor are an integrally formed structure; the second electrode T2c-2 of the second transistor and the second electrode T4c-2 of the fourth transistor are an integrally formed structure; the second voltage signal line VGH, the first electrode T5c-1 of the fifth transistor and the first electrode T9c-1 of the ninth transistor are an integrally formed structure; the second electrode T6c-2 of the sixth transistor and the second electrode T12c-2 of the twelfth transistor are an integrally formed structure; the second electrode T8c-2 of the eighth transistor and the second electrode T9c-2 of the ninth transistor are an integrally formed structure; the first electrode T10c-1 of the tenth transistor and the first electrode T11c-1 of the eleventh transistor are an integrally formed structure; the first voltage signal line VGL1 close to the display area and the second electrode T11c-2 of the eleventh transistor are an integrally formed structure. The first electrode T1c-1 of the first transistor, the first electrode T2c-1 of the second transistor, the second electrode T3c-2 of the third transistor, the second electrode T7c-2 of the seventh transistor, the first electrode T8c-1 of the eighth transistor, the first electrode T12c-1 of the twelfth transistor, and the second electrode T10c-2 of the tenth transistor can be set separately.

[0356] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1, the second voltage signal line VGH, the third clock signal line CLK3, the fourth clock signal line CLK4 away from the display area, and the first voltage signal line VGL1 close to the display area are arranged in sequence along a side close to the display area. Any one of the input signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first voltage signal line VGL1, the second voltage signal line VGH, the third clock signal line CLK3, the fourth clock signal line CLK4 away from the display area, and the first voltage signal line VGL1 close to the display area extends along the first direction D1.

[0357] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the first electrode T1c-1 of the first transistor can be strip-shaped and extend along the second direction D2. The first electrode T1c-1 of the first transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are located away from the display area. The first electrode T1c-1 of the first transistor is electrically connected to the first region T1a-1 of the active layer of the first transistor through a second via V2, and is electrically connected to the second connection portion L2 of the shift register unit of the same stage through a third via V3.

[0358] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T1c-2 of the first transistor (also the first electrode T7c-1 of the seventh transistor) can be strip-shaped and extend along the second direction D2. The second electrode T1c-2 of the first transistor (also the first electrode T7c-1 of the seventh transistor) is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The second electrode T1c-2 of the first transistor (also the first electrode T7c-1 of the seventh transistor) is electrically connected to the second region T1a-2 of the active layer of the first transistor (also the first region T7a-1 of the active layer of the seventh transistor) through a fifth via V5, and is electrically connected to the third electrode T3b of the third transistor (also the third electrode T4b of the fourth transistor) through a fifteenth via V15.

[0359] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the first electrode T2c-1 of the second transistor can be strip-shaped and extend along a first direction D1. The first electrode T2c-1 of the second transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are located away from the display area. The first electrode T2c-1 of the second transistor is electrically connected to the first region T2a-1 of the active layer of the second transistor via a tenth via V10, and is electrically connected to the second plate C1-2 of the first capacitor via a ninth via V9.

[0360] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T2c-2 of the second transistor (also the second electrode T4c-2 of the fourth transistor) can be strip-shaped and extend along the first direction D1. The second electrode T2c-2 of the second transistor (also the second electrode T4c-2 of the fourth transistor) is located between the first voltage signal line VGL1 and the second voltage signal line VGH, away from the display area. The second electrode T2c-2 of the second transistor (also the second electrode T4c-2 of the fourth transistor) is electrically connected to the second region T2a-2 of the active layer of the second transistor (also the second region T4a-2 of the active layer of the fourth transistor) through an eleventh via V11, and is electrically connected to the third electrode T5b of the fifth transistor through a twenty-ninth via V29.

[0361] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T3c-2 of the third transistor can be strip-shaped and extend along the second direction D2. The second electrode T3c-2 of the third transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are away from the display area. The second electrode T3c-2 of the third transistor is electrically connected to the second region T3a-2 of the active layer of the third transistor through a thirteenth via V13, and is electrically connected to the third electrode T2b of the second transistor (also the first plate C1-1 of the first capacitor) through a twelfth via V12.

[0362] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T7c-2 of the seventh transistor can be strip-shaped and extend along the second direction D2. The second electrode T7c-2 of the seventh transistor is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are away from the display area. The second electrode T7c-2 of the seventh transistor is electrically connected to the second region T7a-2 of the active layer of the seventh transistor through a seventh via V7, and is electrically connected to the third electrode T12b of the twelfth transistor through a twenty-third via V23.

[0363] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the first electrode T5c-1 of the fifth transistor (also the first electrode T9c-1 of the ninth transistor) can be strip-shaped and extend along the second direction D2. The first electrode T5c-1 of the fifth transistor (also the first electrode T9c-1 of the ninth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The first electrode T5c-1 of the fifth transistor is electrically connected to the first electrode T5a-1 of the active layer of the fifth transistor through a nineteenth via V19, and the first electrode T9c-1 of the ninth transistor is electrically connected to the first electrode T9a-1 of the active layer of the ninth transistor through a twenty-fourth via V24.

[0364] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T6c-2 of the sixth transistor (also the second electrode T12c-2 of the twelfth transistor) can be strip-shaped and extend along the first direction D1. The second electrode T6c-2 of the sixth transistor (also the second electrode T12c-2 of the twelfth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The second electrode T6c-2 of the sixth transistor is electrically connected to the second electrode T6a-2 of the active layer of the sixth transistor through a seventeenth via V17, and is electrically connected to the third electrode T3b of the third transistor (also the third electrode T4b of the fourth transistor) through a sixteenth via V16. The second electrode T12c-2 of the twelfth transistor is electrically connected to the second electrode T12a-2 of the active layer of the twelfth transistor through a twenty-seventh via V27.

[0365] In some embodiments of the present disclosure, as shown in FIG. 25 and FIG. 26 , the shape of the first electrode T12c-1 of the twelfth transistor may be The first electrode T12c-1 of the twelfth transistor is located between the second voltage signal line VGH and the third clock signal line CLK3. The first electrode T12c-1 of the twelfth transistor is electrically connected to the first electrode T12a-1 of the active layer of the twelfth transistor through a twenty-eighth via V28.

[0366] In some embodiments of the present disclosure, as shown in FIG. 25 and FIG. 26 , the shape of the first electrode T8c-1 of the eighth transistor can be The first electrode T8c-1 of the eighth transistor is located between the second voltage signal line VGH and the third clock signal line CLK3. The first electrode T8c-1 of the eighth transistor is electrically connected to the first region T8a-1 of the active layer of the eighth transistor through a twenty-first via V21, electrically connected to the fourth connection portion L4 through a twenty-second via V22, and electrically connected to the third electrode T6b of the sixth transistor through an eighteenth via V18.

[0367] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T8c-2 of the eighth transistor (also the second electrode T9c-2 of the ninth transistor) can be shaped like an "F". The second electrode T8c-2 of the eighth transistor (also the second electrode T9c-2 of the ninth transistor) is located between the second voltage signal line VGH and the third clock signal line CLK3. The second electrode T8c-2 of the eighth transistor can be electrically connected to the second region T8a-2 of the active layer of the eighth transistor through a twentieth via V20, the second electrode T9c-2 of the ninth transistor can be electrically connected to the second region T9a-2 of the active layer of the ninth transistor through a twenty-fifth via V25, and the second electrode T8c-2 of the eighth transistor (also the second electrode T9c-2 of the ninth transistor) is electrically connected to the second plate C2-2 of the second capacitor through a twenty-sixth via V26.

[0368] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T11c-2 of the eleventh transistor can be strip-shaped and extend along the second direction D2. The second electrode T11c-2 of the eleventh transistor is located on a side of the first voltage signal line VGL1 close to the display area. The second electrode T11c-2 of the eleventh transistor can be electrically connected to the second region T11a-2 of the active layer of the eleventh transistor through a thirty-first via V31.

[0369] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the second electrode T10c-2 of the tenth transistor can be in an "F" shape. The second electrode T10c-2 of the tenth transistor is located on a side of the first voltage signal line VGL1 close to the display area. The second electrode T10c-2 of the tenth transistor can be electrically connected to the second region T10-2 of the active layer of the tenth transistor via a thirty-second via V32.

[0370] In some embodiments of the present disclosure, as shown in Figures 25 and 26, the first electrode T10c-1 of the tenth transistor (also the first electrode T11c-1 of the eleventh transistor) can be shaped like a comb, with its "comb teeth" located on the side of the "comb back" away from the display area. The first electrode T10c-1 of the tenth transistor (also the first electrode T11c-1 of the eleventh transistor) is located on the side of the first voltage signal line VGL1 close to the display area. The first electrode T10c-1 of the tenth transistor is electrically connected to the first area T10a-1 of the active layer of the tenth transistor through the thirty-second via V32, and the first electrode T11c-1 of the eleventh transistor is electrically connected to the first area T11a-1 of the active layer of the eleventh transistor through the thirtieth via V30. The first electrode T10c-1 of the tenth transistor (also the first electrode T11c-1 of the eleventh transistor) is electrically connected to the sixth connection portion L6 through the thirty-fifth via V35.

[0371] In some embodiments of the present disclosure, as shown in FIG. 26 , the orthographic projection of the first voltage signal line VGL1VGL1 close to the display area on the base substrate partially overlaps with the orthographic projection of the fourth capacitor on the base substrate.

[0372] The sixth step is forming a fourth insulating layer pattern, which includes depositing a fourth insulating film on the substrate having the aforementioned pattern, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure, wherein the fourth insulating layer has a via pattern. As shown in Figures 27 and 28, Figure 27 is a schematic diagram of the second via pattern in Figure 17, and Figure 28 is a schematic diagram of Figure 17 after the fourth insulating layer pattern is formed.

[0373] In some embodiments of the present disclosure, as shown in FIG. 27 and FIG. 28 , the via hole pattern may include: a thirty-eighth via hole V38 .

[0374] In some embodiments of the present disclosure, as shown in Figures 27 and 28, the orthographic projection of the thirty-eighth via hole V38 on the substrate is located within the range of the orthographic projection of the first electrode T12c-1 of the twelfth transistor on the substrate, and the thirty-eighth via hole V38 exposes the surface of the first electrode T12c-1 of the twelfth transistor. The thirty-eighth via hole V38 is configured to electrically connect the third voltage signal line VGL2 formed in a subsequent process to the first electrode T12c-1 of the twelfth transistor through the via hole.

[0375] The seventh step, forming a fourth conductive layer pattern, includes depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern. As shown in Figures 29 and 30, Figure 29 is a schematic diagram of the fourth conductive layer pattern in Figure 17, and Figure 30 is a schematic diagram of Figure 17 after the fourth conductive layer pattern is formed. In some embodiments of the present disclosure, the fourth conductive layer may be referred to as a second source / drain metal layer (SD2).

[0376] In some embodiments of the present disclosure, as shown in FIG. 29 and FIG. 30 , the fourth conductive layer pattern may include: a third voltage signal line VGL2 .

[0377] In some embodiments of the present disclosure, as shown in Figures 29 and 30, the third voltage signal line VGL2 can be linear and extend along the first direction D1. The orthographic projection of the third voltage signal line VGL2 on the substrate is located between the second voltage signal line VGH and the third clock signal line CLK3, and the orthographic projection on the substrate partially overlaps with the orthographic projections of the eighth transistor, the ninth transistor, and the second capacitor on the substrate.

[0378] In some embodiments of the present disclosure, as shown in FIG. 29 and FIG. 30 , the third voltage signal line VGL2 is electrically connected to the first electrode T12 c - 1 of the twelfth transistor through the thirty-eighth via V38 .

[0379] The eighth step is to form a planar layer pattern, including: depositing a fifth insulating film on the base substrate with the aforementioned pattern, coating a planar film, and patterning the fifth insulating film and the planar film through a patterning process to form a fifth insulating layer pattern and a planar layer pattern covering the aforementioned pattern.

[0380] At this point, the drive structure layer is completed on the base substrate. In a plane parallel to the display substrate, the drive structure layer may include multiple shift register units, and the drive structure layer may be disposed on the base substrate. The drive structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a planar layer disposed sequentially on the base substrate.

[0381] In some embodiments of the present disclosure, as shown in Figure 31, the first clock signal line CLK1 and the second clock signal line CLK2 can be arranged on the same layer as the third voltage signal line VGL2. In this case, the input signal line, the first voltage signal line away from the display area, and the first clock signal line and the second clock signal line are arranged on different layers. In some embodiments of the present disclosure, the driving structure layer provided on the base substrate includes: a semiconductor layer, a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a planar layer sequentially stacked on the base substrate. The following is an exemplary description using the preparation process of the display substrate.

[0382] The first step is to form a semiconductor layer pattern on the base substrate. This process is similar to the above-mentioned preparation process and will not be repeated here.

[0383] The second step, forming a first conductive layer, includes depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the first insulating film and the first conductive film through a patterning process to form a first insulating layer pattern and a first conductive pattern disposed on the first insulating layer pattern, as shown in Figures 32 and 33. Figure 32 is a schematic diagram of the first conductive layer pattern in Figure 31, and Figure 33 is a schematic diagram of Figure 31 after the first conductive layer pattern is formed. In some embodiments of the present disclosure, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0384] In some embodiments of the present disclosure, as shown in Figures 32 and 33, the third electrode T1b' of the first transistor includes a first third electrode portion T1b'-1 and a second third electrode portion T1b'-2. The third electrode T1b' of the first transistor is in the shape of a letter "ㄈ". The first third electrode portion T1b'-1 and the second third electrode portion T1b'-2 of the first transistor both extend along the second direction D2. The end of the first third electrode portion T1b'-1 of the first transistor is connected to the end of the second third electrode portion T1b'-2 of the first transistor.

[0385] In some embodiments of the present disclosure, the preparation process of the first conductive layer is similar to the aforementioned preparation process and will not be repeated here.

[0386] The third step is to form a second conductive layer pattern, including: depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern, and patterning the second insulating film and the second conductive film through a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer pattern. As shown in Figures 21 and 22, Figure 21 is a schematic diagram of the second conductive layer pattern in Figure 17, and Figure 22 is a schematic diagram of Figure 17 after the second conductive layer pattern is formed. In some embodiments of the present disclosure, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0387] In some embodiments of the present disclosure, as shown in Figures 34 and 35, the second conductive layer pattern may include: a second plate C1-2 of a first capacitor located in at least one level of shift register unit, a second plate C2-2 of a second capacitor, a second plate C4-2 of a fourth capacitor, a second connection part L2, a third connection part L3, a fourth connection part L4 and a sixth connection part L6.

[0388] In some embodiments of the present disclosure, the preparation process of the second conductive layer is similar to the aforementioned preparation process and will not be repeated here.

[0389] The fourth step is to form a third insulating layer pattern, including: depositing a third insulating film on the base substrate on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in Figures 36 and 37, Figure 36 is a schematic diagram of the third insulating layer via pattern in Figure 31, and Figure 37 is a schematic diagram of Figure 31 after the third insulating layer pattern is formed.

[0390] In some embodiments of the present disclosure, as shown in FIG. 23 and FIG. 24 , the plurality of via hole patterns may include: second to seventh via holes V2 to V7 , and ninth to thirty-seventh via holes V9 to V37 .

[0391] In some embodiments of the present disclosure, the preparation process of the third insulating layer is similar to the aforementioned preparation process and will not be repeated here.

[0392] The fifth step is forming a third conductive layer pattern, which includes depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film through a patterning process to form a third conductive layer pattern, as shown in Figures 38 and 39. Figure 38 is a schematic diagram of the third conductive layer pattern in Figure 31, and Figure 39 is a schematic diagram of Figure 31 after the third conductive pattern is formed. In some embodiments of the present disclosure, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0393] In some embodiments of the present disclosure, as shown in Figures 38 and 39, the third conductive layer pattern may include: an input signal line STV, two first voltage signal lines VGL1, a second voltage signal line VGH, a third clock signal line CLK3, a fourth clock signal line CLK4, a seventh connection part L7, an eighth connection part L8, and the first electrode T1c-1 and the second electrode T1c-2 of the first transistor to the first electrode T12c-1 and the second electrode T12c-2 of the twelfth transistor located in the shift register unit of this level.

[0394] In some embodiments of the present disclosure, the preparation process of the third conductive layer is similar to the aforementioned preparation process and will not be repeated here.

[0395] The sixth step is forming a fourth insulating layer pattern, which includes depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure, wherein the fourth insulating layer has a via pattern. As shown in Figures 40 and 41, Figure 40 is a schematic diagram of the second via pattern in Figure 31, and Figure 42 is a schematic diagram of Figure 31 after the fourth insulating layer pattern is formed.

[0396] In some embodiments of the present disclosure, as shown in FIG. 40 and FIG. 41 , the via hole pattern may include a first via hole V1 ′, an eighth via hole V8 ′, and a thirty-eighth via hole V38 .

[0397] In some embodiments of the present disclosure, as shown in Figures 40 and 41, the orthographic projection of the first via V1' on the substrate is located within the range of the orthographic projection of the third electrode of the first transistor on the substrate. The second insulating layer, the third insulating layer, and the third conductive layer below the first via V1' are etched away, exposing the surface of the third electrode of the first transistor. The first via V1' is configured to electrically connect one of the first clock signal line and the second clock signal line formed in a subsequent process to the third electrode of the first transistor.

[0398] In some embodiments of the present disclosure, as shown in Figures 40 and 41, the orthographic projection of the eighth via V8' on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate. The third insulating layer and the third conductive layer below the eighth via V8' are etched away, exposing the surface of the second plate of the first capacitor. The eighth via V8' is configured to electrically connect the other of the first clock signal line and the second clock signal line formed in a subsequent process to the second plate of the first capacitor.

[0399] In some embodiments of the present disclosure, the preparation process of the fourth insulating layer is similar to the aforementioned preparation process and will not be repeated here.

[0400] The seventh step is forming a fourth conductive layer pattern, which includes depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern. As shown in Figures 42 and 43, Figure 42 is a schematic diagram of the fourth conductive layer pattern in Figure 31, and Figure 42 is a schematic diagram of Figure 31 after the fourth conductive layer pattern is formed. In some embodiments of the present disclosure, the fourth conductive layer may be referred to as a second source / drain metal layer (SD2).

[0401] In some embodiments of the present disclosure, as shown in FIG. 42 and FIG. 43 , the fourth conductive layer pattern may include: a first clock signal line CLK1 , a second clock signal line CLK2 , and a third voltage signal line VGL2 .

[0402] In some embodiments of the present disclosure, as shown in Figures 42 and 43, the first clock signal line CLK1 can be linear and extend along a first direction D1. The orthographic projection of the first clock signal line CLK1 on the substrate is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are located away from the display area. The orthographic projection of the first clock signal line CLK1 on the substrate partially overlaps with the orthographic projections of the first transistor, the seventh transistor, and the first capacitor on the substrate.

[0403] In some embodiments of the present disclosure, as shown in FIG. 42 and FIG. 43 , the first clock signal line CLK1 is electrically connected to the third electrode T1 b of the first transistor through a first via V1 ′.

[0404] In some embodiments of the present disclosure, as shown in Figures 42 and 43, the second clock signal line CLK2 can be linear and extend along a first direction D1. The orthographic projection of the second clock signal line CLK2 on the substrate is located between the first voltage signal line VGL1 and the second voltage signal line VGH, which are located away from the display area. The orthographic projection of the second clock signal line CLK2 on the substrate partially overlaps with the orthographic projections of the second transistor and the first capacitor on the substrate.

[0405] In some embodiments of the present disclosure, as shown in FIG. 42 and FIG. 43 , the second clock signal line CLK2 is electrically connected to the second plate C2 - 2 of the first capacitor through an eighth via V8 ′.

[0406] In some embodiments of the present disclosure, as shown in Figures 42 and 43, the third voltage signal line VGL2 can be linear and extend along the first direction D1. The orthographic projection of the third voltage signal line VGL2 on the substrate is located between the second voltage signal line VGH and the third clock signal line CLK3, and the orthographic projection on the substrate partially overlaps with the orthographic projection of the second capacitor on the substrate.

[0407] In some embodiments of the present disclosure, as shown in FIG. 42 and FIG. 43 , the third voltage signal line VGL2 is electrically connected to the first electrode T12 c - 1 of the twelfth transistor through the thirty-eighth via V38 .

[0408] The eighth step is to form a flat layer pattern. This process is similar to the above-mentioned preparation process and will not be described again here.

[0409] In some embodiments of the present disclosure, the first clock signal line CLK1, the second clock signal line CLK2 and the third voltage signal line VGL2 are arranged on the same layer, which can reduce the size of the shift register unit along the first direction by about 25 microns, effectively reducing the size of the shift register unit, and further reducing the border length of the non-display area, which is conducive to narrow border design.

[0410] In some embodiments of the present disclosure, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide comprising indium and tin, an oxide comprising tungsten and indium, an oxide comprising tungsten, indium, and zinc, an oxide comprising titanium and indium, an oxide comprising titanium, indium, and tin, an oxide comprising indium and zinc, an oxide comprising silicon, indium, and tin, or an oxide comprising indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0411] In some embodiments of the present disclosure, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0412] In some embodiments of the present disclosure, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer.

[0413] In some embodiments of the present disclosure, the planar layer may be made of organic materials such as resin.

[0414] In some embodiments of the present disclosure, after the driving structure layer is prepared, a light-emitting structure layer is prepared on the driving structure layer. The preparation process of the light-emitting structure layer may include the following operations.

[0415] An anode conductive film is deposited on the substrate substrate on which the aforementioned pattern is formed, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the flat layer. A pixel definition film is deposited on the substrate substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. An organic light-emitting material is coated on the substrate substrate on which the pixel definition layer pattern is formed, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern. A cathode conductive film is deposited on the substrate substrate on which the organic material layer pattern is formed, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.

[0416] At this point, the light emitting structure layer is completed on the base substrate.

[0417] In some embodiments of the present disclosure, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0418] In some embodiments of the present disclosure, the anode conductive layer includes at least a plurality of anode patterns.

[0419] In some embodiments of the present disclosure, the anode conductive layer adopts a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or can adopt a multi-layer composite structure, such as ITO / Ag / ITO.

[0420] In some embodiments of the present disclosure, the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.

[0421] In some embodiments of the present disclosure, the cathode conductive layer may include at least: cathodes of a plurality of light-emitting devices.

[0422] In some embodiments of the present disclosure, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0423] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0424] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0425] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0426] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register unit, comprising: The shift register is configured to output a cascade signal through a cascade output terminal; An output circuit electrically connected to the shift register, wherein the output circuit is configured to control the driving output terminal to output a gate scanning signal according to a signal at the first voltage signal terminal and a signal at the reference signal terminal; Wherein, the shift register comprises: a first control subcircuit; The first control subcircuit is electrically connected to the first node, the second node, the second voltage signal terminal, and the first clock signal terminal in the shift register; the first control circuit is configured to control the voltage of the second node according to the voltage of the first node and the signal of the first clock signal terminal.

2. The shift register unit according to claim 1, wherein: The shift register further comprises: an input subcircuit; The input sub-circuit is configured to provide a signal at an input signal terminal to the first node according to a signal at a second clock signal terminal.

3. The shift register unit according to claim 2, wherein: The input subcircuit comprises: a first transistor; A first electrode of the first transistor is electrically connected to the input signal terminal, a second electrode of the first transistor is electrically connected to the first node, and a third electrode of the first transistor is electrically connected to the second clock signal terminal.

4. The shift register unit according to claim 1, wherein: The first control subcircuit includes: a second transistor, a third transistor, a fourth transistor and a first capacitor; A first electrode of the second transistor is electrically connected to the first clock signal terminal, a second electrode of the second transistor is electrically connected to the second node, and a third electrode of the second transistor is electrically connected to the third node; The first electrode of the third transistor is electrically connected to the second voltage signal terminal, the second electrode of the third transistor is electrically connected to the third node, and the third electrode of the third transistor is electrically connected to the first node; A first electrode of the fourth transistor is electrically connected to the second voltage signal terminal, a second electrode of the fourth transistor is electrically connected to the second node, and a third electrode of the fourth transistor is electrically connected to the first node; The first electrode of the first capacitor is electrically connected to the first clock signal end. The second electrode is electrically connected to the third node.

5. The shift register unit according to claim 1, wherein: The shift register further includes: a second control subcircuit; The second control subcircuit is electrically connected to the first node, the second node, the second voltage signal terminal and the first clock signal terminal; the second control subcircuit is configured to transmit the signal from the second voltage signal terminal to the first node based on the voltage of the second node and the signal of the first clock signal terminal.

6. The shift register unit according to claim 5, wherein: The second control subcircuit includes: a fifth transistor and a sixth transistor; A first electrode of the fifth transistor is electrically connected to the second voltage signal terminal, a second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, and a third electrode of the fifth transistor is electrically connected to the second node; A second electrode of the sixth transistor is electrically connected to the first node, and a third electrode of the sixth transistor is electrically connected to the first clock signal terminal.

7. The shift register unit according to claim 1, wherein: The shift register further includes: a voltage stabilization subcircuit; The voltage stabilization subcircuit is electrically connected to the first node, the fourth node and the first voltage signal terminal. The voltage stabilization circuit is configured to transmit the voltage from the first node to the fourth node according to the signal of the first voltage signal terminal.

8. The shift register unit according to claim 7, wherein: The voltage stabilization subcircuit includes: a seventh transistor; A first electrode of the seventh transistor is electrically connected to the first node, a second electrode of the seventh transistor is electrically connected to the fourth node, and a third electrode of the seventh transistor is electrically connected to the first voltage signal terminal.

9. The shift register unit according to claim 1, wherein: The shift register further comprises: a cascade subcircuit; The cascade sub-circuit is electrically connected to the second node, the fourth node, the first clock signal terminal and the second voltage signal terminal. The cascade sub-circuit is configured to enable the cascade output terminal to output the cascade signal according to the voltages of the second node and the fourth node.

10. The shift register unit according to claim 9, wherein: The cascade sub-circuit comprises: an eighth transistor, a ninth transistor and a second capacitor; The first electrode of the eighth transistor is electrically connected to the first clock signal terminal, the second electrode of the eighth transistor is electrically connected to the cascade output terminal, and the third electrode of the eighth transistor is electrically connected to the fourth Nodes are electrically connected; A first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, a second electrode of the ninth transistor is electrically connected to the cascade output terminal, and a third electrode of the ninth transistor is electrically connected to the second node; A first electrode of the second capacitor is electrically connected to the fourth node, and a second electrode of the second capacitor is electrically connected to the cascade output terminal.

11. The shift register unit according to claim 10, wherein: The cascade sub-circuit comprises: a third capacitor; A first electrode of the third capacitor is electrically connected to the second voltage signal terminal, and a second electrode of the third capacitor is electrically connected to the cascade output terminal.

12. The shift register unit according to claim 7, wherein: The shift register further comprises: a pull-down subcircuit; The pull-down sub-circuit is electrically connected to the third voltage signal terminal and the first node, and is configured to transmit a signal from the third voltage signal terminal to the first node.

13. The shift register unit according to claim 12, wherein: The amplitude of the voltage signal at the third voltage signal terminal is greater than the amplitude of the voltage signal at the first voltage signal terminal.

14. The shift register unit according to claim 13, wherein: The pull-down sub-circuit comprises: a twelfth transistor; The first electrode of the twelfth transistor is electrically connected to the third voltage signal terminal, the second electrode of the twelfth transistor is electrically connected to the first node, and the third electrode of the twelfth transistor is electrically connected to the fourth node.

15. The shift register unit according to claim 13, wherein: The pull-down sub-circuit comprises: a twelfth transistor; The first electrode of the twelfth transistor is electrically connected to the third voltage signal terminal, the second electrode of the twelfth transistor is electrically connected to the first node, and the third electrode of the twelfth transistor is electrically connected to the first node.

16. The shift register unit according to claim 1, wherein: The output circuit comprises: a tenth transistor and an eleventh transistor; A first electrode of the tenth transistor is electrically connected to the reference signal terminal, a second electrode of the tenth transistor is electrically connected to the driving output terminal, and a third electrode of the tenth transistor is electrically connected to the first node; The first electrode of the eleventh transistor is electrically connected to the first voltage signal terminal, the second electrode of the eleventh transistor is electrically connected to the drive output terminal, and the third electrode of the eleventh transistor is electrically connected to the drive output terminal. The second node is electrically connected.

17. The shift register unit according to claim 1, wherein: The output circuit comprises: a tenth transistor, an eleventh transistor and a thirteenth transistor; A first electrode of the tenth transistor is electrically connected to the reference signal terminal, a second electrode of the tenth transistor is electrically connected to the driving output terminal, and a third electrode of the tenth transistor is electrically connected to the second electrode of the thirteenth transistor; A first electrode of the eleventh transistor is electrically connected to the first voltage signal terminal, a second electrode of the eleventh transistor is electrically connected to the driving output terminal, and a third electrode of the eleventh transistor is electrically connected to the second node. A first electrode of the thirteenth transistor is electrically connected to the first node, and a third electrode of the thirteenth transistor is electrically connected to the first voltage signal terminal.

18. The shift register unit according to claim 16 or 17, wherein: The output circuit further includes: a fourth capacitor; A first electrode of the fourth capacitor is electrically connected to the first voltage signal terminal, and a second electrode of the fourth capacitor is electrically connected to the second node.

19. The shift register unit according to claim 1, wherein: The signal at the reference signal end and the signal at the first clock signal end are inverted signals.

20. The shift register unit according to claim 2, wherein: The signal at the first clock signal terminal and the signal at the second clock signal terminal are not valid level signals at the same time.

21. A display panel, comprising: A substrate, comprising a display area and a non-display area; The display area includes: Multiple sub-pixels; A plurality of scan lines, wherein a row of the sub-pixels in the plurality of sub-pixels is electrically connected to at least one of the scan lines in the plurality of scan lines; The non-display area includes: A gate drive circuit comprises a plurality of shift register units as described in any one of claims 1 to 20, wherein a drive output end of each of the plurality of shift register units is electrically connected to at least one of the plurality of scan lines.

22. The display panel according to claim 21, wherein: It also includes: an input signal line electrically connected to the gate drive circuit and arranged in the non-display area, a first voltage signal line far away from the display area, a first clock signal line and a second clock signal line; The input signal line, the first voltage signal line far away from the display area, the first clock signal line Any one of the gate line and the second clock signal line extends along a first direction, the gate line extends along a second direction, and the first direction intersects the second direction.

23. The display panel according to claim 22, wherein: The input signal line, the first clock signal line, the second clock signal line and the first voltage signal line away from the display area are arranged in sequence along the direction close to the display area on the substrate, and are located on the side of the shift register unit away from the display area.

24. The display panel according to claim 23, wherein: The input signal line, the first clock signal line, the second clock signal line and the first voltage signal line far away from the display area are arranged in the same layer.

25. The display panel according to claim 22, wherein: The input signal line, the first voltage signal line away from the display area, the first clock signal line and the second clock signal line are arranged in sequence along the direction close to the display area on the substrate, and are set on the side of the shift register unit away from the display area.

26. The display panel according to claim 25, wherein: The input signal line and the first voltage signal line away from the display area are arranged on the same layer, the first clock signal line and the second clock signal line are arranged on the same layer, and the input signal line, the first voltage signal line away from the display area and the first clock signal line, the second clock signal line are arranged on different layers.

27. The display panel according to claim 22, wherein: Also includes: A second voltage signal line is electrically connected to the gate driving circuit and disposed in the non-display area, wherein the second voltage signal line extends along a first direction.

28. The display panel according to claim 27, wherein: The second voltage signal line is arranged on a side of the first voltage signal line far from the display area and close to the display area.

29. The display panel according to claim 27, wherein: The device further comprises: a third voltage signal line electrically connected to the gate driving circuit and disposed in the non-display area, wherein the third voltage signal line extends along the first direction.

30. The display panel according to claim 29, wherein: The third voltage signal line is arranged on a side of the second voltage signal line close to the display area.

31. The display panel according to claim 29, wherein: It also includes: a third clock signal line, a fourth clock signal line, and a first voltage signal line close to the display area, which are electrically connected to the gate drive circuit and arranged in the non-display area, and the third clock signal line, the fourth clock signal line, and the first voltage signal line close to the display area extend along a first direction.

32. The display panel according to claim 31, wherein: Any one of the third clock signal line and the fourth clock signal line is arranged on a side of the third voltage signal line close to the display area; The first voltage signal line close to the display area is located at a side of any one of the third clock signal line and the fourth clock signal line close to the display area.

33. The display panel according to claim 31, wherein: The reference signal end of the i-th shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the reference signal end of the i+1-th shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

34. The display panel according to claim 22, wherein: The first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line; The first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.

35. The display panel according to claim 31, wherein: The width of any one of the input signal line, the first voltage signal line, the second voltage signal line and the third voltage signal line along the second direction is smaller than the width of any one of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line along the second direction.

36. The display panel according to claim 31, wherein: The shift register unit comprises: a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor and a first capacitor; At least a portion of any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor and the first capacitor is located between the first voltage signal line and the second voltage signal line.

37. The display panel according to claim 31, wherein: The shift register unit includes: a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a twelfth transistor and a second capacitor; At least a portion of any one of the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the twelfth transistor and the second capacitor is located between the second voltage signal line and the third voltage signal line.

38. The display panel according to claim 37, wherein: The active layer of the twelfth transistor extends along the first direction, at least a portion of any one of the first electrode and the second electrode of the twelfth transistor extends along the second direction, and the third electrode of the twelfth transistor extends along the second direction.

39. The display panel according to claim 31, wherein: The shift register unit comprises: a tenth transistor, an eleventh transistor and a third capacitor; At least a portion of any one of the tenth transistor, the eleventh transistor and the third capacitor is located on a side of the first voltage signal line close to the display area close to the display area; The orthographic projection of the first voltage signal line close to the display area on the base substrate partially overlaps with the orthographic projection of the third capacitor on the base substrate.

40. The display panel according to any one of claims 21 to 39, characterized in that: A channel width of an active layer of the tenth transistor is greater than a channel width of an active layer of the eighth transistor.

41. The display panel according to claim 40, characterized in that The channel width of the active layer of the tenth transistor is not less than 90 micrometers.

42. The display panel according to claim 40, characterized in that: The channel width of the active layer of the eighth transistor is not greater than 50 micrometers.

43. The display panel according to any one of claims 21 to 39, characterized in that: A channel width of an active layer of the eleventh transistor is greater than a channel width of an active layer of the ninth transistor.

44. The display panel according to claim 43, characterized in that The channel width of the active layer of the eleventh transistor is not less than 90 micrometers.

45. The display panel according to claim 43, characterized in that The channel width of the active layer of the ninth transistor is not greater than 50 micrometers.

46. ​​A display device comprising: A display panel as described in any one of claims 21 to 45.

47. A shift register driving method, comprising: The input subcircuit provides the signal of the input signal terminal to the first node under the control of the signal of the second clock signal terminal; A first control subcircuit controls the voltage of the second node under the control of the voltage of the first node and the signal of the first clock signal terminal; a second control subcircuit, under the control of the voltage of the second node and the signal of the first clock signal terminal, providing a signal of a second voltage signal terminal to the first node; a voltage stabilization subcircuit, under the control of a signal at the first voltage signal terminal, providing the voltage of the first node to a fourth node; a cascade sub-circuit, under the control of the voltages of the second node and the fourth node, providing a signal of the second voltage signal terminal or the first clock signal terminal to the cascade output terminal; The output circuit provides a signal of a reference signal terminal or a first voltage signal terminal to a driving output terminal under the control of the voltages of the first node and the second node.

48. The method of claim 47, wherein: The shift register unit further includes: a pull-down subcircuit; The method further includes: the pull-down sub-circuit provides a signal of a third voltage signal terminal to the first node under the control of the voltage of the first node or the fourth node.