“memory device including phase change memory cell and operation method thereof”

Abstract

A memory device includes a phase change memory (PCM) cell connected between a bit line and a word line. An X-decoder provides a word line voltage to the word line during a reset operation, and a Y-decoder provides a bit line voltage to the bit line during the reset operation. A voltage bias circuit generates the word line voltage and the bit line voltage based on a first bias during a first period of the reset operation, the word line voltage and the bit line voltage based on a second bias greater than the first bias during a second period of the reset operation, and the word line voltage and the bit line voltage based on a third bias smaller than the first and second biases during a third period of the reset operation. Fig. 1

Description

BACKGROUND

[0002] Embodiments of the present disclosure described herein relate to asemiconductor memory, and more particularly, relate to a memory device including aphase change memory cell and an operation method thereof.

[0003] A semiconductor memory is classified as a volatile memory, in whichstored data disappear when power is turned off, such as a static random accessmemory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatilememory, in which stored data are retained even when power is turned off, such as aflash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), aresistive RAM (RRAM), or a ferroelectric RAM (FRAM).

[0004] For example, a phase change memory (PCM) stores data by using aphysical characteristic of a phase change material (e.g., GST). The phase changematerial may have a crystalline state or an amorphous state, and a state of the phasechange material may be changed by controlling a magnitude of a current provided tothe phase change material or a time during which the current is applied to the phasechange material. A large write current is necessary to change a state of the phasechange material from the crystalline state to the amorphous state. The large writecurrent causes the degradation of the phase change memory or makes a distributionof high-speed cells worse.SUMMARY

[0005] Embodiments of the present disclosure provide a memory deviceincluding a phase change memory cell having improved lifetime and improvedreliability and an operation method thereof.

[0006] According to an embodiment, a memory device includes a first phasechange memory cell that is connected with a first bit line and a first word line. An Xdecoderprovides a selection word line voltage to the first word line during a resetwrite operation for changing a state of the first phase change memory cell from a setstate to a reset state. A Y-decoder provides a selection bit line voltage to the first bitline during the reset write operation. A voltage bias circuit generates the selectionword line voltage and the selection bit line voltage based on a first voltage biasduring a first period of the reset write operation, generates the selection word linevoltage and the selection bit line voltage based on a second voltage bias greater thanthe first voltage bias during a second period of the reset write operation, andgenerates the selection word line voltage and the selection bit line voltage based on athird voltage bias smaller than the first voltage bias and the second voltage biasduring a third period of the reset write operation.

[0007] According to an embodiment, an operation method of a memorydevice which includes a phase change memory cell includes: (1) applying a firstvoltage bias to a bit line and a word line, which are connected with the phase changememory cell, during a first period of a reset write operation for writing the phasechange memory cell to a reset state, (2) applying a second voltage bias greater thanthe first voltage bias to the bit line and the word line connected with the phasechange memory cell during a second period of the reset write operation after the firstperiod, and (3) applying a third voltage bias equal to or smaller than the first voltagebias to the bit line and the word line connected with the phase change memory cellduring a third period of the reset write operation after the second period.

[0008] According to an embodiment, an operation method of a memorydevice which includes a phase change memory cell includes turning on the phasechange memory cell, applying a reset write current to the phase change memory cell,and applying at least one current pulse to the phase change memory cell. While the atleast one current pulse is applied to the phase change memory cell, a voltage of a bitline connected with the phase change memory cell and a voltage of a word lineconnected with the phase change memory cell are uniformly maintained.

[0009] According to an embodiment, an operation method of a memorydevice, which includes a plurality of phase change memory cells connected to aplurality of bit lines and a plurality of word lines, includes: (1) selecting a targetmemory cell of the plurality of phase change memory cells, (2) applying a firstvoltage bias to a target bit line connected with the target memory cell from amongthe plurality of bit lines and a target word line connected with the target memory cellfrom among the plurality of word lines, during a first period of a reset writeoperation for changing a state of the target memory cell to a reset state, (3) applyinga second voltage bias greater than the first voltage bias to the target bit line and thetarget word line, during a second period of the reset write operation after the firstperiod, and (4) applying a third voltage bias equal to or smaller than the first voltagebias to the target bit line and the target word line during a third period of the resetwrite operation after the second period.BRIEF DESCRIPTION OF THE FIGURES

[0010] The above and other objects and features of the present disclosure willbecome apparent by describing in detail embodiments thereof with reference to theaccompanying drawings.

[0011] FIG. 1 is a block diagram illustrating a memory device according toan embodiment of the present disclosure.

[0012] FIG. 2 is a diagram illustrating a memory cell array of FIG. 1.

[0013] FIG. 3 is a diagram illustrating one of memory cells of FIG. 2.

[0014] FIGS. 4A and 4B are diagrams for describing a characteristicaccording to a state of a memory cell.

[0015] FIG. 5 is a flowchart illustrating a write operation of a memory deviceof FIG. 1.

[0016] FIG. 6 is a diagram for describing an operation according to aflowchart of FIG. 5.

[0017] FIG. 7 is a timing diagram illustrating a current flowing through atarget memory cell depending on an operation of a flowchart of FIG. 6.

[0018] FIGS. 8A to 8D are timing diagrams illustrating voltage biasesaccording to an operation of a flowchart of FIG. 6.

[0019] FIGS. 9A to 9C are distribution diagrams, current-voltage graphs, andtiming diagrams for describing operation S130 of FIG. 5.

[0020] FIG. 10 is a flowchart illustrating an operation of a memory device ofFIG. 1.

[0021] FIG. 11 is a timing diagram illustrating voltage biases according to anoperation of a flowchart of FIG. 10.

[0022] FIG. 12 is a circuit diagram illustrating a current bias circuit of FIG.1.

[0023] FIG. 13 is a timing diagram for describing an operation of a currentbias circuit of FIG. 12.

[0024] FIG. 14 is a block diagram illustrating a memory device according toan embodiment of the present disclosure.

[0025] FIG. 15 is a circuit diagram illustrating a three-dimensional structureof a memory device according to an embodiment of the present disclosure.

[0026] FIG. 16 is a block diagram illustrating a memory system including amemory device according to the present disclosure.

[0027] FIG. 17 is a block diagram illustrating a user system to which amemory device according to the present disclosure is applied.DETAILED DESCRIPTION

[0028] Below, embodiments of the present disclosure may be described indetail and clearly to such an extent that one skilled in the art easily implements thepresent disclosure.

[0029] FIG. 1 is a block diagram illustrating a memory device according toan embodiment of the present disclosure. Referring to FIG. 1, a memory device 100may include a memory cell array 110, a row decoder (X-DEC) (hereinafter referredto as an "X-decoder") 120, a column decoder (Y-DEC) (hereinafter referred to as a"Y-decoder") 130, a voltage bias circuit 140, a current bias circuit 150, and a controllogic circuit 160.

[0030] The memory cell array 110 may include a plurality of memory cells.The plurality of memory cells may be connected with word lines WL and bit linesBL.

[0031] The X-decoder 120 may be connected with the memory cell array 110through the plurality of word lines WL. The X-decoder 120 may be configured tocontrol voltage levels of the plurality of word lines WL. For example, the X-decoder120 may select at least one of the plurality of word lines WL, may provide aselection word line voltage VWL_sel to the selected word line, and may provide anon-selection word line voltage VWL_unsel to unselected word lines.

[0032] The Y-decoder 130 may be connected with the memory cell array 110through the plurality of bit lines BL. The Y-decoder 130 may be configured tocontrol voltage levels of the plurality of bit lines BL. For example, the Y-decoder130 may select at least one of the plurality of bit lines BL, may provide a selectionbit line voltage VBL_sel to the selected bit line, and may provide a non-selection bitline voltage VBL_unsel to unselected bit lines.

[0033] The voltage bias circuit 140 may be configured to generate variousvoltages necessary for the memory device 100 to operate. For example, the voltagebias circuit 140 may be configured to generate various voltages such as the selectionword line voltage VWL_sel, the non-selection word line voltage VWL_unsel, theselection bit line voltage VBL_sel, and the non-selection bit line voltage VBL_unsel.In an embodiment, the above-described voltages may be voltages that are used in awrite operation of the memory device 100 (in particular, an operation of changingmemory cells from a set state to a reset state, an operation of writing memory cells tothe reset state, or a reset operation associated with memory cells). However, thepresent disclosure is not limited thereto. For example, the voltage bias circuit 140may be configured to generate various voltages that are used in other operations formemory cells, such as a read operation and a set operation.

[0034] The current bias circuit 150 may be configured to generate a currentbias CB. The current bias CB may be used to restrict or control a magnitude of acurrent flowing through the bit line BL in a write operation (in particular, a resetwrite operation) of the memory device 100. For example, the Y-decoder 130 mayrestrict a current flowing through a selected bit line to a magnitude of the current biasCB. In an embodiment, the current bias CB may have a magnitude that is determinedin advance depending on a physical characteristic of memory cells. The current biasCB will be more fully described with reference to the following drawings.

[0035] The control logic circuit 160 may be configured to control overalloperations of the memory device 100. For example, the control logic circuit 160 maybe configured to control the voltage bias circuit 140 and the current bias circuit 150for the purpose of writing data in the memory cell array 110.

[0036] In an embodiment, the memory device 100 according to anembodiment of the present disclosure may be a phase change memory (PCM) device.That is, the memory cell array 110 may include phase change memory (PCM) cells.However, the present disclosure is not limited thereto. For example, like a resistivememory (ReRAM), the memory device 100 may include memory elements thatallow threshold voltages or resistance values of memory cells to be variabledepending on a write current. Below, for convenience of description, it is assumedthat the memory device 100 includes a phase change memory.

[0037] A phase change memory cell may have a set state or a reset statedepending on a magnitude of a threshold voltage Vth. That is, data may be written inthe phase change memory cell by adjusting a magnitude of a threshold voltage of thephase change memory cell. Below, to describe the present disclosure easily, it isassumed that the memory device 100 according to an embodiment of the presentdisclosure performs an operation of changing states of memory cells from the setstate to the reset state (hereinafter, the operation being referred to as a "resetoperation" or a "reset write operation" for a memory cell). However, the presentdisclosure is not limited thereto.

[0038] In general, a large write current is used in the reset write operation fora memory cell. In this case, because a large write current flows to a memory cell,memory cells may be degraded. In contrast, in the case where the magnitude and thetime of a write current used in the reset operation are not sufficient, becausethreshold voltages of memory cells are not normally changed, a read margin for thememory cells (i.e., a difference between a threshold voltage distribution of the setstate and a threshold voltage distribution of the reset state) may not be secured. Thatis, the reliability of the memory device 100 may be reduced.

[0039] The memory device 100 according to an embodiment of the presentdisclosure may be configured to apply a plurality of current pulses (or spike currents)to target memory cells in the reset write operation. In this case, because a large writecurrent is not used during a long time, the degradation of memory cells may bereduced, and a read margin for the memory cells (i.e., a difference between athreshold voltage distribution of the set state and a threshold voltage distribution ofthe reset state) may also be secured. Accordingly, a memory device with improvedreliability and improved lifetime is provided. The write operation (i.e., the reset writeoperation) of the memory device 100 according to an embodiment of the presentdisclosure will be more fully described with reference to the following drawings.

[0040] FIG. 2 is a diagram illustrating a memory cell array of FIG. 1. FIG. 3is a diagram illustrating one of memory cells of FIG. 2. For brevity of drawing andconvenience of description, it is assumed that the memory cell array 110 includes 9memory cells MC11 to MC33 arranged in 3 rows and 3 columns (i.e., a 3x3 matrix).However, the present disclosure is not limited thereto. For example, the number ofmemory cells and the arrangement of memory cells may be variously changed ormodified. Also, one memory cell (e.g., MC22) will be described with reference toFIG. 3, but the present disclosure is not limited thereto. For example, the remainingmemory cells may also have a structure similar to that of the memory cell MC22 ofFIG. 3.

[0041] Referring to FIGS. 1 and 3, the memory cell array 110 may includethe plurality of memory cells MC11 to MC33. The plurality of memory cells MC11to MC33 may be connected with a plurality of word lines WL1 to WL3 and aplurality of bit lines BL1 to BL3.

[0042] Each of the plurality of memory cells MC11 to MC33 may be a phasechange memory cell. For example, one memory cell (e.g., MC22) of the plurality ofmemory cells MC11 to MC33 is illustrated in FIG. 3. As illustrated in FIG. 3, thememory cell MC22 may be connected between the second word line WL2 and thesecond bit line BL2. The memory cell MC22 may include an ovonic threshold switchOTS and a phase change material GST.

[0043] The ovonic threshold switch OTS may be a switching element havinga bidirectional characteristic. In an embodiment, the ovonic threshold switch OTSmay be a switching element having a non-linear current-voltage characteristic (or asnapback characteristic). In an embodiment, the ovonic threshold switch OTS mayhave a crystalline-amorphous phase transition temperature higher than a phasechange material (e.g., GST). For example, a phase transition temperature of theovonic threshold switch OTS may be about 350°C to about 450°C.

[0044] In an embodiment, the ovonic threshold switch OTS may include atleast one of GeSe, GeS, AsSe, AsTe, AsS SiTe, SiSe, SiS, GeAs, SiAs, SnSe, andSnTe. In an embodiment, the ovonic threshold switch OTS may include at least oneof GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe,GaAsTe, InAsSe, InAsTe, SnAsSe, and SnAsTe. In an embodiment, the ovonicthreshold switch OTS may include at least one of GeSiAsTe, GeSiAsSe, GeSiSeTe,GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb,GeAsTeSb, GeAsTeBi, GeAsSeBi, GeAsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl,GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTeSn,and GeAsTeZn. In an embodiment, the ovonic threshold switch OTS may include atleast one of GeSiAsSeTe, GeAsSeTeS, GeSiAsSeS, GeSiAsTeS, GeSiSeTeS,GeSiAsSeP, GeSiAsTeP, GeAsSeTeP, GeSiAsSeIn, GeSiAsSeGa, GeSiAsSeAl,GeSiAsSeTl, GeSiAsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl,GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa,GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTeSn, GeAsSeSIn, GeAsSeSGa,GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa,GeAsTeSAl, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl,GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl,GeAsSeGaZn, GeAsSeGaSn, GeAsSeAlTl, GeAsSeAlZn, GeAsSEAlSn,GeAsSeTlZn, GeAsSeTlSn, and GeAsSeZnSn. In an embodiment, the ovonicthreshold switch OTS may include at least one of GeSiAsSeTeS, GeSiAsSeTeIn,GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn, GeSiAsSeTeSn,GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl,GeSiAsSeSZn, GeSiAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl,GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeTePIn, GeAsSeTePGa,GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa,GeSiAsSeInAl, GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl,GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGaSn, GeSiAsSeAlSn, GeAsSeTeInGa,GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTeGaAl,GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa,GeAsSeSInAl, GeAsSeSInTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl,GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, and GeAsSeSAlSn.

[0045] The phase change material GST may have one of a crystalline stateand an amorphous state. For example, a threshold voltage of the phase changematerial GST being in the crystalline state may be lower than a threshold voltage ofthe phase change material GST being in the amorphous state. In an embodiment, inthe case where the phase change material GST is in the crystalline state, the memorycell MC22 may be in the set state; in the case where the phase change material GSTis in the amorphous state, the memory cell MC22 may be in the reset state.

[0046] A state (i.e., the crystalline state or the amorphous state) of the phasechange material GST may be determined depending on a temperature. In anembodiment, a crystalline-amorphous phase transition temperature of the phasechange material GST may be about 250°C to about 350°C. A temperature of thephase change material GST may be determined depending on a magnitude and a time(or duration) of a write current Iwr flowing through the memory cell MC22. Forexample, in the case where the write current Iwr is at a first level and is appliedduring a first time (or first duration or a first time period), the phase change materialGST may have the crystalline state; in the case where the write current Iwr is at asecond level higher than the first level and is applied during a second time (or secondduration or a second time period), the phase change material GST may have theamorphous state. That is, a state of the memory cell MC22 may be changeddepending on the magnitude and the time of the write current Iwr, and thus, data maybe written in the memory cell MC22. In an embodiment, the magnitude and the timeof the write current Iwr may be determined depending on a voltage difference of thesecond bit line BL2 and the second word line WL2 and a characteristic of the ovonicthreshold switch OTS.

[0047] In an embodiment, the phase change material GST may be formed ofa compound of at least one of Te, Se, and S being a chalcogen element and at leastone selected from a group of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, andC.

[0048] In an embodiment, the phase change material GST may include atleast one of GeTe, GeSe, GeS, SbSe, SbTe, SbS, SbSe, SnSb, InSe, InSb, AsTe,AlTe, GaSb, AlSb, BiSb, ScSb, Ysb, CeSb, DySb, and NdSb. In an embodiment, thephase change material GST may include at least one of GeSbSe, AlSbTe, AlSbSe,SiSbSe, SiSbTe, GeSeTe, InGeTe, GeSbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe,GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTe, ScSbTe,ScSbSe, ScSbS, YSbTe, YSbSe, YSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe,DySbS, NdSbTe, NdSbSe, and NdSbS. In an embodiment, the phase change materialGST may include at least one of GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe,GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe, BiSiGeSe, BiSiGeTe,GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn,GeSbSeZn, GeSbTeIn, GeSbTeGa, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn,ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGeSbSe, YGeSbS, CeGeSbTe,CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe,and NdGeSbS. In an embodiment, the phase change material GST may include atleast one of InSbTeAsSe, GeScSbSeTe, GeSbSeTeS, GeScSbSeS, GeScSbTeS,GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa,GeScSbSeAl, GeScSbSeTl, GeScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa,GeSbAsTeAl, GeScSbTeTl, GeScSbTeZn, GeScSbTeSn, GeSbSeTeIn,GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, GeSbSeTeSn, GeSbSeSIn,GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTeSIn,GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa,GeSbSeInAl, GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl,GeSbSeGaZn, GeSbSeGaSn, GeSbSeAlTl, GeSbSeAlZn, GeSbSeAlSn,GeSbSeTlZn, GeSbSeTlSn, and GeSbSeZnSn.

[0049] An embodiment is illustrated in FIG. 3 in which the ovonic thresholdswitch OTS is connected with the second bit line BL2 and the phase change materialGST is connected between the ovonic threshold switch OTS and the second wordline WL2, but the present disclosure is not limited thereto. For example, because theovonic threshold switch OTS is a bidirectional switching element, the ovonicthreshold switch OTS may be connected with a word line and the phase changematerial GST may be connected between the ovonic threshold switch OTS and a bitline.

[0050] An embodiment is illustrated in FIG. 3 in which the write current Iwrflows from a bit line to a word line, but the present disclosure is not limited thereto.For example, a direction of the write current Iwr or a read current (not illustrated)may be variously changed or modified depending on a way to implement a memorydevice (i.e., a WL to BL direction or a BL to WL direction). Below, for convenienceof description, it is assumed that a write current (in particular, a current for the resetwrite operation) flows toward a word line from a bit line.

[0051] FIGS. 4A and 4B are diagrams for describing a characteristicaccording to a state of a memory cell. FIG. 4A shows threshold voltage distributionsof memory cells, and FIG. 4B shows voltage-current curves according to states ofmemory cells. In the distributions of FIG. 4A, a horizontal axis represents a thresholdvoltage of a memory cell and a vertical axis represents the number of memory cells.In the graphs of FIG. 4B, a horizontal axis represents a voltage applied to a memorycell (i.e., a voltage difference between a bit line and a word line) and a vertical axisrepresents a current flowing through a memory cell.

[0052] Referring to FIGS. 4A and 4B, as described above, a memory cellmay have one of a set state SET and a reset state RST. A threshold voltage Vth of amemory cell of the set state SET may be smaller than a threshold voltage Vth of amemory cell of the reset state RST. For example, an upper limit value of thethreshold voltage distribution of the set state SET may be smaller than a lower limitvalue of the threshold voltage distribution of the reset state RST. For example, asillustrated in FIG. 4B, a threshold voltage of a memory cell of the set state SET maybe a first threshold voltage Vth1 and a threshold voltage of a memory cell of the resetstate RST may be a second threshold voltage Vth2 greater than the first thresholdvoltage Vth1.

[0053] To read data stored in a specific memory cell, a read voltage Vreadmay be applied between a bit line and a word line connected with the specificmemory cell. In this case, as illustrated in FIG. 4B, when the specific memory cell isin the set state SET, the specific memory cell may be turned on; when the specificmemory cell is in the reset state RST, the specific memory cell may be turned off.That is, data stored in the specific memory cell may be read by determining whetherthe specific memory cell is turned on or turned off, with the read voltage Vreadapplied between the bit line and the word line connected with the specific memorycell.

[0054] FIG. 5 is a flowchart illustrating a write operation of a memory deviceof FIG. 1. FIG. 6 is a diagram for describing an operation according to the flowchartof FIG. 5. Below, for convenience of description, it is assumed that the memorydevice 100 performs the reset write operation on the memory cell MC22. That is, thememory device 100 may change a state of the memory cell MC22 from the set stateSET to the reset state RST through a write method to be described below. Below, thememory cell MC22 is referred to as a "target memory cell", and the second bit lineBL2 and the second word line WL2 are respectively referred to as a "target bit line"and a "target word line".

[0055] Below, the terms "voltage bias" and "current bias" are used. Thevoltage bias may indicate a voltage difference of a relevant bit line and a relevantword line. The current bias may indicate a restriction current flowing to the relevantbit line. In this case, the restriction current by the current bias may not be absolute;even though a current is restricted by the current bias, it may be understood that acurrent larger than the current bias flows in a moment depending on any othervoltage bias or a physical state of a target memory cell.

[0056] Referring to FIGS. 1, 5, and 6, in operation S101, the memory device100 may select a target memory cell. For example, the memory device 100 mayreceive an address and data from an external device (e.g., a memory controller) andmay select a target memory cell based on the received address and data. In this case,the target memory cell may indicate a memory cell to be changed from the set stateSET to the reset state RST.

[0057] In detail, as illustrated in FIG. 6, the memory cell MC22 (hereinafter,MC22 being referred to as a "target memory cell") may be selected as a targetmemory cell. The target memory cell MC22 may indicate a memory cell to bechanged from the set state SET to the reset state RST.

[0058] In operation S110, the memory device 100 may control a target bitline BL and a target word line WL corresponding to the target memory cell MC22such that the target memory cell MC22 is turned on. For example, the memorydevice 100 may apply a first voltage bias VB1 between a target bit line BL2 and atarget word line WL2 connected with the target memory cell MC22. In detail, asillustrated in FIG. 6, the selection bit line voltage VBL_sel may be applied to thetarget bit line BL2 connected with the target memory cell MC22 and the selectionword line voltage VWL_sel may be applied to the target word line WL2 connectedwith the target memory cell MC22. In this case, a difference between the selectionword line voltage VWL_sel and the selection bit line voltage VBL_sel may be thefirst voltage bias VB1.

[0059] The memory device 100 may apply a first current bias CB1 to thetarget bit line BL2 connected with the target memory cell MC22. A current flowingthrough the target bit line BL2 may be restricted by the first current bias CB1.

[0060] In an embodiment, the first voltage bias VB1 may be a voltage levelhigher than a threshold voltage of a memory cell of the reset state RST. That is, inthe case where the first voltage bias VB1 is applied to the target bit line BL2 and thetarget word line WL2 of the target memory cell MC22, the target memory cell MC22may be turned on. The first current bias CB1 may be a set write current (to bedescribed with reference to FIG. 7).

[0061] In an embodiment, the non-selection word line voltage VWL_unselmay be applied to unselected word lines (e.g., WL1 and WL3), and the non-selectionbit line voltage VBL_unsel may be applied to unselected bit lines BL1 and BL3. Thenon-selection word line voltage VWL_unsel and the non-selection bit line voltageVBL_unsel may be set such that the remaining memory cells MC11 to MC13,MC21, MC23, and MC31 to MC33 other than the target memory cell MC22 are notturned on.

[0062] For example, the memory cell MC11 may not be turned on by thenon-selection word line voltage VWL_unsel of the first word line WL1 and the nonselectionbit line voltage VBL_unsel of the first bit line BL1. The memory cellMC12 may not be turned on by the non-selection word line voltage VWL_unsel ofthe first word line WL1 and the selection bit line voltage VBL_sel of the second bitline BL2. The memory cell MC21 may not be turned on by the non-selection wordline voltage VWL_unsel of the second word line WL2 and the non-selection bit linevoltage VBL_unsel of the first bit line BL1.

[0063] In operation S120, the memory device 100 may control the target bitline BL2 and the target word line WL2 corresponding to the target memory cellMC22 such that a reset write current is provided to the target memory cell MC22.For example, the memory device 100 may control the selection bit line voltageVBL_sel and the selection word line voltage VWL_sel such that a second voltagebias VB2 is applied to the target bit line BL2 and the target word line WL2 of thetarget memory cell MC22. The memory device 100 may apply a second current biasCB2 to the target bit line BL2 connected with the target memory cell MC22.

[0064] Operation S120 is similar to operation S110 except that a voltage biasand a current bias between a target bit line and a target word line connected with atarget memory cell in operation S120 are different from those in operation S110, andthus, additional description will be omitted to avoid redundancy. In an embodiment,the second voltage bias VB2 may be greater than the first voltage bias VB1 and thesecond current bias CB2 may be greater than the first current bias CB1. In anembodiment, the second current bias CB2 may correspond to a magnitude of thereset write current.

[0065] In operation S130, the memory device 100 may control the second bitline BL2 and the second word line WL2 corresponding to the target memory cellMC22 such that spike currents (or current pulses) are provided to the target memorycell MC22. For example, the memory device 100 may control the selection bit linevoltage VBL_sel and the selection word line voltage VWL_sel such that a thirdvoltage bias VB3 is applied to the second bit line BL2 and the second word line WL2of the target memory cell MC22. The memory device 100 may apply a third currentbias CB3 to the target bit line BL2 connected with the target memory cell MC22.

[0066] Operation S130 is similar to operation S110 except that a voltage biasand a current bias between a target bit line and a target word line connected with atarget memory cell in operation S130 are different from those in operation S110, andthus, additional description will be omitted to avoid redundancy. In an embodiment,the third current bias CB3 may be smaller than each of the first and second currentbiases CB1 and CB2. In an embodiment, the third current bias CB3 may be smallerthan or equal to a hold current Ihold according to a current-voltage characteristic ofthe target memory cell MC22. In an embodiment, the hold current Ihold may indicatea minimum current magnitude necessary for the target memory cell MC2 to maintaina turn-on state.

[0067] In an embodiment, in the case where the third voltage bias VB3 andthe third current bias CB3 are applied to the target memory cell MC22 in operationS130, at least one spike current (or at least one current pulse) may be generated by aphysical characteristic of the target memory cell MC22. In an embodiment, at leastone spike current may be generated by an iterative switching operation of a targetmemory cell.

[0068] A threshold voltage of a target memory cell may be finely adjusted (orincreased) by the at least one spike current (or the at least one current pulse). That is,as the threshold voltage of the target memory cell is increased by the at least onespike current (or the at least one current pulse), a read margin may be secured. Awrite operation using at least one spike current (or at least one current pulse) will bedescribed with reference to the following drawings.

[0069] As described above, according to an embodiment of the presentdisclosure, the memory device 100 may turn on a target memory cell based on thefirst voltage bias VB1. Afterwards, the memory device 100 may apply the reset writecurrent to the target memory cell based on the second voltage bias VB2 such that thethreshold voltage of the target memory cell increases. Afterwards, the memorydevice 100 may apply at least one spike current or at least one current pulse to thetarget memory cell based on the third voltage bias VB3 such that the thresholdvoltage of the target memory cell slowly increases.

[0070] In an embodiment, the memory device 100 according to anembodiment of the present disclosure may generate at least one current pulse in astate where a voltage bias between a target bit line and a target word line connectedwith the target memory cell is uniformly maintained.

[0071] In an embodiment, a time during which a reset write current is appliedin the memory device 100 according to an embodiment of the present disclosure maybe shorter than a time during which a reset write current is applied in a conventionalphase change memory. However, in the present disclosure, as a threshold voltage ofa target memory cell is stepwise or gradually increased through at least one spikecurrent or at least one current pulse, data may be normally written in the targetmemory cell. Accordingly, the reliability and lifetime of the memory device 100 maybe provided.

[0072] FIG. 7 is a timing diagram illustrating a current flowing through atarget memory cell depending on an operation of the flowchart of FIG. 6. In thetiming diagram of FIG. 7, a horizontal axis represents time and a vertical axisrepresents a current flowing through the target memory cell MC22.

[0073] Referring to FIGS. 6 and 7, the memory device 100 may change astate of the target memory cell MC22 from the set state SET to the reset state RSTthrough first to third periods PR1 to PR3. The first period PR1 may correspond tooperation S110 of FIG. 5, the second period PR2 may correspond to operation S120of FIG. 5, and the third period PR3 may correspond to operation S130 of FIG. 5.

[0074] First, in the first period PR1 from a 0-th time t0 to a first time t1, thefirst voltage bias VB1 may be applied to the second bit line BL2 and the secondword line WL2 of the target memory cell MC22. In this case, such a current asillustrated in the first period PR1 of FIG. 7 may flow through the target memory cellMC22. In detail, at the 0-th time t0, the target memory cell MC22 may have the setstate SET. The first voltage bias VB1 may be higher than an upper limit value of athreshold voltage distribution of the set state SET. Accordingly, at the 0-th time t0,when the first voltage bias VB1 is applied, the target memory cell MC22 may beturned on, and thus, a peak current Isp may flow in a moment. Afterwards, as thecurrent decreases depending on a current-voltage characteristic (i.e., a snapbackcharacteristic) of the target memory cell MC22, a current magnitude may bemaintained at a set write current Iset.

[0075] In an embodiment, the first current bias CB1 applied in the first periodPR1 may be correspond to the set write current Iset. In an embodiment, in the casewhere the set write current Iset is consistently maintained, the target memory cellMC22 may have the set state SET. That is, in the case where there is a need to switcha state of the target memory cell MC22 from the reset state RST to the set state SET,a current flowing through the target memory cell MC22 may be maintained at the setwrite current Iset.

[0076] During the second period PR2 from the first time t1 to a second timet2, the second voltage bias VB2 may be applied to the second bit line BL2 and thesecond word line WL2 of the target memory cell MC22. In this case, such a resetwrite current Irst as illustrated in the second period PR2 of FIG. 7 may flow throughthe target memory cell MC22. The reset write current Irst may be greater than the setwrite current Iset. The reset write current Irst may be a current for setting the phasechange material GST of the target memory cell MC22 to the amorphous state. In anembodiment, the second current bias CB2 applied in the second period PR2 may becorrespond to the reset write current Irst.

[0077] During the third period PR3 from the second time t2 to a third time t3,the third voltage bias VB3 may be applied to the second bit line BL2 and the secondword line WL2 of the target memory cell MC22. In this case, the third voltage biasVB3 may be lower than the second voltage bias VB2 or may be equal to or lowerthan the first voltage bias VB1.

[0078] During the third period PR3, as the third voltage bias VB3 is appliedto the second bit line BL2 and the second word line WL2 of the target memory cellMC22, as illustrated in FIG. 7, a plurality of spike currents (or a plurality of currentpulses) may flow through the target memory cell MC22. In an embodiment, a peakvalue of the plurality of spike currents may correspond to a value of Isp or may bechanged depending on the number of current pulses to be generated. Alternatively,the peak value of the plurality of spike currents may be determined depending on acurrent state or a physical characteristic of the target memory cell MC22.

[0079] In an embodiment, the number of spike currents may be changeddepending on the current state or the physical characteristic of the target memory cellMC22.

[0080] In an embodiment, each of a time (i.e., t0 to t1) of the first periodPR1, a time (i.e., t1 to t2) of the second period PR2, and a time (i.e., t2 to t3) of thethird period PR3 may be a given time. In an embodiment, the times of the first tothird periods PR1 to PR3 may have a relationship of PR2 > PR3 ≥ PR1.

[0081] FIGS. 8A to 8D are timing diagrams illustrating voltage biasesaccording to an operation of the flowchart of FIG. 6. In the timing diagrams of FIGS.8A to 8D, a horizontal axis represents time and a vertical axis represents voltage. Forbrevity of drawing, in each timing diagram, a dash-single dotted line indicates theselection word line voltage VWL_sel and a solid line indicates the selection bit linevoltage VBL_sel. The selection bit line voltage VBL_sel and the selection word linevoltage VWL_sel to be described with reference to FIGS. 8A to 8D may begenerated or adjusted by the voltage bias circuit 140 described with reference to FIG.1.

[0082] First, as illustrated in FIG. 8A, during the reset write operation, theselection word line voltage VWL_sel may maintain a uniform level and the selectionbit line voltage VBL_sel may change in the first to third periods PR1 to PR3. Forexample, in the first period PR1, the selection bit line voltage VBL_sel may increasesuch that a voltage difference of the selection bit line voltage VBL_sel and theselection word line voltage VWL_sel is the first voltage bias VB1. Next, in thesecond period PR2, the selection bit line voltage VBL_sel may increase such that avoltage difference of the selection bit line voltage VBL_sel and the selection wordline voltage VWL_sel is the second voltage bias VB2. Then, in the third period PR3,the selection bit line voltage VBL_sel may decrease such that a voltage difference ofthe selection bit line voltage VBL_sel and the selection word line voltage VWL_selis the third voltage bias VB3. In an embodiment, the selection word line voltageVWL_sel may be a ground voltage or may be a given voltage.

[0083] First, as illustrated in FIG. 8B, during the reset write operation, theselection word line voltage VWL_sel and the selection bit line voltage VBL_sel maychange in the first to third periods PR1 to PR3. For example, in the first period PR1,the selection bit line voltage VBL_sel may increase from a voltage Va, and theselection word line voltage VWL_sel may decrease from the voltage Va; thus, in thefirst period PR1, a voltage difference of the selection bit line voltage VBL_sel andthe selection word line voltage VWL_sel may be the first voltage bias VB1. Next, inthe second period PR2, the selection bit line voltage VBL_sel may increase, and theselection word line voltage VWL_sel may decrease; thus, in the second period PR2,a voltage difference of the selection bit line voltage VBL_sel and the selection wordline voltage VWL_sel may be the second voltage bias VB2. Then, in the third periodPR3, the selection bit line voltage VBL_sel may decrease, and the selection wordline voltage VWL_sel may increase; thus, in the third period PR3, a voltagedifference of the selection bit line voltage VBL_sel and the selection word linevoltage VWL_sel may be the third voltage bias VB3. In an embodiment, the voltageVa may be the ground voltage or may be a given voltage.

[0084] Then, as illustrated in FIG. 8C, during the reset write operation, theselection word line voltage VWL_sel and the selection bit line voltage VBL_sel maychange in the first to third periods PR1 to PR3. For example, in the first period PR1,the selection word line voltage VWL_sel may maintain the voltage Va and theselection bit line voltage VBL_sel may increase such that a voltage difference of theselection bit line voltage VBL_sel and the selection word line voltage VWL_sel isthe first voltage bias VB1. Next, in the second period PR2, the selection bit linevoltage VBL_sel may increase and the selection word line voltage VWL_sel maydecrease; thus, in the second period PR2, a voltage difference of the selection bit linevoltage VBL_sel and the selection word line voltage VWL_sel may be the secondvoltage bias VB2. Then, in the third period PR3, the selection bit line voltageVBL_sel may decrease and the selection word line voltage VWL_sel may increase;thus, in the third period PR3, a voltage difference of the selection bit line voltageVBL_sel and the selection word line voltage VWL_sel may be the third voltage biasVB3. In an embodiment, the selection word line voltage VWL_sel in the first andthird periods PR1 and PR3 may be the same as the voltage Va. The voltage Va maybe the ground voltage or may be a given voltage.

[0085] Then, as illustrated in FIG. 8D, during the reset write operation, theselection bit line voltage VBL_sel may maintain a uniform level and the selectionword line voltage VWL_sel may change in the first to third periods PR1 to PR3. Forexample, in the first period PR1, the selection word line voltage VWL_sel maydecrease such that a voltage difference of the selection bit line voltage VBL_sel andthe selection word line voltage VWL_sel is the first voltage bias VB1. Next, in thesecond period PR2, the selection word line voltage VWL_sel may decrease such thata voltage difference of the selection bit line voltage VBL_sel and the selection wordline voltage VWL_sel is the second voltage bias VB2. Then, in the third period PR3,the selection word line voltage VWL_sel may increase such that a voltage differenceof the selection bit line voltage VBL_sel and the selection word line voltageVWL_sel is the third voltage bias VB3. In an embodiment, the selection bit linevoltage VBL_sel may be the ground voltage or may be a given voltage.

[0086] The above way to control a bit line and a word line is provided as anexample, and the present disclosure is not limited thereto. For example, the memorydevice 100 according to an embodiment of the present disclosure may control a bitline and a word line of a target memory cell in various manners, during the resetwrite operation. In this case, the memory device 100 may control the bit line and theword line of the target memory cell such that voltage differences of the bit line andthe word line of the target memory cell are the first to third voltage biases VB1 toVB3 in the first to third periods PR1 to PR3, respectively.

[0087] In an embodiment, the non-selection bit line voltage VBL_unsel andthe non-selection word line voltage VWL_unsel may be variously controlleddepending on a way to drive the selection word line voltage VWL_sel and theselection bit line voltage VBL_sel. In an embodiment, in each of the first to thirdperiods PR1 to PR3, the non-selection bit line voltage VBL_unsel and the nonselectionword line voltage VWL_unsel may have an intermediate value of theselection word line voltage VWL_sel and the selection bit line voltage VBL_sel. Forexample, referring to the timing diagram of FIG. 8A, in the first period PR1, the nonselectionbit line voltage VBL_unsel and the non-selection word line voltageVWL_unsel may be greater than the selection word line voltage VWL_sel by asmuch as half the first voltage bias VB1 (i.e., VB1 / 2); in the second period PR2, thenon-selection bit line voltage VBL_unsel and the non-selection word line voltageVWL_unsel may be greater than the selection word line voltage VWL_sel by asmuch as half the second voltage bias VB2 (i.e., VB2 / 2); in the third period PR3, thenon-selection bit line voltage VBL_unsel and the non-selection word line voltageVWL_unsel may be greater than the selection word line voltage VWL_sel by asmuch as half the third voltage bias VB3 (i.e., VB3 / 2). Alternatively, in the casewhere the selection bit line voltage VBL_sel and the selection word line voltageVWL_sel are driven as illustrated in FIG. 8B, the non-selection bit line voltageVBL_unsel and the non-selection word line voltage VWL_unsel may be the specificvoltage Va.

[0088] In this case, because a voltage difference of an unselected word lineand an unselected bit line is 0 V and a voltage difference of a selected bit line and theunselected word line and a voltage difference of the unselected bit line and theunselected word line are a maximum of VB2 / 2, memory cells (e.g., MC11, MC12,MC13, MC21, MC23, MC31, MC32, and MC33 of FIG. 6) connected with theunselected word line and the unselected bit line may not be turned on.

[0089] The above ways to control the non-selection bit line voltageVBL_unsel and the non-selection word line voltage VWL_unsel are provided as anexample, and the present disclosure is not limited thereto. For example, the nonselectionbit line voltage VBL_unsel and the non-selection word line voltageVWL_unsel may be controlled in various manners.

[0090] FIGS. 9A to 9C are distribution diagrams, current-voltage graphs, andtiming diagrams for describing operation S130 of FIG. 5. In the distribution diagramsof FIGS. 9A and 9B, a horizontal axis represents a threshold voltage of memory cellsand a vertical axis represents the number of memory cells. In the current-voltagegraphs of FIGS. 9A to 9C, a horizontal axis represents a voltage applied to a memorycell (i.e., a voltage between a bit line and a word line) and a vertical axis represents acurrent flowing through a memory cell. In the timing diagrams of FIGS. 9A to 9C, ahorizontal axis represents time and a vertical axis represents a current flowingthrough a memory cell.

[0091] For brevity of drawing and convenience of description, thedistribution diagrams, current-voltage graphs, and timing diagrams illustrated inFIGS. 9A to 9C are associated with a memory cell at a specific time, but the presentdisclosure is not limited thereto.

[0092] First, referring to FIGS. 5 and 9A, after operation S120 is completed,a target memory cell may have a first threshold voltage Vth1 as illustrated in thedistribution diagram of FIG. 9A. That is, even though a threshold voltage of thetarget memory cell increases compared to the set state SET, the threshold voltage ofthe target memory cell may fail to reach the reset state RST, which is an intendedstate of the target memory cell.

[0093] In this case, the third voltage bias VB3 may be applied to a bit lineand a word line of the target memory cell. The third voltage bias VB3 may be higherthan an upper limit value of the threshold voltage distribution of the set state SETand may be lower than a lower limit value of the threshold voltage distribution of thereset state RST. In an embodiment, the third voltage bias VB3 may correspond to theread voltage Vread described with reference to FIGS. 4A and 4B. Alternatively, thethird voltage bias VB3 may correspond to the lower limit value of the thresholdvoltage distribution of memory cells belonging to the reset state RST.

[0094] In the case where the third voltage bias VB3 is applied to the bit lineand the word line of the target memory cell, as illustrated in the current-voltagegraph of FIG. 9A, because the third voltage bias VB3 is higher than the firstthreshold voltage Vth1 of the target memory cell, a first peak current Isp1 may flowthrough the target memory cell (operation 1).

[0095] Because the third current bias CB3 is applied through the bit line ofthe target memory cell, after operation 1, a current flowing through the targetmemory cell may slowly decrease to the third current bias CB3 (operation 2). In anembodiment, the third current bias CB3 may be smaller than or equal to the holdcurrent Ihold of the target memory cell. The hold current Ihold may indicate aminimum current necessary for the target memory cell to maintain a turn-on state. Inthis case, when a current flowing through the target memory cell decreases to thehold current Ihold or lower, the target memory cell may be turned off (operation 3).

[0096] Through operation 1 , operation 2 , and operation 3 describedabove, a current flowing through the target memory cell may be the same as a currentillustrated in the timing diagram of FIG. 9A. That is, in the case where the thirdvoltage bias VB3 is applied to the bit line and the word line of the target memory celland the third current bias CB3 is applied to the target memory cell, a spike current(or a current pulse) having the first peak current Isp1 may be generated by a turn-onand a turn-off of the target memory cell (i.e., the ovonic threshold switch OTS).

[0097] In an embodiment, a threshold voltage of the target memory cell maybe increased by the spike current (or the current pulse) by as much as a given level asillustrated in FIG. 9B. For example, the threshold voltage of the target memory cellmay increase from the first threshold voltage Vth1 to a second threshold voltageVth2 by the spike current (or the current pulse) described with reference to FIG. 9A.In this case, a current-voltage characteristic of the target memory cell is illustrated bya dash-single dotted line of the current-voltage graph of FIG. 9B.

[0098] In this case, the memory device 100 may be in a state where a voltagedifference of the bit line and the word line of the target memory cell is maintained atthe third voltage bias VB3. As in the above description, because the third voltagebias VB3 is higher than the second threshold voltage Vth2, the target memory cellmay be turned on, and thus, a second peak current Isp2 may flow through the targetmemory cell (4). In an embodiment, the second peak current Isp2 may be greaterthan the first peak current Isp2 described with reference to FIG. 9A. However, thepresent disclosure is not limited thereto. For example, peak values of a plurality ofspike currents may be the same or different depending on a physical characteristic ofa memory cell.

[0099] Afterwards, as in the above description, a current flowing through thetarget memory cell may slowly decrease to the third current bias CB3 (operation 5;when the current flowing through the target memory cell is lower than the holdcurrent Ihold, the target memory cell may be turned off (operation 6).

[00100] As in the above description, in the case where the third voltage biasVB3 is applied to the bit line and the word line of the target memory cell and thethird current bias CB3 is applied to the target memory cell, the target memory cell (inparticular, the ovonic threshold switch OTS) may be repeatedly turned on and turnedoff by a physical characteristic (e.g., a snapback characteristic of a current-voltage)of the target memory cell. A spike current or a current pulse may be generated by theturn-on and turn-off operation of the target memory cell (in particular, the ovonicthreshold switch OTS) and a threshold voltage of the target memory cell may slowlyincrease by the generated spike current or current pulse.

[00101] In an embodiment, the iteration of the turn-on and turn-off operationof the target memory cell (in particular, the ovonic threshold switch OTS) may bemade until the threshold voltage of the target memory cell increases to a specificvalue (e.g., the third voltage bias VB3 or a reset threshold voltage Vth_RST).

[00102] For example, as illustrated in FIG. 9C, in the case where the thirdvoltage bias VB3 is applied to the bit line and the word line of the target memory celland the third current bias CB3 is applied to the target memory cell, spike currents orcurrent pulses may be generated by iterative turn-on and turn-off operations of thetarget memory cell. The generated spike currents or current pulses may allow thethreshold voltage of the target memory cell to slowly increase and then reach thereset threshold voltage Vth_RST.

[00103] In this case, a current-voltage characteristic of the target memory cellis illustrated by a solid line in the current-voltage graph of FIG. 9C. As illustrated inthe current-voltage graph of FIG. 9C, because the threshold voltage (i.e., Vth_RST)of the target memory cell is higher than the third voltage bias VB3, the targetmemory cell may maintain a turn-off state. Accordingly, a spike current or a currentpulse described above may not be generated.

[00104] As described above, during the reset write operation, the memorydevice 100 according to an embodiment of the present disclosure may apply the resetwrite current Irst to the target memory cell such that a threshold voltage of the targetmemory cell increases. Afterwards, the memory device 100 may apply the thirdvoltage bias VB3 between the bit line and the word line of the target memory celland may apply the third current bias CB3 to the target memory cell. In this case, asthe target memory cell is repeatedly turned on and turned off, a plurality of spikecurrents or a plurality of current pulses may flow through the target memory cell.The threshold voltage of the target memory cell may slowly increase to an intendedthreshold voltage (e.g., Vth_RST) through the plurality of spike currents or theplurality of current pulses. In an embodiment, the target memory cell may berepeatedly turned on and turned off until the threshold voltage of the target memorycell is the intended threshold voltage or higher. The number of times of a turn-on andturn-off operation of the target memory cell or the number of spike currents may bevariable depending on a physical characteristic, a current state, or a current thresholdvoltage of the target memory cell.

[00105] FIG. 10 is a flowchart illustrating an operation of a memory device ofFIG. 1. Referring to FIGS. 1 and 10, the memory device 100 may perform operationS201, operation 210, operation S220, and operation S230. Operation S201, operationS210, operation S220, and operation S230 are similar to operation S101, operationS110, operation S120, and operation S130 of FIG. 5, and thus, additional descriptionwill be omitted to avoid redundancy.

[00106] After operation S230, in operation S240, the memory device 100 maycontrol a bit line BL and a word line WL corresponding to a target memory cell suchthat a threshold voltage of the target memory cell is stabilized. For example, thememory device 100 may apply a fourth voltage bias VB4 between the bit line BLand the word line WL connected with the target memory cell and may apply a fourthcurrent bias CB4 to the bit line BL connected with the target memory cell. In anembodiment, the fourth voltage bias VB4 may be lower than a lower limit value of athreshold voltage distribution of memory cells in the set state SET. An electric fieldmay be applied to a target memory cell having the reset state RST through operationS240, and thus, a threshold voltage change of the target memory cell having the resetstate RST may be stabilized.

[00107] As described above, immediately after the reset write operation iscompletely performed on the target memory cell, the fourth voltage bias VB4 may beapplied to the bit line BL and the word line WL of the target memory cell. In thiscase, a threshold voltage change of the target memory cell may be stabilized throughthe electric field formed by the fourth voltage bias VB4.

[00108] FIG. 11 is a timing diagram illustrating voltage biases according to anoperation of the flowchart of FIG. 10. In the timing diagram of FIG. 11, a horizontalaxis represents time and a vertical axis represents a voltage. For brevity of drawing,in the timing diagram, a dash-single dotted line indicates the selection word linevoltage VWL_sel and a solid line indicates the selection bit line voltage VBL_sel.

[00109] Referring to FIGS. 1, 10, and 11, the memory device 100 mayperform the reset write operation by controlling a bit line and a word line of a targetmemory cell as illustrated in FIG. 11. For example, the memory device 100 maycontrol the selection bit line voltage VBL_sel and the selection word line voltageVWL_sel through the first to third periods PR1 to PR3. The first to third periods PR1to PR3 are the same as those described with reference to FIG. 8A, and thus,additional description will be omitted to avoid redundancy.

[00110] After the third period PR3, during a fourth period PR4 (i.e., from t3 tot4), the memory device 100 may decrease the selection bit line voltage VBL_sel suchthat a difference between the selection bit line voltage VBL_sel and the selectionword line voltage VWL_sel is the fourth voltage bias VB4. That is, as the fourthvoltage bias VB4 is applied to the bit line and the word line of the target memory cellduring the fourth period PR4, a threshold voltage change of the target memory cellmay be stabilized.

[00111] In an embodiment, the fourth voltage bias VB4 applied in the fourthperiod PR4 may be a voltage level lower than the first threshold voltage Vth1 (referto FIG. 4B) indicating a threshold voltage of each memory cell in the set state SET.In an embodiment, the fourth voltage bias VB4 applied in the fourth period PR4 maybe controlled in a multi-step manner. That is, the fourth voltage bias VB4 may becontrolled to increase or decrease stepwise or gradually during the fourth period PR4.A maximum value of the fourth voltage bias VB4 controlled in the multi-step mannermay be a voltage level lower than the first threshold voltage Vth1 (refer to FIG. 4B)indicating a threshold voltage of each memory cell in the set state SET.

[00112] In an embodiment, how the selection bit line voltage VBL_sel and theselection word line voltage VWL_sel are controlled is described with reference toFIG. 11, but the present disclosure is not limited thereto. For example, the memorydevice 100 may control a voltage applied to a bit line and a word line of a targetmemory cell based on the method described with reference to FIGS. 8A to 8D orbased on various other methods. In this case, voltage differences between a bit lineand a word line in respective periods may be controlled to correspond to the first tofourth voltage biases VB1 to VB4, respectively.

[00113] FIG. 12 is a circuit diagram illustrating a current bias circuit of FIG.1. FIG. 13 is a timing diagram for describing an operation of a current bias circuit ofFIG. 12. In the timing diagram of FIG. 13, a horizontal axis represents time and avertical axis represents a current flowing through a target memory cell. Forconvenience of description, one spike current (or one current pulse) is illustrated inFIG. 13. Referring to FIGS. 1, 12, and 13, the current bias circuit 150 may include aplurality of switches SW1 to SWn and a plurality of capacitors C1 to Cn. Theplurality of switches SW1 to SWn may respectively correspond to the plurality ofcapacitors C1 to Cn to form a plurality of switch and capacitor pairs. Thecorresponding switch and the corresponding capacitor (or a switch and a capacitor ofeach of the plurality of switch and capacitor pairs) may be connected in seriesbetween a current bias (CB) node and a specific voltage node.

[00114] Each of the plurality of switches SW1 to SWn may be turned on orturned off under control of the control logic circuit 160. As the number of switchesturned on from among the plurality of switches SW1 to SWn increases, a totalcapacitance value formed by the plurality of capacitors C1 to Cn may increase. Asthe total capacitance value increases, a time during which one spike current or onecurrent pulse is maintained may increase.

[00115] For example, as illustrated in FIG. 13, in the case where "a" switchesof the plurality of switches SW1 to SWn are turned on, one spike current may bemaintained during a first time p1. In other words, one spike current may decreasefrom a peak value to "0" during the first time p1. In the case where "b" switches ("b"being more than "a") of the plurality of switches SW1 to SWn are turned on, onespike current may be maintained during a second time p2 longer than the first timep1. In the case where all the switches SW1 to SWn are turned on, one spike currentmay be maintained during an n-th time pn longer than the second time p2.

[00116] As described above, as a plurality of switches are controlled, a totalcapacitance value of the current bias circuit 150 may be adjusted, and a time duringwhich one spike current is maintained or a time during which one spike currentdecreases from a peak value to "0" may be adjusted by the total capacitance valuethus adjusted.

[00117] FIG. 14 is a block diagram illustrating a memory device according toan embodiment of the present disclosure. Referring to FIG. 14, a memory device 200may include a memory cell array 210, a row decoder (X-DEC) (hereinafter referredto as an "X-decoder") 220, a column decoder (Y-DEC) (hereinafter referred to as a"Y-decoder") 230, a voltage bias circuit 240, a current bias circuit 250, a controllogic circuit 260, and a compensation circuit 270. The memory cell array 210, the Xdecoder220, the Y-decoder 230, the voltage bias circuit 240, the current bias circuit250, and the control logic circuit 260 are described above, and thus, additionaldescription will be omitted to avoid redundancy.

[00118] The memory device 200 of FIG. 14 may further include thecompensation circuit 270. The compensation circuit 270 may perform variouscompensation operations of the memory device 200. For example, the compensationcircuit 270 may be configured to control a voltage bias or a current bias to be appliedto a target memory cell depending on a temperature of the memory device 200. In anembodiment, during a compensation operation, the voltage bias may be controlled bycontrolling the selection word line voltage VWL_sel, the non-selection word linevoltage VWL_unsel, the selection bit line voltage VBL_sel, and the non-selection bitline voltage VBL_unsel. In an embodiment, during the compensation operation, thecurrent bias may be controlled by controlling a total capacitance value of the currentbias circuit 250.

[00119] For example, the compensation circuit 270 may perform acompensation operation on the voltage bias based on a temperature of the memorydevice 200. In the case where a temperature of the memory device 200 increases, aresistance on a path through which a write current flows may increase. In this case,the compensation circuit 270 may control the voltage bias based on positivetemperature coefficient (PTC) temperature compensation. That is, as a temperatureof the memory device 200 increases, temperature compensation may be performedon the voltage bias by increasing a magnitude of the voltage bias (e.g., a voltagedifference of a word line and a bit line). Because a magnitude of a reset write currentof a memory cell changes depending on a temperature, an offset according to atemperature change may be applied to the current bias.

[00120] In an embodiment, temperature information of the memory device200 may be provided in the form of a temperature code or temperature data from aseparate temperature detector and the compensation circuit 270 may be configured todetermine an offset to be applied to the voltage bias and the current bias based on thetemperature data or the temperature code.

[00121] In an embodiment, the compensation circuit 270 may be configured toperform location compensation depending on a location of a memory cell in thememory cell array 210 such that the voltage bias or the current bias is controlled. Forexample, in the case where a physical location of a target memory cell is distant fromthe X-decoder 220 and the Y-decoder 230, even though the same voltage bias and thesame current bias are applied, a magnitude of a current flowing through the targetmemory cell or a magnitude of a voltage or a current affecting the target memory cellmay decrease. That is, in the case where a physical location of a target memory cellis distant from the X-decoder 220 and the Y-decoder 230, the location compensationmay be performed by applying an offset to each of the voltage bias and the currentbias.

[00122] In detail, referring to the memory cell array 110 illustrated in FIG. 2,the memory cell MC31 may be a memory cell the closest to the X-decoder 120 andthe Y-decoder 130 from among illustrated memory cells, and the memory cell MC13may be a memory cell the most distant from the X-decoder 120 and the Y-decoder130 among the illustrated memory cells. A distance of a memory cell from the Xdecoder120 and the Y-decoder 130 (i.e., a distance or a physical location of amemory cell) may correspond to a sum of a length of a word line between thememory cell and the X-decoder 120 and a length of a bit line between the memorycell and the Y-decoder 130. In an embodiment, a distance or a physical location of amemory cell may be determined based on address information.

[00123] As a distance of a target memory cell increases, an offset of thevoltage bias may increase. That is, as a distance of a target memory cell increases,the location compensation may be performed by applying an increased offset to thevoltage bias. In an embodiment, on the basis of a memory cell of the closest distance,a value of an offset to be applied as a distance increases may correspond to a productof a magnitude of a current flowing through a memory cell and a resistance valuechanging depending on a length increase of a word line and a bit line.

[00124] As described above, the memory device 200 according to anembodiment of the present disclosure may be configured to perform variouscompensation operations (e.g., temperature compensation, location combination, or acombination thereof) such that the voltage bias or the current bias is controlled. Assuch, the reliability of the memory device 200 may be improved.

[00125] FIG. 15 is a circuit diagram illustrating a three-dimensional structureof a memory device according to an embodiment of the present disclosure. Referringto FIG. 15, a memory device may be implemented in a three-dimensional stackedstructure. For example, the memory device includes first to fourth memory cell arraylayers MCA1 to MCA4. The first to fourth memory cell array layers MCA1 toMCA4 may include a plurality of memory cells MC1, MC2, MC3, and MC4.

[00126] The first to fourth memory cell array layers MCA1 to MCA4 may bestacked in a third direction D3, and conductive lines CL1 and CL2 extending in afirst direction D1 and a second direction D2 may be alternately formed between thefirst to fourth memory cell array layers MCA1 to MCA4. For example, the firstconductive lines CL1 may extend in the first direction D1 and the second conductivelines CL2 may extend in the second direction D2. The first memory cell array layerMCA1 may be formed above the first conductive lines CL1, and the secondconductive lines CL2 may be formed between the first and second memory cell arraylayers MCA1 and MCA2. The first conductive lines CL1 may be formed between thesecond and third memory cell array layers MCA2 and MCA3, and the secondconductive lines CL2 may be formed between the third and fourth memory cell arraylayers MCA3 and MCA4. The first conductive lines CL1 may be formed above thefourth memory cell array layer MCA4. The first and second conductive lines CL1and CL2 may be electrically connected with memory cells MC adjacent in the thirddirection D3.

[00127] In an embodiment, the first conductive line CL1 may be a bit line or aword line described with reference to FIGS. 1 to 14 and the second conductive lineCL2 may be a word line or a bit line described with reference to FIGS. 1 to 14. Forexample, in the case where the first conductive lines CL1 are word lines and thesecond conductive lines CL2 are bit lines, the first and second memory cell arraylayers MCA1 and MCA2 may share bit lines, the second and third memory cell arraylayers MCA2 and MCA3 may share word lines, and the third and fourth memory cellarray layers MCA3 and MCA4 may share bit lines.

[00128] In an embodiment, a target bit line and a target word line may bedetermined depending on a location of a target memory cell. For example, in the casewhere the first memory cell MC1 of the first memory cell array layer MCA1 is atarget memory cell, conductive lines CL1a and CL2a may be selected as target linesand the selected target lines CL1a and CL2a may be controlled based on the methoddescribed with reference to FIGS. 1 to 14. In the case where the second memory cellMC2 of the second memory cell array layer MCA2 is a target memory cell,conductive lines CL2a and CL1b may be selected as target lines and the selectedtarget lines CL2a and CL1b may be controlled based on the method described withreference to FIGS. 1 to 14. In the case where the third memory cell MC3 of the thirdmemory cell array layer MCA3 is a target memory cell, conductive lines CL1b andCL2b may be selected as target lines and the selected target lines CL1b and CL2bmay be controlled based on the method described with reference to FIGS. 1 to 14.That is, target lines may be determined depending on a location of a target memorycell and each of the selected target lines may be used as a bit line or a word linedepending on a location of the target memory cell. However, the present disclosure isnot limited thereto.

[00129] The memory device of the three-dimensional structure illustrated inFIG. 15 is an example, and the present disclosure is not limited thereto. For example,the number of memory cell array layers, the number of conductive lines, and thenumber of memory cells may increase or decrease depending on a way to implementa memory device.

[00130] FIG. 16 is a block diagram illustrating a memory system including amemory device according to the present disclosure. Referring to FIG. 16, a memorysystem 1000 may include a controller 1100 and a memory device 1200. Thecontroller 1100 may store data "DATA" in the memory device 1200 or may read thedata "DATA" stored in the memory device 1200. For example, the controller 1200may transmit an address ADDR, a command CMD, and the data "DATA" to thememory device 1200 to store the data "DATA" in the memory device 1200 or maytransmit the address ADDR and the command CMD to the memory device 1200 toread the data "DATA" stored in the memory device 1200.

[00131] In an embodiment, the memory device 1200 may be the memorydevice 100 or 200 described with reference to FIGS. 1 to 15 or may operate based onthe operation method described with reference to FIGS. 1 to 15. In an embodiment,the controller 1100 may provide bias information BS to the memory device 1200.The bias information BS may include information associated with various voltagebiases and current biases described with reference to FIGS. 1 to 15. The memorydevice 1200 may be configured to store the data "DATA" based on the biasinformation BS.

[00132] In an embodiment, the memory system 1000 may be implementedwith a memory module or a storage device and may store data under control of anexternal host. In this case, the controller 1100 may communicate with the externalhost through a given host interface. The host interface may comply with at least oneof protocols for various interfaces such as a SATA (Serial ATA) interface, a PCIe(Peripheral Component Interconnect Express) interface, an SAS (Serial AttachedSCSI) interface, an NVMe (Nonvolatile Memory express) interface, and a UFS(Universal Flash Storage) interface.

[00133] In an embodiment, the controller 1100 may communicate with thememory device 1200 through a given memory interface. The given memory interfacemay include a high-speed interface such as a DDR4.0 interface or a DDR-Tinterface.

[00134] FIG. 17 is a block diagram illustrating a user system to which amemory device according to the present disclosure is applied. Referring to FIG. 17, auser system 2000 may include a processor 2001 and a plurality of memories 2110 to2140.

[00135] The processor 2001 may include a memory controller 2002. Thememory controller 2002 may communicate with the plurality of memories 2110 to2140 through a bus 2003. In an embodiment, the bus 2003 may include dedicatedbuses that are respectively connected with the plurality of memories 2110 to 2140 ora common bus shared by the plurality of memories 2110 to 2140.

[00136] In an embodiment, at least a part of the plurality of memories 2110 to2140 may be the memory device 100, 200, or 1200 described with reference to FIGS.1 to 16 or may operate based on the operation method described with reference toFIGS. 1 to 16.

[00137] In an embodiment, at least a part of the plurality of memories 2110 to2140 may include a phase change memory described with reference to FIGS. 1 to 16,and the remaining memories may include a different kind of memory (e.g., a DRAM,a NAND flash memory, or an MRAM).

[00138] According to the present disclosure, a memory device may make atarget memory cell have a reset state by applying at least one current pulse to thetarget memory cell. In this case, the at least one current pulse is a current pulsegenerated by a physical characteristic of a switching element (e.g., an OTS).Accordingly, because an application time of a reset write current decreases, thedegradation of phase change memory cells included in the memory device may bereduced. In addition, because a threshold voltage of a phase change memory cell isfinely adjusted by at least one current pulse, the reliability of the memory device maybe improved.

[00139] As is traditional in the field, embodiments may be described andillustrated in terms of blocks which carry out a described function or functions.These blocks, which may be referred to herein as units or modules or the like, arephysically implemented by analog and / or digital circuits such as logic gates,integrated circuits, microprocessors, microcontrollers, memory circuits, passiveelectronic components, active electronic components, optical components, hardwiredcircuits and the like, and may optionally be driven by firmware and / or software. Thecircuits may, for example, be embodied in one or more semiconductor chips, or onsubstrate supports such as printed circuit boards and the like. The circuitsconstituting a block may be implemented by dedicated hardware, or by a processor(e.g., one or more programmed microprocessors and associated circuitry), or by acombination of dedicated hardware to perform some functions of the block and aprocessor to perform other functions of the block. Each block of the embodimentsmay be physically separated into two or more interacting and discrete blocks withoutdeparting from the scope of the disclosure. Likewise, the blocks of the embodimentsmay be physically combined into more complex blocks without departing from thescope of the disclosure. An aspect of an embodiment may be achieved throughinstructions stored within a non-transitory storage medium and executed by aprocessor.

[00140] While the present disclosure has been described with reference toembodiments thereof, it will be apparent to those of ordinary skill in the art thatvarious changes and modifications may be made thereto without departing from thespirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A memory device comprising: a first phase change memory cell connected between a first bit line and a first word line; an X-decoder configured to provide a selection word line voltage to the first word line during a reset write operation for changing a state of the first phase change memory cell from a set state to a reset state; a Y-decoder configured to provide a selection bit line voltage to the first bit line during the reset write operation; and a voltage bias circuit configured to: generate the selection word line voltage and the selection bit line voltage based on a first voltage bias during a first period of the reset write operation, generate the selection word line voltage and the selection bit line voltage based on a second voltage bias greater than the first voltage bias during a second period of the reset write operation, and generate the selection word line voltage and the selection bit line voltage based on a third voltage bias smaller than the first voltage bias and the second voltage bias during a third period of the reset write operation.

2. The memory device of claim 1, further comprising a current bias circuit configured to: provide a first current bias to the first bit line during the first period of the reset write operation; provide a second current bias to the first bit line during the second period of the reset write operation; and provide a third current bias to the first bit line during the third period of the reset write operation.

3. The memory device of claim 2, wherein: the current bias circuit includes a plurality of switches and a plurality of capacitors, and each of the plurality of switches and each of the plurality of capacitors are connected between an output node, from which the first to third current biases are respectively output in the first to third periods, and a specific voltage.

4. The memory device of claim 3, further comprising a control logic circuit configured to control the plurality of switches.

5. The memory device of claim 2, wherein: the first current bias corresponds to a magnitude of a set write current, the second current bias corresponds to a magnitude of a reset write current, and the third current bias is equal to or smaller than a magnitude of a hold current, which is a minimum current for maintaining a turn-on state of the first phase change memory cell.

6. The memory device of claim 1, wherein the first phase change memory cell includes: an ovonic threshold switch (OTS) connected with the first bit line; and a phase change material (GST) connected between the ovonic threshold switch and the first word line.

7. The memory device of claim 1, wherein the first phase change memory cell includes: an ovonic threshold switch (OTS) connected with the first word line; and a phase change material (GST) connected between the ovonic threshold switch and the first bit line.

8. The memory device of claim 1, wherein the first bit line extends in a first direction and the first word line extends in a second direction perpendicular to the first direction.

9. The memory device of claim 8, further comprising a second phase change memory cell stacked above the first phase change memory cell in a direction perpendicular to a plane defined by the first direction and the second direction and connected with the first bit line and a second word line extending in the second direction.

10. The memory device of claim 1, further comprising a compensation circuit configured to apply an offset, which is determined based on a temperature of the memory device or a physical location of the first phase change memory cell, to each of the first to third voltage biases.

11. An operation method of a memory device which includes a phase change memory cell, the method comprising: applying a first voltage bias to a bit line and a word line, which are connected with the phase change memory cell, during a first period of a reset write operation for writing the phase change memory cell to a reset state; applying a second voltage bias greater than the first voltage bias to the bit line and the word line connected with the phase change memory cell during a second period of the reset write operation after the first period; and applying a third voltage bias equal to or smaller than the first voltage bias to the bit line and the word line connected with the phase change memory cell during a third period of the reset write operation after the second period.

12. The method of claim 11, further comprising: applying a first current bias to the bit line during the first period; applying a second current bias greater than the first current bias to the bit line during the second period; and applying a third current bias smaller than the first current bias to the bit line during the third period.

13. The method of claim 12, wherein: the first current bias corresponds to a magnitude of a set write current of the phase change memory cell, the second current bias corresponds to a magnitude of a reset write current of the phase change memory cell, and the third current bias is equal to or smaller than a magnitude of a hold current being a minimum current for maintaining a turn-on state of the phase change memory cell.

14. The method of claim 12, wherein: the third voltage bias indicates a voltage difference of the bit line and the word line, and the third voltage bias is uniformly maintained during the third period.

15. The method of claim 14, wherein at least one current pulse flowing through the phase change memory cell is generated during the third period.

16. The method of claim 12, wherein: the phase change memory cell includes an ovonic threshold switch and a phase change material, which are connected between the bit line and the word line, and the ovonic threshold switch is repeatedly turned on and turned off until a threshold voltage of the phase change memory cell is greater than the third voltage bias.

17. The method of claim 11, wherein a length of the first period is shorter than a length of the second period, and a length of the third period is shorter than the length of the first period.

18. The method of claim 11, further comprising applying a fourth voltage bias smaller than the third voltage bias to the bit line and the word line during a fourth period of the reset write operation after the third period.

19. The method of claim 11, further comprising applying the third voltage bias to the bit line and the word line of the phase change memory cell to read data written in the phase change memory cell.

20. An operation method of a memory device which includes a phase change memory cell, the method comprising: turning on the phase change memory cell; applying a reset write current to the phase change memory cell; and applying at least one current pulse to the phase change memory cell, wherein while the at least one current pulse is applied to the phase change memory cell, a voltage of a bit line connected with the phase change memory cell and a voltage of a word line connected with the phase change memory cell are uniformly maintained.