Electronic device

Abstract

To provide a novel electronic device.SOLUTION: The electronic device has a housing and a display device. The display device has a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer has a driving circuit and a calculation circuit. The second layer has a pixel circuit and a cell array. The third layer has a light-receiving device and a light-emitting device. The pixel circuit has a function of controlling the light emission from the light-emitting device. The driving circuit has a function of controlling the pixel circuit. The calculation circuit has a function of performing calculation processing based on first data according to the current output from the light-receiving device and second data according to the potential held by the cell array.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an electronic device. Another aspect of the present invention relates to a wearable electronic device equipped with a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. [Background technology]

[0003] In recent years, HMD (Head-Mounted Display) type electronic devices suitable for applications such as virtual reality (VR) and augmented reality (AR) have become widespread. Because HMDs can display images in a 360-degree field of view around the observer in response to the user's head movements, gaze, or actions, users can experience a high level of immersion and realism.

[0004] The display device provided in the HMD is configured to be viewed by magnifying it through optical elements. In this case, there is a risk of the housing becoming larger due to the inclusion of optical elements, or a risk that the user will perceive pixels as easily visible and feel a strong sense of graininess. Therefore, the display device is required to be high resolution and / or miniaturized. For example, Patent Document 1 discloses an HMD having fine pixels by using transistors capable of high-speed driving. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2000-2856 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In HMD-type electronic devices, it is desirable to incorporate sensing functions in addition to display functions to provide a more advanced user experience. However, when multiple sensors such as image sensors or temperature sensors are mounted on the housing, the number of components increases, which can lead to the HMD-type electronic device becoming bulky and significantly impairing wearability.

[0007] One aspect of the present invention aims to provide an electronic device that is miniaturized and lightweight. Alternatively, one aspect of the present invention aims to provide an electronic device that is easy to wear. Alternatively, one aspect of the present invention aims to provide a novel electronic device.

[0008] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One aspect of the present invention is an electronic device comprising a housing and a display device, the display device having a first layer, a second layer and a third layer, the first layer, the second layer and the third layer being provided on different layers, the first layer having a drive circuit and an arithmetic circuit, the second layer having a pixel circuit and a cell array, the third layer having a light-receiving device and a light-emitting device, the pixel circuit having a function to control the light emission of the light-emitting device, the drive circuit having a function to control the pixel circuit, and the arithmetic circuit having a function to perform arithmetic processing based on first data corresponding to the current output by the light-receiving device and second data corresponding to the potential held in the cell array.

[0010] In one embodiment of the present invention, an electronic device is preferred in which the first layer has a first transistor having a semiconductor layer with silicon in the channel formation region, and the second layer has a second transistor having a semiconductor layer with a metal oxide in the channel formation region.

[0011] In one embodiment of the present invention, an electronic device having a metal oxide of In, element M (where M is Al, Ga, Y, or Sn), and Zn is preferred.

[0012] In one embodiment of the present invention, an electronic device is preferred in which the light-receiving device has an organic light-emitting diode and the light-emitting device is an organic EL device.

[0013] In one embodiment of the present invention, an electronic device is preferred in which the separation of the light-emitting device and the light-receiving device is performed by photolithography.

[0014] In one embodiment of the present invention, the housing is preferably an electronic device having the function of positioning the display device in a location that can capture images of the user's eyes, and the light-receiving device has the function of capturing images of the user's eyes and / or the area around the eyes.

[0015] In one embodiment of the present invention, an electronic device is preferred in which the light-emitting device is provided on the display section of the display device, and the light-receiving devices are arranged at both ends of the display section.

[0016] In one embodiment of the present invention, the housing is preferably an electronic device that includes a mounting portion and a pair of lenses.

[0017] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings. [Effects of the Invention]

[0018] One aspect of the present invention can provide an electronic device that is miniaturized and lightweight. Alternatively, one aspect of the present invention can provide an electronic device that is easy to wear. Alternatively, one aspect of the present invention can provide a novel electronic device.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0020] [Figure 1] Figures 1(A) to 1(C) illustrate examples of the configuration of a display device and an electronic device. [Figure 2] Figures 2(A) through (E) illustrate examples of the configuration of a display device. [Figure 3] Figures 3(A) and 3(B) illustrate examples of the configuration of a display device. [Figure 4] Figures 4(A) and 4(B) illustrate examples of the configuration of a display device. [Figure 5] Figures 5(A) and (B) illustrate examples of the configuration of a display device. [Figure 6] Figures 6(A) and 6(B) illustrate examples of the configuration of an electronic device. [Figure 7] Figures 7(A) and 7(B) illustrate examples of the configuration of a display device. [Figure 8] Figures 8(A) and 8(B) illustrate examples of neural network configurations. [Figure 9] Figure 9 illustrates an example of a display device configuration. [Figure 10] Figure 10 illustrates an example of a display device configuration. [Figure 11] Figure 11 illustrates an example of a display device configuration. [Figure 12] Figure 12 illustrates an example of a display device configuration. [Figure 13] Figures 13(A) and (B) illustrate examples of the configuration of a display device. [Figure 14] Figures 14(A) to (D) illustrate examples of the configuration of a display device. [Figure 15] Figures 15(A) to (D) illustrate examples of the configuration of a display device. [Figure 16] Figures 16(A) and (B) illustrate examples of the configuration of a display device. [Figure 17] Figures 17(A) to (D) illustrate examples of the configuration of a display device. [Figure 18] Figures 18(A) to (D) illustrate examples of the configuration of a display device. [Figure 19] Figures 19(A) and (B) illustrate examples of the configuration of a display device. [Figure 20] Figures 20(A) to (G) illustrate examples of the configuration of a display device. [Figure 21] Figure 21 illustrates an example of a display device configuration. [Modes for carrying out the invention]

[0021] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different forms, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0022] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0023] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state in an n-channel transistor is defined as the voltage V between the gate and source. gs The threshold voltage V th Lower than (in p-channel transistors, V thThis refers to a state that is higher than [a certain value].

[0024] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having an oxide or oxide semiconductor.

[0025] (Embodiment 1) One aspect of the present invention describes an electronic device according to one aspect of the present invention. The electronic device according to one aspect of the present invention can also be suitably used as a wearable electronic device for VR and AR applications.

[0026] <Example of electronic device configuration> Figure 1(A) is a perspective view of a goggle-type electronic device 100, which is an example of a wearable electronic device. The electronic device 100 shown in Figure 1(A) illustrates how a pair of display devices 10_L and 10_R are housed within a housing 101. Figure 1(A) also illustrates the user's eyes 102 (eyeballs) when the electronic device 100 is worn. As shown in Figure 1(A), the pair of display devices 10_L and 10_R are positioned to overlap with the eyes 102, for example. The housing 101 is equipped with an acceleration sensor such as a gyro sensor, which can detect the orientation of the user's head and display an image corresponding to that orientation.

[0027] In this specification, for example, when describing matters common to display devices 10_L and 10_R, or when there is no need to distinguish between them, the term "display device 10" may be used.

[0028] Figure 1(B) is a schematic perspective view of a display device 10 applicable to the display devices 10_L and 10_R shown in Figure 1(A).

[0029] The display device 10 has a substrate 11 and a substrate 12. The display device 10 has a display unit 13 and a light receiving unit 14 provided between the substrate 11 and the substrate 12.

[0030] The display unit 13 is the area in the display device 10 that displays images. The display unit 13 is provided with pixels, which consist of a pixel circuit and light-emitting elements connected to the pixel circuit. The display unit 13 is also provided with light-emitting elements 61 whose light intensity is controlled by the pixel circuit.

[0031] The light-receiving unit 14 is an area that captures images of the area around the display device 10. The signals generated by the light-receiving unit 14 can be processed in an area where an arithmetic processing unit, consisting of an arithmetic circuit and a cell array, is provided. The light-receiving unit 14 is equipped with a light-receiving element 62 that outputs a current (photocurrent) corresponding to the intensity of light. The light-receiving element 62 is an element that converts light energy into electrical energy, and is sometimes called a photoelectric conversion element.

[0032] In this specification, the term "element" may sometimes be replaced with "device." For example, display elements, light-emitting elements, and liquid crystal elements may be replaced with, for example, display devices, light-emitting devices, and liquid crystal devices.

[0033] The display device 10 receives various signals and power potentials from the outside via the terminal section 15, and can display information on the display section 13 and capture images on the light receiving section 14. Multiple layers are provided between the substrate 11 and the substrate 12, and each layer is provided with a transistor for performing circuit operation, a photodetector 62 that outputs a signal according to the received light, or a light-emitting element 61 that emits light. In the layer where the transistor is provided, there is a pixel circuit that has the function of controlling the light emission of the light-emitting element 61, a drive circuit that has the function of controlling the pixel circuit, an arithmetic circuit that has the function of processing the signals generated by the photodetector 62, and a cell array in which transistors are provided for performing calculations in the arithmetic circuit.

[0034] Figure 1(C) is a schematic diagram illustrating how a display device 10, which includes a display unit 13 and a light-receiving unit 14, is positioned close to the user's eyes 102. In Figure 1(C), the arrangement of the display unit 13 and the light-receiving unit 14 is such that the display unit 13 is positioned between the light-receiving units 14.

[0035] The user's eye 102 can see the image through the light 13A from the light-emitting element 61 in the display unit 13. The light 13A may include not only visible light but also infrared light and other types of light.

[0036] Furthermore, the reflected light 14A from the user's eye 102 and / or its surroundings is converted into an electrical signal by the light-receiving element 62 in the light-receiving unit 14. The information acquired by the light-receiving unit 14 may be an image of the eyeball (or the state of the pupil) for gaze detection, or an image of the movement around the eyeball (for example, the eyelids, glabella, inner corner of the eye, outer corner of the eye, etc.).

[0037] <Example of display and light receiving unit arrangement> Figures 2(A) to 2(E) are schematic diagrams illustrating examples of the arrangement of the display unit 13 and the light receiving unit 14 shown in Figures 1(B) and 1(C).

[0038] In the example shown in Figure 2(A), a configuration is illustrated in which the area of ​​the display unit 13 and the area of ​​the light-receiving unit 14 are located in separate positions. In Figure 2(A), the light-receiving unit 14 is arranged in a line at both ends of the display unit 13. If the image captures an up-and-down movement of the eyelids, such as blinking, it can be detected by the line-shaped light-receiving unit 14. By detecting the blinking motion of the eyelids in this way, the calculation circuit connected to the light-receiving unit 14 can perform inference operations according to the presence or absence of blinking. Note that the light-receiving unit 14, which can be arranged in a line, may also be configured to be provided in multiples between the display units 13, as shown in Figure 2(B).

[0039] Furthermore, the example shown in Figure 2(C) illustrates a configuration in which the light-receiving unit 14 is arranged around the display unit 13. In Figure 2(C), the light-receiving unit 14 is arranged in a ring shape. In this ring-shaped configuration of the light-receiving unit 14, it is possible to detect movements around the eyeball, such as the eyelids, glabella, inner corner of the eye, and outer corner of the eye. Therefore, the arithmetic circuit connected to the light-receiving unit 14 can perform gaze direction inference without imaging the movement of the eyeball. It is preferable that the ring-shaped light-receiving unit 14 be arranged around the display unit 13, which is larger than the size of the eye 102, as shown in Figure 2(D). In this case, the panel size L of the display device 10 D By setting the diagonal size to 0.1 inches to 5 inches, preferably 0.5 inches to 3 inches, more preferably 1 inch to 2 inches, more preferably 1.3 inches to 1.7 inches, and even more preferably 1.5 inches to 1.6 inches, a configuration can be made in which a display unit 13 and a light-receiving unit 14 corresponding to the size of the eye 102 can be provided. With this configuration, when the display device 10 is brought close to the user's eye 102, information about the user's eye 102 and its surroundings can be acquired by the light-receiving unit 14, and the field of view of the image displayed on the display unit 13 can be enlarged.

[0040] In Figures 2(A) to 2(D), the display area 13 and the light-receiving area 14 are located in separate locations. In other words, the light-emitting element 61 and the light-receiving element 62 are arranged in separate locations. This configuration allows for different layout densities for the light-emitting element 61 and the light-receiving element 62.

[0041] Furthermore, the light-emitting element 61 in the display unit 13 may be configured to correspond to the light-receiving element 62 in the light-receiving unit 14. For example, as shown in Figure 2(E), the area of ​​the display unit 13 and the area of ​​the light-receiving unit 14 may be in the same position. In the case of Figure 2(E), for example, one pixel can be provided with light-emitting elements 61R, 61G, and 61B corresponding to each of the RGB colors, and a light-receiving element 62. By adopting this configuration, the area of ​​the display unit 13 and the light-receiving unit 14 can be increased. The density of the light-emitting elements 61 and the light-receiving elements 62 can be made uniform.

[0042] <Example of display device configuration> The configuration of the display device 10 applicable to the display devices 10_L and 10_R shown in Figures 1(A) and 1(B) will be explained with reference to Figures 3(A), (B) to 5.

[0043] Figure 3(A) is a schematic perspective view showing the configuration of each layer provided between substrate 11 and substrate 12 in the display device 10 shown in Figure 1(B).

[0044] A layer 20 is provided on the substrate 11. For example, the layer 20 contains a drive circuit 30 and an arithmetic circuit 40. The layer 20 has a transistor 21 (also called a Si transistor) with silicon in its channel formation region 22. The substrate 11 is, for example, a silicon substrate. A silicon substrate is preferred over a glass substrate because it has higher thermal conductivity.

[0045] Transistor 21 can be, for example, a transistor having single-crystal silicon in its channel formation region. In particular, using a transistor having single-crystal silicon in its channel formation region as the transistor provided in layer 20 allows for a large on-current of the transistor. Therefore, it is preferable because it allows the circuit in layer 20 to be driven at high speed. Furthermore, since Si transistors can be formed with microfabrication such as a channel length of 3 nm to 10 nm, it is possible to provide dedicated arithmetic circuits 40 such as artificial neural networks (hereinafter sometimes referred to as neural networks) and / or driving circuits 30, as well as accelerators such as CPUs and GPUs, application processors, etc.

[0046] The drive circuit 30 includes, for example, a gate driver circuit and a source driver circuit. The gate driver circuit and source driver circuit can be arranged on top of the display unit 13 and / or the light receiving unit 14. Therefore, compared to the case where the drive circuit 30 and the display unit 13 are arranged side by side, the width of the non-display area (also called a frame) on the outer periphery of the display unit 13 of the display device 10 can be made extremely narrow, enabling the realization of a compact display device 10. Furthermore, when arranged on the outer periphery of the display unit 13 of the display device 10, the gate driver circuit and source driver circuit are arranged in a concentrated manner on the outer periphery, but the drive circuit 30 can be divided into multiple parts and arranged in the area overlapping with the display unit 13.

[0047] The arithmetic circuit 40 is a circuit that has the function of performing multiply-accumulate operations in an artificial neural network. For example, it is a circuit that has the function of performing inference processing based on hierarchical neural networks such as deep neural networks (DNNs) and convolutional neural networks (CNNs), and the detailed configuration will be described in detail in Embodiment 2. Since the arithmetic circuit 40 can perform multiply-accumulate operations using minute currents corresponding to the analog voltage in the cell array CA described later, it can perform arithmetic processing using minute currents flowing through the photodetector 62 as input data. Therefore, it is effective in reducing the circuit area, lowering power consumption, and improving computation efficiency.

[0048] A layer 50 is provided on layer 20. Layer 50 is provided with a pixel circuit section 51P having multiple pixel circuits 51 and a cell array CA having multiple cells IM. Layer 50 has a transistor 52 (also called an OS transistor) having a metal oxide (also called an oxide semiconductor) in the channel formation region 54. Layer 50 can be configured to be stacked on layer 20. It is also possible to form layer 50 on a separate substrate and then bond it together.

[0049] It is preferable to use an OS transistor (OS transistor) as transistor 52, which has an oxide containing at least one of indium, element M (where element M is aluminum, gallium, yttrium, or tin), and zinc in its channel formation region. Such an OS transistor has the characteristic of having a very low off-current. Therefore, it is preferable to use an OS transistor as the transistor provided in the pixel circuit 51 and cell IM in particular, because it can retain the analog data written to the pixel circuit 51 and cell IM for a long period of time.

[0050] A layer 60 is provided on layer 50. A substrate 12 is provided on layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. Layer 60 has a display section 13 on which a plurality of light-emitting elements 61 are provided, and a light-receiving section 14 on which a plurality of light-receiving elements 62 are provided. Layer 60 can be configured to be stacked on layer 50. As the light-emitting elements 61, for example, organic electroluminescent elements (also called organic EL elements) can be used. However, the light-emitting elements 61 are not limited to this, and for example, inorganic EL elements made of inorganic materials may be used. Note that "organic EL elements" and "inorganic EL elements" are sometimes collectively referred to as "EL elements". The light-emitting elements 61 may have inorganic compounds such as quantum dots. For example, quantum dots can be used as the light-emitting layer to function as a light-emitting material.

[0051] As shown in Figure 3(A), a display device 10 according to one aspect of the present invention can have a stacked configuration of a light-emitting element 61, a pixel circuit 51, and a drive circuit 30, which allows for an extremely high aperture ratio (effective display area ratio) of pixels. Furthermore, the pixel circuits 51 can be arranged at an extremely high density, allowing for extremely high pixel resolution. Because such a display device 10 is extremely high resolution, it can be suitably used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration where the display part of the display device 10 is viewed through an optical element such as a lens, the display device 10 has an extremely high resolution display part, so even if the display part is magnified with a lens, the pixels are not visible, enabling a highly immersive display.

[0052] Furthermore, as shown in Figure 3(A), the display device 10 according to one aspect of the present invention can have a stacked configuration of a light-receiving element 62, a cell array CA, and an arithmetic circuit 40, enabling highly efficient arithmetic processing using the minute current output by the light-receiving element 62 as input data. In addition, the display device 10 can be configured to have the light-receiving unit 14 positioned close to the display unit 13, allowing the user to view the image with their eyes and simultaneously capture images of the user's eyes and / or surrounding area. Moreover, the cell IM of the cell array CA can hold analog data written in response to minute currents for a long time. Furthermore, the arithmetic circuit 40, which performs multiply-accumulate operations using minute currents, can perform calculations with excellent computational efficiency.

[0053] Figure 3(B) shows block diagrams of the configurations of layers 20, 50, and 60 in Figure 3(A). The drive circuit 30 in layer 20 outputs signals GS and DS (for example, GS is a signal to drive the gate line, and DS is a signal corresponding to the image data) to control the pixel circuit section 51P in layer 50. The pixel circuit section 51P in layer 50 supplies a current I corresponding to the image data to the light-emitting element 61 (not shown) in the display section 13 in layer 60. EL It outputs the following. The light-emitting element 61 (not shown) in the display unit 13 in layer 60 emits current I ELIt emits light according to the situation, enabling the user to visually recognize the image.

[0054] Also, in the block diagram shown in FIG. 3(B), a light-receiving element 62 (not shown) in the light-receiving unit 14 in layer 60 captures an image of the user's eye and / or the area around the eye, and outputs a current I PS flowing through it. The current I PS is output to the cell array CA in layer 50 and the arithmetic circuit 40 in layer 20. The cell array CA in layer 50 outputs a signal D PS corresponding to the sum-of-products operation according to the current I MAC from the light-receiving unit 14 in layer 60 and the control signal of the arithmetic circuit 40 in layer 20 to the arithmetic circuit 40 in layer 20. The arithmetic circuit 40 in layer 20 can perform inference processing based on a neural network.

[0055] Note that the layer 50 provided on layer 20 can have a structure of two or more layers. For example, as shown in FIG. 4(A), it can be layers 50_1 and 50_2 each having a transistor 52 which is an OS transistor. In FIG. 4(A), a pixel circuit portion 51P having a pixel circuit 51 is provided in layer 50_1, and a cell array CA having a cell IM is provided in layer 50_2. With this configuration, the area where the pixel circuit 51 and the cell IM can be provided can be increased.

[0056] In FIG. 4(B), in the same manner as in FIG. 3(B), block diagrams of the respective configurations of layer 20, layer 50_1, layer 50_2, and layer 60 in FIG. 4(A) are shown. As shown in FIG. 4(B), the drive circuit 30 in layer 20 and the pixel circuit portion 51P in layer 50_1 are electrically connected via layer 50_2. It is preferable to have a layer for providing wiring between layer 20 and layer 50_1 and between layer 50_1 and layer 50_2, because it can facilitate the electrical connection of circuits between different layers.

[0057] Furthermore, as shown in Figure 4(B), the light-receiving unit 14 in layer 60 and the cell array in layer 50_2 are electrically connected via layer 50_1. It is preferable to have layers with wiring between layer 60 and layer 50_1, and between layer 50_1 and layer 50_2, as this facilitates the electrical connection of circuits between different layers.

[0058] Furthermore, the arithmetic circuit 40 in layer 20 can perform inference processing based on a neural network, as described above. In Figure 5(A), the output data D is produced by the inference processing based on the neural network NN of the arithmetic circuit 40 in the block diagram shown in Figure 3(B). OUT This is illustrated.

[0059] An example of inference processing in a neural network (NN) will be explained with reference to Figure 5(B). The arithmetic circuit 40, which is capable of computational processing based on the neural network (NN), captures images of the user's eye 102 and its surroundings using the photodetector element 62 of the photodetector 14, and uses the minute current flowing through the photodetector element 62 as input data. The arithmetic circuit 40 and the cell array CA perform multiply-accumulate operations using the input data and weight data held in the cell IM, and execute computational processing based on the neural network. Output data D obtained from the arithmetic circuit 40 OUT For example, factors such as "whether or not the user blinks," "degree of eye opening," and "body temperature" can be inferred from the user's eyes 102 and the surrounding area.

[0060] As described above, one aspect of the present invention can have a configuration in which a light-emitting element, a pixel circuit, and a drive circuit are stacked. The drive circuit, which is a peripheral circuit, can be arranged on top of the pixel circuit, and the width of the bezel can be made extremely narrow, so that a miniaturized and lightweight display device can be made. For this reason, one aspect of the present invention can be an electronic device with excellent mounting properties.

[0061] Furthermore, one aspect of the present invention allows for a lightweight display device by stacking the circuits, thereby shortening the wiring connecting the circuits. Additionally, one aspect of the present invention allows for a display unit with increased pixel resolution. Therefore, an electronic device equipped with this display device can be an electronic device with superior display quality.

[0062] Furthermore, a display device according to one aspect of the present invention can have a configuration in which a light-receiving element, a cell array, and an arithmetic circuit are stacked. Because the distance between the light-receiving element, the cell array, and the arithmetic circuit can be brought close, the minute current output by the light-receiving element can be used as input data. The arithmetic circuit and the cell array can perform arithmetic processing with excellent computational efficiency. In addition, in an electronic device equipped with a display device according to one aspect of the present invention, the light-receiving element can be positioned close to the display unit, so that the user can view the image with their eyes and also capture images of the user's eyes and / or surrounding area. Furthermore, the cell array in the display device can hold analog data written in response to minute currents for a long time. The arithmetic circuit that performs multiply-accumulate operations using minute currents can perform calculations with excellent computational efficiency.

[0063] <Other configuration examples of electronic devices> Figure 6(A) is a perspective view showing the rear, bottom, and right side of the electronic device 100 described in Figure 1(A).

[0064] In Figure 6(A), the housing 101 of the electronic device 100 includes, for example, a mounting section 106, a buffer member 107, a pair of lenses 108, and a pair of displays 10_L and 10_R. The display sections 13 of the pair of displays 10_L and 10_R are positioned so that they can be seen through the lenses 108 inside the housing 101.

[0065] Furthermore, the light-receiving units 14 in the pair of display devices 10_L and 10_R are positioned to acquire information about the user's eye 102 and its surroundings. The acquisition of information about the user's eye 102 and its surroundings by the light-receiving unit 14 may be performed via a lens 108 inside the housing 101, or it may be performed without using the lens 108.

[0066] Furthermore, the housing 101 shown in Figure 6(A) is provided with an input terminal 109 and an output terminal 110. The input terminal 109 can be connected to a cable that supplies image signals (image data) from a video output device or other device, or power to charge a battery provided inside the housing 101. The output terminal 110 functions, for example, as an audio output terminal, and earphones, headphones, etc., can be connected to it.

[0067] Furthermore, it is preferable that the housing 101 has a mechanism that allows adjustment of the left and right positions of the lens 108 and the display devices 10_L and 10_R so that they are in the optimal position according to the user's eye position. It is also preferable that the housing 101 has a mechanism that adjusts the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0068] The cushioning member 107 is the part that comes into contact with the user's face (forehead, cheeks, etc.). By ensuring that the cushioning member 107 is in close contact with the user's face, light leakage can be prevented, thereby enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it comes into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels good against the skin and prevents the user from feeling cold when wearing it in cold seasons. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the attachment part 106, removable so that they can be easily cleaned or replaced.

[0069] An electronic device according to one aspect of the present invention may further include an earphone 106A. The earphone 106A has a communication unit (not shown) and has wireless communication functionality. The earphone 106A can output audio data through its wireless communication functionality. The earphone 106A may also have a vibration mechanism that functions as a bone conduction earphone.

[0070] Furthermore, the earphone 106A can be configured to be directly connected to the mounting part 106 or connected via a wire, as shown in Figure 6(B) with earphone 106B. The earphone 106B and the mounting part 106 may also have magnets. This allows the earphone 106B to be fixed to the mounting part 106 by magnetic force, making storage easier and preferable.

[0071] Figure 7(A) is a perspective view of a spectacle-type electronic device 100A, which is shown as another example of a wearable electronic device. The electronic device 100A shown in Figure 7(A) illustrates how a pair of display devices 10_L and 10_R are housed in a housing 101.

[0072] The electronic device 100A can project images displayed by the display units 13 of the display devices 10_L and 10_R onto the display area 104 of the optical element 103. Furthermore, because the optical element 103 is translucent, the user can view the image displayed in the display area 104 superimposed on the transmitted image seen through the optical element 103. Therefore, the electronic device 100A is an electronic device capable of AR display.

[0073] The housing 101 also includes a connector to which a wireless receiver or cable can be connected (not shown), allowing video signals and other signals to be supplied to the housing 101. Furthermore, by equipping the housing 101 with an acceleration sensor such as a gyro sensor, the orientation of the user's head can be detected, and an image corresponding to that orientation can be displayed in the display area 104.

[0074] Next, using Figure 7(B), the method for projecting an image onto the display area 104 of the electronic device 100A will be explained. Inside the housing 101, a display device 10, a lens 111, and a reflector 112 are provided. In addition, the portion of the optical element 103 corresponding to the display area 104 has a reflective surface 113 that functions as a half-mirror.

[0075] Light 115 emitted from the display device 10 passes through the lens 111 and is reflected towards the optical element 103 by the reflector 112. Inside the optical element 103, the light 115 undergoes total internal reflection repeatedly at the end face of the optical element 103 and reaches the reflective surface 113, thereby projecting an image onto the reflective surface 113. As a result, the user can see both the light 115 reflected by the reflective surface 113 and the transmitted light 116 that has passed through the optical element 103 (including the reflective surface 113).

[0076] Figure 7(B) shows an example where the reflector 112 and the reflective surface 113 each have curved surfaces. This increases the degree of freedom in optical design and allows for a thinner optical component 103 compared to when they are flat. However, the reflector 112 and the reflective surface 113 may also be flat.

[0077] As the reflector 112, a material having a mirror surface can be used, and it is preferable that it has a high reflectivity. Also, as the reflective surface 113, a half-mirror that utilizes the reflection of a metal film may be used, but using a prism that utilizes total internal reflection can increase the transmittance of transmitted light 116.

[0078] Here, it is preferable that the housing 101 has a mechanism for adjusting the distance between the lens 111 and the display device 10, or the angle between them. This makes it possible to adjust the focus, enlarge or reduce the image, etc. For example, one or both of the lens 111 or the display device 10 may be configured to move in the optical axis direction.

[0079] Furthermore, it is preferable that the housing 101 has a mechanism that allows the angle of the reflector 112 to be adjusted. By changing the angle of the reflector 112, the position of the display area 104 on which the image is displayed can be changed. This makes it possible to position the display area 104 in an optimal position according to the user's eye position.

[0080] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0081] (Embodiment 2) An arithmetic circuit in a display device according to one aspect of the present invention will be described. The arithmetic circuit can be used for the computational processing of an artificial neural network. As an example of the artificial neural network, a hierarchical neural network can be applied.

[0082] <Hierarchical Neural Network> A hierarchical neural network, for example, has one input layer, one or more hidden layers, and one output layer, and is composed of a total of three or more layers. The hierarchical neural network ANN shown in Figure 8(A) is an example of such a network, and the neural network ANN has layers 1 through R (where R can be an integer of 4 or greater). In particular, layer 1 corresponds to the input layer, layer R corresponds to the output layer, and the other layers correspond to hidden layers. Note that in Figure 8(A), layers (k-1) and k (where k is an integer between 3 and R-1) are shown as hidden layers, and the other hidden layers are not shown.

[0083] Each layer of a neural network ANN has one or more neurons. In Figure 8(A), the first layer is neuron N1 (1) Neuron N p (1) (Here, p is an integer greater than or equal to 1.) The (k-1)th layer has neuron N1 (k-1) Neuron N m(k-1) (Here, m is an integer greater than or equal to 1.) The k-th layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1.) The R layer has neurons N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1.)

[0084] Note that Figure 8(A) shows neuron N1 (1) , Neuron N p (1) , neuron N1 (k-1) , Neuron N m (k-1) , neuron N1 (k) , Neuron N n (k) , neuron N1 (R) , Neuron N q (R) In addition, the (k-1) layer neurons N i (k-1) (Here, i is an integer between 1 and m, inclusive.) Neuron N of layer k j (k) (Here, j is an integer between 1 and n, inclusive.) is also illustrated, while the other neurons are not shown in the diagram.

[0085] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals that are input and output in each neuron. Note that in this explanation, we will assume that the neurons in layer k are N j (k) Let's focus on that.

[0086] Figure 8(B) shows the neurons N in layer k. j (k) And, neuron N j (k) The signal input to and neuron N j (k) The signal output from and is shown. Also, Figure 8(B) shows the weight data w1 between the (k-1)th layer and the kth layer. (k-1) j(k) , w i (k-1) j (k) , w m (k-1) j (k) , and the activation function f(u j (k) This illustrates the following:

[0087] Specifically, the (k-1) neuron N1 (k-1) Neuron N m (k-1) z1 is the output signal of each of the following: (k-1) ~z m (k-1) However, neuron N j (k) It is outputting towards neuron N. j (k) is z1 (k-1) ~z m (k-1) z j (k) Generate z j (k) This is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0088] <Example of arithmetic circuit configuration 1> Next, an example configuration of the arithmetic circuit 40_1, which can be used in the hierarchical neural network described above, will be explained. The arithmetic circuit 40_1 is applicable to the arithmetic circuit 40 described in the above embodiment.

[0089] The arithmetic circuit 40_1 shown in Figure 9 includes, as an example, an array unit ALP, a circuit ILD, a circuit WLD, a circuit XLD, a circuit AFP, and circuits TW[1] to TW[n].

[0090] Circuit ILD and circuit AFP are electrically connected to wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n] via circuits TW[1] to TW[n].

[0091] Circuits TW[1] through TW[n] function as switching circuits. Each of circuits TW[1] through TW[n] can switch between inputting the output signals of wiring OL[1] through wiring OL[n] and wiring OLB[1] through wiring OLB[n] to circuit AFP, and inputting the output signals of circuit ILD to wiring OL[1] through wiring OL[n] and wiring OLB[1] through wiring OLB[n].

[0092] Circuit WLD is electrically connected to wiring WL[1] to wiring WL[m] and wiring WX1L[1] to wiring WX1L[m]. Circuit XLD is electrically connected to wiring WX1L[1] to wiring WX1L[m].

[0093] The arithmetic circuit 40_1 shown in Figure 9 has circuits MP arranged in an m × n matrix of array units ALP. In Figure 9, the circuit MP located in row i and column j (where i is an integer between 1 and m, and j is an integer between 1 and n) is denoted as circuit MP[i,j]. However, in Figure 9, only circuits MP[1,1], MP[1,m], MP[i,j], MP[n,1], and MP[n,m] are shown, and the other circuits MP are omitted from the illustration.

[0094] Circuit MP[i,j] is electrically connected to wiring WL[i], wiring WX1L[i], wiring OL[j], and wiring OLB[j].

[0095] Circuit MP[i,j] has the function of holding weight coefficients (also called first data). Weight coefficients are sometimes also called weight values. Specifically, circuit MP[i,j] holds information corresponding to the weight coefficients input from wiring OL[j] and wiring OLB[j].

[0096] The circuit ILD has the function of outputting information corresponding to the first data, which is a weighting coefficient, to the wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n].

[0097] For example, information such as electric potential, resistance, and current can be used as the information corresponding to the weighting coefficient. When using current values ​​as the information corresponding to the weighting coefficient, the input current can be generated using a current-output type digital-to-analog converter (IDAC).

[0098] Furthermore, circuit MP[i,j] has the function of outputting the product of the input value (also called the second data) input from wiring WX1L[i] and the weighting coefficient (first data). As a specific example, when circuit MP[i,j] receives the second data from wiring WX1L[i], it outputs a current corresponding to the product of the first data and the second data to wiring OL[j] and wiring OLB[j]. Although Figure 9 shows an example where wiring OL[j] and wiring OLB[j] are arranged, one aspect of the present invention is not limited to this. Only one of wiring OL[j] and wiring OLB[j] may be arranged.

[0099] Circuit XLD has the function of supplying a second data, which is an input value, to wiring WX1L[1] to wiring WX1L[m].

[0100] The information corresponding to the input value can be, for example, electric potential or current value. When using current value as the information corresponding to the input value, the input current can be generated using a current-output type digital-to-analog conversion circuit.

[0101] The currents corresponding to the product of the first data and the second data output from circuit MP[1,j] or circuit MP[m,j] are added together and output to wiring OL[j] and wiring OLB[j]. In this way, the arithmetic circuit can perform a sum-of-products operation on the weight coefficients and input values.

[0102] Furthermore, circuits XLD and WLD have the function of selecting the circuit MP to which information will be written according to the first data input from circuit ILD. For example, when writing information to circuits MP[i,1] to MP[i,n] located in row i of array ALP, circuit XLD supplies a signal to wiring WX1L[i] to turn on or off the writing switching elements included in circuits MP[i,1] to MP[i,n], and supplies a potential to wiring WX1L to turn off the writing switching elements included in circuits MP other than row i. Circuit WLD also supplies a signal to wiring WL[i] to turn on or off the writing switching elements included in circuits MP[i,1] to MP[i,n], and supplies a potential to wiring WL to turn off the writing switching elements included in circuits MP other than row i.

[0103] Circuit AFP has circuits ACTF[1] to ACTF[n]. Circuit ACTF[j] is electrically connected to wiring OL[j] and wiring OLB[j] via circuit TW[j] which has a switching function. Circuit ACTF[j] generates a signal corresponding to information (e.g., potential, current value, etc.) corresponding to the result of the sum-of-accumulate operation input from wiring OL[j] and wiring OLB[j], and z j (k) It can be output as follows. Circuit AFP compares information corresponding to the results of the sum-of-accumulate operation input from wiring OL[j] and wiring OLB[j] (e.g., potential, current value, etc.), generates a signal according to the comparison result, z j (k) It can be output as follows.

[0104] <Circuit MP> Next, circuit MP will be described. An example of a circuit configuration applicable to circuit MP[i,j] is shown in Figure 10. It has transistors M1 to M3 and capacitor C1. For example, the holding part HC is formed by transistor M2 and capacitor C1.

[0105] In circuit MP shown in Figure 10, circuit MCr has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are denoted with the letter "r" to distinguish them from the circuit elements of circuit MC.

[0106] The transistors M1 to M3 shown in Figure 10 are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of transistors M1 to M3 has a first gate and a second gate.

[0107] Furthermore, the arithmetic circuit 40_1 described in this embodiment does not depend on the connection configuration of the transistor's back gate. Transistors M1 to M3 shown in Figure 10 have back gates, and the connection configuration of these back gates is not shown, but the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected in order to increase the on-current of the transistor.

[0108] In circuit MP of Figure 10, the first terminal of transistor M1 is electrically connected to wiring VE. The second terminal of transistor M1 is electrically connected to the first terminal of transistor M3. The gate of transistor M1 is electrically connected to the first terminal of capacitor C1 and the first terminal of transistor M2. The second terminal of capacitor C1 is electrically connected to wiring VE. The second terminal of transistor M2 is electrically connected to wiring OL. The gate of transistor M2 is electrically connected to wiring WL. The second terminal of transistor M3 is electrically connected to wiring OL, and the gate of transistor M3 is electrically connected to wiring WX1L.

[0109] In circuit MCr, the connection configuration differs from that of circuit MC. The second terminal of transistor M3r is electrically connected to wiring OLB, not wiring OL. The first terminal of transistor M1r and the first terminal of capacitor C1r are electrically connected to wiring VEr.

[0110] In the holding section HC shown in Figure 10, node n1 is defined as the electrical connection point between the gate of transistor M1, the first terminal of capacitor C1, and the first terminal of transistor M2.

[0111] The holding unit HC has the function of holding a potential corresponding to the weighting coefficient (first data). Holding this potential in the holding unit HC included in the circuit MC in Figure 10 can be done by turning on transistors M2 and M3, inputting a current of a predetermined value from wiring OL, writing a potential corresponding to that current value to capacitor C1, and then turning off transistor M2. This makes it possible to hold the potential of node n1 as a potential corresponding to the weighting coefficient (first data). Therefore, the influence of variations in the current characteristics (threshold voltage, etc.) of transistor M1 can be reduced when inputting the first data.

[0112] The current input to the wiring OL can be input and generated using a current-output type digital-to-analog conversion circuit.

[0113] Furthermore, since transistor M1 maintains the potential of node n1 for a long time, it is preferable to use a transistor with low off-current. For example, an OS transistor can be used as a transistor with low off-current. Alternatively, a transistor with a back gate may be used as transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side and reduce the off-current.

[0114] This provides a highly accurate arithmetic circuit.

[0115] <Example of arithmetic circuit configuration 2> Next, we will describe another example, an arithmetic circuit 40_2 that performs a sum-of-products operation. The arithmetic circuit 40_2 is applicable to the arithmetic circuit 40 described in the above embodiment.

[0116] Figure 11 shows an example of a configuration of an arithmetic circuit that performs a sum-of-products operation on a first data point (positive or "0") and a second data point (positive or "0"). The arithmetic circuit 40_2 shown in Figure 11 is a circuit that performs a sum-of-products operation on the first data point corresponding to the potential held in each cell and the input second data point, and then performs an activation function calculation using the result of the sum-of-products operation. The first data point and the second data point can be analog data or multi-level data (discrete data), for example.

[0117] This arithmetic circuit also functions as a memory for holding the first data, and can therefore be called a memory. In particular, when analog data is used as the first data, it can be called an analog memory.

[0118] The arithmetic circuit 40_2 includes circuit WCS, circuit XCS, circuit WSD, circuit PTC, circuit SWS1, circuit SWS2, cell array CA, and circuit ITS.

[0119] A circuit PTC has circuits PTR[1] to PTR[m]. Circuits PTR[1] to PTR[m] have the function of making the connection between wiring EIL[1] to wiring EIL[m] and wiring XCL[1] to wiring XCL[m] conductive or non-conductive. In other words, each of circuits PTR[1] to PTR[m] functions as a switching element. Each of circuits PTR[1] to PTR[m] has, for example, a switch SA[1] to switch SA[m].

[0120] The cell array CA comprises cells IM[1,1] to IM[m,n] (where m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1) and cells IMref[1] to IMref[m]. Each of cells IM[1,1] to IM[m,n] has the function of holding a potential corresponding to the amount of current corresponding to the first data, and cells IMref[1] to IMref[m] have the function of supplying a potential corresponding to the second data, which is necessary to perform a sum-of-products operation with the held potential, to the wiring XCL[1] to XCL[m].

[0121] Note that while the cell array CA in Figure 11 has n+1 cells arranged in the row direction and m cells in the column direction in a matrix, the cell array CA may also be configured with 2 or more cells arranged in the row direction and 1 or more cells in the column direction in a matrix.

[0122] Each of cells IM[1,1] through IM[m,n] has, for example, a transistor F1, a transistor F2, and a capacitor C5, and each of cells IMref[1] through IMref[m] has, for example, a transistor F1m, a transistor F2m, and a capacitor C5m.

[0123] In particular, it is preferable that the size of transistor F1 contained in each of cells IM[1,1] to IM[m,n] (e.g., channel length, channel width, transistor configuration, etc.) is equal to that of each cell IM[1,1] to IM[m,n], and that the size of transistor F2 contained in each of cells IM[1,1] to IM[m,n] is equal to that of each cell. Furthermore, it is preferable that the size of transistor F1m contained in each of cells IMref[1] to IMref[m] is equal to that of each cell. Furthermore, it is preferable that the sizes of transistor F1 and transistor F1m are equal to that of each cell. Furthermore, it is preferable that the sizes of transistor F2 and transistor F2m are equal to that of each cell.

[0124] Unless otherwise specified, transistors F1 and F1m are assumed to operate in the linear region when they are ON. That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above are assumed to be appropriately biased to voltages within the range in which they operate in the linear region. However, one aspect of the present invention is not limited thereto. For example, transistors F1 and F1m may operate in the saturation region when they are ON, and they may operate in a mixture of the linear region and the saturation region.

[0125] Furthermore, unless otherwise specified, transistors F2 and F2m are assumed to operate in the subthreshold region (i.e., in transistor F2 or F2m, when the gate-source voltage is lower than the threshold voltage, more preferably when the drain current increases exponentially with respect to the gate-source voltage). In other words, the gate voltage, source voltage, and drain voltage of each of the transistors described above are assumed to be appropriately biased to voltages within the range of operation in the subthreshold region. For this reason, transistors F2 and F2m are assumed to operate such that an off-current flows between the source and drain.

[0126] Furthermore, transistor F1 and / or transistor F1m are preferably OS transistors, for example. In addition, the channel-forming region of transistor F1 and / or transistor F1m is more preferably an oxide containing at least one of indium, element M (element M may be one or more selected from aluminum, gallium, yttrium, or tin, etc.), and zinc.

[0127] By using OS transistors as transistor F1 and / or transistor F1m, the leakage current of transistor F1 and / or transistor F1m can be suppressed, thereby reducing the power consumption of the arithmetic circuit. Specifically, when transistor F1 and / or transistor F1m are in a non-conductive state, the leakage current from the holding node to the write word line can be made very small, which reduces the refresh operation of the holding node's potential and thus reduces the power consumption of the multiply-accumulate circuit. Furthermore, by making the leakage current from the holding node to the write word line very small, the cell can hold the holding node's potential for a long time, which improves the calculation accuracy of the arithmetic circuit.

[0128] Furthermore, by using OS transistors for transistor F2 and / or transistor F2m, they can be operated within a wide current range in the subthreshold region, thereby reducing current consumption. Also, by using OS transistors for transistor F2 and / or transistor F2m, they can be fabricated simultaneously with transistors F1 and F1m, which may shorten the fabrication process for the multiply-accumulate circuit. In addition, transistors F2 and / or transistor F2m can be transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors), other than OS transistors. Examples of silicon that can be used include amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon.

[0129] Incidentally, when arithmetic circuits and other components are highly integrated onto a chip, heat may be generated on the chip due to the operation of the circuit. This heat can cause the temperature of transistors to rise, altering their characteristics and potentially leading to changes in field-effect mobility or a decrease in operating frequency. OS transistors have higher thermal resistance than Si transistors, so their field-effect mobility is less susceptible to changes due to temperature fluctuations, and their operating frequency is also less likely to decrease. Furthermore, OS transistors tend to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage, even at high temperatures. Therefore, using OS transistors makes it easier to perform the multiply-accumulate operations described later, even in high-temperature environments. For this reason, when constructing arithmetic circuits that are resistant to heat generated by operation, it is preferable to use OS transistors.

[0130] In each of cells IM[1,1] through IM[m,n], the first terminal of transistor F1 is electrically connected to the gate of transistor F2. The first terminal of transistor F2 is electrically connected to wiring VE. The first terminal of capacitor C5 is electrically connected to the gate of transistor F2.

[0131] Furthermore, in each of cells IMref[1] through IMref[m], the first terminal of transistor F1m is electrically connected to the gate of transistor F2m. The first terminal of transistor F2m is electrically connected to wiring VE. The first terminal of capacitor C5m is electrically connected to the gate of transistor F2m.

[0132] Furthermore, the arithmetic circuit described in this embodiment does not depend on the polarity of the transistors included in the arithmetic circuit. For example, although transistors F1 and F2 shown in Figure 11 are n-channel type transistors, some or all of the transistors may be replaced with p-channel type transistors.

[0133] The above examples of changes to the structure and polarity of transistors are not limited to transistors F1 and F2. For example, the same applies to transistors F1m, F2m, transistors F3[1] to F3[n], F4[1] to F4[n] described later, and transistors described elsewhere in the specification or illustrated in other drawings.

[0134] Wiring VE is a wiring for conducting current between the first and second terminals of transistor F2 in cells IM[1,1], IM[m,1], IM[1,n], and IM[m,n], and also functions as wiring for conducting current between the first and second terminals of transistor F2 in cells IMref[1] and IMref[m]. For example, wiring VE functions as wiring that supplies a constant voltage. This constant voltage can be, for example, a low-level potential or ground potential.

[0135] In cell IM[1,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In Figure 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,1] is defined as node NN[1,1].

[0136] In cell IM[m,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In Figure 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,1] is defined as node NN[m,1].

[0137] In cell IM[1,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In Figure 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[1,n] is defined as node NN[1,n].

[0138] In cell IM[m,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In Figure 11, the connection point between the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 in cell IM[m,n] is defined as node NN[m,n].

[0139] In cell IMref[1], the second terminal of transistor F1m is electrically connected to wiring XCL[1], and the gate of transistor F1m is electrically connected to wiring WSL[1]. The second terminal of transistor F2m is electrically connected to wiring XCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In Figure 11, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[1] is defined as node NNref[1].

[0140] In cell IMref[m], the second terminal of transistor F1m is electrically connected to wiring XCL[m], and the gate of transistor F1m is electrically connected to wiring WSL[m]. The second terminal of transistor F2m is electrically connected to wiring XCL[m], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In Figure 11, the connection point between the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 in cell IMref[m] is defined as node NNref[m].

[0141] The aforementioned nodes NN[1,1], NN[m,1], NN[1,n], NN[m,n], NNref[1], and NMref[m] function as holding nodes for their respective cells.

[0142] In cells IM[1,1] through IM[m,n], for example, when transistor F1 is ON, transistor F2 is configured as a diode connection. With the constant voltage supplied by wiring VE as the ground potential (GND), when transistor F1 is ON and a current of amount I flows from wiring WCL to the second terminal of transistor F2, the potential of the gate (node ​​NN) of transistor F2 is determined according to the current amount I. Ideally, the potential of the second terminal of transistor F2 is equal to that of the gate (node ​​NN) of transistor F2 because transistor F1 is ON. By turning transistor F1 OFF, the potential of the gate (node ​​NN) of transistor F2 is maintained. As a result, transistor F2 can supply a current of amount I between its source and drain, corresponding to the ground potential of its first terminal and the potential of its gate (node ​​NN). In this specification, such operation is referred to as "transistor F2 is programmed to have the amount of current flowing between its source and drain set to I."

[0143] Circuit SWS1, for example, includes transistors F3[1] to F3[n]. The first terminal of transistor F3[1] is electrically connected to wiring WCL[1], the second terminal of transistor F3[1] is electrically connected to circuit WCS, and the gate of transistor F3[1] is electrically connected to wiring SWL1. The first terminal of transistor F3[n] is electrically connected to wiring WCL[n], the second terminal of transistor F3[n] is electrically connected to circuit WCS, and the gate of transistor F3[n] is electrically connected to wiring SWL1.

[0144] The transistors F3[1] to F3[n] are preferably OS transistors applicable to, for example, transistor F1 and / or transistor F2.

[0145] Circuit SWS1 functions as a circuit that creates a conductive or non-conductive state between circuit WCS and each of the wirings WCL[1] to WCL[n].

[0146] Circuit SWS2 includes, for example, transistors F4[1] to F4[n]. The first terminal of transistor F4[1] is electrically connected to wiring WCL[1], the second terminal of transistor F4[1] is electrically connected to the input terminal of conversion circuit ITRZ[1], and the gate of transistor F4[1] is electrically connected to wiring SWL2. The first terminal of transistor F4[n] is electrically connected to wiring WCL[n], the second terminal of transistor F4[n] is electrically connected to the input terminal of conversion circuit ITRZ[n], and the gate of transistor F4[n] is electrically connected to wiring SWL2.

[0147] The transistors F4[1] to F4[n] are preferably OS transistors applicable to, for example, transistor F1 and / or transistor F2.

[0148] Circuit SWS2 functions as a circuit that makes the connection between wiring WCL[1] and conversion circuit ITRZ[1], and between wiring WCL[n] and conversion circuit ITRZ[n], either conductive or nonconductive.

[0149] The WCS circuit has the function of supplying data to be stored in each cell of the CA cell array.

[0150] Circuit XCS is electrically connected to wiring XCL[1] to wiring XCL[m]. Circuit XCS has the function of supplying current to each of cells IMref[1] to cell IMref[m] of the cell array CA according to the reference data or according to the second data.

[0151] Circuit WSD is electrically connected to wiring WSL[1] to wiring WSL[m]. When writing first data to cells IM[1,1] to cells IM[m,n], circuit WSD has the function of selecting the row of cell array CA to which the first data will be written by supplying a predetermined signal to wiring WSL[1] to wiring WSL[m].

[0152] Furthermore, circuit WSD is electrically connected, for example, to wiring SWL1 and wiring SWL2. Circuit WSD has the function of making circuit WCS and cell array CA conductive or non-conductive by supplying a predetermined signal to wiring SWL1, and the function of making conversion circuits ITRZ[1] to ITRZ[n] and cell array CA conductive or non-conductive by supplying a predetermined signal to wiring SWL2.

[0153] Each of the conversion circuits ITRZ[1] to ITRZ[n] has, for example, an input terminal and an output terminal. For example, the output terminal of conversion circuit ITRZ[1] is electrically connected to wiring OL[1], and the output terminal of conversion circuit ITRZ[n] is electrically connected to wiring OL[n].

[0154] Each of the conversion circuits ITRZ[1] to ITRZ[n] has the function of converting the current input to the input terminal into a voltage corresponding to that current and outputting it from the output terminal. This voltage can be, for example, an analog voltage or a digital voltage. Furthermore, each of the conversion circuits ITRZ[1] to ITRZ[n] may have a function-based arithmetic circuit. In this case, for example, the converted voltage may be used by the arithmetic circuit to perform a function calculation and the result of the calculation may be output to wiring OL[1] to wiring OL[n].

[0155] In particular, when performing calculations on hierarchical neural networks, the functions mentioned above include, for example, the sigmoid function, tanh function, softmax function, ReLU function, and threshold function.

[0156] A current-output type digital-to-analog conversion circuit can be used as the WCS circuit shown in Figure 11. Similarly, a current-output type digital-to-analog conversion circuit can be used as the XCS circuit shown in Figure 11.

[0157] <Three-dimensional structure of sensors and computing circuits> Next, the three-dimensional structure of the arithmetic circuit 40, which is capable of performing calculations using the output of a sensor provided in a part of the display device 10, will be described. The display device 10_SDV shown in Figure 12 has layers PDL, ERL, CCL, and PHL. Layers CCL and PHL are provided with the configurations of the arithmetic circuit 40_2 described above.

[0158] The display device 10_SDV shown in Figure 12 is represented as a three-dimensional structure, and therefore, arrows indicating the x, y, and z directions are included in Figure 12. Here, the x, y, and z directions are shown as mutually orthogonal directions, for example. In this specification, one of the x, y, or z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0159] Layer CCL is located above layer PHL, layer ERL is located above layer CCL, and layer PDL is located above layer ERL. In other words, layers PHL, CCL, ERL, and PDL are stacked sequentially in the z direction.

[0160] Layer PDL has, for example, a sensor array SCA. Sensor array SCA has multiple electrodes and multiple sensors. In Figure 12, as an example, multiple electrodes are shown as electrodes DNK[1] to DNK[m] (where m is an integer of 1 or more), and multiple sensors are shown as sensors SNC[1] to SNC[m]. In addition, in layer PDL, as an example, m electrodes DNK are arranged in a matrix, and sensors SNC[1] to SNC[m] are provided on each electrode DNK[1] to DNK[m].

[0161] In the layer PDL shown in Figure 12, the symbols of electrode DNK[1], electrode DNK[i] (where i is an integer between 1 and m) and electrode DNK[m] are extracted and shown from among electrode DNK[1] to electrode DNK[m]. Also, in the layer PDL shown in Figure 12, the symbols of sensor SNC[1], sensor SNC[i] and sensor SNC[m] are extracted and shown from among sensor SNC[1] to sensor SNC[m].

[0162] Sensor SNC[1] to sensor SNC[m] have the function of converting sensed information into an electric current and outputting that electric current. Furthermore, each of electrodes DNK[1] to electrode DNK[m] functions as a terminal for outputting the electric current in sensor SNC[1] to sensor SNC[m]. For example, a photodetector can be used as the sensor SNC. By using a photodetector as sensor SNC[1] to sensor SNC[m], the layer PDL can be made part of the image sensor. In this case, it is desirable that the range of light intensity that the photodetector can sense includes the intensity of light irradiated in the environment in which the photodetector is used. Figure 12 also shows a display device 10_SDV in which a sensor SNC having a photodiode PD is used as the photodetector. It is preferable to use an organic light-emitting diode that can be provided in the same layer as the light-emitting element as the photodiode PD.

[0163] Furthermore, the circuit configuration of sensor SNC[i] may be such that either the input terminal or output terminal of the photodiode PD included in sensor SNC[i] is electrically connected to wiring EIL[i] via electrode DNK[i]. Additionally, the circuit configuration of sensor SNC[i] may include a switch to temporarily shut off the power supply to sensor SNC[i]. A light-emitting element (not shown) for display purposes may be provided on the same layer as sensor SNC[i].

[0164] Layer ERL has wiring EIL[1] to EIL[m]. Note that in the layer ERL shown in Figure 12, the symbols of wiring EIL[1], wiring EIL[i], and wiring EIL[m] are shown separately from wiring EIL[1] to EIL[m].

[0165] Wiring EIL[1] is electrically connected to electrode DNK[1] of layer PDL. Wiring EIL[i] is also electrically connected to electrode DNK[i] of layer PDL. Wiring EIL[m] is also electrically connected to electrode DNK[m] of layer PDL.

[0166] Specifically, for example, in a top view of the display device 10_SDV (viewpoint in the opposite direction of the z-axis arrow shown in Figure 12), each of the electrodes DNK[1] to DNK[m] is provided with a plug (sometimes called a contact hole, etc.) at the point where it intersects with the wiring EIL[1] to EIL[m], thereby electrically connecting each of the electrodes DNK[1] to DNK[m] with each of the wiring EIL[1] to EIL[m].

[0167] Therefore, the wiring EIL[1] to EIL[m] functions as a path through which a current corresponding to the amount of information output by each of the sensors SNC[1] to SNC[m] flows when information is sensed by each of the sensors SNC[1] to SNC[m].

[0168] Furthermore, it is preferable that the layer PDL be configured such that each of the sensors SNC[1] to SNC[m] performs sensing sequentially and current is sequentially supplied to each of the wiring EIL[1] to EIL[m]. In this case, for example, the layer PDL can be configured to have a signal line for selecting sensors SNC[1] to SNC[m], and signals can be sequentially transmitted to the signal line to operate sensors SNC[1] to SNC[m] sequentially.

[0169] Furthermore, if the sensor SNC[1] to sensor SNC[m] is a light-receiving element composed of a photodiode or the like, the layer PDL of the display device 10_SDV can be configured such that, for example, the output terminal (cathode) of the photodiode is electrically connected to the electrode DNK. Alternatively, as another example of the layer PDL configuration of the display device 10_SDV, the input terminal (anode) of the photodiode may be electrically connected to the electrode DNK.

[0170] Furthermore, if the sensors SNC[1] to SNC[m] are light-receiving elements composed of photodiodes or the like, then, for example, by providing a filter that illuminates only one of the sensors SNC[1] to SNC[m], the sensors SNC[1] to SNC[m] can be operated sequentially. Since there are m sensors, there are m types of filters that illuminate only one sensor SNC. In addition, if a filter is provided that does not illuminate any of the sensors SNC[1] to SNC[m], then there are m+1 types of filters. When light is illuminating the layer PDL, the sensors SNC[1] to SNC[m] can perform sensing sequentially by sequentially switching between such filters.

[0171] Furthermore, if the sensors SNC[1] to SNC[m] are light-receiving elements composed of photodiodes or the like, the display device 10_SDV may be configured to individually illuminate each of the sensors SNC[1] to SNC[m] with light. By illuminating each sensor SNC[1] to SNC[m] sequentially with light, the sensors SNC[1] to SNC[m] can perform sensing sequentially.

[0172] Layer CCL has a cell array CA. Layer PHL, for example, has a circuit PTC, a circuit XCS, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2. As shown in Figure 12, the cell array CA can be configured to be located above the peripheral circuits XCS, WCS, WSD, ITS, SWS1, and SWS2 of the cell array CA.

[0173] A cell array CA has multiple cells. The multiple cells contained in the cell array CA have functions such as holding the first data for performing sum-of-accumulate operations and performing multiplication of the first data and the second data.

[0174] Furthermore, the cell array CA is electrically connected to multiple wires. Specifically, for example, Figure 12 shows a configuration in which the cell array CA is electrically connected to wires WCL[1] to WCL[n] (where n is an integer of 1 or more), wires WSL[1] to WSL[m], and wires XCL[1] to XCL[m]. In particular, wires WCL[1] to WCL[n] are wires that electrically connect circuits SWS1 and SWS2. In other words, circuit SWS1 is electrically connected to circuit SWS2 via the cell array CA through wires WCL[1] to WCL[n]. Note that in Figure 12, wires WSL[1] to WSL[m], wires XCL[1] to XCL[m], and wires WCL[1] to WCL[n] extend in the z direction.

[0175] Furthermore, each of the multiple cells in the cell array CA is electrically connected to one of the wirings WCL[1] through WCL[n], one of the wirings WSL[1] through WSL[m], and one of the wirings XCL[1] through XCL[m]. For this reason, the multiple cells included in the cell array CA are arranged in a matrix of at least m rows and n columns.

[0176] Circuit WCS has the function of supplying an amount of current corresponding to the first data to wiring WCL[1] through WCL[n]. Therefore, circuit WCS is electrically connected to each of wiring WCL[1] through WCL[n] via circuit SWS1.

[0177] Circuit SWS1 has the function of making the circuit WCS and each of the wirings WCL[1] to WCL[n] conductive or non-conductive.

[0178] Circuit WSD is electrically connected to wiring WSL[1] through WSL[m]. When writing first data to a cell in the cell array CA, circuit WSD has the function of selecting the row in the cell array CA to which the first data will be written by supplying a predetermined signal to wiring WSL[1] through WSL[m]. In other words, wiring WSL[1] through WSL[m] functions as a write word line.

[0179] Circuit XCS is electrically connected to wiring XCL[1] to wiring XCL[m]. Circuit XCS has the function of supplying current to wiring XCL[1] to wiring XCL[m] in an amount corresponding to the reference data described later, or an amount corresponding to the second data.

[0180] The circuit PTC has circuits PTR[1] to PTR[m]. The first terminal of circuit PTR[1] is electrically connected to wiring XCL[1], the first terminal of circuit PTR[i] is electrically connected to wiring XCL[i], and the first terminal of circuit PTR[m] is electrically connected to wiring XCL[m].

[0181] Furthermore, the second terminal of circuit PTR[1] is electrically connected to the wiring EIL[1] of layer ERL, the second terminal of circuit PTR[i] is electrically connected to the wiring EIL[i] of layer ERL, and the second terminal of circuit PTR[m] is electrically connected to the wiring EIL[m] of layer ERL.

[0182] Specifically, for example, in a top view of the display device 10_SDV, plugs or the like are provided at the points where the second terminals of circuits PTR[1] to PTR[m] intersect with the wiring EIL[1] to EIL[m], thereby electrically connecting the second terminals of circuits PTR[1] to PTR[m] with the wiring EIL[1] to EIL[m].

[0183] Circuit PTR[1] has the function of making the connection between wiring EIL[1] and wiring XCL[1] conductive or non-conductive. Similarly, circuit PTR[i] has the function of making the connection between wiring EIL[i] and wiring XCL[i] conductive or non-conductive, and circuit PTR[m] has the function of making the connection between wiring EIL[m] and wiring XCL[m] conductive or non-conductive. In other words, each of circuits PTR[1] through PTR[m] functions as a switching element.

[0184] The circuit ITS has the function of acquiring the amount of current flowing through wiring WCL[1] to WCL[n] and outputting the result corresponding to that current amount to wiring OL[1] to OL[n]. For this reason, circuit ITS is electrically connected to each of wiring WCL[1] to WCL[n] via circuit SWS2. In addition, circuit ITS is electrically connected to each of wiring OL[1] to OL[n].

[0185] Circuit SWS2 has the function of making the circuit ITS and each of the wirings WCL[1] to WCL[n] conductive or non-conductive.

[0186] In the layer ERL of Figure 12, it is preferable that the wiring EIL[1] to wiring EIL[m] extends along the x-direction, for example. That is, the direction in which the wiring EIL[1] to wiring EIL[m] extends is preferably approximately parallel to the wiring XCL[1] to wiring XCL[m] in the line of sight in the y-direction, and more preferably parallel. Also, for example, it is preferable that the wiring EIL[1] to wiring EIL[m] is approximately parallel to the wiring XCL[1] to wiring XCL[m] included in layer CCL in the top view, and more preferably parallel.

[0187] As described above, by applying the display device 10_SDV shown in Figure 12, the placement of the sensor array SCA on the display device, which constitutes the arithmetic circuit (layer CCL), can be determined almost freely. For example, the sensor array SCA can be placed in the center or near the center when viewed from above the display device. Furthermore, since the layout of the arithmetic circuit included in layer CCL does not depend on the placement of the sensor array SCA, the degree of freedom in the layout of the arithmetic circuit and its surrounding wiring can be increased.

[0188] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0189] (Embodiment 3) This embodiment describes the three-dimensional structure of the drive circuit, pixel circuit and light-emitting element, an example of the pixel circuit configuration, a schematic top view of the light-emitting element and its schematic cross-sectional view, an example of the configuration of the light-emitting element, an example of the configuration of the light-emitting element and light-receiving element, and an example of the configuration of a cross-sectional view of the display device.

[0190] <Three-dimensional structure of the driving circuit, pixel circuit, and light-emitting element> Figures 13(A) and 13(B) show an example configuration of the pixel circuit 51 and the light-emitting element 61 connected to the pixel circuit 51. Figure 13(A) is a diagram showing the connections of each element, and Figure 13(B) is a diagram schematically showing the hierarchical relationship between the layer 20 containing the drive circuit 30, the layer 50 containing the multiple transistors of the pixel circuit 51, and the layer 60 containing the light-emitting element 61.

[0191] The pixel circuit 51 shown as an example in Figures 13(A) and 13(B) comprises transistors 52A, 52B, 52C, and capacitor 53. Transistors 52A, 52B, and 52C can be composed of OS transistors. Each OS transistor of transistors 52A, 52B, and 52C preferably has a back gate electrode, in which case the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode.

[0192] Transistor 52B comprises a gate electrode electrically connected to transistor 52A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to wiring ANO. Wiring ANO is a wire that provides a potential for supplying current to the light-emitting element 61.

[0193] Transistor 52A has a function to control whether it is conducting or not based on a first electrode electrically connected to the gate electrode of transistor 52B, a second electrode electrically connected to wiring SL which functions as a source line, and wiring GL1 which functions as a gate line.

[0194] Transistor 52C has a function to control the conduction or non-conduction state based on a first electrode electrically connected to wiring V0, a ​​second electrode electrically connected to the light-emitting element 61, and the potential of wiring GL2 which functions as a gate line. Wiring V0 is a wire for providing a reference potential and a wire for outputting the current flowing through the pixel circuit 51 to the drive circuit 30 or the arithmetic circuit 40.

[0195] Capacitor 53 comprises a conductive film electrically connected to the gate electrode of transistor 52B and a conductive film electrically connected to the second electrode of transistor 52C.

[0196] The light-emitting element 61 comprises a first electrode electrically connected to the first electrode of the transistor 52B, and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61.

[0197] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with the image signal applied to the gate electrode of transistor 52B. Furthermore, variations in the gate-source potential of transistor 52B can be suppressed by the reference potential of the wiring V0 provided via transistor 52C.

[0198] Furthermore, the wiring V0 can output a current value that can be used to set pixel parameters. More specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the arithmetic circuit 40 or the like.

[0199] In one aspect of the present invention, the light-emitting element described refers to a self-emissive light-emitting element such as an organic light-emitting element (OLED (Organic Light Emitting Diode)). The light-emitting element electrically connected to the pixel circuit can be a self-emissive light-emitting element such as an LED (Light Emitting Diode), microLED, QLED (Quantum-dot Light Emitting Diode), or semiconductor laser.

[0200] In the configuration shown as an example in Figure 13(B), the wiring electrically connecting the pixel circuit 51 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance. As a result, data can be written at high speed, and the display device 10 can be driven at high speed. This allows for a sufficient frame duration even with a large number of pixel circuits 51 in the display device 10, thus increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 improves the resolution of the image displayed by the display device 10. For example, the pixel density of the display device 10 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, and can be suitably applied to electronic devices where the distance between the display unit and the user is close, such as HMDs.

[0201] Furthermore, layers 20, 50, and 60 shown in Figures 13(A) and 13(B) can be provided with the arithmetic circuit 40, cell array CA, and photodiode PD, which are light-receiving elements, respectively, as described in Embodiment 2 above. Therefore, the display device 10 can be configured to include an arithmetic circuit and a driving circuit, a pixel circuit and a cell array, and a light-emitting element and a light-receiving element.

[0202] Figures 13(A) and 13(B) show a pixel circuit 51 having a total of three transistors as an example, but the present invention is not limited to this. Below, we will describe examples of pixel circuit configurations applicable to the pixel circuit 51.

[0203] The pixel circuit 51A shown in Figure 14(A) includes transistors 52A and 52B, and capacitor 53. Figure 14(A) also shows a light-emitting element 61 connected to the pixel circuit 51A. Wirings SL, GL, ANO, and VCOM are electrically connected to the pixel circuit 51A.

[0204] Transistor 52A's gate is electrically connected to wiring GL, and one of its source and drain is electrically connected to wiring SL, while the other is electrically connected to the gate of transistor 52B and one electrode of capacitor C1. Transistor 52B's source and drain are electrically connected to wiring ANO, while the other is electrically connected to the anode of light-emitting element 61. Capacitor C1's other electrode is electrically connected to the anode of light-emitting element 61. Light-emitting element 61's cathode is electrically connected to wiring VCOM.

[0205] The pixel circuit 51B shown in Figure 14(B) is configured by adding a transistor 52C to the pixel circuit 51A. Furthermore, wiring V0 is electrically connected to the pixel circuit 51B.

[0206] The pixel circuit 51C shown in Figure 14(C) is an example in which transistors 52A and 52B of the pixel circuit 51A are replaced with transistors having a pair of gates. Similarly, the pixel circuit 51D shown in Figure 14(D) is an example in which the same transistors are replaced with those in the pixel circuit 51B. This increases the current that the transistors can supply. While transistors with a pair of gates were used in this example, the design is not limited to this. Furthermore, transistors with a pair of gates that are electrically connected to different wirings may also be used. For example, reliability can be improved by using a transistor in which one of the gates and the source are electrically connected.

[0207] The pixel circuit 51E shown in Figure 15(A) is configured by adding a transistor 52D to the above-mentioned pixel circuit 51B. Furthermore, three wires (wires GL1, GL2, and GL3) that function as gate lines are electrically connected to the pixel circuit 51E.

[0208] Transistor 52D has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor 52B, while the other is electrically connected to wiring V0. Also, the gate of transistor 52A is electrically connected to wiring GL1, and the gate of transistor 52C is electrically connected to wiring GL2.

[0209] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0210] The pixel circuit 51F shown in Figure 15(B) is an example in which a capacitor 53A is added to the above pixel circuit 51E. The capacitor 53A functions as a retaining capacitor.

[0211] The pixel circuit 51G shown in Figure 15(C) and the pixel circuit 51H shown in Figure 15(D) are examples of applying a transistor having a pair of gates to the above-mentioned pixel circuit 51E or pixel circuit 51F, respectively. Transistors 52A, 52C, and 52D are transistors in which a pair of gates are electrically connected, while transistor 52B is a transistor in which one of its gates is electrically connected to the source.

[0212] <Schematic diagram of the top surface of a light-emitting element and its schematic cross-sectional view> Figure 16(A) is a schematic top view showing an example configuration of a display device 10 according to one embodiment of the present invention, in which a light-emitting element and a light-receiving element are arranged within a single pixel. The display device 10 has multiple light-emitting elements 61R that emit red light, multiple light-emitting elements 61G that emit green light, multiple light-emitting elements 61B that emit blue light, and multiple light-receiving elements 62. In Figure 16(A), the labels R, G, and B are added to the light-emitting area of ​​each light-emitting element 61 for easy distinction. The label PD is added to the light-receiving area of ​​each light-receiving element 62.

[0213] The light-emitting elements 61R, 61G, 61B, and light-receiving elements 62 are each arranged in a matrix. Figure 16(A) shows an example in which the light-emitting elements 61R, 61G, and 61B are arranged in the X direction, with the light-receiving elements 62 arranged below them. Figure 16(A) also shows an example configuration in which light-emitting elements 61 that emit light of the same color are arranged in the Y direction intersecting the X direction. In the display device 10 shown in Figure 16(A), for example, a pixel 80 can be composed of sub-pixels having light-emitting elements 61R, sub-pixels having light-emitting elements 61G, and sub-pixels having light-receiving elements 61B arranged in the X direction, and sub-pixels having light-receiving elements 62 provided below these sub-pixels.

[0214] It is preferable to use EL elements such as OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) as the light-emitting elements 61R, 61G, and 61B. Examples of light-emitting materials for EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (TADF) materials.

[0215] For example, a pn-type or pin-type photodiode can be used as the light-receiving element 62. The light-receiving element 62 functions as a photoelectric conversion element that detects light incident on it and generates an electric charge. The amount of charge generated is determined based on the amount of incident light.

[0216] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving element 62. Organic photodiodes can be easily made thinner, lighter, and larger in area, and because they offer a high degree of freedom in shape and design, they can be applied to various display devices.

[0217] In one aspect of the present invention, an organic EL element is used as the light-emitting element 61, and an organic photodiode is used as the light-receiving element 62. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element. It is preferable to separate the organic EL elements and the organic photodiode by photolithography. This allows the spacing between the light-emitting elements and the organic photodiode to be reduced, thus enabling a display device with a higher aperture ratio compared to the case where a shadow mask such as a metal mask is used.

[0218] Figure 16(A) shows a common electrode 81 and a connecting electrode 82. Here, the connecting electrode 82 is electrically connected to the common electrode 81. The connecting electrode 82 is provided outside the display section where the light-emitting element 61 and the light-receiving element 62 are arranged. Also in Figure 16(A), the common electrode 81 having an overlapping region with the light-emitting element 61, the light-receiving element 62, and the connecting electrode 82 is shown by a dashed line.

[0219] The connecting electrode 82 can be provided along the outer circumference of the display unit. For example, it may be provided along one side of the outer circumference of the display unit, or it may be provided across two or more sides of the outer circumference of the display unit. That is, if the top surface shape of the display unit is rectangular, the top surface shape of the connecting electrode 82 can be strip-shaped, L-shaped, U-shaped (angle bracket-shaped), or square, etc.

[0220] Figure 16(B) is a schematic top view showing an example configuration of the display device 10, and is a modified version of the display device 10 shown in Figure 16(A). The display device 10 shown in Figure 16(B) differs from the display device 10 shown in Figure 16(A) in that it has a light-emitting element 61IR that emits infrared light. The light-emitting element 61IR can emit, for example, near-infrared light (light with a wavelength of 750 nm to 1300 nm).

[0221] In the example shown in Figure 16(B), light-emitting elements 61R, 61G, and 61B, as well as light-emitting element 61IR, are arranged in the X direction, with a light-receiving element 62 arranged below them. The light-receiving element 62 has the function of detecting infrared light.

[0222] Figure 17(A) is a cross-sectional view corresponding to the dashed line A1-A2 in Figure 16(A), and Figure 17(B) is a cross-sectional view corresponding to the dashed line B1-B2 in Figure 16(A). Furthermore, Figure 17(C) is a cross-sectional view corresponding to the dashed line C1-C2 in Figure 16(A), and Figure 17(D) is a cross-sectional view corresponding to the dashed line D1-D2 in Figure 16(A). The light-emitting element 61R, light-emitting element 61G, light-emitting element 61B, and light-receiving element 62 are provided on the substrate 83. In addition, if the display device 10 has a light-emitting element 61IR, the light-emitting element 61IR is provided on the substrate 83.

[0223] In this specification, for example, when we refer to "B on A" or "B below A," it is not necessarily required that A and B have areas in contact.

[0224] Figure 17(A) shows an example of the cross-sectional configuration of the light-emitting element 61R, light-emitting element 61G, and light-emitting element 61B. Figure 17(B) shows an example of the cross-sectional configuration of the light-receiving element 62.

[0225] The light-emitting element 61R has a pixel electrode 84R, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a common electrode 81. The light-emitting element 61G has a pixel electrode 84G, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a common electrode 81. The light-emitting element 61B has a pixel electrode 84B, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a common electrode 81. The light-receiving element 62 has a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81.

[0226] In the light-emitting element 61, the common layer 89 functions as an electron injection layer. On the other hand, in the photodetector 62, the common layer 89 functions as an electron transport layer. Therefore, the photodetector 62 does not need to have an electron transport layer 88PD.

[0227] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be called functional layers.

[0228] The pixel electrode 84, hole injection layer 85, hole transport layer 86, light-emitting layer 87, and electron transport layer 88 can be provided separately for each element. The common layer 89 and common electrode 81 are provided in common for the light-emitting element 61R, light-emitting element 61G, light-emitting element 61B, and light-receiving element 62.

[0229] Furthermore, the light-emitting element 61 and the light-receiving element 62 may have a hole-blocking layer and an electron-blocking layer in addition to the layers shown in Figure 17(A). Also, the light-emitting element 61 and the light-receiving element 62 may have layers containing bipolar material (a material with high electron transport and hole transport properties), etc.

[0230] A gap is provided between the common layer 89 and the insulating layer 92, which will be described later. This prevents the common layer 89 from coming into contact with the sides of the light-emitting layer 87, the light-receiving layer 90, the hole transport layer 86, and the hole injection layer 85. This prevents short circuits in the light-emitting element 61 and the light-receiving element 62.

[0231] The above-mentioned voids are more likely to form when the distance between the light-emitting layers 87 is shorter, for example. For example, if the distance is 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less, the above-mentioned voids can be suitably formed.

[0232] Figure 17(A) shows a configuration in which the light-emitting element 61 is provided with, in order from the bottom layer, a pixel electrode 84, a hole injection layer 85, a hole transport layer 86, a light-emitting layer 87, an electron transport layer 88, a common layer 89 (electron injection layer), and a common electrode 81, and the light-receiving element 62 is provided with, in order from the bottom layer, a pixel electrode 84PD, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81. However, the present invention is not limited to this configuration. For example, the light-emitting element 61 may be provided with, in order from the bottom layer, a pixel electrode, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, a hole injection layer, and a common electrode, and the light-receiving element 62 may be provided with, in order from the bottom layer, a pixel electrode, an electron transport layer, a light-receiving layer, a hole transport layer, and a common electrode. In this case, the hole injection layer of the light-emitting element 61 can be a common layer, and this common layer can be provided between the hole transport layer of the photodetector 62 and the common electrode. Furthermore, in the light-emitting element 61, the electron injection layer can be separated for each element.

[0233] In the following explanation, we will assume that the electron transport layer is located above the hole transport layer. However, by, for example, substituting "electron" with "hole" and "hole" with "electron," the following explanation can also be applied when the electron transport layer is located below the hole transport layer.

[0234] The hole injection layer is a layer that injects holes from the anode into the hole transport layer, and is a layer containing a material with high hole injection capabilities. Examples of materials with high hole injection capabilities include aromatic amine compounds and composite materials containing hole transport materials and acceptor materials (electron-accepting materials).

[0235] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. The hole transport layer is a layer containing a hole-transporting material. As for the hole-transporting material, 10 -6 cm 2Materials having a hole mobility of / Vs or higher are preferred. However, other materials can also be used as long as they have higher hole transport capabilities than electron transport. Preferred hole transport materials include π-electron-rich heteroaromatic compounds (e.g., carbazole derivatives, thiophene derivatives, furan derivatives, etc.) and aromatic amines (compounds having an aromatic amine skeleton), which are materials with high hole transport capabilities.

[0236] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. The electron transport layer is a layer containing an electron-transporting material. The electron-transporting material is 1 × 10⁻¹⁶ -6 cm 2 Materials having an electron mobility of / Vs or higher are preferred. However, other materials can also be used as long as they have higher electron transport capabilities than holes. Examples of electron-transporting materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds containing nitrogen-containing heteroaromatic compounds.

[0237] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer, and is a layer containing a material with high electron injection capabilities. Alkali metals, alkaline earth metals, or compounds thereof can be used as materials with high electron injection capabilities. Composite materials containing both electron transport materials and donor materials (electron-donating materials) can also be used as materials with high electron injection capabilities.

[0238] Examples of electron injection layers include lithium, cesium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF2), 8-(quinolinolato)lithium (abbreviated as Liq), 2-(2-pyridyl)phenolate (abbreviated as LiPP), 2-(2-pyridyl)-3-pyridinolatritium (abbreviated as LiPPy), 4-phenyl-2-(2-pyridyl)phenolate (abbreviated as LiPPP), and lithium oxide (LiO2). x ), alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used.

[0239] Alternatively, an electron-transporting material may be used as the electron injection layer described above. For example, a compound having a lone pair of electrons and an electron-deficient heteroaromatic ring can be used as the electron-transporting material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), or a triazine ring can be used.

[0240] Furthermore, it is preferable that the lowest unoccupied molecular orbital (LUMO) of an organic compound containing a lone pair of electrons is between -3.6 eV and -2.3 eV. In general, the highest occupied molecular orbital (HOMO) level and LUMO level of an organic compound can be estimated by methods such as cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, and inverse photoelectron spectroscopy.

[0241] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), diquinoxalino[2,3-a:2’,3’-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3’-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), etc. can be used for organic compounds having lone pairs of electrons. Note that NBPhen has a higher glass transition temperature (Tg) and excellent heat resistance compared to BPhen.

[0242] The light-emitting layer is a layer containing a light-emitting substance. The light-emitting layer can have one or more light-emitting substances. As the light-emitting substance, substances that emit light of colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, red, etc. can be appropriately used. Also, as the light-emitting substance, a substance that emits near-infrared light can be used.

[0243] Examples of the light-emitting substance include a fluorescent material, a phosphorescent material, a TADF material, a quantum dot material, etc.

[0244] Examples of the fluorescent material include a pyrene derivative, an anthracene derivative, a triphenylene derivative, a fluorene derivative, a carbazole derivative, a dibenzothiophene derivative, a dibenzofuran derivative, a dibenzoquinoxaline derivative, a quinoxaline derivative, a pyridine derivative, a pyrimidine derivative, a phenanthrene derivative, a naphthalene derivative, etc.

[0245] Examples of the phosphorescent material include an organometallic complex (especially an iridium complex) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton, an organometallic complex (especially an iridium complex) having a phenylpyridine derivative having an electron-withdrawing group as a ligand, a platinum complex, a rare earth metal complex, etc.

[0246] The light-emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more of these organic compounds may be hole-transporting materials and / or electron-transporting materials. Alternatively, one or more of these organic compounds may be bipolar materials or TADF materials.

[0247] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that emits light overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0248] The light-emitting layer 87R of the light-emitting element 61R has a luminescent organic compound that emits light having a peak in at least the red wavelength range. The light-emitting layer 87G of the light-emitting element 61G has a luminescent organic compound that emits light having a peak in at least the green wavelength range. The light-emitting layer 87B of the light-emitting element 61B has a luminescent organic compound that emits light having a peak in at least the blue wavelength range. The light-receiving layer 90 of the light-receiving element 62 has, for example, an organic compound that has detection sensitivity in the visible light wavelength range.

[0249] A conductive film that is transparent to visible light is used on either the pixel electrode 84 or the common electrode 81, and a conductive film that is reflective is used on the other. By making the pixel electrode 84 transparent and the common electrode 81 reflective, the display device 10 can be made into a bottom-emission type display device. On the other hand, by making the pixel electrode 84 reflective and the common electrode 81 transparent, the display device 10 can be made into a top-emission type display device. Furthermore, by making both the pixel electrode 84 and the common electrode 81 transparent, the display device 10 can be made into a dual-emission type display device.

[0250] Furthermore, it is preferable that the light-emitting element 61 has a microcavity structure. This allows the light emitted from the light-emitting layer 87 to resonate between the pixel electrode 84 and the common electrode 81, thereby strengthening the light emitted from the light-emitting element 61.

[0251] When the light-emitting element 61 has a microcavity structure, it is preferable that one of the common electrode 81 or the pixel electrode 84 is an electrode that has both light transmission and reflectivity (a semi-transparent / semi-reflective electrode), and the other of the common electrode 81 or the pixel electrode 84 is a reflective electrode (a reflective electrode). Here, the semi-transparent / semi-reflective electrode can be a laminated structure of a reflective electrode and an electrode that transmits visible light (also called a transparent electrode). The transparent electrode can be called an optical adjustment layer.

[0252] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode for the light-emitting element 61 that has a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm). The visible light reflectance of the semi-transparent / semi-reflective electrode shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes shall be 1 × 10⁻⁶ -2It is preferable that the value be Ωcm or less. Furthermore, when a light-emitting element that emits near-infrared light is used in the display device, it is preferable that the transmittance and reflectance of these electrodes for near-infrared light (light with a wavelength of 750 nm to 1300 nm) are also within the above numerical range.

[0253] An insulating layer 92 is provided to cover the ends of the pixel electrode 84R, the ends of the pixel electrode 84G, the ends of the pixel electrode 84B, and the ends of the pixel electrode 84PD. The ends of the insulating layer 92 are preferably tapered. The insulating layer 92 may be omitted if it is not needed.

[0254] For example, the hole injection layer 85R, hole injection layer 85G, hole injection layer 85B, and hole transport layer 86PD each have a region in contact with the upper surface of the pixel electrode 84 and a region in contact with the surface of the insulating layer 92. Furthermore, the ends of the hole injection layer 85R, the ends of the hole injection layer 85G, the ends of the hole injection layer 85B, and the ends of the hole transport layer 86PD are located on the insulating layer 92.

[0255] As shown in Figure 17(A), a gap is provided between light-emitting elements 61 that emit light of different colors, for example, between two light-emitting layers 87. In this way, it is preferable that light-emitting layers 87R, 87G, and 87B are arranged so that they do not touch each other. This effectively prevents current from flowing through two adjacent light-emitting layers 87 and causing unintended light emission. As a result, the contrast of the display device 10 can be increased, and thus the display quality of the display device 10 can be improved.

[0256] A protective layer 91 is provided on the common electrode 81. The protective layer 91 has the function of preventing impurities such as water from diffusing to each light-emitting element from above.

[0257] The protective layer 91 can be, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide film, silicon oxide nitride film, silicon nitride film, silicon nitride film, aluminum oxide film, aluminum oxide nitride film, and hafnium oxide film. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide may be used as the protective layer 91.

[0258] In this specification, a silicon oxide-nitride film refers to a film in which the oxygen content is greater than the nitrogen content. Similarly, a silicon nitride-oxide film refers to a film in which the nitrogen content is greater than the oxygen content.

[0259] Furthermore, a laminated film of an inorganic insulating film and an organic insulating film can also be used as the protective layer 91. For example, it is preferable to have a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films. It is also preferable that the organic insulating film functions as a planarizing film. This makes the upper surface of the organic insulating film flat, thereby improving the coverage of the inorganic insulating film on top of it and enhancing its barrier properties. In addition, since the upper surface of the protective layer 91 is flat, it is preferable because it reduces the influence of uneven shapes caused by the structure below when a structure (e.g., a color filter, touch sensor electrodes, or lens array, etc.) is provided above the protective layer 91.

[0260] Figure 17(C) shows an example of the cross-sectional configuration of the display device 10 in the Y direction, specifically showing an example of the cross-sectional configuration of the light-emitting element 61R and the light-receiving element 62. Note that the light-emitting elements 61G and 61B can also be arranged in the Y direction in the same way as the light-emitting element 61R.

[0261] Figure 17(D) shows a connection portion 93 where the connecting electrode 82 and the common electrode 81 are electrically connected. In the connection portion 93, the common electrode 81 is placed in contact with the connecting electrode 82, and a protective layer 91 is provided to cover the common electrode 81. In addition, an insulating layer 92 is provided to cover the end of the connecting electrode 82.

[0262] <Configuration Example of Light-Emitting Element> As shown in FIG. 18(A), the light-emitting element has an EL layer 686 between a pair of electrodes (electrode 672 and electrode 688). The EL layer 686 can be composed of a plurality of layers such as layer 4420, light-emitting layer 4411, and layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron injection property (electron injection layer) and a layer containing a substance with high electron transport property (electron transport layer). The light-emitting layer 4411 has, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole injection property (hole injection layer) and a layer containing a substance with high hole transport property (hole transport layer).

[0263] The configuration having the layer 4420, light-emitting layer 4411, and layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and in this specification, the configuration of FIG. 18(A) is referred to as a single structure.

[0264] Further, FIG. 18(B) is a modified example of the EL layer 686 included in the light-emitting element shown in FIG. 18(A). Specifically, the light-emitting element shown in FIG. 18(B) has a layer 4430-1 on the electrode 672, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and an electrode 688 on the layer 4420-2. For example, when the electrode 672 is an anode and the electrode 688 is a cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Or, when the electrode 672 is a cathode and the electrode 688 is an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By adopting the layer structure shown in FIG. 18(B), carriers can be efficiently injected into the light-emitting layer 4411, and the efficiency of carrier recombination in the light-emitting layer 4411 can be increased.

[0265] Furthermore, as shown in Figure 18(C), a configuration in which multiple light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0266] Furthermore, as shown in Figure 18(D), a configuration in which multiple light-emitting units (EL layer 686a, EL layer 686b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure in this specification. In this specification, the configuration shown in Figure 18(D) is referred to as a tandem structure, but it is not limited to this, and for example, a tandem structure may also be called a stack structure. By using a tandem structure, a light-emitting element capable of high-brightness light emission can be made.

[0267] Furthermore, in Figures 18(C) and 18(D), as shown in Figure 18(B), layer 4420 and layer 4430 may be a laminated structure consisting of two or more layers.

[0268] Furthermore, a structure in which each light-emitting element produces a different emission color (in this case, blue (B), green (G), and red (R)) is sometimes called an SBS (Side By Side) structure.

[0269] Furthermore, when comparing the single structure, tandem structure, and SBS structure described above, power consumption can be reduced in the order of SBS structure, tandem structure, and single structure. If you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single structure and tandem structure are preferable because their manufacturing process is simpler than that of the SBS structure, which can lead to lower manufacturing costs or higher manufacturing yields.

[0270] The light-emitting color of the light-emitting element can be red, green, blue, cyan, magenta, yellow, or white, depending on the material constituting the EL layer 686. Furthermore, the color purity can be further enhanced by adding a microcavity structure to the light-emitting element.

[0271] A light-emitting element that emits white light preferably has a configuration that includes two or more types of light-emitting materials in its light-emitting layer. To obtain white light emission, it is sufficient to select light-emitting materials such that the light emitted by each of the two or more materials is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary in color, a light-emitting element that emits white light as a whole can be obtained. The same applies to light-emitting elements that have three or more light-emitting layers.

[0272] The light-emitting layer preferably contains two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, it is preferable to have two or more light-emitting materials, and for each light-emitting material to emit light that contains spectral components of two or more colors from R, G, and B.

[0273] <Example of light-emitting element and light-receiving element configuration>

[0274] One embodiment of the present invention is a top-emission type display device that emits light in the direction opposite to the substrate on which the light-emitting element is formed. In this embodiment, a display device equipped with a top-emission type light-emitting element and a light-receiving element will be described as an example.

[0275] In this specification, unless otherwise specified, when describing a configuration having multiple elements (such as light-emitting elements and light-emitting layers), the letters will be omitted when describing matters common to each element. For example, when describing matters common to light-emitting layers 383R and 383G, etc., it may be written as light-emitting layer 383.

[0276] The display device 380A shown in Figure 19(A) includes a light-receiving element 370PD, a light-emitting element 370R that emits red (R) light, a light-emitting element 370G that emits green (G) light, and a light-emitting element 370B that emits blue (B) light.

[0277] Each light-emitting element has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​a light-emitting layer, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order. Light-emitting element 370R has a light-emitting layer 383R, light-emitting element 370G has a light-emitting layer 383G, and light-emitting element 370B has a light-emitting layer 383B. Light-emitting layer 383R has a light-emitting material that emits red light, light-emitting layer 383G has a light-emitting material that emits green light, and light-emitting layer 383B has a light-emitting material that emits blue light.

[0278] The light-emitting element is an electroluminescent element that emits light towards the common electrode 375 when a voltage is applied between the pixel electrode 371 and the common electrode 375.

[0279] The photodetector 370PD has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order.

[0280] The light-receiving element 370PD is a photoelectric conversion element that receives light incident from outside the display device 380A and converts it into an electrical signal.

[0281] In this embodiment, both the light-emitting element and the light-receiving element are described as having a pixel electrode 371 functioning as the anode and a common electrode 375 functioning as the cathode. In other words, the light-receiving element can detect light incident on it, generate an electric charge, and extract it as an electric current by driving it with a reverse bias applied between the pixel electrode 371 and the common electrode 375.

[0282] In the display device of this embodiment, an organic compound is used for the active layer 373 of the light-receiving element 370PD. The layers of the light-receiving element 370PD other than the active layer 373 can have the same configuration as those of the light-emitting element. Therefore, by simply adding a step of forming the active layer 373 to the manufacturing process of the light-emitting element, the light-receiving element 370PD can be formed in parallel with the formation of the light-emitting element. Furthermore, the light-emitting element and the light-receiving element 370PD can be formed on the same substrate. Thus, the light-receiving element 370PD can be incorporated into the display device without significantly increasing the manufacturing process.

[0283] In the display device 380A, an example is shown where the light-receiving element 370PD and the light-emitting element have a common configuration, except that the active layer 373 of the light-receiving element 370PD and the light-emitting layer 383 of the light-emitting element are manufactured separately. However, the configuration of the light-receiving element 370PD and the light-emitting element is not limited to this. In addition to the active layer 373 and the light-emitting layer 383, the light-receiving element 370PD and the light-emitting element may have layers that are manufactured separately from each other. It is preferable that the light-receiving element 370PD and the light-emitting element have one or more layers that are used in common (common layers). This makes it possible to incorporate the light-receiving element 370PD into the display device without significantly increasing the manufacturing process.

[0284] Of the pixel electrode 371 and the common electrode 375, the electrode that extracts light preferably uses a conductive film that transmits visible light. Furthermore, it is preferable to use a conductive film that reflects visible light on the electrode that does not extract light.

[0285] In this embodiment, it is preferable that the light-emitting element of the display device has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes of the light-emitting element has an electrode that is transparent to and reflective to visible light (a semi-transmitting / semi-reflective electrode), and the other has an electrode that is reflective to visible light (a reflective electrode). By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0286] Furthermore, semi-transmissive / semi-reflective electrodes can have a laminated structure consisting of a reflective electrode and an electrode that transmits visible light (also called a transparent electrode).

[0287] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a visible light transmittance (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more in the light-emitting element. The visible light reflectance of the semi-transparent / semi-reflective electrode shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes shall be 1 × 10⁻⁶ -2 It is preferable that the value be Ωcm or less. Furthermore, if the light-emitting element emits near-infrared light (light with a wavelength of 750 nm to 1300 nm), it is preferable that the transmittance or reflectance of these electrodes in near-infrared light satisfies the above numerical range, similar to the transmittance or reflectance of visible light.

[0288] The light-emitting element has at least an emissive layer 383. The light-emitting element may further have layers other than the emissive layer 383 that include a material with high hole injection properties, a material with high hole transport properties, a hole blocking material, a material with high electron transport properties, a material with high electron injection properties, an electron blocking material, or a bipolar material (a material with high electron transport and hole transport properties).

[0289] For example, a light-emitting element and a photodetector can have one or more layers from among the hole injection layer, hole transport layer, electron transport layer, and electron injection layer in common. Alternatively, one or more layers from among the hole injection layer, hole transport layer, electron transport layer, and electron injection layer can be manufactured separately for each element.

[0290] The hole injection layer is a layer that injects holes from the anode into the hole transport layer, and is a layer containing a material with high hole injection properties. As the material with high hole injection properties, aromatic amine compounds or composite materials containing a hole transport material and an acceptor material (electron-accepting material) can be used.

[0291] In a light-emitting device, the hole transport layer is a layer that transports holes injected from the anode to the light-emitting layer by the hole injection layer. In a light-receiving device, the hole transport layer is a layer that transports holes generated based on light incident on the active layer to the anode. The hole transport layer is a layer containing a hole-transporting material. As the hole-transporting material, a substance having a hole mobility of 1×10 -6 cm 2 / Vs or more is preferable. In addition, as long as the substance has higher hole transportability than electrons, other substances can also be used. As the hole-transporting material, a material having high hole transportability such as a π-electron-excessive heteroaromatic compound (for example, a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton) is preferable.

[0292] In a light-emitting device, the electron transport layer is a layer that transports electrons injected from the cathode to the light-emitting layer by the electron injection layer. In a light-receiving device, the electron transport layer is a layer that transports electrons generated based on light incident on the active layer to the cathode. The electron transport layer is a layer containing an electron-transporting material. As the electron-transporting material, a substance having an electron mobility of 1×10 -6 cm 2 / Vs or more is preferable. In addition, as long as the substance has higher electron transportability than holes, other substances can also be used. As the electron-transporting material, in addition to a metal complex having a quinoline skeleton, a metal complex having a benzoquinoline skeleton, a metal complex having an oxazole skeleton, a metal complex having a thiazole skeleton, etc., an oxadiazole derivative, a triazole derivative, an imidazole derivative, an oxazole derivative, a thiazole derivative, a phenanthroline derivative, a quinoline derivative having a quinoline ligand, a benzoquinoline derivative, a quinoxaline derivative, a dibenzoquinoxaline derivative, a pyridine derivative, a bipyridine derivative, a pyrimidine derivative, and other electron-transporting materials including nitrogen-containing heteroaromatic compounds such as π-electron-deficient heteroaromatic compounds can be used.

[0293] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer, and is a layer containing a material with high electron injection capabilities. Alkali metals, alkaline earth metals, or compounds thereof can be used as materials with high electron injection capabilities. Composite materials containing both electron transport materials and donor materials (electron-donating materials) can also be used as materials with high electron injection capabilities.

[0294] The light-emitting layer 383 is a layer containing a light-emitting material. The light-emitting layer 383 may contain one or more types of light-emitting materials. The light-emitting material may be a substance that exhibits a light emission color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red. A substance that emits near-infrared light may also be used as the light-emitting material.

[0295] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0296] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0297] Examples of phosphorescent materials include organometallic complexes (especially iridium complexes) having a 4H-triazole skeleton, 1H-triazole skeleton, imidazole skeleton, pyrimidine skeleton, pyrazine skeleton, or pyridine skeleton; organometallic complexes (especially iridium complexes) using phenylpyridine derivatives having electron-withdrawing groups as ligands; platinum complexes; and rare earth metal complexes.

[0298] The light-emitting layer 383 may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more types of organic compounds may include hole-transporting materials and electron-transporting materials, or both. Alternatively, one or more types of organic compounds may include bipolar materials or TADF materials.

[0299] The light-emitting layer 383 preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. With such a configuration, light emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material), can be efficiently obtained. By selecting a combination that forms an excitation complex that exhibits light emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be efficiently obtained. This configuration enables high efficiency, low-voltage operation, and long lifespan of the light-emitting element simultaneously.

[0300] For a combination of materials to form an excited complex, it is preferable that the HOMO level (highest occupied orbital level) of the hole-transporting material is greater than or equal to the HOMO level of the electron-transporting material. It is also preferable that the LUMO level (lowest unoccupied orbital level) of the hole-transporting material is greater than or equal to the LUMO level of the electron-transporting material. The LUMO and HOMO levels of the materials can be derived from the electrochemical properties (reduction potential and oxidation potential) of the materials measured by cyclic voltammetry (CV).

[0301] The formation of excited complexes can be confirmed, for example, by comparing the emission spectra of a hole-transporting material, an electron-transporting material, and a mixed film made by mixing these materials, and observing that the emission spectrum of the mixed film shifts to a longer wavelength than the emission spectra of each individual material (or has a new peak on the longer wavelength side). Alternatively, it can be confirmed by comparing the transient photoluminescence (PL) of a hole-transporting material, an electron-transporting material, and a mixed film made by mixing these materials, and observing differences in the transient response, such as the transient PL lifetime of the mixed film having a longer lifetime component or a larger proportion of the delayed component than the transient PL lifetime of each individual material. Furthermore, the transient PL mentioned above can be read as transient electroluminescence (EL). That is, the formation of excited complexes can also be confirmed by comparing the transient EL of a hole-transporting material, an electron-transporting material, and a mixed film made by mixing these materials, and observing the differences in the transient response.

[0302] The active layer 373 contains a semiconductor. Examples of such semiconductors include inorganic semiconductors such as silicon, and organic semiconductors containing organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer 373. Using an organic semiconductor is preferable because the light-emitting layer 383 and the active layer 373 can be formed by the same method (for example, vacuum deposition), and the manufacturing equipment can be shared.

[0303] The n-type semiconductor material of the active layer 373 is fullerene (for example, C 60 , C 70Examples of the electron-accepting organic semiconductor materials include fullerenes, fullerene derivatives, etc. Fullerene has a shape like a soccer ball, and this shape is energetically stable. For fullerene, both the HOMO level and the LUMO level are deep (low). Since the LUMO level of fullerene is deep, its electron-accepting (acceptor) property is extremely high. Usually, like benzene, when the π-electron conjugation (resonance) spreads in a plane, the electron-donating (donor) property becomes high. However, since fullerene has a spherical shape, despite the large spread of π electrons, its electron-accepting property is high. A high electron-accepting property is beneficial for a light-receiving element because it can cause charge separation efficiently at high speed. C 60 , C 70 both have broad absorption bands in the visible light region. In particular, C 70 is preferable because it has a larger π-electron conjugation system than C 60 and also has a broad absorption band in the long wavelength region. In addition, examples of fullerene derivatives include [6,6]-Phenyl-C71-butyric acid methyl ester (abbreviation: PC70BM), [6,6]-Phenyl-C61-butyric acid methyl ester (abbreviation: PC60BM), 1’,1’’,4’,4’’-Tetrahydro-di[1,4]methanonaphthaleno[1,2:2’,3’,56,60:2’’,3’’][5,6]fullerene-C60 (abbreviation: ICBA), etc.

[0304] In addition, examples of the n-type semiconductor materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, naphthalene derivatives, anthracene derivatives, coumarin derivatives, rhodamine derivatives, triazine derivatives, quinone derivatives, etc.

[0305] Examples of p-type semiconductor materials for the active layer 373 include electron-donating organic semiconductor materials such as copper(II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), zinc phthalocyanine (ZnPc), tin phthalocyanine (SnPc), and quinacridone.

[0306] Furthermore, examples of p-type semiconductor materials include carbazole derivatives, thiophene derivatives, furan derivatives, and compounds having an aromatic amine skeleton. In addition, examples of p-type semiconductor materials include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indrocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylenevinylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, and polythiophene derivatives.

[0307] The HOMO level of electron-donating organic semiconductor materials is preferably shallower (higher) than the HOMO level of electron-accepting organic semiconductor materials. The LUMO level of electron-donating organic semiconductor materials is preferably shallower (higher) than the LUMO level of electron-accepting organic semiconductor materials.

[0308] It is preferable to use spherical fullerenes as electron-accepting organic semiconductor materials and organic semiconductor materials with a near-planar shape as electron-donating organic semiconductor materials. Molecules with similar shapes tend to aggregate, and when molecules of the same type aggregate, their molecular orbital energy levels are close, which can improve carrier transport.

[0309] For example, the active layer 373 is preferably formed by co-depositing an n-type semiconductor and a p-type semiconductor. Alternatively, the active layer 373 may be formed by stacking an n-type semiconductor and a p-type semiconductor.

[0310] The light-emitting element and the light-receiving element may use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element and the light-receiving element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0311] For example, polymer compounds such as poly(3,4-ethylenedioxythiophene) / poly(styrenesulfonic acid) (PEDOT / PSS), and inorganic compounds such as molybdenum oxide and copper iodide (CuI) can be used as hole transport materials. In addition, inorganic compounds such as zinc oxide (ZnO) can be used as electron transport materials.

[0312] Furthermore, the active layer 373 can use polymer compounds such as Poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b']dithiophene-2,6-diyl]-2,5-thiophenediyl[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c']dithiophene-1,3-diyl]]polymer (abbreviated as PBDB-T) or PBDB-T derivatives, which function as donors. For example, a method of dispersing the acceptor material in PBDB-T or a PBDB-T derivative can be used.

[0313] Furthermore, the active layer 373 may contain a mixture of three or more materials. For example, to broaden the wavelength range, a third material may be mixed with an n-type semiconductor material and a p-type semiconductor material. In this case, the third material may be a low-molecular-weight compound or a high-molecular-weight compound.

[0314] The display device 380B shown in Figure 19(B) differs from the display device 380A in that the light-receiving element 370PD and the light-emitting element 370R have the same configuration.

[0315] The light-receiving element 370PD and the light-emitting element 370R both share an active layer 373 and a light-emitting layer 383R.

[0316] Here, it is preferable that the light-receiving element 370PD has a common configuration with the light-emitting element that emits light with a longer wavelength than the light to be detected. For example, the light-receiving element 370PD configured to detect blue light can have the same configuration as one or both of the light-emitting elements 370R and 370G. For example, the light-receiving element 370PD configured to detect green light can have the same configuration as the light-emitting element 370R.

[0317] By using a common configuration for the light-receiving element 370PD and the light-emitting element 370R, the number of film deposition steps and masks can be reduced compared to a configuration where the light-receiving element 370PD and the light-emitting element 370R have distinct layers. Therefore, the manufacturing process and cost of the display device can be reduced.

[0318] Furthermore, by using a common configuration for the light-receiving element 370PD and the light-emitting element 370R, the margin for misalignment can be narrowed compared to a configuration where the light-receiving element 370PD and the light-emitting element 370R have distinct layers. This allows for an increase in the aperture ratio of the pixels, thereby improving the light extraction efficiency of the display device. This extends the lifespan of the light-emitting element. In addition, the display device can display high brightness. Furthermore, it is possible to increase the resolution of the display device.

[0319] The light-emitting layer 383R has a light-emitting material that emits red light. The active layer 373 has an organic compound that absorbs light with a shorter wavelength than red (for example, green light and / or blue light). Preferably, the active layer 373 has an organic compound that does not easily absorb red light and absorbs light with a shorter wavelength than red. As a result, red light is efficiently extracted from the light-emitting element 370R, and the photodetector 370PD can detect light with a shorter wavelength than red with high accuracy.

[0320] Furthermore, although the display device 380B shows an example in which the light-emitting element 370R and the light-receiving element 370PD have the same configuration, the light-emitting element 370R and the light-receiving element 370PD may each have optical adjustment layers of different thicknesses.

[0321] The display device 380C shown in Figures 20(A) and 20(B) has a light-receiving element 370SR, an element 370G, and an element 370B that emit red (R) light and have a light-receiving function. The configuration of the element 370G and the element 370B can be adapted from that of the display device 380A, etc.

[0322] The light-receiving element 370SR has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, ​​an active layer 373, a light-emitting layer 383R, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order. The light-receiving element 370SR has the same configuration as the light-receiving element 370R and the light-receiving element 370PD exemplified in the display device 380B described above.

[0323] Figure 20(A) shows the case where the light-emitting element 370SR functions as a light-emitting element. Figure 20(A) shows an example where the light-emitting element 370B emits blue light, the light-emitting element 370G emits green light, and the light-emitting element 370SR emits red light.

[0324] Figure 20(B) shows the case where the light-receiving element 370SR functions as a light-receiving element. Figure 20(B) shows an example in which the light-receiving element 370SR receives blue light emitted by the light-emitting element 370B and green light emitted by the light-emitting element 370G.

[0325] The light-emitting element 370B, the light-emitting element 370G, and the light-receiving element 370SR each have a pixel electrode 371 and a common electrode 375, respectively. In this embodiment, the case in which the pixel electrode 371 functions as an anode and the common electrode 375 functions as a cathode will be described as an example. The light-receiving element 370SR can detect light incident on it, generate an electric charge, and extract it as an electric current by driving it with a reverse bias applied between the pixel electrode 371 and the common electrode 375.

[0326] The light-receiving element 370SR can be described as a light-emitting element with an active layer 373 added. In other words, by simply adding a step of depositing the active layer 373 to the manufacturing process of the light-emitting element, the light-receiving element 370SR can be formed in parallel with the formation of the light-emitting element. Furthermore, the light-emitting element and the light-receiving element can be formed on the same substrate. Therefore, without significantly increasing the manufacturing process, it is possible to provide the display unit with either or both imaging and sensing functions.

[0327] The stacking order of the light-emitting layer 383R and the active layer 373 is not limited. Figures 20(A) and 20(B) show an example in which the active layer 373 is provided on the hole transport layer 382 and the light-emitting layer 383R is provided on the active layer 373. The stacking order of the light-emitting layer 383R and the active layer 373 may be reversed.

[0328] Furthermore, the light-emitting / receiving element does not necessarily have to have at least one of the hole injection layer 381, hole transport layer 382, ​​electron transport layer 384, and electron injection layer 385. The light-emitting / receiving element may also have other functional layers, such as a hole blocking layer or an electron blocking layer.

[0329] In a light-receiving and light-emitting device, it is preferable to use a conductive film that transmits visible light on the electrode that extracts light, and to use a conductive film that reflects visible light on the electrode that does not extract light.

[0330] The functions and materials of each layer constituting the light-emitting and light-receiving elements are the same as those of each layer constituting the light-emitting and light-receiving elements, so a detailed explanation is omitted.

[0331] Figures 20(C) to 20(G) show examples of stacked structures of light-emitting and receiving devices.

[0332] The light-emitting and receiving device shown in Figure 20(C) includes a first electrode 377, a hole injection layer 381, a hole transport layer 382, ​​a light-emitting layer 383R, an active layer 373, an electron transport layer 384, an electron injection layer 385, and a second electrode 378.

[0333] Figure 20(C) shows an example in which a light-emitting layer 383R is provided on a hole transport layer 382, ​​and an active layer 373 is laminated on the light-emitting layer 383R.

[0334] As shown in Figures 20(A) to 20(C), the active layer 373 and the light-emitting layer 383R may be in contact with each other.

[0335] Furthermore, it is preferable to provide a buffer layer between the active layer 373 and the light-emitting layer 383R. In this case, it is preferable that the buffer layer has hole-transporting and electron-transporting properties. For example, it is preferable to use a bipolar material for the buffer layer. Alternatively, at least one layer from among a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, a hole-blocking layer, and an electron-blocking layer can be used as the buffer layer. Figure 20(D) shows an example in which a hole transport layer 382 is used as the buffer layer.

[0336] By providing a buffer layer between the active layer 373 and the light-emitting layer 383R, the transfer of excitation energy from the light-emitting layer 383R to the active layer 373 can be suppressed. Furthermore, the buffer layer can be used to adjust the optical path length (cavity length) of the microcavity structure. Therefore, a light-emitting / receiving device having a buffer layer between the active layer 373 and the light-emitting layer 383R can achieve high luminescence efficiency.

[0337] Figure 20(E) shows an example of a laminated structure in which a hole transport layer 382-1, an emissive layer 383R, a hole transport layer 382-2, and an active layer 373 are stacked in that order on a hole injection layer 381. The hole transport layer 382-2 functions as a buffer layer. The hole transport layer 382-1 and the hole transport layer 382-2 may contain the same material or different materials. Alternatively, a layer that can be used as a buffer layer as described above may be used instead of the hole transport layer 382-2. Furthermore, the positions of the active layer 373 and the emissive layer 383R may be swapped.

[0338] The light-receiving element shown in Figure 20(F) differs from the light-receiving element shown in Figure 20(A) in that it does not have a hole transport layer 382. Thus, the light-receiving element does not need to have at least one of the hole injection layer 381, hole transport layer 382, ​​electron transport layer 384, and electron injection layer 385. Furthermore, the light-receiving element may have other functional layers such as a hole blocking layer or an electron blocking layer.

[0339] The light-receiving element shown in Figure 20(G) differs from the light-receiving element shown in Figure 20(A) in that it does not have an active layer 373 and a light-emitting layer 383R, but has a layer 389 that serves as both a light-emitting layer and an active layer.

[0340] As a layer that serves as both an emissive layer and an active layer, for example, a layer can be used that contains three materials: an n-type semiconductor that can be used in the active layer 373, a p-type semiconductor that can be used in the active layer 373, and an emissive material that can be used in the emissive layer 383R.

[0341] Furthermore, it is preferable that the lowest energy absorption band of the absorption spectrum of the mixed material of n-type and p-type semiconductors and the maximum peak of the emission spectrum (PL spectrum) of the luminescent material do not overlap, and it is even more preferable that they are sufficiently far apart.

[0342] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0343] <Example of cross-sectional view configuration> Figure 21 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 has a configuration in which a transistor 310 with a channel formed on a substrate 301 and a transistor 320 containing a metal oxide in the semiconductor layer where the channel is formed are stacked.

[0344] An insulating layer 261 is provided covering the transistor 310, and a conductive layer 251 is provided on the insulating layer 261. An insulating layer 262 is provided covering the conductive layer 251, and a conductive layer 252 is provided on the insulating layer 262. The conductive layers 251 and 252 each function as wiring. An insulating layer 263 and an insulating layer 332 are provided covering the conductive layer 252, and a transistor 320 is provided on the insulating layer 332. An insulating layer 265 is provided covering the transistor 320, and a capacitor 240 is provided on the insulating layer 265. The capacitor 240 and the transistor 320 are electrically connected by a plug 274.

[0345] Transistor 320 can be used as a transistor constituting a pixel circuit or a transistor constituting a memory cell. Transistor 310 can be used as a transistor constituting a memory cell, a transistor constituting a drive circuit for driving the pixel circuit, or a transistor constituting an arithmetic circuit. Transistors 310 and 320 can also be used as transistors constituting various circuits such as arithmetic circuits or memory circuits.

[0346] The transistor 310 is a transistor having a channel formation region in the substrate 301. The substrate 301 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 310 comprises a portion of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region of the substrate 301 doped with impurities and functions as either a source or a drain. The insulating layer 314 covers the side surface of the conductive layer 311 and functions as an insulating layer.

[0347] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

[0348] Transistor 320 is a transistor in which a metal oxide (also called an oxide semiconductor) is applied to the semiconductor layer where the channel is formed.

[0349] The transistor 320 has a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a pair of conductive layers 325, an insulating layer 326, and a conductive layer 327.

[0350] The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320, and prevents oxygen from detaching from the semiconductor layer 321 to the insulating layer 332. As the insulating layer 332, for example, a film that is less susceptible to hydrogen or oxygen diffusion than a silicon oxide film can be used, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0351] A conductive layer 327 is provided on an insulating layer 332, and an insulating layer 326 is provided covering the conductive layer 327. The conductive layer 327 functions as the first gate electrode of the transistor 320, and a portion of the insulating layer 326 functions as the first gate insulating layer. It is preferable to use an oxide insulating film, such as a silicon oxide film, for at least the portion of the insulating layer 326 that is in contact with the semiconductor layer 321. It is preferable that the upper surface of the insulating layer 326 is flattened.

[0352] The semiconductor layer 321 is provided on the insulating layer 326. Preferably, the semiconductor layer 321 has a metal oxide (also called an oxide semiconductor) film having semiconductor properties. Preferably, the semiconductor layer 321 uses a metal oxide containing at least one of indium, element M (where element M is aluminum, gallium, yttrium, or tin), and zinc. OS transistors using such metal oxides in the channel formation region have the characteristic of having a very low off-current. Therefore, using an OS transistor as a transistor provided in a pixel circuit is preferable because it can retain analog data written to the pixel circuit for a long period of time. Similarly, using an OS transistor as a transistor used in a memory cell is preferable because it can retain analog data written to the memory cell for a long period of time.

[0353] A pair of conductive layers 325 are provided in contact with the semiconductor layer 321 and function as source and drain electrodes.

[0354] Furthermore, an insulating layer 328 is provided covering the top and side surfaces of the pair of conductive layers 325, as well as the side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided on the insulating layer 328. The insulating layer 328 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the semiconductor layer 321 from the insulating layer 264, etc., and to prevent oxygen from detaching from the semiconductor layer 321. As the insulating layer 328, an insulating film similar to that of the insulating layer 332 can be used.

[0355] An opening is provided in the insulating layer 328 and the insulating layer 264 that reaches the semiconductor layer 321. Inside this opening, the insulating layer 323 and the conductive layer 324 are embedded, in contact with the sides of the insulating layer 264, the insulating layer 328, and the conductive layer 325, as well as the upper surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0356] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are flattened so that their heights are roughly the same, and the insulating layer 329 and insulating layer 265 are provided covering them.

[0357] Insulating layers 264 and 265 function as interlayer insulating layers. Insulating layer 329 functions as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 320 from insulating layer 265, etc. As insulating layer 329, an insulating film similar to that used for insulating layers 328 and 332 can be used.

[0358] A plug 274, which is electrically connected to one of the pair of conductive layers 325, is provided so as to be embedded in the insulating layer 265, insulating layer 329, and insulating layer 264.

[0359] Capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located between them. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as the dielectric of the capacitor 240.

[0360] The conductive layer 245 is provided on the insulating layer 265 and embedded in the insulating layer 254. The conductive layer 245 is electrically connected to either the source or drain of the transistor 320 by plugs 274 embedded in the insulating layers 328, 264, 329, and 265. The insulating layer 243 is provided covering the conductive layer 245. The conductive layer 241 is provided in the region that overlaps with the conductive layer 245 via the insulating layer 243.

[0361] An insulating layer 255 is provided covering the capacitance 240, and a light-emitting element 61 and a light-receiving element 62 are provided on the insulating layer 255. A protective layer 91 is provided on the light-emitting element 61 and the light-receiving element 62, and a substrate 420 is bonded to the upper surface of the protective layer 91 by a resin layer 419. A light-transmitting substrate can be used for the substrate 420.

[0362] The pixel electrode 84 of the light-emitting element 61 and the pixel electrode 84PD of the light-receiving element 62 are electrically connected to either the source or drain of the transistor 320 by a plug 256 embedded in the insulating layer 255, a conductive layer 245 embedded in the insulating layer 254, and a plug 274 embedded in the insulating layers 328, 264, 329, and 265.

[0363] This configuration allows for the placement of OS transistors constituting pixel circuits and memory cells directly beneath the light-receiving and light-emitting elements, as well as the placement of drive circuits and arithmetic circuits, making it possible to miniaturize a high-performance display device.

[0364] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0365] <Notes regarding the description in this specification, etc.> The above embodiments and a description of each component in those embodiments are provided below.

[0366] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0367] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0368] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0369] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0370] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

[0371] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0372] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the context.

[0373] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0374] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0375] In this specification, terms such as "film" and "layer" may be interchanged depending on the context or situation. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0376] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0377] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0378] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0379] In this specification, "A and B are connected" includes not only those that are directly connected, but also those that are electrically connected. Here, "electrically connected" means that when there is an object between A and B that has some kind of electrical effect, it enables the exchange of electrical signals between A and B.

[0380] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. In addition, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0381] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting element (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting element capable of emitting white light may be referred to as a white light-emitting element. A white light-emitting element can be combined with a colored layer (for example, a color filter) to create a light-emitting element capable of full-color display.

[0382] Furthermore, light-emitting elements can be broadly classified into single structures and tandem structures. A single-structure element has one light-emitting unit between a pair of electrodes, and it is preferable that this light-emitting unit includes one or more light-emitting layers. To obtain white light emission, one should select light-emitting layers such that the light emitted from each of the two or more layers is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. The same applies to light-emitting elements having three or more light-emitting layers.

[0383] In a tandem structure, it is preferable that the element has two or more light-emitting units between a pair of electrodes, and each light-emitting unit includes one or more light-emitting layers. To obtain white light emission, the light from the light-emitting layers of the multiple light-emitting units is combined to produce white light emission. The configuration for obtaining white light emission is the same as that for a single structure. In a tandem structure, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0384] Furthermore, when comparing the aforementioned white light-emitting elements (single or tandem structure) with SBS structure light-emitting elements, SBS structure light-emitting elements can consume less power than white light-emitting elements. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting elements. On the other hand, white light-emitting elements are preferable because their manufacturing process is simpler than that of SBS structure light-emitting elements, which can lead to lower manufacturing costs or higher manufacturing yields. [Explanation of symbols]

[0385] 10_L Display device 10_R Display device 101 cabinets 102 Eyes 11 circuit boards 12 circuit boards 13 Display section 14 Light receiving part 15 Terminal section 61 Light-emitting element 62 Photodetector

Claims

1. The device has a housing and a display device, the display device having a first layer, a second layer, and a third layer; the first layer, the second layer, and the third layer are provided on different layers, the first layer includes a driving circuit and an arithmetic circuit; the second layer includes a pixel circuit and a cell array; the third layer having a light receiving device and a light emitting device; the pixel circuit has a function of controlling light emission of the light-emitting device, the drive circuit has a function of controlling the pixel circuit, a light receiving section in which the light receiving device is arranged is disposed so as to surround a display section in which the light emitting device is arranged, in a plan view; the arithmetic circuit has a function of performing arithmetic processing based on first data corresponding to a current output by the light receiving device and second data corresponding to a potential held in the cell array; the housing has a function of disposing the display device at a position where the display device can capture an image of a user's eye; The light receiving device is an electronic device having the function of capturing an image of the user's eye and / or the area around the eye.

2. In claim 1, the first layer includes a first transistor having a semiconductor layer having silicon in a channel formation region; The second layer includes a second transistor having a semiconductor layer having a metal oxide in a channel formation region.

3. In claim 2, The electronic device, wherein the metal oxide comprises In, an element M (wherein M is Al, Ga, Y, or Sn), and Zn.

4. In any one of claims 1 to 3, the light receiving device comprises an organic light emitting diode; The electronic device, wherein the light emitting device is an organic electroluminescence device.

5. In claim 4, The electronic device, wherein the light emitting device and the light receiving device are separated by a photolithographic method.

6. In any one of claims 1 to 5, The electronic device, wherein the housing includes a mounting portion and a pair of lenses.

Images