Dual mode average power tracking (APT) controller

Abstract

To provide a dual mode average power tracking (APT) controller.SOLUTION: A dual mode average power tracking (APT) controller operates in a first mode to move the control voltage quickly without concern for ripple or ringing. When this coarse adjustment takes control voltage to within a desired margin of a target, the controller may switch to a second mode, where the APT controller more slowly approaches the target, but has reduced ringing or ripples. The mode is changed by changing a resistance value and a capacitance value in a loop filter within an APT circuit. In a further aspect, a pulse shaper circuit may inject a pulse to force the control voltage to change more rapidly. By switching modes in this fashion, the control voltage may quickly reach the desired target, and then remain in the second mode during a transmission time slot such that the control voltage is clean throughout.SELECTED DRAWING: Figure 3

Description

Technical Field

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[0001] The technology of the present disclosure generally relates to average power tracking (APT) in wireless communication devices.

Background Art

[0002] Mobile communication devices are becoming increasingly common in today's society. The spread of these mobile communication devices is driven in part by the many functions currently enabled by such devices. The increase in processing power in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0003] The redefined user experience requires higher data rates provided by wireless communication technologies such as Wi-Fi, Long-Term Evolution (LTE), and 5th Generation New Radio (5G-NR). Partly due to the frequencies at which 5G-NR operates, 5G-NR implements a strict power control scheme with frequent changes in transmission power levels. Frequent changes in transmission power levels, in turn, require the ability to rapidly change the output of the power amplifier array, which is typically done through some form of envelope tracking (ET) or average power tracking (APT). Even with ET and APT approaches, frequent power level changes necessarily result in frequent changes to the control signals sent to the power amplifier array.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventional approaches to rapid changes in control signals generated by ET and APT circuits involve changing the size of capacitors and inductors within the control circuit, specifically reducing their size, which generally results in faster control signal changes. However, reducing the size of capacitors and inductors can introduce unwanted ripple into the control signal. Therefore, improvements in control techniques are warranted. [Means for solving the problem]

[0005] Embodiments disclosed in the detailed description include a dual-mode averaged power tracking (APT) controller. In a first mode, the APT controller operates to rapidly move the control voltage without concerns of ripple or ringing. This coarse adjustment allows the controller to switch to a second mode when the control voltage is within a desired margin of the target, in which case the APT controller gradually approaches the target but with reduced ringing or ripple. The mode is changed by varying the resistance and capacitance values ​​of the loop filter in the APT circuit. In a further embodiment, a pulse shaper circuit may inject pulses to change the control voltage more rapidly. By switching modes in this way, the control voltage can rapidly reach a desired target and then maintain the second mode during the transmit time slot so that the control voltage remains clean throughout.

[0006] In one embodiment, an APT circuit is disclosed. The APT circuit comprises a digital-to-analog converter (DAC) having a change signal output and a target control voltage signal output. The APT circuit also comprises a transition management circuit having a mode output coupled to the change signal output and configured to provide a mode signal. The APT circuit also comprises a loop filter coupled to the target control voltage signal output and the mode output. A change in the mode signal causes the loop filter to switch between a first mode and a second mode, and the loop filter is configured to provide a signal. The APT circuit also comprises an output circuit mechanism configured to provide a voltage control signal based on the signal from the loop filter.

[0007] Those skilled in the art will recognize the scope of this disclosure and, after reading the following detailed description in conjunction with the accompanying drawings, will be able to understand additional embodiments thereof.

[0008] The accompanying drawings incorporated herein and forming part thereof serve to illustrate some aspects of the present disclosure and, together with the description, to illustrate the principles of the present disclosure. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram of a conventional average power tracking (APT) circuit. [Figure 2A] The control signals and frequency responses of a traditional APT circuit are shown. [Figure 2B] This shows the control signal and frequency response of an accelerated traditional APT circuit. [Figure 3] This is a block diagram of a dual-mode APT circuit according to an exemplary embodiment of the present disclosure. [Figure 4] Figure 3 shows the control signal and frequency response of the APT circuit. [Figure 5] This is a signal-to-time graph showing a comparison between the control signal of a dual-mode APT circuit and the control signal of a conventional APT circuit. [Figure 6]This is a block diagram of a dual-mode APT circuit having a pulse shaping circuit added according to an exemplary embodiment of the present disclosure. [Figure 7A] This is a schematic diagram of an exemplary loop filter circuit having variable resistors and capacitances modified according to a mode in an exemplary aspect of the present disclosure. [Figure 7B] This is a schematic diagram of an exemplary loop filter having a plurality of resistors and capacitors, along with switches for selecting between them, according to the exemplary modes of the present disclosure. [Modes for carrying out the invention]

[0010] The embodiments described below represent the information necessary to enable those skilled in the art to carry out the embodiments and illustrate the best mode for carrying out the embodiments. By reading the following description in reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize the applications of these concepts that are not specifically addressed herein. It should be understood that these concepts and applications are within the scope of this disclosure and the accompanying claims.

[0011] Terms such as "first," "second," etc., may be used herein to describe various elements, but it will be understood that these elements are not limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, it is possible to refer to the first element as the second element, and similarly, the second element as the first element. Where used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items.

[0012] When an element such as a layer, region, or substrate is described as being "on" or "extending onto" another element, it will be understood that it may be directly on the other element, or it may extend directly onto the other element, or there may be an intervening element. In contrast, when an element is described as being "directly on" or "extending directly onto" another element, there is no intervening element. Similarly, when an element such as a layer, region, or substrate is described as being "over" or "extending over" another element, it will be understood that it may be directly on the other element, or it may extend directly onto the other element, or there may be an intervening element. In contrast, when an element is described as being "directly over" or "extending directly over" another element, there is no intervening element. When an element is said to be "connected" or "joined" to another element, it should be understood that it may be directly connected to or joined to the other element, or there may be an intermediary element. In contrast, when an element is said to be "directly connected" or "directly joined" to another element, there is no intermediary element.

[0013] Relative terms such as “downward,” “upward,” “upper,” “lower,” “horizontal,” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another, as illustrated in the figures. It will be understood that these terms, and those discussed above, are intended to encompass various orientations of the device, in addition to the orientation depicted in the figures.

[0014] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context otherwise explicitly indicates. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” identify the presence of the described features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0015] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to the extent of this disclosure. Terms used herein are to be construed as having their meanings consistent with their meanings in the context of this specification and related art, and it will be further understood that they are not to be construed in an idealized or overly formal sense unless expressly defined herein.

[0016] Embodiments disclosed in the detailed description include a dual-mode averaged power tracking (APT) controller. In a first mode, the APT controller operates to rapidly move the control voltage without concerns of ripple or ringing. This coarse adjustment allows the controller to switch to a second mode when the control voltage is within a desired margin of the target, in which case the APT controller gradually approaches the target but with reduced ringing or ripple. The mode is changed by varying the resistance and capacitance values ​​of the loop filter in the APT circuit. In a further embodiment, a pulse shaper circuit may inject pulses to change the control voltage more rapidly. By switching modes in this way, the control voltage can rapidly reach a desired target and then maintain the second mode during the transmit time slot so that the control voltage remains clean throughout.

[0017] In this regard, Figure 1 illustrates a block diagram of a conventional APT circuit 10. The APT circuit 10 includes a digital-to-analog converter (DAC) 12. The DAC 12 includes an input 14 (which may be a pin or node as is well understood) that receives a digital signal 16 from an envelope tracking (ET) circuit (not shown). The DAC 12 converts the digital signal 16 into an analog target control voltage signal 18. An adder 20 adds the target control voltage signal 18 to an inverting (negative) feedback signal 22. The adder 20 is coupled to a loop filter 24. The loop filter 24 may also include a controller (not shown) and / or an error amplifier (not shown). The signal 26 from the adder 20 is filtered by the loop filter 24 to produce a signal 28. The signal 28 is provided to a switch control circuit 30 that turns on and off the switches of a switch array circuit 32 based on the signal 28. The switch control circuit 30 represents the function of controlling the output of the switch array circuit 32 by sequence-processing the closing of various power supply switches of the switch array circuit 32. In an exemplary embodiment, the switch control circuit 30 may be a pulse-width modulation (PWM) modulator. The output of the switch array circuit 32 is filtered by an inductor 34 and a capacitor 36 to provide a voltage control signal 38 (also referred to as Vcc) used to control a power amplifier in a transmitter (not shown). The voltage control signal 38 is also supplied to a feedback circuit 40, which provides a feedback signal 22 to an adder 20.

[0018] New mobile phone standards such as 5G have changed the RF output power control scheme so that power changes are more frequent, especially when compared to previous mobile phone standards. For example, 5G-NR can cause a power change within 8.3 microseconds (μs) at a subcarrier spacing (SCS) of 120 kilohertz (kHz). As a result, the voltage of the power amplifier must settle very quickly when there is a change in the power level. In the case of APT, Vcc is only supposed to change when the power supply is required to change, and such a fast transition is difficult while having a stable Vcc during an invariant slot.

[0019] In a conventional system, assuming "ideal" control of the switches of the switch array circuit 32 for a given load, the limit of how fast Vcc can change is the combined capacitance of the capacitor 36 and the rate of charging of the capacitor (i.e., how quickly current can be "poured" into the capacitor 36). The charging rate is a function of the inductor 34, and as the inductance of the inductor 34 decreases, the rate increases. Further, the greater the voltage across the inductor 34, the higher the rate of change of the current. Using a traditional system, as seen in Figure 2A, slow settling can result, and the graph 50 shows that Vcc requires a time Tsettle to reach the lower threshold 52 and even more time to reach the final target level 54. The slow approach to the final target level 54 results in relatively low ringing in the frequency domain, as indicated by the spur 56.

[0020] One approach to obtaining a high-speed APT transition is to reduce the inductance and capacitance of inductor 34 and capacitor 36. However, reducing these values increases ripple or ringing at harmonics. Using this approach results in the graph 60 shown in FIG. 2B, where Vcc reaches the lower threshold 62 relatively quickly, as indicated by a small Tsettle, but has a ripple 64 before settling to the final target level 66. Also, there is significant ringing as shown by spur 68. The presence of this ripple necessitates increasing the switching frequency to limit the ripple. The net result of this approach is to adversely affect the noise performance and efficiency, so this solution is not commercially practical for 5G-NR.

[0021] Exemplary aspects of the present disclosure employ a two-mode approach, using a first high-speed mode, but a circuit prone to inducing ringing or ripple, to perform a coarse adjustment to rapidly change Vcc to a value within a predefined threshold of the target Vcc value, and using a second low-speed mode to change Vcc to the final target Vcc value and provide a clean, non-ringing, but relatively slow fine adjustment to Vcc to hold Vcc cleanly at this final target over a desired duration (e.g., in a "slot"). To switch modes, the loop filter circuit is changed. Specifically contemplated aspects include changing the resistance(s) and / or capacitance(s) within the loop filter. In a further aspect, a pulse shaper circuit can be used to inject a hard pulse form to assist in changing the input to the switch control circuit to the desired target value.

[0022] In this regard, Figure 3 illustrates an APT circuit 80 including a DAC 82. The DAC 82 includes an input 84 (which may be a pin or node as is well understood) that receives a digital signal 86 from an ET circuit (not shown). The DAC 82 converts the digital signal 86 into an analog target control voltage signal 88 at a target control voltage signal output 89 (which may be a pin or node). An adder 90 (equivalently an adder circuit) adds the target control voltage signal 88 to an inverting (negative) feedback signal 92. The adder 90 is coupled to a loop filter 94, which is therefore indirectly coupled to the target control voltage signal output 89. The loop filter 94 may also include a controller (not shown) and / or an error amplifier (not shown). The signal 96 from the adder 90 is filtered by the loop filter 94 to produce a signal 98. The signal 98 is provided to a switch control circuit 100 that turns on and off the switches of a switch array circuit 102 based on the signal 98. The switch control circuit 100 represents the function of controlling the output of the switch array circuit 102 by sequence-processing the closing of various power supply switches of the switch array circuit 102. In exemplary embodiments, the switch control circuit 100 may be a PWM modulator. The output of the switch array circuit 102 is filtered by an inductor 104 and a capacitor 106 to provide a voltage control signal 108 (also referred to as Vcc) to an output 109 (which may be a pin or node). The voltage control signal 108 is used to control the power amplifier of a transmitter (not shown). The voltage control signal 108 is also supplied to a feedback circuit 110, which provides a feedback signal 92 to an adder 90. Collectively, the switch control circuit 100, the switch array circuit 102, and the filter formed by the inductor 104 and the capacitor 106 can be considered as an output circuit mechanism configured to provide the voltage control signal 108 based on the signal 98 at output 109. The components of the output circuit mechanism may vary without departing from the scope of this disclosure.

[0023] Continuing to refer to Figure 3, the DAC82 also includes a change signal output 112 (which may be a pin or node) that provides a signal 114 indicating a change in the state of the DAC82. In an exemplary embodiment, the signal 114 is generated whenever there is a change in the state of the DAC82. Alternatively, the signal 114 may be generated only when the change in state exceeds a predefined threshold. The signal 114 may contain information not only about the presence of a change in state, but also about the magnitude and direction of the change. A change in the state of the DAC82 indicates a required change in the voltage control signal 108, and therefore, small changes required in the voltage control signal 108 may not require the implementation of the fast mode of this disclosure.

[0024] The transition management circuit 116 is coupled to the change signal output 112 to receive the signal 114. The transition management circuit 116 is configured to provide a mode signal 118 to the loop filter 94. Based on the mode signal 118, the loop filter 94 can change between a first mode (i.e., fast mode) and a second mode (i.e., slow mode). Figure 4 illustrates the difference between modes. Specifically, graph 130 shows that Vcc rises rapidly in the first mode 132 until it reaches a threshold 134, at which point the mode signal 118 changes the loop filter 94 to the second mode 136, which allows Vcc to settle slowly to the target value 138 with virtually no ripple and little to no ringing 142, as shown by the spectral graph 140.

[0025] Exemplary test results comparing the dual-mode approach of this disclosure with a conventional system are shown in Graph 150 of Figure 5, where the first mode 132 lasts for approximately 65.25 μs–66 μs (or about 0.75 μs), after which the second mode 136 begins. Vcc 152 reaches a zone close to the target Vcc value much faster than the Vcc baseline 154 of the conventional approach. Signal 114 from DAC82 is also included to show the transition in response to changes in DAC82.

[0026] Figure 6 provides an alternative configuration in which a pulse shaping circuit 160 is added to the APT circuit 80'. The pulse shaping circuit 160 is coupled to an adder 162 (equivalently an adder circuit or a second adder circuit) located between the loop filter 94 and the switch control circuit 100. The pulse shaping circuit 160 can facilitate a faster change in Vcc by injecting a voltage spur or other pulse signal 164 (positive or negative) through the adder 162.

[0027] In exemplary embodiments, the pulse shaping circuit 160 is controlled by the transition management circuit 116 and may have a programmable duration. That is, the height and / or length of the injected pulse can vary. The programmable duration may be a function of the battery voltage and / or voltage step change. For example, if there is a relatively small voltage step change of 1 volt (1V), a pulse smaller (in magnitude and / or duration) may be applied than if there were a relatively large step change of 3 volts (3V).

[0028] The loop filter 94 can take any number of forms, including, for example, type I, II, or III loop filters, but most such filters include one or more resistors and one or more capacitors. Exemplary embodiments of the present disclosure vary these resistors and capacitances to change between a first mode and a second mode. In the first exemplary embodiment, a variable resistor is used, as illustrated in Figure 7A. In the second exemplary embodiment, a switch is used to switch between resistors and / or capacitors having different values, as shown in Figure 7B.

[0029] In this regard, Figure 7A illustrates a loop filter 94A having variable capacitors 180(1) to 180(N) and variable resistors 182(2) to 182(N). A mode signal 118 changes the values ​​of the variable elements.

[0030] Similarly, Figure 7B illustrates a loop filter 94B having switches 190(1) to 190(N) that can be used to switch between different capacitances and resistances. Note that, as illustrated, switch 190(N) allows switching only the resistances, while the capacitances associated with them remain constant. Other switching configurations are possible. Similar to loop filter 94A, a mode signal 118 opens and closes switches 190(1) to 190(N) to switch between a first mode and a second mode.

[0031] Those skilled in the art will recognize improvements and modifications to embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the following claims.

Claims

1. 1. An average power tracking (APT) circuit, comprising:

1. A digital-to-analog converter (DAC), comprising: A changing signal output, and a DAC having a target control voltage signal output; a transition management circuit comprising a mode output coupled to the change signal output and configured to provide a mode signal; a loop filter coupled to the target control voltage signal output and to the mode output, the loop filter configured to provide a signal such that a change in the mode signal causes the loop filter to switch between a first mode and a second mode, the first mode comprising a fast mode and the second mode comprising a slow mode, the fast mode changing the signal faster than the slow mode; output circuitry configured to provide a voltage control signal based on the signal from the loop filter; The APT circuit comprises:

2. the output circuitry comprising: a switch control circuit coupled to the loop filter and the transition management circuit, the switch control circuit configured to receive the signal from the loop filter; a switch array circuit comprising a plurality of power supply switches coupled to the switch control circuit, the switch control circuit configured to control which of the plurality of power supply switches are open and which are closed based on the signal; The APT circuit of claim 1 .

3. a summer circuit disposed between the DAC and the loop filter; a feedback circuit coupled to the adder circuit; The APT circuit of claim 1 further comprising:

4. 2. The APT circuit of claim 1, further comprising a pulse shaper circuit coupled to said transition management circuit and to said target control voltage signal output.

5. 5. The APT circuit of claim 4, further comprising a second summer circuit coupled to the loop filter and the pulse shaper circuit, the pulse shaper circuit configured to provide a pulse signal that is added to the signal from the loop filter by the second summer circuit.

6. An average power tracking (APT) circuit, comprising:

1. A digital-to-analog converter (DAC), comprising: A changing signal output, and a DAC having a target control voltage signal output; a transition management circuit comprising a mode output coupled to the change signal output and configured to provide a mode signal; a loop filter coupled to the target control voltage signal output and to the mode output, the loop filter being configured to switch between a first mode and a second mode in response to a change in the mode signal, the loop filter being configured to provide a signal; output circuitry configured to provide a voltage control signal based on the signal from the loop filter; The APT circuit comprises:

7. 2. The APT circuit of claim 1, wherein the loop filter is configured to operate with a first resistance in the first mode and with a second resistance in the second mode, the first resistance not equal to the second resistance.

8. 2. The APT circuit of claim 1, wherein the loop filter is configured to operate with a first capacitance in the first mode and with a second capacitance in the second mode, the first capacitance not equal to the second capacitance.

9. The APT circuit of claim 1 , wherein the loop filter comprises at least one variable resistor.

10. The APT circuit of claim 1 , wherein the loop filter comprises at least one variable capacitor.

11. 2. The APT circuit of claim 1, wherein the loop filter comprises at least two resistors and a switch configured to connect one or the other of the at least two resistors based on the signal.

12. 2. The APT circuit of claim 1, wherein the loop filter comprises at least two capacitors and a switch configured to connect one or the other of the at least two capacitors based on the signal.

13. 2. The APT circuit of claim 1, wherein the transition management circuit is configured to change modes using the mode signal from the first mode to the second mode after approximately one microsecond (1 μs) in the first mode.

14. 2. The APT circuit of claim 1, wherein the transition management circuit is configured to change modes using the mode signal from the first mode to the second mode approximately four microseconds (4 μs) prior to the first mode.

15. 2. The APT circuit of claim 1, wherein the DAC further comprises an input configured to receive a digital target voltage signal, the DAC configured to provide a changing signal at the changing signal output when the digital target voltage signal changes.

16. 2. The APT circuit of claim 1, wherein the DAC further comprises an input configured to receive a digital target voltage signal, the DAC configured to provide a change signal at the change signal output when the digital target voltage signal changes beyond a predefined threshold.

17. The APT circuit of claim 4 , wherein the pulse shaper circuit is configured to have a programmable duration.

18. 20. The APT circuit of claim 17, wherein the programmable duration is a function of battery voltage.

19. 20. The APT circuit of claim 17, wherein the programmable duration is a function of a voltage step change.

20. An average power tracking (APT) circuit, comprising:

1. A digital-to-analog converter (DAC), comprising: A changing signal output, and a DAC having a target control voltage signal output; a transition management circuit comprising a mode output coupled to the change signal output and configured to provide a mode signal; a loop filter coupled to the target control voltage signal output and to the mode output, the loop filter being configured to switch between a first mode and a second mode in response to a change in the mode signal, the loop filter being configured to provide a signal; output circuitry configured to provide a voltage control signal based on the signal from the loop filter; Equipped with the output circuitry comprising: a switch control circuit coupled to the loop filter and the transition management circuit, the switch control circuit configured to receive the signal from the loop filter; a switch array circuit comprising a plurality of power supply switches coupled to the switch control circuit, the switch control circuit configured to control which of the plurality of power supply switches are open and which are closed based on the signal; Equipped with APT circuit.

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