Power amplifier, package module and wireless device

Abstract

To provide a power amplifier that can reduce gain variation against temperature variation.SOLUTION: A power amplifier 100 includes an amplifier transistor Q1 including an input node and an output node. A signal in the input node has a first power level. An amplification signal in the output node has an input stage with a second power level. The power amplifier further includes a bias circuit 113 that sends a bias signal to the amplifier transistor, and a feedback circuit that couples the output node of the amplifier transistor Q1 to the input node of the amplifier transistor. The feedback circuit includes a resistor R1 and a capacitance C6 arranged in series. The power amplifier further includes a gain compensation circuit including a variable attenuator 110 and mounted on the input stage so that the second power level is compensated against the temperature variation associated with the power amplifier.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority to U.S. Provisional Application No. 63 / 168,870, entitled "Power Amplification with Reduced Gain Variation," filed on March 31, 2021, the disclosure of which is hereby expressly incorporated by reference in its entirety.

[0002] This disclosure relates to the power amplification of signals such as radio frequency (RF) signals.

Background Art

[0003] In many radio frequency (RF) applications, it is desirable to amplify a signal. In the context of a transmission operation, such signal amplification provides power amplification of the signal, and the power - amplified signal is transmitted from an RF device such as a wireless device.

Summary of the Invention

[0004] According to some implementations, this disclosure relates to a power amplifier including an input stage that includes an amplifier transistor having an input node and an output node, where the signal at the input node has a first power level and the amplified signal at the output node has a second power level. The power amplifier further includes a bias circuit configured to provide a bias signal to the amplifier transistor and a feedback circuit that couples the output node of the amplifier transistor to the input node of the amplifier transistor. The feedback circuit includes a resistor and a capacitance arranged in series. The power amplifier further includes a gain compensation circuit implemented with respect to the input stage such that the second power level is compensated for variations in temperature associated with the power amplifier.

[0005] In some embodiments, the gain compensation circuit may be implemented along the input path to the input node of the amplifying transistor. This allows the gain compensation circuit to adjust a first power level of the signal supplied to the input node of the amplifying transistor based on temperature variations. The gain compensation circuit may include a variable attenuator configured to provide different attenuation values ​​based on a temperature-dependent control signal.

[0006] In some embodiments, the gain compensation circuit may be implemented along the output path from the input node of the amplifying transistor. This allows the gain compensation circuit to adjust the second power level of the amplified signal from the output node of the amplifying transistor based on temperature variations. The gain compensation circuit may include a variable attenuator configured to provide different attenuation values ​​based on a temperature-dependent control signal.

[0007] In some embodiments, a gain compensation circuit may be implemented along a feedback circuit to adjust the gain of the input stage based on temperature variations. The gain compensation circuit may include a variable resistor circuit configured to provide a variable resistance value based on temperature variations. The variable resistance value can provide some or all of the resistance of the feedback circuit. The variable resistor circuit may be configured to provide a number of discontinuous values ​​based on temperature variations.

[0008] In some embodiments, the variable resistor circuit may include a plurality of resistors arranged electrically in parallel with at least one of a plurality of resistors configured to be switchable.

[0009] In some embodiments, the variable resistor circuit may be configured to provide an analog value based on temperature variations. The variable resistor circuit may include a diode resistor circuit controlled by a temperature-dependent control signal. The variable resistor circuit may include a plurality of transistors arranged in series and controlled by a control voltage to provide a variable resistance value based on temperature variations. The control voltage applied to the variable resistor circuit may depend on temperature variations. The plurality of transistors arranged in series may include a plurality of BiHEMT transistors.

[0010] In some embodiments, the gain compensation circuit may include a variable capacitance circuit configured to provide a variable capacitance value based on temperature variations. The variable capacitance value can provide part or all of the capacitance of the feedback circuit. The variable capacitance circuit may be configured to provide a plurality of discontinuous values ​​based on temperature variations. The variable capacitance circuit may include a plurality of capacitances electrically arranged in parallel with at least one capacitance among a plurality of capacitors configured to be switchable.

[0011] In some embodiments, the variable capacitance circuit may be configured to provide an analog value based on temperature variations. The variable capacitance circuit may include a diode capacitance circuit controlled by a temperature-dependent control signal. The variable capacitance circuit includes a plurality of diodes, which are controlled by a control voltage to provide a variable capacitance value based on temperature variations. The control voltage applied to the variable capacitance circuit may depend on temperature variations. The plurality of diodes include a first diode and a second diode, which are arranged such that the anode of the first diode is on the input side of the variable capacitance circuit, the anode of the second diode is on the output side of the variable capacitance circuit, and the cathodes of the first and second diodes are coupled to each other so that a control voltage is applied to the node between the cathodes of the first and second diodes.

[0012] In some embodiments, the power amplifier further includes a second stage configured to further amplify the amplified signal from the input stage. In some embodiments, the second stage may include a first and second amplifying transistors arranged in a cascode configuration.

[0013] In some embodiments, the bias circuit is configured such that the bias signal supplied to the amplifying transistor depends on temperature fluctuations. The bias circuit is configured to utilize a reference current to generate the bias signal, and this reference current depends on temperature fluctuations.

[0014] In some teachings, the disclosure relates to a semiconductor die including a substrate and a power amplifier mounted on the substrate. The power amplifier includes an input stage including an amplifying transistor having an input node and an output node, wherein the signal at the input node has a first power level and the amplified signal at the output node has a second power level. The power amplifier further includes a feedback circuit that couples the output node of the amplifying transistor to the input node of the amplifying transistor. The feedback circuit includes a resistor and a capacitance arranged in series. The power amplifier further includes a gain compensation circuit that is mounted on the input stage such that the second power level is compensated for temperature fluctuations associated with the power amplifier.

[0015] In some embodiments, the power amplifier may further include a bias circuit configured to supply a bias signal to the amplification transistor.

[0016] In some implementation examples, the disclosure relates to a package module comprising a packaging substrate and a semiconductor die mounted on the packaging substrate, which includes a power amplifier. The power amplifier includes an input stage comprising an amplifying transistor having an input node and an output node, wherein the signal at the input node has a first power level and the amplified signal at the output node has a second power level. The power amplifier further includes a feedback circuit coupling the output node of the amplifying transistor to the input node of the amplifying transistor. The feedback circuit includes a resistor and a capacitance arranged in series. The power amplifier further includes a gain compensation circuit implemented with respect to the input stage such that the second power level is compensated for temperature variations associated with the power amplifier.

[0017] In some embodiments, the package module may further include a bias circuit configured to supply a bias signal to an amplifying transistor. In some embodiments, the bias circuit may be mounted on a semiconductor die.

[0018] In some embodiments, the package module may further include one or more passive devices, each generating at least some heat during the operation of the power amplifier. Temperature fluctuations may result from either or both the operation of the power amplifier and the use of the one or more passive devices.

[0019] In some implementation examples, the disclosure relates to a wireless device comprising a transceiver configured to generate a signal and a power amplifier configured to amplify the signal. The power amplifier includes an input stage comprising an amplifying transistor having an input node and an output node, wherein the signal at the input node has a first power level and the amplified signal at the output node has a second power level. The power amplifier further includes a feedback circuit coupling the output node of the amplifying transistor to the input node of the amplifying transistor. The feedback circuit includes a resistor and a capacitance arranged in series. The power amplifier further includes a gain compensation circuit implemented with respect to the input stage such that the second power level is compensated for temperature fluctuations associated with the power amplifier. The wireless device further includes an antenna configured to communicate with the power amplifier and support the transmission of the amplified signal provided by the power amplifier.

[0020] For the purpose of summarizing this disclosure, certain aspects, advantages, and novel features of the present invention have been described herein. It should be understood that not all of such advantages are necessarily achieved according to any particular embodiment of the present invention. That is, the present invention may be embodied or implemented in a manner that achieves or optimizes one or more advantages or groups thereof taught herein, without necessarily achieving other advantages that may be taught or suggested herein. [Brief explanation of the drawing]

[0021] [Figure 1] Draw a block diagram of a radio frequency (RF) module that includes a power amplifier and / or is coupled to a gain compensation circuit. [Figure 2] Show an example of a power amplifier that includes a gain compensation circuit and / or in which a gain compensation circuit is provided. [Figure 3] Show that in some embodiments, the power amplifier of FIG. 2 may include a gain compensation circuit implemented along the input path of a transistor. [Figure 4] Show that in some embodiments, the power amplifier of FIG. 2 may include a gain compensation circuit implemented along the inter-stage path. [Figure 5] Show that in some embodiments, the power amplifier of FIG. 2 may include a gain compensation circuit implemented along a feedback circuit that couples the output of a transistor to the input of the transistor. [Figure 6] Show another example where the power amplifier of FIG. 2 may include a gain compensation circuit implemented along a feedback circuit that couples the output of a transistor to the input of the transistor. [Figure 7] Show an example of a variable attenuator that can be used for a gain compensation circuit in each of the exemplary power amplifiers of FIGS. 3 and 4. [Figures 8A-8C] FIGS. 8A-8C show an example of a variable resistance circuit that can be used for a gain compensation circuit in the exemplary power amplifier of FIG. 5. [Figure 9A-9B] FIGS. 9A and 9B show examples of variable capacitance circuits that can be used for a gain compensation circuit in the exemplary power amplifier of FIG. 6. [Figure 10] Show an example of a gain and linearity plot and how such parameters can change over a certain temperature range. [Figure 11A-11B] FIGS. 11A-11G show various plots related to power amplifier operating conditions, performance, etc. that can be considered for designing a desired configuration of a gain compensation circuit in which the variable capacitance circuit of FIG. 9B is implemented. [Figure 11C-11D]Figures 11A to 11G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable capacitance circuit of FIG. 9B is implemented. [Figure 11E] Figures 11A to 11G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable capacitance circuit of FIG. 9B is implemented. [Figure 11F] Figures 11A to 11G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable capacitance circuit of FIG. 9B is implemented. [Figure 11G] Figures 11A to 11G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable capacitance circuit of FIG. 9B is implemented. [Figure 12A] Figures 12A to 12G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable resistance circuit of FIG. 8C is implemented. [Figure 12B] Figures 12A to 12G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable resistance circuit of FIG. 8C is implemented. [Figures 12C-12D] Figures 12A to 12G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable resistance circuit of FIG. 8C is implemented. [Figure 12E] Figures 12A to 12G show various plots related to power amplifier operating conditions, performance, etc., which can be considered in designing a desired configuration of a gain compensation circuit in which the variable resistance circuit of FIG. 8C is implemented. [Figure 12F]Figures 12A to 12G show various plots related to power amplifier operating conditions, performance, etc., that can be considered in designing a desired configuration of the gain compensation circuit in which the variable resistor circuit of Figure 8C is implemented. [Figure 12G] Figures 12A to 12G show various plots related to power amplifier operating conditions, performance, etc., that can be considered in designing a desired configuration of the gain compensation circuit in which the variable resistor circuit of Figure 8C is implemented. [Figure 13] In some embodiments, the semiconductor die may include one or more amplifiers as described herein. [Figure 14] In some embodiments, we will show that one or more of the features described herein can be implemented in a package module. [Figure 15] An example of a wireless device possessing one or more of the advantageous features described here is shown. [Modes for carrying out the invention]

[0022] The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

[0023] In many electronic applications, such as radio frequency (RF) applications, amplifiers, such as power amplifiers, are mounted on semiconductor dies, which are often attached to modules such as power amplifier modules (PAMs) or front-end modules (FEMs). Such power amplifiers can experience gain variations over a temperature range due to a number of factors. For example, the beta parameter of a power amplifier transistor degrades with increasing temperature, resulting in a loss of gain at high temperatures. In another example, the equivalent series resistance (ESR) of a power amplifier increases (or the quality factor Q decreases) as the temperature rises in passive devices such as matching and / or filter inductors and capacitors, resulting in increased losses at high temperatures. In yet another example, the on-resistance of an RF switch associated with a power amplifier increases with increasing temperature, resulting in increased losses at high temperatures. In yet another example, the losses of RF filters and / or duplexers (e.g., SAW filters, FBAR filters, BAW filters and / or related devices) increase with increasing temperature, resulting in increased losses at high temperatures.

[0024] Each of the exemplary factors described above can contribute to gain variations in the module over a certain temperature range. Such gain variations, when the gain decreases (for example at high temperatures), place an excessive burden on the transmitter / receiver supplying high power to the power amplifier.

[0025] In some situations, a decrease in power amplifier gain due to rising temperature can increase the output power of the transceiver or the input power of the power amplifier. However, such solutions typically require significant calibration and / or increased complexity due to the wide range of power amplifier gain variations across temperature. Furthermore, the transceiver also requires high power requirements to ensure that sufficient power is supplied to the antenna over a certain temperature range.

[0026] In some situations, a temperature compensation circuit can be implemented to supply the appropriate bias current to the power amplifier. However, such a solution may result in a degradation of linearity over a certain temperature range.

[0027] Figure 1 shows a block diagram of a radio frequency (RF) module 120 including a power amplifier 100. In some embodiments, such a power amplifier includes and / or is coupled to a gain compensation circuit 110 having one or more of the features described herein. Several examples of such gain compensation circuits are described herein in detail.

[0028] As shown in Figure 1, the RF module 120 may further include one or more passive components 102, one or more filters 104, and one or more switches 106. As described herein, some or all of such components may cause the temperature of module 120 to rise during operation. Therefore, such a temperature rise may result in a change in the gain of power amplifier 100 (e.g., a decrease in gain).

[0029] Figure 2 shows an example of a power amplifier 100 that includes and / or is provided with a gain compensation circuit (110 in Figure 1). The exemplary power amplifier 100 is shown to include an input node RF_in that receives the signal to be amplified. Such an input node is shown to be coupled to the input of a first-stage amplified transistor Q1 through an input path. The partially amplified signal from the output of Q1 is shown to be coupled to the input of a second-stage amplified transistor Q2 through an interstage path. Transistor Q2 is shown to be coupled to another amplified transistor Q3 in a cascode configuration. As a result, the output of transistor Q3 is coupled to the output node RF_out of the power amplifier 100.

[0030] In the example in Figure 2, amplifiers Q1, Q2, and Q3 are shown to be implemented as bipolar junction transistors having a base, emitter, and collector. That is, Q1 is shown to have a base as input, a collector as output, and an emitter coupled to ground. Q2, shown to be implemented as a common emitter device, is coupled to Q3, which is implemented as a common base device. That is, Q2 has a base as input (coupled to the output of Q1), a collector as output, and an emitter coupled to ground. Q3 has an emitter as input (coupled to the output (collector) of Q2), a collector as output (coupled to the power amplifier output RF_out), and a base coupled to ground via capacitance C5.

[0031] In the example in Figure 2, transistor Q1 is shown to have the supply voltage VCC applied to its collector via a choke inductance L2. It is also understood that the supply voltage may be applied to Q3 through its collector. It is also understood that each of transistors Q1, Q2, and Q3 may be provided with a bias signal for operation through their bases.

[0032] In the example in Figure 2, the input matching circuit is shown to be provided as a T-type circuit having, for example, series capacitances C1 and C2, and an inductance L1 connecting the node between C1 and C2 to ground. The capacitance values ​​of C1 and C2 may be the same or different. Similarly, the interstage matching circuit is shown to be provided as a T-type circuit having, for example, series capacitances C3 and C4, and an inductance L3 connecting the node between C3 and C4 to ground. The capacitance values ​​of C3 and C4 may be the same or different. It should be understood that a power amplifier having one or more of the features described herein may or may not have any of these matching circuits, and such matching circuits may be implemented in other forms (e.g., other than T-type circuits).

[0033] In the example in Figure 2, the feedback circuit is shown to couple the output of Q1 to the input of Q1. In some embodiments, such a feedback circuit may include a resistor R1 and a capacitance C6 arranged in series.

[0034] Figure 2 shows that in several embodiments, a gain compensation circuit (110 in Figure 1) may be implemented in one or more parts of the power amplifier 100. For example, the gain compensation circuit may be implemented along the input path of transistor Q1, and such an example is shown as 111 along the input path (e.g., between the input node RF_in and the input matching circuit). In another example, the gain compensation circuit may be implemented along the interstage path between Q1 and Q2, and such an example is shown as 111 along the interstage path (e.g., between the output of Q1 and the interstage matching circuit). In yet another example, the gain compensation circuit may be implemented along a feedback circuit for Q1, and such an example is shown as 111 along the feedback circuit between the output of Q1 and the input of Q1.

[0035] In the example shown in Figure 2, the power amplifier 100 may include a bias circuit 113 configured to supply a bias signal to the amplification transistor Q1. In some embodiments, such a bias signal may be generated based on a reference current supplied in or to the bias circuit 113. In some embodiments, such a reference current may be supplied at least in part based on the temperature of a module associated with the power amplifier 100.

[0036] In some embodiments, gain compensation for the power amplifier 100 may be based on the gain compensation circuit alone at the mounting location 111, or in combination with temperature-based compensation of the bias signal provided by the bias circuit 113.

[0037] Figure 3 shows that in some embodiments, the power amplifier 100 of Figure 2 may include a gain compensation circuit 110 implemented along the input path of transistor Q1. In some embodiments, such a gain compensation circuit may include, for example, a variable attenuator 110 configured to provide variable attenuation of the input signal received at the input node RF_in. This causes the input signal applied to the input of Q1 to be attenuated by different amounts depending on the temperature of the module associated with the power amplifier 100.

[0038] As can be seen in the example in Figure 3, the variable attenuator 110 may be implemented in situations where design considerations such as little to no impact on the driver stage load line, little to no impact on power addition efficiency, and low input power are desired or present, and where the possibility of noise figure degradation is acceptable or may be acceptable.

[0039] Figure 7 shows an example of a variable attenuator 110 that may be used for the variable attenuator 110 associated with the power amplifier 100 in Figure 3. It is understood that the variable attenuator 110 in Figure 3 may be implemented in a configuration different from the example in Figure 7.

[0040] Figure 4 shows that in some embodiments, the power amplifier 100 of Figure 2 may include a gain compensation circuit 110 implemented along the interstage path between Q1 and Q2. In some embodiments, such a gain compensation circuit may include, for example, a variable attenuator configured to provide variable attenuation of the partially amplified signal provided by Q1. This causes the input signal provided to the input of Q2 to be attenuated by different amounts depending on the temperature of the module associated with the power amplifier 100.

[0041] As can be seen in the example in Figure 4, the variable attenuator 110 may be implemented in situations where a small impact on the noise figure is desired or present, and where factors such as increased supply current (associated with VCC), pull-on driver stage load lines, and high signal power are acceptable or present.

[0042] Figure 7 shows an example of a variable attenuator 110 that may be used for the variable attenuator 110 associated with the power amplifier 100 in Figure 4. It should be understood that the variable attenuator 110 in Figure 4 may be implemented in a different configuration than the example in Figure 7. It should also be understood that the attenuations in Figures 3 and 4 may or may not be configured similarly.

[0043] Figure 5 shows that in some embodiments, the power amplifier 100 of Figure 2 may include a gain compensation circuit 110 implemented along a feedback circuit that couples the output of Q1 to the input of Q1. In the example of Figure 5, the gain compensation circuit 110 is shown to include a variable resistor configured to provide a variable resistance in place of or in addition to the resistor R1 described herein with reference to Figure 2. Thus, in some embodiments, the resistor associated with the feedback circuit may be based on the temperature of the module associated with the power amplifier 100.

[0044] Examples of variable resistors that may be implemented for the gain compensation circuit 110 are shown here with reference to Figures 8A to 8C.

[0045] As can be seen in the example in Figure 5, the variable resistor circuit 110 may be implemented in situations where resistance is dominant in the feedback of Q1, where it is desirable or present that the impact on power addition efficiency be small, and where a high voltage amplitude in the variable resistor circuit 110 is acceptable or present.

[0046] Figure 6 shows that in some embodiments, the power amplifier 100 of Figure 2 may include a gain compensation circuit 110 implemented along a feedback circuit that couples the output of Q1 to the input of Q1. In the example of Figure 6, the gain compensation circuit 110 is shown to include a variable capacitance configured to provide a variable capacitance in place of or in addition to the capacitance C6 described herein with reference to Figure 2. Thus, in some embodiments, the capacitance associated with the feedback circuit may be based on the temperature of the module associated with the power amplifier 100.

[0047] Examples of variable capacitances that may be implemented for the gain compensation circuit 110 are shown here with reference to Figures 9A and 9B.

[0048] As can be seen in the example in Figure 6, the variable resistor circuit 110 may be implemented in situations where capacitance is dominant in the feedback of Q1, where it is desirable or present that the impact on the noise figure be small, and where the possibility of Hartree oscillation in the feedback is acceptable or present.

[0049] Figure 7 shows an example of a variable attenuator 110 that may be used for the gain compensation circuit 110 in the exemplary power amplifier 100 of Figures 3 and 4, respectively. The exemplary variable attenuator 110 in Figure 7 is shown to have a π-type configuration with a series resistor Ra between the input and output nodes and a shunt resistor Rb between each input and output node and ground.

[0050] In some embodiments, some or all of the resistors Ra, Rb, and Rb may be configured to provide different resistance values, for example, based on the control of a switchable resistor, in order to provide different attenuation values ​​between the input and output nodes. In some embodiments, one or more control signals associated with the operation of such a variable attenuator 110 may be based on the temperature of a module associated with the power amplifier 100 in Figures 3 and 4. This ensures that the different attenuation values ​​between the input and output nodes are based on the module temperature.

[0051] Figures 8A to 8C show examples of variable resistor circuits 110 that may be used for the gain compensation circuit 110 in the exemplary power amplifier 100 of Figure 5. In each of the examples in Figures 8A to 8C, each variable resistor circuit 110 is shown to be implemented between input and output nodes. Referring to Figure 5, the input node is coupled to the output of Q1, and the output node is coupled to capacitance C6.

[0052] Figure 8A shows that in some embodiments, the variable resistor circuit 110 may include multiple resistors electrically arranged in parallel between the input and output nodes. At least one of these resistors is switchable to provide multiple overall resistance values ​​between the input and output nodes. For example, in Figure 8A, three resistors Ra, Rb, and Rc are shown arranged electrically in parallel between the input and output nodes. A switch Sb is shown in series with resistor Rb, and a switch Sc is shown in series with resistor Rc. That is, the overall resistance values ​​between the input and output nodes may include values ​​associated with Ra alone (Sb and Sc each open), Ra and Rb in parallel (Sb closed, Sc open), Ra and Rc in parallel (Sb open, Sc closed), and Ra, Rb, and Rc all in parallel (Sb and Sc each closed).

[0053] In the example in Figure 8A, control signals can be applied to control the two exemplary switches Sb and Sc, thereby controlling the overall resistance between the input and output nodes. More specifically, in the exemplary configuration of Figure 8A, the overall resistance decreases when the switches are closed by providing each parallel path. That is, the control signals can be configured to increase or decrease the overall resistance based on the temperature (for example, of the modules associated with each power amplifier).

[0054] As can be seen, the variable resistor circuit 110 in Figure 8A is an example of a circuit that can provide a certain number of resistance values ​​in discontinuous steps. The number of such resistance values ​​and the size of the discontinuous step can be determined by the appropriate selection of the switchable resistor and the value of that resistor. For example, in the example in Figure 8A, two switches (Sb and Sc) are shown to provide four resistance states. In another example, a 4dB compensation range is desired for a power amplifier. In this situation, the four switches in the variable resistor circuit 110 in Figure 8A provide 16 different resistance values, and with these resistance values, a 4dB gain range can be achieved in approximately 0.25dB gain steps.

[0055] In some embodiments, the resistor in the example in Figure 8A can be implemented using a process such as BiHEMT, CMOS, or SOI. In some embodiments, such a resistor device can be implemented on the same die as the corresponding switch, or on a separate die from the switch. In some embodiments, the variable resistor circuit 110 in Figure 8A can be implemented on the same die as the corresponding power amplifier. In some embodiments, the variable resistor circuit 110 in Figure 8A can be implemented on a separate die from the die containing the corresponding power amplifier.

[0056] Figure 8B shows an example of a variable resistor circuit 110 that may be used for the gain compensation circuit 110 in the exemplary power amplifier 100 of Figure 5. In some embodiments, the variable resistor circuit 110 may be configured to provide a diode-based resistor to give analog control of the overall resistance between the input and output nodes. This allows for analog control of the gain compensation for the corresponding power amplifier 100.

[0057] For example, referring to Figure 8B, a diode D can be placed between the input node and the output node such that its anode is on the input side and its cathode is on the output side. Capacitance Ca is shown to exist between the anode of diode D and the input node, and capacitance Cb is shown to exist between the cathode of diode D and the output node. Inductance Lbig is shown to connect the node between diode D and capacitance Cb to ground.

[0058] In the example shown in Figure 8B, a reference current (IREF) is applied to the anode of diode D via resistor R_Feed to control the resistance provided by diode D. More specifically, in the exemplary configuration of Figure 8B, the value of the resistance provided by diode D decreases as the reference current IREF increases. That is, the control signal in the form of IREF can be configured to increase or decrease the resistance based on the temperature (for example, of the module associated with each power amplifier).

[0059] In some embodiments, the diode-based resistor in the example of Figure 8B can be implemented using, for example, an HBT process. In some embodiments, such a diode device may be implemented as a transistor device with capacitance. This capacitance (e.g., Ca and / or Cb) is specific to the transistor device. In some embodiments, the variable resistor circuit 110 in Figure 8B can be implemented on the same die as the corresponding power amplifier (e.g., an HBT power amplifier). In some embodiments, the variable resistor circuit 110 in Figure 8B can be implemented on a separate die from the die containing the corresponding power amplifier.

[0060] Figure 8C shows another example of a variable resistor circuit 110 that may be used for the gain compensation circuit 110 in the exemplary power amplifier 100 of Figure 5. In some embodiments, the variable resistor circuit 110 may be configured to provide a variable BiHEMT resistor to give analog control of the overall resistance between the input and output nodes. This allows for analog control of the gain compensation for the corresponding power amplifier 100.

[0061] For example, referring to Figure 8C, multiple BiHEMT transistors are arranged in series, with a resistor Rb between the source and drain of each transistor. Such an assembly is shown to be implemented between the input and output nodes. A capacitance Ca is shown to be provided between the input node and the first transistor, and a capacitance Cb is shown to be provided between the last transistor and the output node.

[0062] In the example in Figure 8C, the overall resistance between the input and output nodes can be controlled by a control voltage VCTRL applied to the node between capacitance Ca and the first transistor. More specifically, in the exemplary configuration of Figure 8C, the value of the overall resistance provided by the BiHEMT transistor circuit increases as the control voltage VCTRL increases. That is, the control signal in the form of VCTRL can be configured to increase or decrease the resistance based on the temperature (for example, of the module associated with each power amplifier).

[0063] In some embodiments, the BiHEMT transistor-based resistor circuit 110 in the example of Figure 8C can be mounted on the same die as the corresponding power amplifier. In some embodiments, the variable resistor circuit 110 in Figure 8C can be mounted on a separate die from the die containing the corresponding power amplifier.

[0064] Figures 9A and 9B show examples of variable capacitance circuits 110 that may be used for the gain compensation circuit 110 in the exemplary power amplifier 100 of Figure 6. In each example in Figures 9A and 9B, each variable capacitance circuit 110 is shown to be implemented between input and output nodes. Referring to Figure 6, the input node is coupled to resistor R1 and the output node is coupled to the input of Q1.

[0065] Figure 9A shows that in some embodiments, the variable capacitance circuit 110 may include multiple capacitances electrically arranged in parallel between the input and output nodes. At least one of these capacitances can be switched to provide multiple overall capacitance values ​​between the input and output nodes. For example, in Figure 9A, three capacitances Ca, Cb, and Cc are shown arranged electrically in parallel between the input and output nodes. A switch Sb is shown in series with capacitance Cb, and a switch Sc is shown in series with capacitance Cc. That is, the overall capacitance values ​​between the input and output nodes may include values ​​associated with Ca alone (Sb and Sc each open), Ca and Cb in parallel (Sb closed, Sc open), Ca and Cc in parallel (Sb open, Sc closed), and Ca, Cb, and Cc all in parallel (Sb and Sc each closed).

[0066] In the example in Figure 9A, control signals can be applied to control the two exemplary switches Sb and Sc, thereby controlling the overall capacitance between the input and output nodes. More specifically, in the exemplary configuration of Figure 9A, the value of the overall capacitance increases when the switches are closed by providing each parallel path. That is, the control signals can be configured to increase or decrease the overall capacitance based on the temperature (for example, of the modules associated with each power amplifier).

[0067] As can be seen, the variable capacitance circuit 110 in Figure 9A is an example of a circuit that can provide a certain number of capacitance values ​​in discontinuous steps. The number of such capacitance values ​​and the size of the discontinuous step can be determined by the appropriate selection of the switchable capacitance and the value of that capacitance. For example, in the example in Figure 9A, two switches (Sb and Sc) are shown to provide four capacitance states.

[0068] In some embodiments, the variable capacitance circuit 110 in Figure 9A can be mounted on the same die as the corresponding switch, or on a separate die from the switch. In some embodiments, the variable capacitance circuit 110 in Figure 9A can be mounted on the same die as the corresponding power amplifier. In some embodiments, the variable capacitance circuit 110 in Figure 9A can be mounted on a separate die from the die containing the corresponding power amplifier.

[0069] Figure 9B shows an example of a variable capacitance circuit 110 that may be used for the gain compensation circuit 110 in the exemplary power amplifier 100 of Figure 6. In some embodiments, the variable capacitance circuit 110 may be configured to provide diode-based capacitance to give analog control of the overall capacitance between the input and output nodes. This allows for analog control of the gain compensation for the corresponding power amplifier 100.

[0070] For example, referring to Figure 9B, diodes Da and Db can be placed between the input node and the output node such that the anode of diode Da is on the input side, the anode of diode Db is on the output side, and the cathodes of diodes Da and Db are coupled to each other. Capacitance Ca is shown to be present between the anode of diode Da and the input node, and capacitance Cb is shown to be present between the anode of diode Db and the output node. One resistor Rbig is shown to connect the node between diode Da and capacitance Ca to ground, and another resistor Rbig is shown to connect the node between diode Db and capacitance Cb to ground.

[0071] In the example shown in Figure 9B, a control voltage (VCTRL) is applied to the node between the cathodes of diodes Da and Db via resistor Rbig to control the capacitance provided by diodes Da and Db. More specifically, in the exemplary configuration of Figure 9B, the capacitance value provided by diodes Da and Db decreases as the control voltage VCTRL increases. That is, the control signal in the form of VCTRL can be configured to increase or decrease the capacitance based on the temperature (for example, of the module associated with each power amplifier).

[0072] In some embodiments, the diode-based capacitance in the example of Figure 9B can be implemented using, for example, an HBT process. In some embodiments, such a diode device may be implemented as a transistor device with capacitance. The capacitances (e.g., Ca and / or Cb) are specific to the transistor device. In some embodiments, the variable capacitance circuit 110 of Figure 9B can be implemented on the same die as the corresponding power amplifier (e.g., an HBT power amplifier). In some embodiments, the variable capacitance circuit 110 of Figure 9B can be implemented on a separate die from the die containing the corresponding power amplifier.

[0073] Figures 10 to 12 show various plots related to power amplifier operating conditions, performance, etc., which can be taken into consideration in order to design a desired configuration of a gain compensation circuit having one or more of the features described herein.

[0074] Figure 10 shows plots of gain and linearity obtained from simulations, and how these parameters can change over a temperature range. For example, the gain plot in the left panel shows a significant decrease in gain as the operating temperature changes from a low value of -30°C to a room temperature of 25°C and then to a high value of 100°C. Specifically, there is a gain decrease of approximately 1.25 dB when the temperature rises from -30°C to 25°C, and a further gain decrease of approximately 2.5 dB when the temperature rises from 25°C to 100°C. Assuming such a temperature range, the gain compensation circuit can be configured to provide, for example, gain compensation up to 4 dB.

[0075] Figures 11A to 11G show various plots related to power amplifier operating conditions, performance, etc., that can be considered to design a desired configuration of the gain compensation circuit implemented as the variable capacitance circuit 110 in Figure 9B. Such a design configuration may include the exemplary 4dB gain compensation range described with reference to Figure 10.

[0076] Referring to the variable capacitance circuit 110 in Figure 9B, Figure 11A shows a plot of capacitance obtained by varying the control voltage VCTRL from 0V to 4.0V. It can be seen that when VCTRL is varied from 0V to 3.0V, a resulting capacitance range of approximately 40% is obtained (from 0.48pF at VCTRL=0).

[0077] Figure 11B shows the gain and linearity plots for the power amplifier 100 of Figure 6 when the control voltage VCTRL is applied to the variable capacitance circuit 110 of Figure 9B without temperature-dependent adjustment. Similar to the example in Figure 11A, the control voltage VCTRL is adjusted in 0.5V steps from 0V to 3.0V to obtain a certain number of gain and linearity plots.

[0078] As can be seen from the gain plot in the left panel of Figure 11B, the gain of the power amplifier increases as VCTRL increases (and consequently the overall capacitance decreases). Specifically, it is shown that approximately 3 dB of gain compensation is available for an exemplary control voltage range from 0 V to 3.0 V. Note that the same gain control provided by the variable capacitance circuit 110 in Figure 9B applies almost identically to small signals with low output power and large signals with high output power, as should be noted when referring to the region indicated as 130.

[0079] As can be seen from the linearity plot in the right panel of Figure 11B, in the region shown in detail as 132, there is a relatively small shift in the linear power relationship obtained from the variable capacitance circuit 110 of Figure 9B operating in an exemplary control voltage range from 0V to 3.0V.

[0080] Figure 11C shows an example of how the control voltage VCTRL given to the variable capacitance circuit 110 in Figure 9B can be configured to be temperature-dependent (for example, of the module associated with each power amplifier). For example, VCTRL is estimated to be temperature-dependent in a linear manner, extending to an exemplary control voltage range of 0V to 3.0V over an exemplary temperature range of -35°C to 100°C.

[0081] As described with reference to Figure 2, a power amplifier having a gain compensation circuit, such as the variable capacitance circuit 110 in Figure 9B, may include a bias circuit 113. In some embodiments, such a bias circuit may include the function of providing a temperature-compensated bias signal to the corresponding amplifying transistor (e.g., transistor Q1). In some embodiments, such a temperature-compensated bias signal may be based on a temperature-dependent reference current associated with the bias circuit 113.

[0082] Figure 11D shows an example of how the reference current for the bias circuit 113 of the power amplifier 100 in Figure 6 can be configured to be temperature-dependent (for example, of the module associated with each power amplifier). For example, the reference current may be configured to have an approximately constant value when the temperature is 20°C or below, and to increase at a rate of 0.3% per degree Celsius when the temperature exceeds 20°C.

[0083] Figure 11E shows plots of gain and linearity for the power amplifier 100 of Figure 6 when the temperature-compensated control voltage VCTRL of Figure 11C is applied to the variable capacitance circuit 110 of Figure 9B. In the example of Figure 11E, the bias signal provided by the bias circuit 113 is not compensated for temperature (as in the example of Figure 11D). Compared to the gain fluctuation in Figure 11B (where the control voltage VCTRL for the variable capacitance circuit 110 is not temperature-compensated), the gain fluctuation at an output power (POUT) of 29 dBm is reduced from approximately 3.75 dB (Figure 11B) to approximately 1.25 dB (Figure 11E). As can be seen from the linearity plot in the right panel of Figure 11E, there is some degradation in linearity compared to the example of Figure 11B.

[0084] Figure 11F shows plots of gain and linearity for the power amplifier 100 of Figure 6 when the temperature-compensated control voltage VCTRL of Figure 11C is applied to the variable capacitance circuit 110 of Figure 9B. In the example of Figure 11E, the bias signal supplied from the bias circuit 113 is temperature-compensated (i.e., it has a temperature-compensated reference current, as in the example of Figure 11D). Compared to the gain fluctuation in Figure 11E (where the control voltage VCTRL for the variable capacitance circuit 110 is temperature-compensated but the reference current of the bias circuit 113 is not), the gain fluctuation at an output power (POUT) of 29 dBm is further reduced from approximately 1.25 dB (Figure 11E) to approximately 0.25 dB (Figure 11F).

[0085] Figure 11G shows gain and linearity plots for the power amplifier 100 of Figure 6, configured and operating similarly to the example in Figure 11F, except that the temperature changes in 10°C steps over the exemplary range from -30°C to 100°C. Similar to the example in Figure 11F, the gain variation at the exemplary output power of 29 dBm is extremely low, approximately 0.3 dB. Note that there is a relatively small variation in linearity at the exemplary output power of 29 dBm, as should be noted by referring to the region indicated as 134.

[0086] Figures 12A to 12G show various plots related to power amplifier operating conditions, performance, etc., that can be considered in order to design a desired configuration of a gain compensation circuit to be implemented with respect to the variable resistor circuit 110 of Figure 8C. Such a design configuration may include the exemplary 4dB gain compensation range described with reference to Figure 10.

[0087] Referring to the variable resistor circuit 110 in Figure 8C, Figure 12A shows a plot of resistance obtained by varying the control voltage VCTRL from 0V to 0.6V for exemplary temperatures of -30°C, 25°C, and 100°C. In the example in Figure 12A, each resistor Rb in Figure 8C has a value of 10k ohms, and multiple transistors M have the same configuration (one finger has W=50μm and L=0.8μm). For such an exemplary configuration of the variable resistor circuit, Figure 12A shows an example of a useful tuning range 136 that can be used.

[0088] Figure 12B shows plots of gain and linearity for the power amplifier 100 of Figure 5 when different control voltages VCTRL are applied to the variable resistor circuit 110 of Figure 8C at room temperature (without temperature-dependent adjustment). In the example of Figure 12B, the control voltage VCTRL is adjusted in 0.1V steps from 0V to 0.7V to obtain a certain number of gain and linearity plots.

[0089] As can be seen from the gain plot in the left panel of Figure 12B, the gain of the power amplifier increases as VCTRL increases (and consequently as the overall resistance increases). Note that the gain control provided by the variable resistor circuit 110 in Figure 8C applies almost equally to small signals with low output power and large signals with high output power, as should be noted by referring to the region indicated as 138.

[0090] As can be seen from the linearity plot in the right panel of Figure 12B (the region indicated, for example, as 140), there is a certain degree of shift in the linear power relationship obtained when the variable resistor circuit 110 in Figure 8C operates in the exemplary control voltage range from 0V to 0.7V.

[0091] Figure 12C shows an example of how the control voltage VCTRL provided to the variable resistor circuit 110 in Figure 8C can be configured to be temperature-dependent (for example, of the module associated with each power amplifier). For example, VCTRL can be configured to be temperature-dependent in a first linear mode for temperatures below 25°C and in a second linear mode for temperatures above 25°C. Such linear relationships may be based, for example, on VCTRL = 0.265V at -30°C, VCTRL = 0.30V at 25°C, and VCTRL = 0.475V at 100°C.

[0092] As described with reference to Figure 2, a power amplifier having a gain compensation circuit, such as the variable resistor circuit 110 in Figure 8C, may include a bias circuit 113. In some embodiments, such a bias circuit may include the function of providing a temperature-compensated bias signal to the corresponding amplifying transistor (e.g., transistor Q1). In some embodiments, such a temperature-compensated bias signal may be based on a temperature-dependent reference current associated with the bias circuit 113.

[0093] Figure 12D shows an example of how the reference current for the bias circuit 113 of the power amplifier 100 in Figure 5 can be configured to be temperature-dependent (for example, of the module associated with each power amplifier). For example, the reference current may be configured to have an approximately constant value when the temperature is 20°C or higher, and to change at a rate of -0.1% per degree Celsius when the temperature falls below 20°C.

[0094] Figure 12F shows plots of gain and linearity for the power amplifier 100 of Figure 5 when the temperature-compensated control voltage VCTRL of Figure 12C is applied to the variable capacitance circuit 110 of Figure 8C. In the example of Figure 12E, the bias signal provided by the bias circuit 113 is not compensated for temperature (as in the example of Figure 12D). Compared to the gain fluctuation in Figure 12B (where the control voltage VCTRL for the variable capacitance circuit 110 is not temperature-compensated), the gain fluctuation at an output power (POUT) of 29 dBm is reduced from approximately 3.75 dB (Figure 12B) to approximately 0.5 dB (Figure 12E). Also, an AMAM shift is observed at the exemplary temperature of -30°C.

[0095] Figure 12F shows a plot of gain and linearity for the power amplifier 100 of Figure 5 when the temperature-compensated control voltage VCTRL of Figure 12C is applied to the variable resistor circuit 110 of Figure 8C. In the example of Figure 12E, the bias signal provided by the bias circuit 113 is temperature-compensated (i.e., it has a temperature-compensated reference current, as in the example of Figure 12D). (The control voltage VCTRL for the variable resistor circuit 110 is temperature-compensated, but the reference current of the bias circuit 113 is not.) Compared to the gain fluctuation in Figure 12E, the gain fluctuation at an output power (POUT) of 29 dBm is further reduced from approximately 0.5 dB (Figure 12E) to approximately 0.07 dB (Figure 12F).

[0096] Figure 12G shows gain and linearity plots for the power amplifier 100 of Figure 5, configured and operating similarly to the example in Figure 12F, except that the temperature varies in 10°C steps over the exemplary range from -30°C to 100°C. Similar to the example in Figure 12F, the gain variation at the exemplary output power of 29 dBm is extremely low, approximately 0.15 dB.

[0097] As can be seen, power amplifiers having one or more of the features described herein may have very small or virtually zero gain variation over a wide temperature range. This reduces the calibration time and / or power requirements from the transceiver to obtain the desired output power.

[0098] It should be understood that, in some embodiments, one or more features of this disclosure may also be implemented in other types of amplifiers (e.g., other than power amplifiers).

[0099] It should also be understood that while various examples are described in the context of amplifying transistors implemented as bipolar junction transistors, one or more features of this disclosure may also be implemented in amplifiers utilizing other types of amplifying transistors.

[0100] It should also be understood that while the second stage of the amplifier is described as having a cascode configuration, one or more features of this disclosure may also be implemented in an amplifier that utilizes a non-cascode configuration for the second stage.

[0101] Figure 13 shows that in some embodiments, the semiconductor die 300 may include one or more amplifiers 100 described herein. Such amplifiers can be mounted on a semiconductor substrate 302.

[0102] Figure 14 shows that in some embodiments, one or more of the features described herein can be implemented in a package module 400. Such a package module may include a packaging substrate 402 configured to receive a plurality of components. At least some of the components mounted on the packaging substrate 402 may include dies 300 such as one or more of the exemplary dies 300 in Figure 13.

[0103] In some implementations, devices and / or circuits having one or more of the features described herein may be included in RF devices such as wireless devices. Such devices and / or circuits may be implemented directly in the wireless device, in the modular form described herein, or in any combination thereof. In some embodiments, such wireless devices may include, for example, mobile phones, smartphones, handheld wireless devices with or without telephone functionality, wireless tablets, and the like.

[0104] Figure 15 illustrates an example of a wireless device 900 having one or more of the advantageous features described herein. In some embodiments, one or more power amplifiers 916 may include the gain compensation features described herein.

[0105] In the exemplary wireless device 900, a power amplifier (PA) assembly 916 has multiple PAs that can supply one or more amplified RF signals to a switch 920 (via an assembly of one or more duplexers 918). The switch 920 can route the amplified RF signals to one or more antennas. The PA 916 can receive the corresponding amplified RF signals from a transceiver 914 configured and operating in a well-known manner. The transceiver 914 may also be configured to process the received signals. The transceiver 914 is shown to interact with a baseband subsystem 910. The baseband subsystem 910 is configured to provide a conversion between data and / or voice signals appropriate for the user and RF signals appropriate for the transceiver 914. The transceiver 914 is also shown to connect to a power management component 906 configured to manage the power for the operation of the wireless device 900. Such a power management component may also control the operation of the baseband subsystem 910 and module 910.

[0106] The baseband subsystem 910 is shown to be connected to a user interface 902 to facilitate various inputs and outputs of voice and / or data given to and received from the user. The baseband subsystem 910 is also connected to a memory 904 configured to store data and / or instructions in order to facilitate the operation of the wireless device and / or to store information for the user.

[0107] In some embodiments, the duplexer 918 enables simultaneous transmission and reception using a common antenna (e.g., 924). In Figure 15, the received signal is shown to be routed to an "Rx" path which may include, for example, one or more low-noise amplifiers (LNAs).

[0108] A certain number of other wireless device configurations may utilize one or more of the features described herein. For example, the wireless device does not need to be a multiband device. In other examples, the wireless device may include additional antennas such as diversity antennas, as well as additional connectivity features such as Wi-Fi, Bluetooth®, and GPS.

[0109] Unless the context explicitly requires otherwise, throughout the specification and claims, terms such as “includes,” “equip,” and “compris,” should be interpreted in a comprehensive sense, the opposite of an exclusive or exhaustive sense, i.e., “includes but not limited to.” The term “combined,” as used herein, refers to two or more elements that may be directly connected or connected via one or more intermediate elements. In addition, where used in this application, the terms “here,” “above,” “below,” and similar terms refer to the entire application and not to any particular part of it. Where contextually permissible, terms in the above description that use singular or plural numbers may also include plural or singular numbers. The terms “or” and “or,” referring to a list of two or more items, cover all of the following interpretations of the term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0110] The above description of embodiments of the present invention is not intended to be exhaustive or to limit the invention to any specific form of the above disclosure. While specific embodiments and examples of the present invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as will be apparent to those skilled in the art. For example, while processes or blocks are presented in a given order, alternative embodiments may employ systems having routines or blocks with steps in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these processes or blocks may be implemented in various different ways. Furthermore, while processes or blocks may be shown to be executed in series, these processes or blocks may instead be executed in parallel or at different times.

[0111] The teachings of the present invention given herein can be applied to other systems, not necessarily those described above. The elements and operations of the various embodiments described above may be combined to provide further embodiments.

[0112] While certain embodiments of the present invention have been described, these embodiments are presented only as examples and are not intended to limit the scope of this disclosure. In fact, the novel methods and systems described herein may be embodied in various other forms, and various omissions, substitutions, and modifications of the methods and systems described herein may be made without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. 1. A power amplifier comprising: an input stage including an amplifying transistor having an input node and an output node, a signal at the input node having a first power level and an amplified signal at the output node having a second power level; a bias circuit configured to provide a bias signal to the amplifying transistor; a feedback circuit coupling the output node of the amplifier transistor to the input node of the amplifier transistor, the feedback circuit including a resistor and a capacitance arranged in series; a gain compensation circuit implemented along an output path from the output node of the amplifying transistor, the gain compensation circuit adjusting the second power level based on temperature variations associated with the power amplifier; 2. A power amplifier comprising:

2. 2. The power amplifier of claim 1, wherein the gain compensation circuit comprises a variable attenuator configured to provide different attenuation values ​​based on a control signal that depends on the temperature variation.

3. The power amplifier of claim 1, further comprising a second stage configured to amplify the amplified signal from the input stage.

4. A power amplifier as claimed in claim 1, wherein the bias circuit is configured such that a bias signal provided to the amplifying transistor depends on the temperature fluctuations.

5. A power amplifier, an input stage including an amplifying transistor having an input node and an output node, a signal at the input node having a first power level and an amplified signal at the output node having a second power level; a bias circuit configured to provide a bias signal to the amplifying transistor; a feedback circuit coupling the output node of the amplifier transistor to the input node of the amplifier transistor, the feedback circuit including a resistor and a capacitance arranged in series; a gain compensation circuit implemented along the feedback circuit to adjust the gain of the input stage based on temperature variations, the gain compensation circuit including a resistor of the feedback circuit implemented as a variable resistance circuit configured to provide a variable resistance value based on the temperature variations; Including, The variable resistance circuit includes a diode resistance circuit controlled by a control signal that depends on the temperature variation.

6. A power amplifier, an input stage including an amplifying transistor having an input node and an output node, a signal at the input node having a first power level and an amplified signal at the output node having a second power level; a bias circuit configured to provide a bias signal to the amplifying transistor; a feedback circuit coupling the output node of the amplifier transistor to the input node of the amplifier transistor, the feedback circuit including a resistor and a capacitance arranged in series; a gain compensation circuit implemented along the feedback circuit to adjust the gain of the input stage based on temperature variations, the gain compensation circuit including a resistor of the feedback circuit implemented as a variable resistance circuit configured to provide a variable resistance value based on the temperature variations; Including, the variable resistance circuit includes a plurality of transistors arranged in series; The plurality of transistors are controlled by a control voltage to provide the variable resistance value based on variations in temperature.

7. A power amplifier, an input stage including an amplifying transistor having an input node and an output node, a signal at the input node having a first power level and an amplified signal at the output node having a second power level; a bias circuit configured to provide a bias signal to the amplifying transistor; a feedback circuit coupling the output node of the amplifier transistor to the input node of the amplifier transistor, the feedback circuit including a resistor and a capacitance arranged in series; a gain compensation circuit implemented along the feedback circuit for adjusting a gain of the input stage based on variations in temperature, the gain compensation circuit including a capacitance of the feedback circuit implemented as a variable capacitance circuit configured to provide a variable capacitance value based on variations in temperature; Including, The variable capacitance circuit includes a diode capacitance circuit controlled by a control signal that is dependent on the temperature variation.

8. 8. The power amplifier of claim 7, wherein the variable capacitance circuit includes a plurality of diodes controlled by a control voltage to provide the variable capacitance value based on the temperature variation.

9. 9. The power amplifier of claim 8, wherein the control voltage provided to the variable capacitance circuit is dependent on the temperature variations.

10. the plurality of diodes includes a first diode and a second diode; 9. The power amplifier of claim 8, wherein the first diode and the second diode are arranged such that an anode of the first diode is at an input side of the variable capacitance circuit, an anode of the second diode is at an output side of the variable capacitance circuit, and the cathodes of the first diode and the second diode are coupled together such that the control voltage is applied to a node between the cathodes of the first diode and the second diode.

11. A package module, A packaging substrate; a semiconductor die attached to the packaging substrate; Including, the semiconductor die includes a power amplifier; The power amplifier includes an input stage including an amplifying transistor having an input node and an output node; the signal at the input node has a first power level and the amplified signal at the output node has a second power level; the power amplifier further includes a feedback circuit coupling the output node of the amplifying transistor to the input node of the amplifying transistor; The feedback circuit includes a resistor and a capacitance arranged in series; the power amplifier further includes a gain compensation circuit implemented along an output path from the output node of the power amplifier; The gain compensation circuit adjusts the second power level based on a temperature variation associated with the power amplifier.

12. 1. A wireless device, comprising: a transceiver configured to generate a signal; a power amplifier configured to amplify the signal; an antenna configured to communicate with the power amplifier to support transmission of an amplified signal provided by the power amplifier; Including, The power amplifier includes an input stage including an amplifying transistor having an input node and an output node; the signal at the input node has a first power level and the amplified signal at the output node has a second power level; the power amplifier further includes a feedback circuit coupling an output node of the amplifying transistor to an input node of the amplifying transistor; The feedback circuit includes a resistor and a capacitance arranged in series; the power amplifier further includes a gain compensation circuit implemented along an output path from the output node of the amplifying transistor; The gain compensation circuit adjusts the second power level based on a temperature variation associated with the power amplifier.

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