Power semiconductor module

Abstract

To provide a power semiconductor module containing a semiconductor switch for switching at high speed while being connected in parallel.SOLUTION: A power semiconductor module comprises a plurality of semiconductor switches 4 arranged in groups 2 and 3 of at least two semiconductor switches. Each semiconductor switch 4 includes: a first terminal; a second terminal; and a control terminal (a gate terminal 10) in a controlled path. Each of the groups 2 and 3 includes: a first group contact (a source group contact 14) connected to a first terminal; a second group contact (a drain group contact 15) connected to a second terminal; and a control group contact (a gate group contact 13) connected to the control terminal. In addition, a mating connection bridge 6 for connecting at least two control group contacts and the first group contact is provided. The mating connection bridge has a layer structure in which a first conductive layer and a second conductive layer are separated by an insulation layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor module having a plurality of semiconductor switches arranged in at least two groups, the semiconductor switches having a first terminal and a second terminal of a controlled path and a control terminal.

Background Art

[0002] From EP3113223A1, a power semiconductor module is known in which several power semiconductor switches are connected together using separate substrate metallizations arranged in a stacked manner.

Summary of the Invention

Problems to be Solved by the Invention

[0003] In order to reduce the switching losses of a power module, there is the option of using wide-bandgap semiconductors which in principle have a fast switching behavior. However, the use of fast-switching semiconductors poses new challenges to the design of the module. In addition, the area of a typical wide-bandgap semiconductor device is considerably smaller than the area of a modern Si device, so more of them need to be connected in parallel in order to achieve the targeted rated current.

[0004] The object is to provide a power semiconductor module which is a wide-bandgap semiconductor system and includes a large number of semiconductor switches connected in parallel and having a fast switching behavior.

Means for Solving the Problems

[0005] According to one embodiment, this objective is achieved by the following power semiconductor module, which has a plurality of semiconductor switches arranged in at least two groups, each semiconductor switch having a first terminal and a second terminal of a controlled path and a control terminal, each group having a first group contact connected to the first terminal, a second group contact connected to the second terminal, and a control group contact connected to the control terminal, and the power semiconductor module further comprises an interconnection bridge for connecting the control group contacts and the first group contacts of at least two groups, the interconnection bridge including a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer.

[0006] The state of the semiconductor device is controlled by using a voltage applied between the control group contacts and the first group contacts; that is, this voltage switches the state between an open state and a closed state. Therefore, for low-loss operation, it is important to change this voltage rapidly without significant oscillations. The above embodiment has an improved gate connection. Since both conductive layers are located very close together in an interconnect bridge separated only by a very thin insulating layer, a substantial reduction in gate control loop inductance can be achieved compared to conventional wire bond connections between substrates.

[0007] The physical reason for the reduction in inductance is that inductive coupling increases significantly when two conductors are placed in close proximity. The current flowing through the gate connection layer of the interconnect bridge to the gate terminals of the switches in that group primarily charges the capacitance of the gate electrodes. The associated current flows in the opposite direction through the source connection layer of the interconnect bridge. The antiparallel currents and mutual inductive coupling allow for a substantial reduction in gate inductance.

[0008] The proposed embodiment makes it possible to reduce the impact of different lengths on the gate inductance of different semiconductor switch groups, even in power semiconductor modules where the lengths of connection paths to different semiconductor switch groups vary significantly due to the parallel connection of numerous semiconductor switches, thereby achieving better synchronization and less oscillation of the switching behavior. As a result, the switching behavior during the switching period is improved and power loss is reduced.

[0009] Another advantage of the proposed embodiment is that resistors, such as gate resistors directly located within the module and typically used to dampen vibrations between switches, can be omitted or at least reduced. This further improves the switching behavior. When resistors are omitted, a direct connection can be achieved between the module gate contacts and the control terminals of the multiple semiconductor switches, which means there are no electronic components in between.

[0010] Sufficient vibration reduction would at least make it possible to simplify module manufacturing and reduce manufacturing costs by replacing thick-film resistors with readily available semiconductor resistors.

[0011] According to a more detailed embodiment, the layer structure is formed as a "conventional" or flexible printed circuit board. In such embodiments, both sides of the flexible insulating material are covered at least partially with a conductive material such as a metal. The conductive material is preferably copper, aluminum, or an alloy of copper and aluminum.

[0012] According to another embodiment, the layer structure is formed from a ceramic substrate having two-sided metallization. It is preferable that the interconnection bridge has at least two legs on each face, the legs being connected to the group contacts of both groups by soldering, welding, or adhesive connections. In the embodiments described, a MOSFET, MISFET, or IGBT is typically used as the semiconductor switch. The semiconductor switch may be silicon-based or wide-bandgap material-based, and is typically SiC or GaN.

[0013] This disclosure includes yet another aspect: improvements to gate connections that selectively increase the inductance of some connections within a module. In accordance with this aspect, compensation structures are provided for shorter gate connection paths. This approach can increase the total gate inductance while reducing the differences in inductance between different groups of gate connection paths within a module. This further reduces oscillations and thus improves switching behavior. Compensation structures in accordance with this aspect can be used in combination with the inductance reduction described above. This may be necessary or beneficial because the physical possibilities of inductance reduction are limited and complete equalization cannot be achieved in all practical configurations. However, by combining both aspects, namely reducing the inductance of long connection paths and increasing the inductance of short connection paths, complete equalization or at least a substantial reduction of the gate inductance differences can be achieved.

[0014] Any feature described in relation to one of these aspects is disclosed herein in relation to the other aspect, even if each feature is not explicitly mentioned in the context of a particular aspect.

[0015] The attached drawings are included for further understanding. In the drawings, elements of the same structure and / or function may be referred to using the same reference numerals. It should be understood that the embodiments shown in the drawings are for illustrative purposes only and are not necessarily drawn to a specific scale. [Brief explanation of the drawing]

[0016] [Figure 1] This is a schematic diagram of the first embodiment of the power module. [Figure 2] This figure shows the effect of the first embodiment on gate inductance. [Figure 3] A more specific diagram of the first embodiment is shown. [Figure 4] This figure shows an embodiment with an interconnection bridge. [Figure 5] This is a diagram showing the details of the drawing in Figure 4. [Figure 6] This figure shows another embodiment of an interconnect bridge with increased mechanical stability. [Figure 7] This figure shows another embodiment of an interconnect bridge with increased mechanical stability. [Figure 8] This figure shows a second embodiment of a power module having an additional compensation structure. [Figure 9] This figure shows one of several design options for compensation structures. [Figure 10] This figure shows one of several design options for compensation structures. [Figure 11] This figure shows one of several design options for compensation structures. [Figure 12] This figure shows one of several design options for compensation structures. [Modes for carrying out the invention]

[0017] FIG. 1 is a schematic diagram of a power module 1 including two groups 2 and 3 of semiconductor switches 4. The gate terminals 10 of the semiconductor switches 4 are connected to module gate contacts 5. The length of the conductive path between the module gate contact 5 and the gate terminal 10 of the semiconductor switch 4 is determined according to the geometric arrangement of the components within the module 1. For example, when three or more groups of semiconductor switches are provided, it can be difficult to equalize the length of each connection path of the groups of semiconductor switches.

[0018] Unequal gate connection lengths are a problem. This is because the use of wide bandgap semiconductors such as silicon carbide, abbreviated as SiC, and gallium nitride, abbreviated as GaN, etc., has become more widespread in order to overcome the limitations of silicon-based power semiconductor devices. Typically, wide bandgap devices such as silicon carbide and gallium nitride-based devices are attractive due to their fast switching capabilities that result in low switching losses. However, when using multiple wide bandgap semiconductors within a module, stronger vibrations were observed within the module. To reduce such vibrations, resistors were provided in the gate connection paths. In many cases, a 5 Ω resistor is sufficient to suppress the vibrations. However, to provide such resistors, the use of thick film technology was required, which meant that additional manufacturing processes were needed. Although it is possible to suppress the vibrations in this way, the original advantage of the wide bandgap semiconductors, namely the fast switching function, cannot be fully maintained.

[0019] According to the present disclosure, the goal is not to suppress vibrations but to avoid them from the start. The method for this is not to minimize the total gate inductance of the power semiconductor module 1, but to equalize the gate inductances of different groups of semiconductor switches. The switching function of the power semiconductor module 1 also depends on the total inductance of the gate path, but the vibrations strongly depend on the difference in inductance and path length between two different groups 2 and 3 of the semiconductor switches 4.

[0020] In other words, in order to enable high-speed switching, the module stray inductance must be made low enough to avoid significant voltage overshoot, and the inductance imbalance must be reduced to avoid oscillations between semiconductor switches.

[0021] Referring to FIG. 1, the inductance of the gate path of the first group 2 can be described as the shared inductance L_shared + the interconnection inductance L_interconnection + the inductance L1, and the inductance of the second gate path can be described as the shared inductance L_shared + L2. As can be seen from FIG. 1, the connection path to the first group 2 is longer than the connection path to the second group 3. According to this embodiment, a part of the gate path to the first group 2 is realized by the interconnection bridge 6. Regarding the very close cross-sectional parallel arrangement of the source path from the module source contact 7 to the source terminal of the switch 4, the inductance of this part of the gate path can be reduced. In fact, the gate inductance of the gate path to the first group 2 can be reduced by about 50%.

[0022] The proposed feature can be beneficial, particularly in the design of complex high-power modules based on a number of silicon carbide or gallium nitride switches arranged and connected in parallel on several substrates. However, the concept of the present disclosure can also be realized in smaller power modules such as those shown in FIG. 1.

[0023] Connecting a number of semiconductor switches 4 in parallel to achieve the intended current density / rated current is a typical configuration of the power semiconductor module 1. This also applies to, for example, silicon carbide and gallium nitride semiconductor switches. This is because the footprint of these switches is smaller than that of Si technology switches, so more switches need to be connected in parallel to enable switching of the same current.

[0024] Figure 2 illustrates the effect of the interconnection bridge in such an embodiment. For example, it is possible to group 10 semiconductor switches 4 on one substrate of the module and group another 10 semiconductor switches 4 on another substrate of the module. The 20 semiconductor devices 4 placed on both substrates are connected in parallel. In the case of a half-bridge module configuration, these two substrates would represent the top or bottom surface of the module. Two other such substrates, connected in parallel, would form the other switch of this half-bridge module.

[0025] In Figure 2, the relative gate inductance for each switch placed on one of the two parallel-connected boards is shown as a percentage of the maximum value. This means that switches 1-10 belong to the first group 2, and switches 11-20 belong to the second group 3. As can be seen from the dotted line 8 showing the gate inductance of a conventional wire-bonded power semiconductor module, the maximum difference in gate inductance between groups is 19%, while the difference within a group is only 6%. As can be seen from the solid line 9, the inductance of the gate path in the first group 2 can be reduced by using the interconnect bridge 6. In the configuration with the interconnect bridge 6, the maximum difference in gate inductance is only 12%.

[0026] Another benefit is that vibration is reduced, thereby increasing the switching speed. The applicant's measurements show that the amplitude of gate voltage vibration was reduced by approximately 70%. This reduction in vibration also reduces power loss over the switching time.

[0027] Another desirable effect of using the ideas of this disclosure is that the resistance of the gate path can be reduced to a value of at least less than 2Ω. Such a resistor can be realized as a semiconductor resistor and does not require any additional manufacturing steps.

[0028] This disclosure has the advantage that resistors can be omitted or at least implemented as substrate resistors to suppress vibration.

[0029] Figure 3 shows a more detailed diagram of the two groups 2 and 3 of the semiconductor switch 4. The semiconductor switch 4 is placed on top of the metallization layer. A portion 15 of the metallization layer is used as the drain connection. Another portion of the metallization layer is isolated to form the gate group contact 13, also called the control group contact 13. Yet another portion of the metallization is isolated as the source group contact 14, also called the first group contact 14. This applies to both the substrates of groups 2 and 3.

[0030] The gate terminal 10 of switch 4 is connected to the first-face metallization 11, which appears as the top-face metallization in Figure 3, and from there to the gate group contact 13 shown for group 2 on the left. The first-face metallization can also be divided into two parts connected via a resistor 24 and a bond wire, for example, as shown for group 3 on the right. In this way, vibrations are dampened by incorporating a resistor 24 with a value of less than 2Ω into the gate path.

[0031] The source terminal of switch 4 is connected to another metallization 16 that forms the source wiring, and from there to the first group contact 14. For board-to-board connections, which also mean connections between different switch groups, an interconnection bridge 6 according to this disclosure is used.

[0032] Figure 4 shows a more detailed view of the interconnect bridge 6, which includes two conductive layers 17 and 18. Layer 18 is used as the gate connection, and layer 17 is used as the source connection. These two layers are separated by an insulating layer, which is not shown in this drawing. Legs 19 for the gate connection and legs 20 for the source connection are provided on both sides of the interconnect bridge 6. These legs are connected to the control group contact 13 and the first group contact 14, for example, by welding, sintering, soldering, or adhesive.

[0033] Figure 5 shows a more detailed diagram of the interconnection bridge 6. As can be seen from this diagram, the conductive layers 17 and 18 are separated by the insulating layer 21. The closer the conductive layers 17 and 18 are, the better inductive coupling is obtained between them. And the better this coupling is, the lower the inductance of the gate connection. Therefore, a thin insulating layer is beneficial for the performance of the power semiconductor module. It is beneficial for the thickness of the insulating layer to be less than 150 micrometers, or less than 80 micrometers. A realistic value is 30 to 150 micrometers.

[0034] If reducing the thickness of the layers results in an undesirable decrease in the mechanical stability of the bridge, this mechanical stability can be improved by adding one or more additional layers. Typical embodiments of interconnect bridges 6 with improved mechanical stability are shown in Figures 6 and 7. According to this embodiment, the interconnect bridge includes a laminate having, as a series of layers, an insulating protective layer 25, followed by a first metallization 26 for a first potential, a thin insulating layer 27, a second metallization 28 for a second potential, and a second insulating protective layer 29. For example, layers 25 and 26, and layers 29 and 28, are also provided as PCBs.

[0035] On the opposite side of the second insulating protective layer 29 are terminals 30 and 36, which are used for the electrical connection of both metallizations, namely the first metallization 26 and the second metallization 28. For this purpose, metallizations 26 and 28 can be accessed from the terminal side of the second insulating protective layer 29, for example, using vias.

[0036] Figure 7 is a cross-sectional view of the embodiment shown in Figure 7. Terminals 30 and 36 for two potentials that may be related to gate and source connections are connected by vias to the first metallization 26 and the second metallization 28, respectively.

[0037] Compared to the embodiments shown in Figures 4 and 5, mechanical stability is enhanced. This can be beneficial in the case of very long interconnect bridges, and furthermore, it opens up the possibility of minimizing the thickness of the insulating layer, as there is no need to provide a mechanical function to mechanically stabilize the interconnect bridge.

[0038] Another possibility for mechanically stabilizing the interconnection bridge is to use adhesive somewhere between the terminals to support the bridge. This can be achieved, for example, in all embodiments of the present disclosure.

[0039] Figure 8 shows yet another embodiment of the present disclosure, where groups 2 and 3 of semiconductor switches are integrated within submodule 31. Two additional groups 32 and 33 of semiconductor switches are integrated within a second submodule 34. Each of submodules 31 and 34 includes intergroup connections via interconnect bridge 6 as shown in the drawings above. Additionally, for gate connections between the first submodule 31 and the second submodule 34, an interconnect bridge 35 is used, which is formed similarly to the interconnect bridge 6 for intergroup connections within each of submodules 31 and 34. However, according to this embodiment, the interconnect bridge 35 cannot adequately equalize the differences in gate inductance of the gate paths to submodules 31 and 34. Therefore, an additional compensation structure 36 is provided in accordance with the second aspect of the present disclosure as described above. The compensation structure causes an increase in the inductance of the gate connection path to the switches of the first submodule 31. Both the reduction in inductance due to the interconnection bridge 35 and the increase in inductance due to the compensation structure 36 contribute to more equal inductance in the gate connection paths of both submodules 31 and 34.

[0040] Furthermore, while both gate and source connection paths are necessary for the technical effects of interconnection bridges 6 and 35, only the gate path needs to be modified for the compensation structure 36.

[0041] Regarding the realization of the compensation structure, Figures 9 to 12 show the possibility of easy implementation. Figure 9 shows a meandering structure in which the connection between contact point 38 and contact point 39 is increased by the meandering structure. In Figure 10, the island 40 is formed in the metallization 22 of the substrate 23 and connected by bond wires 41. In this way, the current path between connection points 38 and 39 is also extended.

[0042] In Figure 11, a helical structure is used for a similar effect. In Figure 12, the structure of Figure 11 is used, but the bond wire does not fully utilize the helical structure. In this way, the structure 36 of this configuration can be adapted to the specific needs of individual groups, which are determined by the geometric arrangement within the power semiconductor module 1.

[0043] In the embodiment shown in Figure 3, the compensation structure can also be realized by metallization 11.

[0044] The embodiments shown in Figures 1 to 12 above represent typical embodiments of the improved configuration of a power semiconductor module. Therefore, these embodiments do not constitute a complete list of all embodiments that follow the improved configuration. Actual configurations may differ from the embodiments shown in terms of configuration or devices. [Explanation of Symbols]

[0045] Reference sign 1 Power semiconductor module 2. First Group of Semiconductor Switches 3. Semiconductor switches, Group 2 4. Semiconductor switches 5 Module Gate Contacts 6. Interconnection Bridges 7 Module Source Contact 8. Gate inductance in the case of conventional wire bonding 9. Gate inductance in the case of interconnected bridges 10 Gate terminals 11. First surface metallization 13 Control Group Contacts / Gate Group Contacts 14. First Group Contact / Source Group Contact 15. Second Group Contact / Drain Group Contact 16 Other metallization / source group contacts 17. Conductive layer 18. Conductive layer 19 Gate connection leg 20 Source connection legs 21 Insulating layer 23 circuit boards 24 resistor 25. First insulating protective layer 26. First Bridge Metallization 27 Insulating layer 28. Second Bridge Metallization 29. Second insulating protective layer 30. First bridge terminal 31. First Submodule 32. Semiconductor switches, Group 3 33. Semiconductor switches, Group 4 34. Second submodule 35 Interconnection Bridges 36. First Bridge Terminal 38. First Connection Point 39 Second Connection Point 40 Metallization Island 41 Bonding wire

Claims

1. A power semiconductor module, comprising: a plurality of semiconductor switches arranged in a plurality of groups, each semiconductor switch having a first terminal and a second terminal with a controlled path provided therebetween, and a control terminal; The power semiconductor module, a plurality of first group contacts each connected to the first terminal of the semiconductor switches of that group; a plurality of second group contacts each connected to the second terminal of the semiconductor switches of that group; a plurality of control group contacts each connected to the control terminal of the semiconductor switches of that group; an interconnect bridge connecting the control group contacts and the first group contacts of the plurality of groups; The interconnect bridge includes a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer, the power semiconductor module.

2. The layer structure is formed as a printed circuit board, the power semiconductor module according to claim 1.

3. The layer structure is formed as a flexible printed circuit board, the power semiconductor module according to claim 2.

4. The layer structure is formed by a ceramic substrate having two-sided metallization, the power semiconductor module according to claim 1.

5. The interconnect bridge includes a plurality of first legs provided at a first end of the interconnect bridge and a plurality of second legs provided at a second end of the interconnect bridge, the power semiconductor module according to claim 1.

6. Each leg of the interconnect bridge is connected to a related group contact by soldering, welding, sintering or adhesive bonding, the power semiconductor module according to claim 5.

7. The plurality of semiconductor switches are at least one of MOSFETs or IGBTs of Si-based or wide bandgap material systems, the power semiconductor module according to claim 1.

8. Each of the plurality of semiconductor switches includes a wide bandgap semiconductor material, the power semiconductor module according to claim 1.

9. Further comprising a module control contact directly connected to the control terminals of the plurality of semiconductor switches of at least one group, the power semiconductor module according to claim 1.

10. A resistor having a resistance value of less than 2 Ω, further comprising a module control contact, The resistor is connected between the module control contact and the control terminals of at least one group of the plurality of semiconductor switches, The power semiconductor module according to claim 1.

11. The resistor is a semiconductor resistor disposed on the metallization, The power semiconductor module according to claim 10.

12. The maximum difference in gate inductance within the group is 2 nH, The power semiconductor module according to claim 1.

13. The power semiconductor module is a switch or a half-bridge, The power semiconductor module according to claim 1.

14. The thickness of the insulating layer is less than 150 μm, The power semiconductor module according to claim 1.

15. The thickness of the insulating layer is less than 80 μm, The power semiconductor module according to claim 14.

16. A power semiconductor module, a first group of semiconductor switches, a second group of semiconductor switches, each semiconductor switch of the first group and the second group has a first terminal and a second terminal with a controlled path provided therebetween and a control terminal, The power semiconductor module, a first group contact connected to the first terminal of the semiconductor switches of the first group, a second group contact connected to the first terminal of the semiconductor switches of the second group, a first control group contact connected to the control terminal of the semiconductor switches of the first group, a second control group contact connected to the control terminal of the semiconductor switches of the second group, a power semiconductor module comprising an interconnecting bridge connecting the first control group contact to the second control group contact and connecting the first group contact to the second group contact.

17. A third group of semiconductor switches, a fourth group of semiconductor switches, each semiconductor switch of the third group and the fourth group has a first terminal and a second terminal with a controlled path provided therebetween and a control terminal, The power semiconductor module, a third group contact connected to the first terminal of the semiconductor switches of the third group, a fourth group contact connected to the first terminal of the semiconductor switches of the fourth group, a third control group contact connected to the control terminal of the semiconductor switch of the third group; a fourth control group contact connected to the control terminal of the semiconductor switch of the fourth group; a second interconnection bridge that connects the third control group contact to the fourth control group contact and connects the third group contact to the fourth group contact; a third interconnection bridge that connects the interconnection bridge to the second interconnection bridge such that the control terminals of the first group and the second group are connected to the control terminals of the third group and the fourth group, and the first terminals of the first group and the second group are connected to the first terminals of the third group and the fourth group. The power semiconductor module according to claim 16.

18. The power semiconductor module according to claim 16, wherein the interconnection bridge includes a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer. a third group contact connected to the second terminal of the semiconductor switch of the first group; The power semiconductor module according to claim 16, further comprising a fourth group contact connected to the second terminal of the semiconductor switch of the second group.

20. A power semiconductor module, comprising a plurality of semiconductor switches arranged in a plurality of groups, each semiconductor switch including a wide bandgap semiconductor material and having a first terminal, a second terminal with a controlled path provided therebetween, and a control terminal; The power semiconductor module, a plurality of first group contacts each connected to the first terminal of the semiconductor switch of that group; a plurality of second group contacts each connected to the second terminal of the semiconductor switch of that group; a plurality of control group contacts each connected to the control terminal of the semiconductor switch of that group; a module first terminal contact connected to the plurality of first group contacts; a module control contact connected to the plurality of control group contacts; a resistor connected between the module control contact and at least one of the plurality of control group contacts and having a resistance value of less than 2 Ω comprising an interconnecting bridge connecting the control group contacts of the plurality of groups and the first group contacts; The interconnecting bridge is a power semiconductor module including a layer structure in which a first conductive layer and a second conductive layer are separated by an insulating layer.

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