Firmware updating

Abstract

To update firmware of a device while allowing the device to continue operation without causing the device to shut down.SOLUTION: Examples described herein include a device that, when operating, executes reduced function firmware to maintain operation of the device during an update of firmware for the device, the reduced function firmware provides the device with less functionality than the updated firmware. In some examples, the reduced function firmware comprises verified reduced function firmware. In some examples, the reduced function firmware comprises an updated version of reduced function firmware that overwrites full firmware in a firmware storage.SELECTED DRAWING: Figure 2

Description

[Background technology]

[0001] Computing devices utilize firmware for hardware initialization, low-level hardware management, and managing the boot process. In addition to platform firmware, computing devices may also include dedicated firmware for controller chips, peripheral devices, or other components. Firmware is typically loaded in conjunction with boot at runtime, but may also be updated in conjunction with a dedicated firmware update process.

[0002] Runtime firmware patches may be deployed to various central processing unit (CPU) firmware engines to fix bugs (errors), introduce new capabilities, or revert to a previous firmware version. Some firmware patches require a system reset. However, rebooting a CPU can result in system downtime where the CPU is unable to execute workloads or lead to delays in workload completion. CPU downtime can increase the total cost of ownership (TCO) for the datacenter owner or operator, which may be undesirable. [Brief explanation of the drawings]

[0003] [Figure 1] 1 illustrates an exemplary system.

[0004] [Figure 2] 1 illustrates an exemplary system.

[0005] [Figure 3A] 1 illustrates an exemplary operation. [Figure 3B] An exemplary operation is shown.

[0006] [Figure 4A] 1 illustrates an exemplary process. [Figure 4B] 1 illustrates an exemplary process.

[0007] [Figure 5] 1 illustrates an exemplary system.

[0008] [Figure 6] 1 illustrates an exemplary system. DETAILED DESCRIPTION OF THE INVENTION

[0009] Some examples provide a scheme for enabling device operation to continue while updating device firmware without shutting down the device. During a firmware update, two versions of firmware can be updated. That is, the first version can be reduced feature set firmware and the second version can be full feature set firmware. The authenticity of the firmware update can be verified before the firmware is executed. When a firmware update occurs for a device, executing the first version of firmware can enable the operating system (OS) to continue execution. However, some device functionality may not be available until the second version of firmware is executed. After the second version of firmware is updated and verified, the device can execute the second version of firmware. If a firmware update error or power outage occurs during the update of the first or second version of firmware, the device can revert to the reduced image or the first version recovery image and continue operation. Thus, avoiding a reset during a firmware update can enable continued OS and workload execution during the firmware update. For example, the firmware includes Microsoft Windows® Server Platform Services (SPS). In some examples, the device can have a version of firmware to run in the event of a power loss during or after the firmware update, or an error during the firmware update.

[0010] FIG. 1 illustrates an exemplary system. A central processing unit (CPU) 102 may include cores 104-0 through 104-n. A core may be an execution core or computational engine capable of executing instructions. A core may have access to its own cache and read-only memory (ROM), and multiple cores may share a cache or ROM. Cores may be homogeneous and / or heterogeneous devices. Any type of inter-processor communication technique may be used, such as, but not limited to, messaging, inter-processor interrupts (IPI), inter-processor communication, etc. Cores may be connected in any type of manner, such as, but not limited to, a bus, a ring, or a mesh. The cores may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, California, the Advanced RISC Machines (ARM) instruction set from ARM Holdings of Sunnyvale, California (with optional additional extensions such as NEON), including the instructions described herein. In addition to or as an alternative to using a CPU, an XPU or xPU can be used. An XPU can include one or more of a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a field programmable gate array (FPGA), an accelerated processing unit (APU), an accelerator, or another processor.

[0011] One or more of cores 140-0 through 140-n may execute an operating system (OS). In some examples, the OS may be Linux, Windows Server or Personal Computer, Android, MacOS, iOS, VMware vSphere, or any other operating system. The OS and drivers may run on a CPU or processor sold or designed by, among others, Intel, ARM, AMD, Qualcomm, IBM, Texas Instruments, etc.

[0012] The CPU 102 may cause the boot controller 114 to access firmware code 122 from storage 120 and copy the firmware code into memory 106 for execution by one or more cores (shown as firmware 110). The boot firmware code or firmware may have a header file that identifies a map of which boot code is copied by the CPU 102. For example, the firmware code's .h file may have a flash image layout map of which segments of the firmware code are copied. When executed by the processor, the firmware code may be executed by the processor to perform hardware initialization during the boot process (e.g., power-on start or reboot) and to provide runtime services to the operating system and programs.

[0013] In some examples, the boot controller 114 can access firmware code 122 from storage 120 and copy the firmware code to a memory device for execution by the one or more devices 118. In some examples, the storage 120 can be connected to the boot controller 114 using a fabric or a network, and the firmware update can be sent using one or more packets over a fabric or network interface (not shown). The one or more devices 118 can include one or more of an XPU, an infrastructure processing unit (IPU), a CPU, a CPU socket, a graphics processing unit (GPU), a processor, an accelerator device, a Board Management Controller (BMC), a storage controller, a memory controller, a display engine, a peripheral device, an Intel® Management or Manageability Engine (ME), an AMD Platform Security Processor (PSP), an ARM core with TrustZone extensions, a network interface device, a Platform Controller Hub (PCH), an application-specific integrated circuit (ASIC), etc.

[0014] For example, an ME may include one or more processors and may enable powering on, configuring, controlling, or resetting a computer system via communications received using a network interface device. For example, an ME may provide fan speed control and monitoring of temperature, voltage, current, and fan speed sensors. For example, an ME may provide a secure audio and / or video communication path. For example, an ME may provide a secure boot process by requiring firmware to be verified by its digital signature before booting. A PCH may include a chipset or circuit board that provides data paths and display interfaces, input / output controllers, clocks, and other circuits.

[0015] In some examples, the boot firmware code or firmware may include one or more of a Basic Input / Output System (BIOS), a Video BIOS (VBIOS), a GPU BIOS, a Universal Extensible Firmware Interface (UEFI), or a boot loader. BIOS firmware may be pre-installed on the personal computer's system board or may be accessed via an SPI interface from boot storage (e.g., flash memory). In some examples, the firmware may include an SPS. In some examples, a Universal Extensible Firmware Interface (UEFI) may be used instead of or in addition to the BIOS to boot or reboot a core or processor. UEFI is a specification that defines a software interface between an operating system and platform firmware. In addition to booting from a disk or storage, UEFI can read entries from a disk partition by booting from a specific boot loader at a specific location on a specific disk or storage. UEFI can support remote diagnostics and repair of computers even when no operating system is installed. Boot loaders can be written for UEFI, and the boot code firmware can be executable instructions that boot an operating system. A UEFI boot loader can be a boot loader that can be read from a UEFI type firmware.

[0016] A UEFI capsule is a method of encapsulating a binary image for firmware code updates. However, in some instances, a UEFI capsule is used to update runtime components of firmware code. A UEFI capsule can contain an updatable binary image in the relocatable Portable Executable (PE) file format for executable or dynamic linked library (dll) files based on the Common Object File Format (COFF). For example, a UEFI capsule can contain an executable file (*.exe). This UEFI capsule can be deployed to the target platform as an SMM image via existing OS-specific techniques (e.g., Windows Update for Azure, Linux LVFS).

[0017] Trusted entity 150 may include a BIOS, BMC, or other hardware that can send commands to update firmware, verify firmware, and / or cause execution of a particular reduced or full firmware. For example, trusted entity 150 may send Intelligent Platform Management Interface (IPMI)-consistent commands to an ME or other device to update firmware, verify firmware, and / or cause execution of a particular reduced or full firmware.

[0018] Boot controller 114 may be any type of controller (e.g., a microcontroller) or processor capable of managing the loading and storage of firmware code into memory 106 or other memory. In some examples, boot controller 114 may be implemented using a CPU core (e.g., any of 104-0 through 104-n) or threads of a multithreaded core. In some examples, boot controller 114 may be coupled to storage 120 using interface 130. Interface 130 may provide communication using one or more of the following protocols: serial peripheral interface (SPI), enhanced SPI (eSPI), System Management Bus (SMBus), I2C, MIPI I3C, Peripheral Component Interconnect Express (PCIe), and Compute Express Link (CXL). See, for example, Peripheral Component Interconnection Express (PCIe) Base Specification 1.0 (2002), as well as earlier versions, later versions, and variations thereof. See, for example, Compute Express Link (CXL) Specification revision 2.0, version 0.7 (2019), and earlier versions, later versions, and variations thereof.

[0019] As described herein, device 118 can execute firmware code 122 from at least a first or second slot in storage 120. A bootable and verified copy of firmware can be stored in at least one of the first or second slots in storage 120. Types of executable firmware can include (a) firmware version for performing services essential to the operation of the server system and inhibiting access to the PCH SPI after boot, and (b) firmware version executable for services essential to the operation and management of the server system and extended services (e.g., full firmware). For example, power limiting may not be supported by reduced firmware compared to full firmware that supports power limiting. For example, reduced device power management functionality may be supported by reduced firmware compared to full firmware that supports device power management functionality. For example, reduced power management functionality, or the absence of this functionality, may be supported by reduced firmware compared to full firmware that supports full power monitoring features. For example, reduced platform telemetry collection and reporting, or the absence of this functionality, may be supported by reduced firmware compared to full firmware that supports full platform telemetry collection and reporting functionality. For example, reduced or no input from one or more sensors may be supported by reduced firmware compared to full firmware supporting input from one or more sensors.

[0020] If a feature not supported in the reduced firmware is requested, an error message may be issued to the OS, but the device whose firmware has been updated may continue to operate. In some examples, when a device is running version (a) firmware, the device's firmware may be updated while the system is running the OS to maintain system operability. In some examples, some of the SPS functionality may be limited in the reduced firmware compared to the full firmware.

[0021] For example, a firmware update operation may include the device whose firmware is being updated executing a first reduced firmware and storing a second reduced firmware in one of the slots, such as the slot that stored the previous full firmware version; after verifying the second reduced firmware version, the device whose firmware is being updated executing the second reduced firmware version and storing the full firmware version in another slot, such as the slot that stored the first reduced firmware version; and the device whose firmware is being updated executing the full firmware version.

[0022] FIG. 2 illustrates an exemplary scheme for storing firmware. For example, a layout can be used to store firmware accessible by a device. A slot can be a range of addressable storage areas. For example, slot 201 and slot 202 can be addressable storage areas. In some examples, as described herein, slot 201 and slot 202 can store updated reduced firmware before one of slots 201 or 202 stores full firmware. While two slots are illustrated, note that more than two slots can be used to store reduced or full firmware. In some examples, the firmware update and execution sequencing can include overwriting the full firmware with a second reduced firmware, retaining the fallback reduced firmware, and after verifying the second reduced firmware, executing the second reduced firmware while overwriting the reduced firmware with the second full firmware, and then executing the second full firmware.

[0023] 3A and 3B show an example flow of operation. A firmware update can include three stages of firmware updates: a recovery during operation firmware update stage, a recovery during operation firmware update stage, and an operation firmware update stage. One or more firmware updates can be verified, but if a firmware update is not verified, the device can boot from a verified firmware image.

[0024] The firmware update may include updating at least two versions of firmware: a first version that is reduced functionality firmware (reduced firmware) and a second version that is full functionality firmware (firmware or full firmware). In some examples, prior to the firmware update, a first slot may store the reduced firmware and a second slot may store the full firmware. At 302, the trusted entity may send a command to a device whose firmware is to be updated to execute a reduced firmware image in the first slot. The device may execute the reduced firmware in the first slot. At 304, the device may indicate to the trusted entity that the device is executing the reduced firmware.

[0025] At 306, the trusted entity may write the second reduced firmware to a second slot of the firmware storage, the second slot previously storing the full firmware. At 308, the firmware storage controller may indicate to the trusted entity that the second slot stores the second reduced firmware. At 310, the trusted entity may instruct the device to boot the second reduced firmware from the second slot. If the device fails to boot the reduced firmware from the second slot, the device may boot using the reduced firmware in the first slot.

[0026] At 312, the device may provide a status to the trusted entity that the device has booted the second reduced firmware from the second slot. The status may indicate the running firmware version. The trusted entity may check whether the updated second reduced firmware was properly activated by verifying that the firmware version matches the updated recovery version. If there is a verification failure, the trusted entity may cause the device to run a previously verified firmware version, such as the reduced firmware in the first slot, and / or indicate to an administrator that the full firmware version of the particular device has not been verified.

[0027] At 314, the trusted entity may update the first slot with the third reduced firmware. At 316, the firmware storage controller may indicate to the trusted entity that the first slot stores the third reduced firmware. At 318, the trusted entity may instruct the device to execute the third reduced firmware image in the first slot. The device may execute the third reduced firmware in the first slot. In some examples, the trusted entity may activate execution of the third reduced firmware in the first slot by sending a command to force recovery. If booting the third reduced firmware from the first slot fails, the second reduced firmware in the second slot may be executed. At 320, the device may indicate to the trusted entity that the device is executing the third reduced firmware. For example, the trusted entity may send a Get FW status command, and the device may respond with a FW status having a FW version. The trusted entity can check whether the third reduced firmware in the first slot has been correctly activated by verifying that the FW version matches the new recovery version, and the recovery reason is set to be performed by command.

[0028] At 322, the trusted entity may update the first slot with the second full firmware. At 324, the firmware storage controller may indicate to the trusted entity that the second slot stores the second full firmware. At 326, the trusted entity may activate the second full firmware to run from the second slot by sending a Force ME Recovery command. If the device fails to boot the full firmware from the second slot, the device may boot using the reduced firmware from the second slot. At 328, the device may indicate to the trusted entity that the device is running the updated full firmware. The trusted entity may check whether the updated reduced firmware was activated correctly by verifying that the firmware version matches the updated recovery version. If there is a verification failure, the trusted entity may cause the device to run a previously verified firmware version (including the reduced firmware version) and / or indicate to an administrator that the full firmware version of a particular device has not been verified.

[0029] In some examples, 314-320 are not performed and the device can continue executing the second reduced firmware instead of the third reduced firmware, the second full firmware can be written to the first slot instead of the second slot, and the device can execute the second full firmware from the first slot.

[0030] 4A and 4B show an example of a process that may be performed by a boot controller. At 402, a determination may be made if a firmware update is required. If a firmware update is required, the process may proceed to 404. If a firmware update is not required, the process may repeat 402.

[0031] At 404, the device may boot from reduced firmware from a first slot in firmware storage. The firmware storage slot may store reduced or full firmware. At 406, second reduced firmware may be received. The second reduced firmware may be stored in a second slot in firmware storage. At 408, in response to a request to boot the second reduced firmware from the second slot, the device may boot the second reduced firmware from the second slot and indicate the firmware version to the trusted entity. In some cases, the second reduced firmware is the same firmware as the reduced firmware in the first slot. In some cases, the second reduced firmware is different firmware from the reduced firmware in the first slot.

[0032] At 410, the boot controller may determine whether to receive an indication to execute the particular firmware after updating the reduced firmware. For example, the device may receive an indication to execute the reduced firmware from the first slot based on the second reduced firmware in the second slot being identified as not being verified by the trusted entity. If the device receives an indication to execute the particular firmware after updating the reduced firmware, the process may continue to 430. If the device does not receive an indication to execute the particular firmware after updating the reduced firmware, the process may continue to 430.

[0033] At 412, third reduced firmware may be received. The third reduced firmware may be stored in the first slot. At 414, in response to the request to boot the third reduced firmware from the third slot, the device may boot the third reduced firmware from the third slot and indicate the firmware version to the trusted entity.

[0034] 4B , at 416, the boot controller may determine whether to receive an indication to execute the particular firmware after updating the reduced firmware. For example, the device may receive an indication to execute the reduced firmware from the second slot based on the third reduced firmware in the first slot being identified as not being verified by the trusted entity. If the device receives an indication to execute the particular firmware after updating the reduced firmware, the process may continue to 430. If the device does not receive an indication to execute the particular firmware after updating the reduced firmware, the process may continue to 418.

[0035] At 418, a second full firmware may be received. The second full firmware may be stored in the second slot or another slot. At 420, in response to the request to boot the second full firmware, the device may boot the second full firmware from the second slot and indicate the firmware version to the trusted entity.

[0036] At 422, the boot controller may determine whether it receives an indication to execute the particular firmware after the firmware update. For example, the device may receive an indication to execute the third reduced firmware from the first slot based on the firmware in the second slot being identified as not being verified by the trusted entity. If the device receives an indication to execute the particular firmware after the firmware update, the process may continue to 430. If the device does not receive an indication to execute the particular firmware after the firmware update, the process may end or continue with another operation.

[0037] At 430, the boot controller can execute the verified reduced firmware or full firmware stored in the slot that was not last updated. For example, after storing the second reduced firmware, the verified reduced firmware can be executed. For example, after storing the third reduced firmware, the verified second reduced firmware can be executed. For example, after storing the full firmware, the verified third reduced firmware can be executed.

[0038] 5 illustrates an example process that may be performed by a trusted entity. At 502, the trusted entity may verify firmware recently copied to a device's firmware storage. The verification may be based at least on the firmware version in at least some examples. If the firmware is verified, the process may terminate. If the firmware is not verified, the process may continue to 504, where the trusted entity may cause the device to run a pre-verified reduced firmware or full firmware and notify an administrator of any particular firmware updates that are not verified.

[0039] 6 illustrates a system. Various examples may be used by system 600 to update or access updated firmware, as described herein. System 600 includes a processor 610 that provides processing, operational management, and execution of instructions for system 600. Processor 610 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), processing core, or other processing hardware that provides processing for system 600, or a combination of processors. Processor 610 controls the overall operation of system 600 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of these devices.

[0040] In one example, system 600 includes an interface 612 coupled to processor 610, which can represent a higher-speed or high-throughput interface to system components requiring a higher-bandwidth connection, such as memory subsystem 620 or graphics interface 640 or accelerator 642. Interface 612 represents interface circuitry that can be a standalone component or integrated into the processor die. When present, graphics interface 640 interfaces with graphics components to provide a visual display to a user of system 600. In one example, graphics interface 640 can drive a high-definition (HD) display that provides output to the user. High resolution can refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and can include formats such as Full HD (e.g., 1180p), Retina display, 6K (ultra-high definition or UHD), and the like. In one example, the display can include a touchscreen display. In one example, graphics interface 640 generates a display based on data stored in memory 630, based on operations performed by processor 610, or both. In one example, the graphics interface 640 generates the display based on data stored in the memory 630, or based on operations performed by the processor 610, or both.

[0041] The accelerators 642 may be programmable or fixed-function offload engines that can be accessed or used by the processor 610. For example, an accelerator among the accelerators 642 may provide sequential and speculative decode operations in the manner described herein, compression (DC) capabilities, cryptographic services such as public key encryption (PKE), ciphers, hash / authentication capabilities, decryption, or other capabilities or services. In some embodiments, an accelerator among the accelerators 642 provides field selection controller capabilities as described herein. In some cases, the accelerators 642 may be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that contains a CPU and provides an electrical interface with the CPU). For example, the accelerators 642 may include programmable processing elements such as single or multi-core processors, graphics processing units, logic execution units, single or multi-level caches, functional units usable to independently execute programs or threads, application-specific integrated circuits (ASICs), neural network processors (NNPs), programmable control logic, and field-programmable gate arrays (FPGAs). The accelerator 642 may provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or graphics processing units that may be enabled by artificial intelligence (AI) or machine learning (ML) models. For example, the AI ​​models may use or include any or a combination of reinforcement learning schemes, Q-learning schemes, deep Q-learning, or Asynchronous Advantage Actor-Critic (A3C), combinatorial neural networks, recurrent combinatorial neural networks, or other AI or ML models. The multiple neural networks, processor cores, or graphics processing units may be enabled by the AI ​​or ML models. Firmware updates for the processor 610 or accelerator 642 may occur using the techniques described herein.

[0042] Memory subsystem 620 represents the main memory of system 600, providing storage for code executed by processor 610 or data values ​​used in executing routines. Memory subsystem 620 can include one or more memory devices 630, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM), such as DRAM, or other memory devices, or a combination of such devices. Memory 630 stores and hosts, among other things, an operating system (OS) 632, which provides a software platform for executing instructions in system 600. Additionally, applications 634 can execute on the software platform of OS 632 from memory 630. Applications 634 represent programs having their own operating logic that perform the execution of one or more functions. Processes 636 represent agents or routines that provide auxiliary functionality to OS 632, or one or more applications 634, or a combination. OS 632, applications 634, and processes 636 provide the software logic that provides functionality for system 600. In one example, memory subsystem 620 includes memory controller 622, which is a memory controller that generates and issues commands to memory 630. It will be understood that memory controller 622 may be a physical part of processor 610 or a physical part of interface 612. For example, memory controller 622 may be an integrated memory controller integrated into circuitry with processor 610.

[0043] Although not specifically shown, it will be understood that system 600 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or others. A bus or other signal line can communicatively or electrically couple components together, or communicatively and electrically. A bus can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits or combinations. A bus can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI), a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) 1394 bus (Firewire).

[0044] In one embodiment, system 600 includes interface 614, which may be coupled to interface 612. In one example, interface 614 represents an interface circuit, which may include standalone components and integrated circuits. In one example, multiple user interface and / or peripheral components couple to interface 614. Network interface 650 provides system 600 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 650 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a universal serial bus (USB), or other wired or wireless standards-based or proprietary interface. Network interface 650 may transmit data to a remote device, which may include transmitting data stored in a device or memory located in the same data center or rack. Network interface 650 may receive data from a remote device, which may include storing the received data in memory. Various examples may be used in connection with network interface 650, processor 610, and memory subsystem 620.

[0045] In one example, system 600 includes one or more input / output (I / O) interfaces 660. I / O interface 660 can include one or more interface components (e.g., audio, alphanumeric, haptic / touch, or other interfaces) through which a user interacts with system 600. Peripheral interface 670 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that depend on and connect to system 600. A dependent connection is one in which system 600 provides a software or hardware platform or both on which operations are executed and with which a user interacts.

[0046] In one example, system 600 includes a storage subsystem 680 that stores data in a nonvolatile manner. In one example, in a particular system implementation, at least certain components of storage 680 can overlap with components of memory subsystem 620. Storage subsystem 680 includes storage 684, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, for example, one or more magnetic, solid-state, or optical-based disks, or a combination thereof. Storage 684 holds code or instructions and data 1046 in a persistent state (e.g., values ​​are retained despite interruption of power to system 600). While storage 684 can be generally considered "memory," memory 630 is typically an execution or operating memory that provides instructions to processor 610. While storage 684 is nonvolatile, memory 630 can include volatile memory (e.g., the value or state of the data is indeterminate if power is interrupted to system 600). In one example, storage subsystem 680 includes a controller 682 that interfaces with storage 684. In one example, the controller 682 may be a physical part of the interface 614 or the processor 610 , or may include circuitry or logic in both the processor 610 and the interface 614 .

[0047] Volatile memory is memory whose state (and therefore the data stored in it) is indeterminate when power is interrupted to the device. Dynamic volatile memory can involve refreshing the data stored in the device to maintain its state. An example of dynamic volatile memory includes Dynamic Random Access Memory (DRAM), or some variants such as Synchronous DRAM (SDRAM). Memory subsystems as described herein may be compatible with multiple memory technologies, such as DDR3 (Double Data Rate version 3, originally released by JEDEC (Joint Electronic Device Engineering Council) on June 27, 2007). DDR4 (DDR version 4, initial specification published by JEDEC in September 2012), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version 3, JESD209-3B, by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide Input / output version 2, JESD229-2, originally published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD325, originally published by JEDEC in October 2013), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC), or other combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0048] A nonvolatile memory (NVM) device is memory whose state is well-defined even when power is interrupted to the device. In some examples, an NVM device may include NAND technology, more specifically, a block-addressable memory device such as multi-threshold level NAND flash memory (e.g., single-level cell (SLC), multi-level cell (MLC), quad-level cell (QLC), tri-level cell (TLC), or some other NAND). NVM devices may also include byte-addressable write-in-place three-dimensional cross-point memory devices or other byte-addressable write-in-place NVMs such as single or multi-level PCM (Phase Change Memory) or PCMS (phase change memory with a switch), NVM devices using chalcogenide phase change materials (e.g., chalcogenide glasses), resistive memories including metal oxide-based, oxygen vacancy-based, and CB-RAM (Conductive Bridge Random Access Memory), nanowire memories, ferroelectric random access memories (FeRAM, FRAM®), magnetoresistive random access memories (MRAM) incorporating memristor technology, STT (spin transfer torque)-MRAM, spintronic magnetic tunnel junction memory-based devices, MTJ (magnetic tunneling junction)-based devices, DW (Domain Wall) and SOT (Spin Orbit Transfer)-based devices, thyristor-based memory devices, or combinations of the above, or other memories.

[0049] A power source (not shown) provides power to the components of system 600. More specifically, the power source typically interfaces with one or more power sources in system 600 to provide power to the components of system 600. In one example, the power source includes an AC-DC (alternating current-direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging via proximity of a charging field. In one example, the power source can include an internal battery, an AC power source, a motion-based power source, a solar power supply, or a fuel cell power source.

[0050] In one example, system 600 may be implemented using interconnected computational threads of processors, memory, storage, network interfaces, and other components. High-speed interconnects may be used, such as Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omnipath, Compute Express Link (CXL), HyperTransport, high-speed fabrics, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof. Data may be copied or stored on virtualized storage nodes using protocols such as NVMe-oF (NVMe over Fabrics) or NVMe.

[0051] Examples herein may be implemented with various types of computing and networking equipment, such as switches, routers, racks, and blade servers used in data center and / or server farm environments. Servers used in data centers and server farms include arrayed server configurations, such as rack-based servers or blade servers. These servers are communicatively interconnected via various networking conventions, such as partitioning a set of servers into local area networks (LANs) with appropriate switching and routing capabilities between the LANs to form a private intranet. For example, cloud hosting functions may typically employ large data centers with numerous servers. A blade comprises a separate computing platform configured to perform server-type functions, i.e., a "server on a card." Thus, a blade includes components common to a traditional server, including a main printed circuit board (main board) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted on the board.

[0052] Various examples may be used in base stations supporting communications using wired or wireless protocols (e.g., 3GPP Long Term Evolution (LTE) (4G) or 3GPP 5G), on-premise data centers, off-premise data centers, edge network elements, edge servers and switches, fog network elements, and / or hybrid data centers (e.g., data centers using virtualization, cloud, and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

[0053] Examples herein may be implemented with various types of computing and networking equipment, such as switches, routers, racks, and blade servers used in data center and / or server farm environments. Servers used in data centers and server farms include arrayed server configurations, such as rack-based servers or blade servers. These servers are communicatively interconnected via various networking conventions, such as partitioning a set of servers into local area networks (LANs) with appropriate switching and routing capabilities between the LANs to form a private intranet. For example, cloud hosting functions may typically employ large data centers with numerous servers. Blades comprise separate computing platforms configured to perform server-type functions, i.e., "servers on a card." Thus, each blade includes components common to a traditional server, including a main printed circuit board (main board) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted on the board.

[0054] In some examples, the network interface and other examples described herein may be used in connection with a base station (e.g., 3G, 4G, 5G, etc.), a macro base station (e.g., in a 5G network), a pico station (e.g., an IEEE 802.11 compatible access point), or a nano station (e.g., for Point-to-Multipoint (PtMP) applications).

[0055] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware and / or software elements may vary according to any number of factors, such as desired computation speed, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints, as desired for a given implementation. A processor may be a hardware state machine, digital control logic, a central processing unit, or a combination of one or more of any hardware, firmware, and / or software elements.

[0056] Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium that stores logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0057] According to some examples, a computer-readable medium may include a non-transitory storage medium that stores or maintains instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or actions according to described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions may be implemented according to a predefined computer language, style, or syntax to instruct the machine, computing device, or system to perform a predetermined function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0058] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium that represent various logic within a processor, which, when read by a machine, computing device, or system, causes the machine, computing device, or system to produce logic that performs the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually produce the logic or processor.

[0059] The appearance of the phrase "one example" or "an example" does not necessarily refer to the same example or embodiment. Any aspect described herein can be combined with any other or similar aspect described herein, regardless of whether the aspects are described with reference to the same figure or element. The division, omission, or inclusion of block functions shown in the accompanying drawings does not necessarily infer the division, omission, or inclusion in the examples of hardware components, circuits, software, and / or elements for implementing those functions.

[0060] Some examples may be described using the terms "coupled" and "connected," along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, a description using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other.

[0061] The terms “first,” “second,” etc., as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “a” and “an” as used herein do not denote a limitation of quantity, but rather indicate the presence of at least one of the referenced items. The term “asserted,” as used herein with reference to a signal, indicates that the signal is active and may be achieved by applying any logic level, either a logic 0 or a logic 1, to the signal. The terms “following” or “after” can refer to immediately following or after some other event or events. Other sequences of operations may also be performed by alternative examples. Furthermore, additional operations may be added or deleted depending on the particular application. Any combination of modifications may be used, and one of ordinary skill in the art with the benefit of this disclosure will recognize numerous variations, modifications, and alternative examples thereof.

[0062] Disjunctive language such as the phrase "at least one of X, Y, or Z," unless otherwise specified, is generally understood to mean otherwise in the context in which it is used to indicate that an item, term, etc. may be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that a particular instance requires at least one of X, at least one of Y, or at least one of Z, to be present, respectively. Additionally, conjunctive language such as the phrase "at least one of X, Y, and Z," unless otherwise specified, should also be understood to mean "X, Y, Z," or any combination thereof, including "X, Y, and / or Z."

[0063] Illustrative examples of the devices, systems, and methods disclosed herein are provided below. The example devices, systems, and methods may include any one or more of the examples described below, and any combination thereof.

[0064] Example 1, including one or more examples, includes a method including maintaining operation of a device during a firmware update to a storage device, executing reduced functionality firmware during the firmware update to the storage device, and booting the firmware from the storage device after the firmware update to the storage device.

[0065] Example 2 includes one or more examples that include storing multiple copies of reduced functionality firmware before updating the firmware of the device.

[0066] Example 3 includes one or more examples in which the executed reduced functionality firmware includes verified reduced functionality firmware.

[0067] Example 4 includes one or more examples in which booting firmware from storage after updating firmware to storage is based on verified reduced functionality firmware.

[0068] Example 5 includes one or more examples, and includes copying the reduced-function firmware to a first area of ​​firmware storage; copying second reduced-function firmware to a second area of ​​firmware storage; and overwriting the first area of ​​firmware storage with the firmware.

[0069] Example 6 includes one or more examples in which overwriting the first region of the firmware storage with the firmware is based on verification of at least the second reduced functionality firmware.

[0070] Example 7 includes one or more examples in which the reduced functionality firmware provides one or more of reduced measurement of outputs from nine or more sensors, reduced device power management functionality, limited power monitoring functionality, and / or reduced platform telemetry collection and reporting.

[0071] Example 8 includes one or more examples in which a boot controller executes reduced functionality firmware during an update of the firmware to the storage device and boots the firmware from the storage device after the update of the firmware to the storage device.

[0072] Example 9, including one or more examples, includes an apparatus including a device, the device, when in operation, executing reduced functionality firmware to maintain operation of the device during a firmware update of the device, the reduced functionality firmware providing less functionality to the device than firmware being updated.

[0073] Example 10 includes one or more examples in which the reduced functionality firmware includes verified reduced functionality firmware.

[0074] Example 11 includes one or more examples in which the reduced functionality firmware includes an updated version of the reduced functionality firmware that overwrites the full firmware in firmware storage.

[0075] Example 12 includes one or more examples in which the reduced functionality firmware provides one or more of reduced measurement of outputs from nine or more sensors, reduced device power management functionality, limited power monitoring functionality, and / or reduced platform telemetry collection and reporting.

[0076] Example 13 includes one or more examples in which the firmware provides operation of the reduced functionality firmware to provide one or more of measuring outputs from one or more sensors, device power management functionality, power monitoring functionality, and / or platform telemetry collection and reporting.

[0077] Example 14 includes one or more examples where the device includes one or more of an XPU, an infrastructure processing unit (IPU), a central processing unit (CPU), a CPU socket, a graphics processing unit (GPU), a processor, an accelerator device, a Board Management Controller (BMC), a storage controller, a memory controller, a display engine, a peripheral device, an Intel® Management or Manageability Engine (ME), an AMD Platform Security Processor (PSP), an Advanced RISC Machines (ARM) core with TrustZone extensions, a network interface device, a Platform Controller Hub (PCH), and an application-specific integrated circuit (ASIC).

[0078] Example 15 includes one or more examples, including a server including the device, wherein prior to updating the firmware, the server instructs the device to perform one or more operations, and maintaining operation of the device includes performing the one or more operations.

[0079] Example 16, including one or more examples, includes a computer-readable medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to execute reduced functionality firmware to maintain operation of a device during a firmware update of the device, the reduced functionality firmware providing less functionality to the device than firmware being updated.

[0080] Example 17 includes one or more examples in which the reduced functionality firmware includes verified reduced functionality firmware.

[0081] Example 18 includes one or more examples in which the reduced functionality firmware includes an updated version of the reduced functionality firmware that overwrites the full firmware in firmware storage.

[0082] Example 19 includes one or more examples wherein the reduced functionality firmware provides one or more of reduced measurement of outputs from nine or more sensors, reduced device power management functionality, limited power monitoring functionality, and / or reduced platform telemetry collection and reporting.

[0083] Example 20 includes one or more examples where the device includes one or more of an XPU, an infrastructure processing unit (IPU), a central processing unit (CPU), a CPU socket, a graphics processing unit (GPU), a processor, an accelerator device, a Board Management Controller (BMC), a storage controller, a memory controller, a display engine, a peripheral device, an Intel® Management or Manageability Engine (ME), an AMD Platform Security Processor (PSP), an Advanced RISC Machines (ARM) core with TrustZone extensions, a network interface device, a Platform Controller Hub (PCH), and an application-specific integrated circuit (ASIC).

Claims

1. Maintaining operation of the storage device during a firmware update to the device; executing reduced functionality firmware during the firmware update to the storage device; booting the firmware from the storage device after updating the firmware to the storage device.

2. The method of claim 1 , comprising storing multiple copies of reduced functionality firmware before updating the firmware of the device.

3. The method of claim 1 , wherein the executed reduced functionality firmware comprises verified reduced functionality firmware.

4. The method of claim 1 , wherein booting the firmware from the storage device after updating the firmware to the storage device is based on the reduced functionality firmware being verified.

5. copying the reduced functionality firmware to a first area of ​​firmware storage; copying second reduced functionality firmware to a second area of ​​the firmware storage; and overwriting the first area of ​​the firmware storage with the firmware.

6. The method of claim 5 , wherein overwriting the first area of ​​the firmware storage with the firmware is based on verification of at least the second reduced functionality firmware.

7. 8. The method of claim 1, wherein the reduced functionality firmware provides one or more of reduced measurement of outputs from one or more sensors, reduced device power management functionality, limited power monitoring functionality, and / or reduced platform telemetry collection and reporting.

8. 8. The method of claim 1, wherein a boot controller executes reduced functionality firmware during an update of the firmware to the storage device, and boots the firmware from the storage device after the update of the firmware to the storage device.

9. a device, the device, when in operation, 1. An apparatus that executes reduced functionality firmware to maintain operation of a device during a firmware update of the device, the reduced functionality firmware providing less functionality to the device than the firmware being updated.

10. The apparatus of claim 9 , wherein the executed reduced functionality firmware comprises verified reduced functionality firmware.

11. The apparatus of claim 9 , wherein the reduced functionality firmware comprises an updated version of the reduced functionality firmware that overwrites the full firmware in a firmware storage.

12. 10. The apparatus of claim 9, wherein the reduced functionality firmware provides one or more of reduced measurement of outputs from nine or more sensors, reduced device power management functionality, limited power monitoring functionality, and / or reduced platform telemetry collection and reporting.

13. 13. The apparatus of claim 12, wherein the firmware provides the operation of the reduced functionality firmware and provides one or more of: measurement of outputs from one or more sensors; device power management functions; power monitoring functions; and / or platform telemetry collection and reporting.

14. The devices may be XPUs, IPUs (infrastructure processing units), CPUs (central processing units), CPU sockets, GPUs (graphics processing units), processors, accelerator devices, BMCs (Board Management Controllers), storage controllers, memory controllers, display engines, peripheral devices, Intel® Management or MEs (Manageability Engines), AMD PSPs (Platform Security Processors), ARMs (Advanced RISC Machines) cores with TrustZone extensions, network interface devices, PCHs (Platform Controllers), The apparatus of any one of claims 9 to 13, comprising one or more of the following: a Network Interface Module (NIM) or a Network Hub; an Application Specific Integrated Circuit (ASIC).

15. a server including the device; The apparatus of any one of claims 9 to 14, wherein before updating the firmware, the server instructs the device to perform one or more operations, and maintaining operation of the device includes performing the one or more operations.

16. A computer-readable medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to: A computer-readable medium for causing a device to execute reduced functionality firmware to maintain operation of the device during a firmware update of the device, the reduced functionality firmware providing less functionality to the device than firmware being updated.

17. 17. The computer-readable medium of claim 16, wherein the reduced functionality firmware comprises verified reduced functionality firmware.

18. 17. The computer-readable medium of claim 16, wherein the reduced functionality firmware comprises an updated version of reduced functionality firmware that overwrites full firmware in firmware storage.

19. 19. The computer-readable medium of any one of claims 16-18, wherein the reduced functionality firmware provides one or more of reduced measurement of outputs from one or more sensors, reduced device power management functionality, limited power monitoring functionality, and / or reduced platform telemetry collection and reporting.

20. The devices may be XPUs, IPUs (infrastructure processing units), CPUs (central processing units), CPU sockets, GPUs (graphics processing units), processors, accelerator devices, BMCs (Board Management Controllers), storage controllers, memory controllers, display engines, peripheral devices, Intel® Management or MEs (Manageability Engines), AMD PSPs (Platform Security Processors), ARMs (Advanced RISC Machines) cores with TrustZone extensions, network interface devices, PCHs (Platform Controllers), The computer-readable medium of any one of claims 16 to 19, comprising one or more of the following: a network controller, a network hub, a network interface controller, a network controller application specific integrated circuit (ASIC).

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