Device and method for calibration of receiver offset

Abstract

To provide an integrated circuit for calibrating the offset between differential input terminals.SOLUTION: An integrated circuit 100 includes a plurality of signal inputs 1021 to 1026, receivers 1061 to 1066, calibration circuits 1081 to 1086, and an input switch circuit unit 104. The receiver has differential input terminals. The calibration circuit unit calibrates the input offset between the differential input terminals of the receivers in accordance with setting of the integrated circuit to a calibration mode. The input switch circuit unit switches the electrical connection between the plurality of signal inputs and the differential input terminals of the receivers in response to setting of the integrated circuit to a mode different from the calibration mode. The input switch circuit unit further electrically disconnects the plurality of signal inputs from the differential input terminals of the receivers in response to setting of the integrated circuit to the calibration mode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed technology relates generally to an apparatus and method for calibration of an offset of a receiver adapted to differential signaling.

Background Art

[0002] Differential signaling is widely used in high-speed data transmission. A receiver adapted to differential signaling may be configured to receive a pair of differential input signals and identify data transmitted by the differential input signals based on a difference in signal levels between the differential input signals. One problem with differential signaling may be the input offset of the receiver. The input offset of the receiver may cause a failure in data reception and / or reduce the tolerance to noise, jitter, signal distortion or other undesirable effects.

Summary of the Invention

[0003] This summary is provided to introduce, in a concise form, a selection of concepts that are further described below in the detailed description of the invention. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] In one or more embodiments, an integrated circuit is provided. The integrated circuit comprises a plurality of signal inputs, a receiver, a calibration circuit, and an input switch circuit. The receiver has differential input terminals. The calibration circuit is configured to calibrate the input offset between the differential input terminals of the receiver when the integrated circuit is set to calibration mode. The input switch circuit is configured to switch the electrical connection between the plurality of signal inputs and the differential input terminals of the receiver when the integrated circuit is set to a mode other than calibration mode. The input switch circuit is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver when the integrated circuit is set to calibration mode.

[0005] In one or more embodiments, a display driver is provided. The display driver comprises an interface circuit and a source driver circuit. The interface circuit comprises a plurality of signal inputs, a receiver, a calibration circuit, and an input switch circuit. The receiver comprises differential input terminals. The calibration circuit is configured to calibrate the input offset of the receiver's differential input terminals when the display driver is set to calibration mode. The input switch circuit is configured to switch the electrical connection between the plurality of signal inputs and the receiver's differential input terminals when the display driver is set to a mode other than calibration mode. The input switch circuit is further configured to electrically disconnect the plurality of signal inputs from the receiver's differential input terminals when the display driver is set to calibration mode. The source driver circuit is configured to update the display panel based on the receiver's output.

[0006] In one or more embodiments, a method for calibrating the input offset of a receiver is provided. The method includes an input switching circuit switching the electrical connection between a plurality of signal inputs and the differential input terminals of a receiver based on a communication protocol to which the transmission signals are sent to the plurality of signal inputs. The method further includes the input switching circuit electrically disconnecting the plurality of signal inputs from the differential input terminals of the receiver in a calibration step. The method further includes calibrating the input offset between the differential input terminals of the receiver in the calibration step.

[0007] Other aspects of the embodiments will be apparent from the description below and the attached claims. [Brief explanation of the drawing]

[0008] To enable a detailed understanding of the features of this disclosure, a more specific description of this disclosure, which is briefly summarized above, may be given with reference to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate exemplary embodiments of this disclosure, and since this disclosure allows for other equally valid embodiments, they should not be considered to limit the scope of the invention.

[0009] [Figure 1] Figure 1 illustrates an exemplary configuration of an integrated circuit according to one or more embodiments.

[0010] [Figure 2A] Figure 2A illustrates an exemplary detailed configuration of an integrated circuit according to one or more embodiments.

[0011] [Figure 2B] Figure 2B illustrates the exemplary operation of the input switch circuit section of the integrated circuit shown in Figure 2A, according to one or more embodiments.

[0012] [Figure 2C]FIG. 2C illustrates an exemplary operation of an input switch circuit portion of the integrated circuit illustrated in FIG. 2A according to one or more embodiments.

[0013] [Figure 3] FIG. 3 illustrates an exemplary partial configuration of an integrated circuit according to one or more embodiments.

[0014] [Figure 4] FIG. 4 illustrates an exemplary operation of an integrated circuit in calibration mode according to one or more embodiments.

[0015] [Figure 5] FIG. 5 illustrates an exemplary set of a predetermined external input offset according to one or more embodiments.

[0016] [Figure 6] FIG. 6 illustrates another exemplary set of a predetermined external input offset according to one or more embodiments.

[0017] [Figure 7A] FIG. 7A illustrates an exemplary definition of a first external input offset according to one or more embodiments. <000007*6*>

[0018] [Figure 7B] FIG. 7B illustrates an exemplary definition of a second external input offset according to one or more embodiments.

[0019] [Figure 8] FIG. 8 illustrates an exemplary input / output characteristic of a receiver before calibration according to one or more embodiments. <000008*7*>

[0020] [Figure 9] FIG. 9 illustrates an exemplary input / output characteristic of a receiver after calibration according to one or more embodiments.

[0021] [Figure 10A] FIG. 10A illustrates an exemplary configuration of a receiver and an offset generator according to one or more embodiments.

[0022] [Figure 10B] FIG. 10B illustrates an exemplary configuration of an offset generator according to one or more embodiments.

[0023] [Figure 10C] FIG. 10C illustrates an exemplary configuration of a receiver and an offset generator according to other embodiments.

[0024] [Figure 11] FIG. 11 illustrates an exemplary configuration of a counter circuit section according to one or more embodiments.

[0025] [Figure 12] FIG. 12 illustrates an exemplary intrinsic input offset of a receiver according to one or more embodiments.

[0026] [Figure 13A] FIG. 13A illustrates an exemplary output of a receiver before a calibration process according to one or more embodiments.

[0027] [Figure 13B] [[ID=

[37] ]FIG. 13B illustrates an exemplary output of a receiver during a calibration process according to one or more embodiments.

[0028] [Figure 13C] FIG. 13C illustrates an exemplary output of a receiver after a calibration process according to one or more embodiments.

[0029] [Figure 14] FIG. 14 illustrates an exemplary operation of an integrated circuit according to one or more embodiments.

[0030] [Figure 15A]Figure 15A illustrates an exemplary output of a receiver prior to the calibration process according to one or more embodiments.

[0031] [Figure 15B] Figure 15B illustrates an exemplary output of a receiver during the calibration process according to one or more embodiments.

[0032] [Figure 15C] Figure 15C illustrates an exemplary output of a receiver after a calibration process according to one or more embodiments.

[0033] [Figure 16] Figure 16 illustrates exemplary operation of an integrated circuit according to one or more embodiments.

[0034] [Figure 17A] Figure 17A illustrates an exemplary output of a receiver prior to the calibration process according to one or more embodiments.

[0035] [Figure 17B] Figure 17B illustrates an exemplary output of a receiver during the calibration process according to one or more embodiments.

[0036] [Figure 17C] Figure 17C illustrates an exemplary output of a receiver after a calibration process according to one or more embodiments.

[0037] [Figure 18] Figure 18 illustrates exemplary operation of an integrated circuit according to one or more embodiments.

[0038] [Figure 19] Figure 19 illustrates an exemplary distribution of receiver input offset before and after the calibration process in one or more embodiments.

[0039] [Figure 20] Figure 20 illustrates an exemplary configuration of a display driver according to one or more embodiments.

[0040] [Figure 21] Figure 21 illustrates an exemplary method for operating an integrated circuit according to one or more embodiments.

[0041] For ease of understanding, where possible, the same reference numerals are used to indicate identical elements common to the drawings. Elements disclosed in one embodiment are expected to be usefully used in other embodiments, even without specific mention. Reference numerals may be subscripted to distinguish identical elements from one another. Drawings referenced herein should not be understood to be dimensional unless otherwise noted. Also, for clarity of presentation and explanation, drawings are often simplified by omitting details or components. The drawings and discussions are intended to illustrate the principles discussed below, and similar numerals indicate similar elements. [Modes for carrying out the invention]

[0042] The detailed description below is essentially illustrative and is not intended to limit the disclosure or its applications and use. Furthermore, it is not intended to be bound by any explicit or implicit theory presented in the background, summary, or detailed description below.

[0043] In this application, the term “coupled” means directly connected or connected via an intermediate element or circuit.

[0044] Differential signaling, which transmits data in the form of a voltage difference between a pair of signals, is widely used for high-speed data transmission. Examples of differential signaling include mobile industry processor interface (MIPI) D-PHY, MIPI C-PHY, and low-voltage differential signaling (LVDS). An integrated circuit (IC) that supports differential signaling may include a receiver configured to receive a pair of differential input signals and identify the data being transmitted by the differential signals.

[0045] Receivers for differential signaling may have input offsets due to manufacturing variations or other causes. For example, differences in the electrical characteristics (e.g., threshold voltage and channel conductivity) between input transistors receiving differential signals in a differential input stage can cause input offsets in the receiver. Hereafter, input offsets caused by unavoidable reasons (e.g., manufacturing variations) may also be referred to as intrinsic input offsets. Intrinsic input offsets in receivers can undesirably cause data errors and / or reduce resistance to noise, jitter, signal distortion, or other undesirable effects. The effects of input offsets may be more significant in modern systems where the voltage level difference between differential input signals is very small (e.g., less than 100mV) to reduce electromagnetic interference (EMI).

[0046] On the other hand, integrated circuits are sometimes designed to support multiple differential signaling protocols. For example, in some implementations, the integrated circuit supports both MIPI D-PHY and MIPI C-PHY. Supporting multiple differential signaling protocols can effectively improve the availability of the integrated circuit.

[0047] This disclosure provides an apparatus and method for input offset calibration which may be suitable for integrated circuits that support multiple data transmission protocols. In one or more embodiments, the integrated circuit comprises a plurality of signal inputs, a receiver, a calibration circuit, and an input switch circuit. The receiver comprises differential input terminals. The calibration circuit is configured to calibrate the input offset between the differential input terminals of the receiver when the integrated circuit is set to a calibration mode. The input switch circuit is configured to switch the electrical connection between the plurality of signal inputs and the differential input terminals of the receiver when the integrated circuit is set to a mode other than the calibration mode. The input switch circuit is further configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver when the integrated circuit is set to a calibration mode.

[0048] Figure 1 illustrates an exemplary configuration of an integrated circuit 100 according to one or more embodiments. In the illustrated embodiment, the integrated circuit 100 includes a plurality of signal inputs 1021, 1022, 1023, 1024, 1025, 1026, an input switch circuit 104, a short-circuit switch circuit SW3, a plurality of receivers 1061, 1062, 1063, 1064, 1065, 1066, and a plurality of calibration circuits 1081, 1082, 1083, 1084, 1085, 1086. Signal inputs 1021 to 1026 may be collectively referred to as signal input 102 below. Similarly, receivers 1061 to 1066 may be referred to as receiver 106, and calibration circuits 1081 to 1086 may be referred to as calibration circuit 108. Figure 1 illustrates six signal inputs 1021-1026, six short-circuit switch circuits SW3, six receivers 106, and six calibration circuits 108. However, those skilled in the art will understand that the number of signal inputs 102, short-circuit switch circuits SW3, receivers 106, and calibration circuits 108 can be varied depending on the purpose and application.

[0049] The signal input 102 is configured to receive a transmit signal from an external entity of the integrated circuit 100 (e.g., a controller, host, central processing unit (CPU), application processor, or other processor). The signal input may include pads or other types of conductors. In embodiments where surface mount technology (SMT) is used to mount the integrated circuit 100 onto a substrate (e.g., a display panel, flexible wiring board, flexible resin film, or other substrate), the signal input 102 may be a surface mount pad coupled to a bump configured to be coupled to wiring on the substrate. In other embodiments, the signal input 102 may be a bonding pad coupled to bonding wires. The transmit signal supplied to the signal input 102 includes a plurality of pairs of differential signals.

[0050] The input switch circuit 104 is configured to switch the electrical connection between the signal input 102 and the differential input terminals of the receiver 106. In various embodiments, the input switch circuit 104 is configured to switch the electrical connection to supply different pairs of differential signals to different receivers 106 according to a data transmission protocol used to supply a transmit signal to the integrated circuit 100. The input switch circuit 104 may be configured to electrically connect two selected signal inputs 102 to the differential input terminals of a receiver 106, based on a communication protocol to which a transmit signal is sent to a plurality of signal inputs 102. The input switch circuit 104 may electrically connect two of a first combination of signal inputs 102 to the differential input terminals of a receiver 106 to achieve data transmission according to a first protocol. The input switch circuit 104 may further be configured to electrically connect two of a second combination of signal inputs 102 to the differential input terminals of the receiver 106 to achieve data transmission according to a second protocol, where the second combination is different from the first combination. In one implementation, the first protocol may be the MIPI D-PHY protocol, and the second protocol may be the MIPI C-PHY protocol.

[0051] Each receiver 106 is configured to receive a pair of differential signals at its differential input terminal and to output a single-ended signal corresponding to the data transmitted by the received pair of differential signals. One of the differential input terminals of each receiver 106 is a non-inverting input terminal indicated by “+” in Figure 1, and the other is an inverting input terminal indicated by “-”. In some embodiments, each receiver 106 is configured to set its output to a high level (“H”) depending on whether the voltage level of the non-inverting input terminal is higher than the voltage level of the inverting input terminal, and to set its output to a low level (“L”) depending on whether the voltage level of the non-inverting input terminal is lower than the voltage level of the inverting input terminal. In other embodiments where the single-ended signal is low-active, each receiver 106 may be configured to set its output to a low level (“L”) depending on whether the voltage level of the non-inverting input terminal is higher than the voltage level of the inverting input terminal, and each receiver may be configured to set its output to a high level (“H”) depending on whether the voltage level of the non-inverting input terminal is lower than the voltage level of the inverting input terminal.

[0052] Each short-circuit switch circuit SW3 is coupled to a receiver 106 and configured to short-circuit the corresponding differential input terminal of the receiver 106. In one implementation, the short-circuit switch SW3 is configured to short-circuit the corresponding differential input terminal of the receiver 106 to a ground voltage. In other embodiments, the short-circuit switch SW3 may be configured to short-circuit the corresponding differential input terminal of the receiver 106 to a common-mode voltage which may be fixed. In the illustrated embodiment, each short-circuit switch circuit SW3 comprises a pair of switch elements coupled to the corresponding differential input terminal of the receiver 106, the switch elements configured to short-circuit the differential input terminal to circuit ground.

[0053] Calibration circuits 1081-1086 are configured to calibrate the input offset of the corresponding receivers 1061-1066, respectively. An ideal receiver 106 with an intrinsic input offset of 0V is configured to change or invert its output between "H" and "L" when the input voltage across its differential input terminals crosses 0V. However, due to manufacturing processes or other causes, a real receiver 106 may change its output at input voltages different from 0V. The input offset of a receiver 106 may refer to the input voltage at which the receiver 106 changes its output between "H" and "L". In various embodiments, calibration circuit 108 is configured to calibrate the corresponding receiver 106 by generating an extrinsic input offset and applying it to the differential input terminals of the corresponding receiver 106, thereby mitigating or canceling out the intrinsic input offset of the receiver 106.

[0054] In various embodiments, the calibration of the receiver 106 is performed in calibration mode. Calibration circuits 1081-1086 may be configured to perform calibration of the corresponding receivers 1061-1066 in response to the integrated circuit 100 being set to calibration mode. In such embodiments, the input switch circuit 104 may be configured to electrically disconnect the signal input 102 from the differential input terminal of the receiver 106 in response to the integrated circuit 100 being set to calibration mode, and the short-circuit switch circuit SW3 may be configured to short-circuit the differential input terminal of the receiver 106 to a ground voltage or common-mode voltage in response to the integrated circuit 100 being set to calibration mode. The input switch circuit 104 may further be configured to switch the electrical connection between the signal input 102 and the differential input terminal of the receiver 106 in response to the integrated circuit 100 being set to a mode other than calibration mode.

[0055] Figure 2A illustrates a detailed exemplary configuration of an input switch circuit 104 according to one or more embodiments. In the embodiments illustrated in Figure 2A, the integrated circuit 100 supports two data transmission protocols, MIPI D-PHY and MIPI C-PHY. The input switch circuit 104 includes a D-PHY switch circuit SW1 and a C-PHY switch circuit SW2. Each D-PHY switch circuit SW1 may include a pair of switch elements coupled to the differential input terminal of the corresponding receiver 106. The D-PHY switch circuit SW1 is configured to turn on when data is transmitted to the integrated circuit 100 by the MIPI D-PHY protocol. Each C-PHY switch SW2 may include a pair of switch elements coupled to the differential input terminal of the corresponding receiver 106. The C-PHY switch circuit SW2 is configured to turn on when data is transmitted by the MIPI C-PHY protocol.

[0056] In the illustrated embodiment, the electrical connections in the input switch circuit section 104 are as follows: The non-inverting input terminal and inverting input terminal of receiver 1061 are coupled to signal inputs 1021 and 1022, respectively, via the corresponding D-PHY switch circuit SW1, and further coupled to signal inputs 1021 and 1022, respectively, via the corresponding C-PHY switch circuit SW2. The non-inverting input terminal and inverting input terminal of receiver 1062 are coupled to circuit ground via the corresponding D-PHY switch circuit SW1, and further coupled to signal inputs 1023 and 1021, respectively, via the corresponding C-PHY switch circuit SW2. The non-inverting input terminal and inverting input terminal of receiver 1063 are coupled to signal inputs 1023 and 1024, respectively, via the corresponding D-PHY switch circuit SW1, and further coupled to signal inputs 1023 and 1021, respectively, via the corresponding C-PHY switch circuit SW2. The non-inverting and inverting input terminals of receiver 1064 are connected to circuit ground via the corresponding D-PHY switch circuit SW1 and to signal inputs 1024 and 1025, respectively, via the corresponding C-PHY switch circuit SW2. The non-inverting and inverting input terminals of receiver 1065 are connected to signal inputs 1025 and 1026 via the corresponding D-PHY switch circuit SW1 and to signal inputs 1026 and 1024, respectively, via the corresponding C-PHY switch circuit SW2. The non-inverting and inverting input terminals of receiver 1066 are connected to circuit ground via the corresponding D-PHY switch circuit SW1 and to signal inputs 1025 and 1026, respectively, via the corresponding C-PHY switch circuit SW2.

[0057] Figure 2B illustrates the exemplary operation of the input switch circuit section 104 in D-PHY mode according to one or more embodiments. Here, D-PHY mode is a mode in which D-PHY transmission signals are transmitted to the integrated circuit 100 according to the MIPI D-PHY protocol. In the illustrated embodiment, the integrated circuit 100 receives a first pair of differential data signals D0+ and D0-, a pair of differential clock signals CLK+ and CLK-, and a second pair of differential data signals D1+ and D1- at signal inputs 1021 to 1026 in D-PHY mode.

[0058] In D-PHY mode, the D-PHY switch circuit SW1 of the input switch circuit section 104 is turned on, and the C-PHY switch circuit SW2 is turned off. Receiver 1061 receives a pair of differential data signals D0+ and D0- from signal inputs 1021 and 1022 via the corresponding D-PHY switch circuit SW1, and outputs a single-ended signal D0 corresponding to the differential data signals D0+ and D0-. Receiver 1062 is not used in D-PHY mode, and its differential input terminal is coupled to ground via the corresponding D-PHY switch circuit SW1. Receiver 1063 receives a pair of differential clock signals CLK+ and CLK- from signal inputs 1023 and 1024 via the corresponding D-PHY switch circuit SW1, and outputs a single-ended clock signal CLK corresponding to the differential clock signals CLK+ and CLK-. Receiver 1064 is not used in D-PHY mode, and its differential input terminal is coupled to ground via the corresponding D-PHY switch circuit SW1. Receiver 1065 receives a pair of differential data signals D1+ and D1- from signal inputs 1025 and 1026 via the corresponding D-PHY switch circuit SW1 and outputs a single-ended data signal D1 corresponding to the differential data signal D1+ and D1- pair. Receiver 1066 is not used in D-PHY mode, and its differential input terminal is coupled to ground via the corresponding D-PHY switch circuit SW1. A single-ended clock signal CLK may be used to latch the single-ended data signals D1 and D2 in a subsequent stage (not shown) coupled to the output of receiver 106.

[0059] Figure 2C illustrates exemplary operation of the input switch circuit 104 in C-PHY mode according to one or more embodiments. Here, C-PHY mode is a mode in which C-PHY transmission signals are transmitted to the integrated circuit 100 according to the MIPI C-PHY protocol. In the illustrated embodiment, in C-PHY mode, the integrated circuit 100 receives a first set of data signals A0, B0, and C0 and a second set of data signals A1, B1, and C1 at signal inputs 1021 to 1026. All pairs of data signals A0, B0, and C0 are used as pairs of differential signals in which data is encoded in the form of a voltage difference. Similarly, all pairs of data signals A1, B1, and C1 are used as pairs of differential signals in which data is encoded in the form of a voltage difference.

[0060] In C-PHY mode, the C-PHY switch circuit SW2 of the input switch circuit section 104 is turned on, and the D-PHY switch circuit SW1 is turned off. Receiver 1061 receives data signals A0 and B0 from signal inputs 1021 and 1022, respectively, via the corresponding C-PHY switch circuit SW2, and outputs a single-ended data signal AB0 corresponding to the voltage difference between data signals A0 and B0. Receiver 1062 receives data signals C0 and A0 from signal inputs 1023 and 1021, respectively, via the corresponding C-PHY switch circuit SW2, and outputs a single-ended data signal CA0 corresponding to the voltage difference between data signals C0 and A0. Receiver 1063 receives data signals B0 and C0 from signal inputs 1022 and 1023, respectively, via the corresponding C-PHY switch circuit SW2, and outputs a single-ended data signal BC0 corresponding to the voltage difference between data signals B0 and C0. Receiver 1064 receives data signals A1 and B1 from signal inputs 1024 and 1025, respectively, via the corresponding C-PHY switch circuit SW2, and outputs a single-ended data signal AB1 corresponding to the voltage difference between data signals A1 and B1. Receiver 1065 receives data signals C1 and A1 from signal inputs 1026 and 1024, respectively, via the corresponding C-PHY switch circuit SW2, and outputs a single-ended data signal CA1 corresponding to the voltage difference between data signals C1 and A1. Receiver 1066 receives data signals B1 and C1 from signal inputs 1025 and 1026, respectively, via the corresponding C-PHY switch circuit SW2, and outputs a single-ended data signal BC1 corresponding to the voltage difference between data signals B1 and C1.

[0061] Figure 3 illustrates an exemplary partial configuration of an integrated circuit 100 according to one or more embodiments. Illustrated in Figure 3 is a portion relating to a single receiver 106, which comprises a D-PHY switch circuit SW1, a C-PHY switch circuit SW2, a short-circuit switch circuit SW3, and a calibration circuit 108. The D-PHY switch circuit SW1 is configured to provide an electrical connection between the differential input terminals of the receiver 106 and two signal inputs 102 that receive a pair of D-PHY transmit signals in D-PHY mode, and the C-PHY switch circuit SW2 is configured to provide an electrical connection between the differential input terminals of the receiver 106 and two signal inputs 102 that receive a pair of C-PHY transmit signals in C-PHY mode.

[0062] In one or more embodiments, the integrated circuit 100 responds to a D-PHY mode signal D-PHY_Mode and a C-PHY mode signal C-PHY_Mode. The D-PHY mode signal D-PHY_Mode is activated in D-PHY mode, and the C-PHY mode signal C-PHY_Mode is activated in C-PHY mode. The D-PHY switch circuit SW1 is configured to turn on in response to the activation of the D-PHY mode signal D-PHY_Mode, and the C-PHY switch circuit SW2 is configured to turn on in response to the C-PHY mode signal C-PHY_Mode.

[0063] The integrated circuit 100 further responds to the calibration mode signal CAL_Mode, which is activated in calibration mode. The calibration circuit 108 is configured to perform calibration of the receiver 106 in calibration mode in response to the activation of the calibration mode signal CAL_Mode.

[0064] Figure 4 illustrates exemplary operation of the integrated circuit 100 in calibration mode according to one or more embodiments. In calibration mode, the calibration mode signal CAL_Mode is activated, while the D-PHY mode signal D-PHY_Mode and the C-PHY mode signal C-PHY_Mode are deactivated. The D-PHY switch circuit SW1 and the C-PHY switch circuit SW2 are turned off in response to the deactivation of the D-PHY mode signal D-PHY_Mode and the C-PHY mode signal C-PHY_Mode, electrically disconnecting the receiver 106 from the signal input 102. Furthermore, the short-circuit switch circuit SW3 is turned on in response to the activation of the calibration mode signal CAL_Mode, short-circuiting the differential input terminals of the receiver 106 to ground voltage.

[0065] In calibration mode, the calibration circuit 108 calibrates the input offset of the receiver 106 with the differential input terminals of the receiver 106 short-circuited by the short-circuit switch circuit SW3. In one implementation, the calibration process may include searching for the optimal extrinsic input offset that can be applied to the differential input terminals of the receiver 106 to mitigate or offset the intrinsic input offset of the receiver 106 with the differential input terminals of the receiver 106 short-circuited by the short-circuit switch circuit SW3. Searching for the optimal extrinsic input offset may include monitoring the output of the receiver 106 while varying the extrinsic input offset generated by the calibration circuit 108. The calibration circuit 108 may further determine the optimal extrinsic input offset that mitigates or offsets the intrinsic input offset of the receiver 106 based on the change in the output of the receiver 106. If the receiver 106 is ideally manufactured and its intrinsic input offset is 0V, the output of the receiver 106 will vary between H and L as the extrinsic input offset crosses 0V. In this case, the optimal extrinsic input offset may be determined to be 0V. If the intrinsic input offset of receiver 106 is not 0V, the output of receiver 106 changes when the extrinsic input offset crosses a voltage value that cancels out the intrinsic input offset. The optimal extrinsic input offset is determined based on the change in the output of receiver 106 to cancel out or mitigate the intrinsic input offset of receiver 106 at least partially.

[0066] In one or more embodiments, the calibration circuit 108 comprises an offset generator 110 and a counter circuit 112. The offset generator 110 is configured to adjust the input offset of the receiver 106 by generating an extrinsic input offset based on the count value received from the counter circuit 112 and applying it to the differential input terminal of the receiver 106. The counter circuit 112 is coupled to the output of the receiver 106 and is configured to count the count value in synchronization with a calibration clock signal CLK_CAL, which may be supplied from a clock generator (not shown). In some embodiments, the counter circuit 112 may be configured to count up (or increment) the count value from zero to a predetermined value in synchronization with the calibration clock signal CLK_CAL. In other embodiments, the counter circuit 112 may be configured to count down (or decrement) the count value from a predetermined value to zero in synchronization with the calibration clock signal CLK_CAL. The counter circuit 112 may receive a calibration mode signal CAL_Mode and be configured to start counting in response to the activation of the calibration mode signal CAL_Mode. The counter circuit 112 may also be configured to monitor the output of the receiver 106 and stop counting in response to changes in the output of the receiver 106.

[0067] In some embodiments, the offset generator 110 may be configured to select one of a plurality of predetermined extrinsic input offsets based on the count value received from the counter circuit 112, and to apply the selected extrinsic input offset to the differential input terminals of the receiver 106 to mitigate or cancel out the intrinsic input offset. Figure 5 illustrates an exemplary set of predetermined extrinsic input offsets according to one or more embodiments. In Figure 5, the exemplary predetermined extrinsic input offsets are illustrated in the form of input voltages of the receiver 106 that cause a change in the output of the receiver 106 for each allowable count value of the counter circuit 112. The input voltage here refers to the voltage between the differential input terminals of the receiver 106 (e.g., the non-inverting input terminal and the inverting input terminal). The predetermined extrinsic input offsets may be defined by equal increments. In the illustrated embodiment, the allowable count values ​​of the counter circuit 112 are "0", "1", and "2", and the predetermined extrinsic input offsets corresponding to the count values ​​"0", "1", and "2" are defined as "-ΔVoff", "0V", and "ΔVoff", respectively, with equal increments ΔVoff. For example, when the count value of the counter circuit 112 is "0", the offset generator 110 selects the extrinsic input offset "-ΔVoff" and applies the extrinsic input offset "-ΔVoff" to the differential input terminal of the receiver 106. The same applies to the count values ​​"1" and "2".

[0068] The number of predetermined extrinsic input offsets is not limited to three and can be changed. Figure 6 illustrates another exemplary set of predetermined extrinsic input offsets according to one or more embodiments. In the illustrated embodiments, the allowable count values ​​of the counter circuit 112 are "0", "1", "2", "3", and "4", and the predetermined extrinsic input offsets corresponding to the count values ​​"0", "1", "2", "3", and "4" are "-2ΔVoff", "-ΔVoff", "0V", "ΔVoff", and "2ΔVoff", respectively. Note that, in the embodiments illustrated in Figure 6 as well, the predetermined extrinsic input offsets are defined in equal increments. By increasing the number of predetermined extrinsic input offsets used, it may be possible to finer control the input offset of the receiver 106.

[0069] In one or more embodiments, the offset generator 110 may be configured to define a first set of extrinsic input offsets for a calibration mode and a second set of extrinsic input offsets for other operating modes, including D-PHY mode and C-PHY mode. Here, each of the second extrinsic input offsets is defined by shifting the corresponding one of the first extrinsic input offsets by a predetermined shift amount. The first extrinsic input offsets may be defined by equal increments, and the predetermined shift amount may be half of the equal increments.

[0070] Figure 7A illustrates an exemplary definition of a first extrinsic input offset for a calibration mode, and Figure 7B illustrates an exemplary definition of a second extrinsic input offset for other operating modes according to one or more embodiments. In the embodiment illustrated in Figure 7A, the allowable count values ​​of the counter circuit 112 are "0", "1", and "2", and the first extrinsic input offset may be defined as "-0.5ΔVoff", "0.5ΔVoff", and "1.5ΔVoff" for count values ​​"0", "1", and "2", respectively, with equal increments ΔVoff. Note that below, the first extrinsic input offsets corresponding to count values ​​"0" and "1" may be referred to as "-Vcal" and "+Vcal", respectively. As illustrated in Figure 7B, the second extrinsic input offset may be defined by shifting the corresponding first extrinsic input offset by a shift amount of 0.5ΔVoff. In the illustrated embodiment, the second extrinsic input offset may be defined as "-ΔVoff", "0V", and "ΔVoff" for count values ​​"0", "1", and "2", respectively.

[0071] The offset generator 110 may be configured to apply one of the first extrinsic input offsets selected from the first set of extrinsic input offsets to the differential input terminal of the receiver 106 in calibration mode, while applying one of the second extrinsic input offsets selected from the first set of extrinsic input offsets to the differential input terminal of the receiver 106 in other operating modes, including D-PHY mode and C-PHY mode. In one implementation, as illustrated in Figure 3, the offset generator 110 may be configured to receive an offset shift signal Offset_Shift from the counter circuit 112 and to switch between the first extrinsic input offset and the second extrinsic input offset based on the offset shift signal Offset_Shift. In one implementation, the counter circuit 112 may be configured to generate the offset shift signal Offset_Shift based on whether the integrated circuit 100 is set to calibration mode. The counter circuit 112 may be configured to set the offset shift signal Offset_Shift to "1" in response to the integrated circuit 100 being set to calibration mode (for example, in response to the activation of the calibration mode signal CAL_Mode), and the offset generator 110 may be configured to apply a selected from the first extrinsic input offsets to the differential input terminal of the receiver 106 in response to the offset shift signal Offset_Shift being set to "1". The counter circuit 112 may also be configured to set the offset shift signal Offset_Shift to "0" in response to the integrated circuit 100 being set to another operating mode (for example, in response to the deactivation of the calibration mode signal CAL_Mode), and the offset generator 110 may be configured to apply a selected from the second extrinsic input offsets to the differential input terminal of the receiver 106 in response to the offset shift signal Offset_Shift being set to "0".

[0072] In one implementation, the offset generator 110 and the counter circuit 112 may be configured to determine an optimal count value for the counter circuit 112 in calibration mode and to adjust the input offset of the receiver 106 by applying one of a second set of extrinsic input offsets corresponding to the optimal count value in other operating modes, including D-PHY mode and C-PHY mode. The offset generator 110 may be configured to sequentially select a first extrinsic input offset in calibration mode as the count value of the counter circuit 112 counts up or down, and to sequentially apply the selected first extrinsic input offset to the differential input terminal of the receiver 106. The counter circuit 112 may be configured to stop counting the count value in response to a change in the output of the receiver 106 and to determine an optimal count value as the count value held by the counter circuit 112 when counting stops. The offset generator 110 may be configured to adjust the input offset between the differential input terminals of the receiver 106 in D-PHY mode and C-PHY mode by selecting one of a second set of extrinsic input offsets based on the optimal count value received from the counter circuit 112, and applying the selected one of the second set of extrinsic input offsets to the differential input terminals of the receiver 106.

[0073] Figures 8 and 9 illustrate exemplary calibration steps for the input offset of receiver 106 according to one or more embodiments. In the embodiment shown in Figure 8, which illustrates exemplary input / output characteristics of receiver 106 before calibration, receiver 106 exhibits an intrinsic input offset of Vx1 close to ΔVoff. In other words, before calibration, receiver 106 is configured to change its output at the same input voltage as Vx1. In this case, as shown in Figure 9, the input offset of receiver 106 can be made closer to 0V by setting the counter value to "0".

[0074] Figure 10A illustrates an exemplary configuration of a receiver 106 and an offset generator 110 according to one or more embodiments. In the illustrated embodiment, the receiver 106 comprises p-channel metal oxide semiconductor (PMOS) transistors MP1, MP2, MP3, MP4, n-channel metal oxide semiconductor (NMOS) transistors MN1, MN2, MN3, MN4, a constant current source 122, and a buffer 124.

[0075] The PMOS transistors MP1 and MP2, NMOS transistors MN1 and MN2, and constant current source 122 are collectively configured as a differential input stage that receives a pair of differential input signals at the non-inverting input terminal IN+ and the inverting input terminal IN-. The gate of PMOS transistor MP1 is coupled to the non-inverting input terminal IN+, and the gate of PMOS transistor MP2 is coupled to the inverting input terminal IN-. The sources of PMOS transistors MP1 and MP2 are commonly coupled to the constant current source 122. The constant current source 122 is configured to supply a constant current to the commonly coupled sources of PMOS transistors MP1 and MP2. The NMOS transistors MN1 and MN2 are diode-connected. The drain and gate of NMOS transistor MN1 are coupled to the drain of PMOS transistor MP1, and the source of NMOS transistor MN1 is coupled to the low-potential-side power supply line 126, which generates the low-potential-side power supply voltage VSS. In one implementation, the low-potential-side power supply voltage VSS may be the ground voltage. The drain and gate of the NMOS transistor MN2 are coupled to the drain of the PMOS transistor MP2, and the source of the NMOS transistor MN2 is coupled to the low-potential side power line 126.

[0076] The PMOS transistors MP3 and MP4 and the NMOS transistors MN3 and MN4 are collectively configured as an active load to generate a voltage corresponding to the voltage difference between the differential input signals supplied to the non-inverting input terminal IN+ and the inverting input terminal IN-. The PMOS transistors MP3 and MP4 are collectively configured as a current mirror. The sources of the PMOS transistors MP3 and MP4 are commonly coupled to a high-potential-side power supply line 128, which generates a high-potential-side power supply voltage VDD, where the high-potential-side power supply voltage VDD is higher than the low-potential-side power supply voltage VSS. The gates of the PMOS transistors MP3 and MP4 are commonly coupled to the drain of the PMOS transistor MP3. The drain of the NMOS transistor MN3 is coupled to the drain of the PMOS transistor MP3, and the gate of the NMOS transistor MN3 is coupled to the drain of the diode-connected NMOS transistor MN1. The drain of the NMOS transistor MN4 is coupled to the drain of the PMOS transistor MP4, and the gate of the NMOS transistor MN4 is coupled to the drain of the diode-connected NMOS transistor MN2. The sources of NMOS transistors MN3 and MN4 are commonly coupled to the low-potential power supply line 126.

[0077] Buffer 124 is configured to generate a single-ended signal corresponding to the differential input signal in response to the voltage generated at the drain of the NMOS transistor MN4. Buffer 124 may include a complementary metal-oxide-semiconductor (CMOS) buffer.

[0078] The receiver 106 configured in this way may have an intrinsic input offset due to the manufacturing process. For example, differences in the electrical characteristics (e.g., threshold voltage and channel conductivity) between PMOS transistors MP1 and MP2 may cause an intrinsic input offset. To mitigate or eliminate the effects of the intrinsic input offset, the offset generator 110 is configured to generate an extrinsic input offset and apply it to the differential input of the receiver 106 to cancel out the intrinsic input offset.

[0079] In the illustrated embodiment, the offset generator 110 comprises PMOS transistors MP5 and MP6, a constant current source 132, variable voltage generators 134 and 136, and a controller 138. The sources of PMOS transistors MP5 and MP6 are commonly coupled to the constant current source 132. The constant current source 132 is configured to supply a constant current to the sources of PMOS transistors MP5 and MP6. The drain of PMOS transistor MP5 is coupled to the drain of diode-connected NMOS transistor MN1 and the gate of NMOS transistor MN3, and the drain of PMOS transistor MP6 is coupled to the drain of diode-connected NMOS transistor MN2 and the gate of NMOS transistor MN4. Variable voltage generator 134 is configured to apply a first variable gate voltage to the gate of PMOS transistor MP5, and variable voltage generator 136 is configured to apply a second variable gate voltage to the gate of PMOS transistor MP6. The controller 138 is configured to control the first and second gate voltages applied to the gates of PMOS transistors MP5 and MP6 based on the count value and offset shift signal Offset_Shift received from the counter circuit section 112 (shown in Figure 3).

[0080] The offset generator 110 in Figure 10A is configured to control the current flowing through diode-connected NMOS transistors MN1 and MN2 by controlling the first and second variable gate voltages applied to PMOS transistors MP5 and MP6. By controlling the current flowing through the diode-connected NMOS transistors MN1 and MN2, an extrinsic input offset is generated as indicated by the count value received from the counter circuit 112 and the offset shift signal Offset_Shift, and applied to the differential input terminal of the receiver 106.

[0081] Figure 10B illustrates another exemplary configuration of an offset generator according to one or more embodiments. The offset generator is denoted by reference numeral 110A. In the illustrated embodiment, the offset generator 110A comprises a pair of variable resistors 142, 144 and a controller 146. Variable resistor 142 is coupled between the source of a PMOS transistor MP1 and a constant current source 122, and variable resistor 144 is coupled between the source of a PMOS transistor MP2 and a constant current source 122. The controller 146 is configured to control the resistances of variable resistors 142 and 144 based on a count value and an offset shift signal received from a counter circuit 112 (illustrated in Figure 3).

[0082] The offset generator 110A in Figure 10B is configured to control the current flowing through diode-connected NMOS transistors MN1 and MN2 by controlling the resistance of variable resistors 142, 142. By controlling the current flowing through diode-connected NMOS transistors MN1 and MN2, an extrinsic input offset is generated as indicated by the count value and the offset shift signal Offset_Shift, and applied to the differential input terminal of receiver 106.

[0083] Figure 10C illustrates another exemplary configuration of the receiver and offset generator in another embodiment. The receiver is indicated by reference numeral 106B, and the offset generator is indicated by reference numeral 110B. The receiver 106B is configured as a sampling latch that operates synchronously with the clock signal CLK. In the illustrated embodiment, the receiver 106B comprises PMOS transistors MN11, MN12, MN13, MN14, and MN15, and NMOS transistors MN11, MN12, MN13, MN14, MN15, and MN16.

[0084] The PMOS transistor MP11 and the NMOS transistors MN11, MN12, MN15, and MN16 are configured to activate the operation of the receiver 106B in synchronization with the clock signal CLK. The PMOS transistor MP11 has a gate to which the clock signal CLK is supplied and a source coupled to the high-potential-side power line 152 from which the high-potential-side power supply voltage VDD is generated. The PMOS transistor MP11 is configured to supply the high-potential-side power supply voltage VDD to the commonly connected source of the PMOS transistors MP12 and MP13 in response to the pull-down of the clock signal CLK. The NMOS transistor MN11 has a gate to which the clock signal CLK is supplied, a drain coupled to the drain of the PMOS transistor MP12, and a source coupled to the low-potential-side power line 154 from which the low-potential-side power supply voltage VSS is generated. The NMOS transistor MN12 has a gate to which the clock signal CLK is supplied, a drain coupled to the drains of the PMOS transistor MP14 and the NMOS transistor MN13, and a source coupled to the low-potential-side power line 154. NMOS transistor MN15 has a gate to which the clock signal CLK is supplied, a drain coupled to the drains of PMOS transistor MP15 and NMOS transistor MN14, and a source coupled to the low-potential power supply line 154. NMOS transistor MN16 has a gate to which the clock signal CLK is supplied, a drain coupled to the drain of PMOS transistor MP13, and a source coupled to the low-potential power supply line 154.

[0085] The PMOS transistors MP12, MP13, MP14 and the NMOS transistors MN13, MN14 are collectively configured to generate a pair of output signals at output terminals OUT+ and OUT- in response to differential input signals supplied to the non-inverting input terminal IN+ and the inverting input terminal IN-. PMOS transistor MP12 has a gate coupled to the non-inverting input terminal IN+, and PMOS transistor MP13 has a gate coupled to the inverting input terminal IN-. The sources of PMOS transistors MP12 and MP13 are commonly coupled to the drain of PMOS transistor MP11. PMOS transistors MP14, MP15 and NMOS transistors MN13, MN14 are collectively configured as a cross-coupled inverter. PMOS transistor MP14 has a source coupled to the drain of PMOS transistor MP12 and a drain coupled to the drain of NMOS transistor MN13. PMOS transistor MP15 has a source coupled to the drain of PMOS transistor MP13 and a drain coupled to the drain of NMOS transistor MN14. The sources of NMOS transistors MN13 and MN14 are commonly coupled to the low-potential power supply line 154. The gates of PMOS transistor MP14 and NMOS transistor MN13 are commonly coupled to the drains of PMOS transistor MP15 and NMOS transistor MN14. The gates of PMOS transistor MP15 and NMOS transistor MN14 are commonly coupled to the drains of PMOS transistor MP14 and NMOS transistor MN13. The drains of PMOS transistor MP14 and NMOS transistor MN13 are commonly coupled to the output terminal OUT-, and the drains of PMOS transistor MP15 and NMOS transistor MN14 are commonly coupled to the output terminal OUT+. Output signals are generated at output terminals OUT+ and OUT-. In one implementation, output terminals OUT+ and OUT- may be coupled to an output buffer (not shown) configured to generate single-ended signals corresponding to differential input signals supplied to the non-inverting input terminal IN+ and the inverting input terminal IN-.

[0086] In the embodiment shown in Figure 10C, the offset generator 110B comprises variable capacitors 156 and 158 and a controller 160. Variable capacitor 156 is coupled between the drain of PMOS transistor MP12 and the low-potential power line 154, and variable capacitor 158 is coupled between the drain of PMOS transistor MP13 and the low-potential power line 154. The controller 160 is configured to control the capacitances of variable capacitors 156 and 158 based on the count value and offset shift signal Offset_Shift received from the counter circuit 112 (shown in Figure 3). The offset generator 110B in Figure 10C is configured to control the capacitances of variable capacitors 156 and 158, thereby generating an extrinsic input offset as indicated by the count value and offset shift signal Offset_Shift received from the counter circuit 112 and applying it to the differential input terminal of receiver 106B.

[0087] Figure 11 illustrates an exemplary configuration of a counter circuit 112 according to one or more embodiments. In the illustrated embodiment, the counter circuit 112 is configured as a 2-bit counter comprising an inverter 162, an OR gate 164, an inverter 166, an AND gate 168, an SR flip-flop 170, an AND gate 172, D flip-flops 174 and 176, inverters 178 and 180, and an AND gate 182.

[0088] Inverter 162, OR gate 164, inverter 166, AND gate 168, SR flip-flop 170, and AND gate 172 together constitute a gating circuit that performs gating of the calibration clock signal CLK_CAL based on the output of receiver 106, the calibration mode signal CAL_Mode, and the count value held by the counter circuit 112. Inverter 162 is configured to receive the output of receiver 106. OR gate 164 has a first input coupled to the output of inverter 162 and a second input coupled to the data output Q of D flip-flop 176. Note that the data output Q of D flip-flop 176 is set to "H" when the count value held by the counter circuit 112 is "2" or greater. Inverter 166 has an input that receives the calibration mode signal CAL_Mode and an output coupled to the set input S of SR flip-flop 170. The AND gate 168 has a first input coupled to the output of the OR gate 164, a second input that receives the calibration mode signal CAL_Mode, and an output coupled to the reset input R of the SR flip-flop 170. The data output Q of the SR flip-flop 170 is coupled to the first input of the AND gate 172 and also to the first input of the AND gate 182. The AND gate 172 is configured to gate the calibration clock signal CLK_CAL. The AND gate 172 is configured to supply the calibration clock signal CLK_CAL to the D flip-flop 174 when the data output Q of the SR flip-flop 170 is set to "H".

[0089] The D flip-flops 174 and 176 and inverters 178 and 180 are configured together to perform a 2-bit counter operation in synchronization with the calibration clock signal CLK_CAL received via the AND gate 172. The D flip-flop 174 has a clock input CK coupled to the output of the AND gate 172, a data output Q coupled to the input of inverter 178, and a data input D coupled to the output of inverter 178. The D flip-flop 176 has a clock input CK coupled to the output of inverter 178, a data output Q coupled to the input of inverter 180, and a data input D coupled to the output of inverter 180. The data output Q of the D flip-flop 174 is used as the lower bit of the 2-bit count value (indicated as “Count[0]” in Figure 11), and the data output Q of the D flip-flop 176 is used as the higher bit of the 2-bit count value (indicated as “Count[1]” in Figure 11). The D flip-flops 174 and 176 further have a reset input RB configured to receive a calibration mode signal CAL_Mode.

[0090] The AND gate 182 has a first input coupled to the data output Q of the SR flip-flop 170, and a second input that receives the calibration mode signal CAL_Mode. The output signal of the AND gate 182 is used as the offset shift signal Offset_Shift.

[0091] The counter circuit 112 in Figure 11 is configured to start counting when the calibration mode signal CAL_Mode is set to "H" (or activated), to stop counting when the output of the receiver 106 changes from "H" to "L", and to stop counting when the count value reaches "2". More specifically, when the integrated circuit 100 is not in calibration mode, the D flip-flops 174 and 176 are reset when the calibration mode signal CAL_Mode is set to "L" (or deactivated), and the count value is reset to "0". On the other hand, the SR flip-flop 170 is set when the calibration mode signal CAL_Mode is set to "L", and allows the calibration clock signal CLK_CAL to be supplied to the D flip-flop 174. When the calibration mode signal CAL_Mode is subsequently set to "H" (or activated) to set the integrated circuit 100 to calibration mode, the counter circuit 112 starts counting the count value in response to the reset inputs of the D flip-flops 174 and 176 being set to "H". The counter circuit 112 continues counting the count value until the output of the receiver 106 is set to "L" or the SR flip-flop 170 is reset in response to the count value reaching "2". Note that when the SR flip-flop 170 is reset, the supply of the calibration clock signal CLK_CAL to the D flip-flop 174 stops.

[0092] Below, we will describe the exemplary operation of the integrated circuit 100, including the counter circuit section 112 shown in Figure 11, for the following three cases (see also Figure 12). Case #1) When the intrinsic input offset of receiver 106 is Va, which is lower than -Vcal. Case #2) When the intrinsic input offset of receiver 106 is Vb, which is between -Vcal and +Vcal. Case #3) When the intrinsic input offset of receiver 106 is Vc, which is higher than +Vcal. Note that -Vcal and +Vcal are the first extrinsic input offset voltages used in the calibration modes for count values ​​"0" and "1," as illustrated in Figure 7A.

[0093] Figures 13A, 13B, 13C, and 14 illustrate exemplary operation of the integrated circuit 100 in case #1 according to one or more embodiments. Figure 13A illustrates an exemplary output of the receiver 106 before calibration. In the illustrated embodiment, the receiver 106 before calibration is configured such that its output changes between "L" and "H" when the input voltage of the receiver 106 crosses a voltage Va lower than 0V. When the calibration process begins, the counter circuit 112 starts counting up in response to the calibration mode signal CAL_Mode being set to "H", as shown in Figure 14. During the count-up, the offset generator 110 successively changes the extrinsic input offset applied to the differential input terminals of the receiver 106 in accordance with the count-up of the count value, changing the input voltage at which the output of the receiver 106 changes from "H" to "L", as shown in Figure 13B. The differential input terminals of receiver 106 are short-circuited by the short-circuit switch circuit SW3 when the calibration mode signal CAL_Mode is set to "H", so the output of receiver 106 is measured for the input voltage of 0V. As illustrated in Figure 14, the output of receiver 106 is "H" for count values ​​"0" and "1", so the count value of counter circuit 112 reaches "2" without the output of receiver 106 changing from "H" to "L". Therefore, as a result of the calibration process, the count value of counter circuit 112 is set to "2". After the calibration process, the offset generator 110 generates an extrinsic input offset corresponding to the count value "2" and applies it to the differential input terminals of receiver 106. Figure 13C illustrates an exemplary output of receiver 106 after the calibration process. Since the final input offset of receiver 106 is the sum of the intrinsic input offset of receiver 106 and the extrinsic input offset generated by the offset generator 110, the calibration process at least partially cancels out the intrinsic input offset of receiver 106.

[0094] Figures 15A, 15B, 15C, and 16 illustrate exemplary operation of the integrated circuit 100 in case #2 according to one or more embodiments. Figure 15A illustrates an exemplary output of the receiver 106 before calibration. In the illustrated embodiment, the receiver 106 before calibration is configured such that its output changes between "L" and "H" when the input voltage of the receiver 106 crosses a voltage Vb relatively close to 0V. When the calibration process begins, the counter circuit 112 starts counting up in response to the calibration mode signal CAL_Mode being set to "H", as illustrated in Figure 16. During the count-up, the offset generator 110 successively changes the extrinsic input offset in accordance with the count-up of the count value, changing the input voltage at which the output of the receiver 106 changes from "H" to "L", as shown in Figure 15B. As illustrated in Figure 16, the output of the receiver 106 is initially "H" for the count value "0". The output of receiver 106 changes from "H" to "L" as the count value increases to "1". Therefore, the count value of counter circuit 112 is set to "1" as a result of the calibration process. After the calibration process, the offset generator 110 generates an extrinsic input offset corresponding to the count value "1" and applies it to the differential input terminal of receiver 106. Figure 15C illustrates an exemplary output of receiver 106 after the calibration process, which at least partially cancels out the intrinsic input offset of receiver 106.

[0095] Figures 17A, 17B, 17C, and 18 illustrate exemplary operation of the integrated circuit 100 in case #3 according to one or more embodiments. Figure 17A illustrates an exemplary output of the receiver 106 before calibration. In the illustrated embodiment, the receiver 106 is configured such that its output changes between "L" and "H" when the input voltage of the receiver 106 crosses a Vc that is higher than 0V. When the calibration process begins, as illustrated in Figure 18, the counter circuit 112 starts counting up in response to the calibration mode signal CAL_Mode being set to "H". As illustrated in Figure 17B, the output of the receiver 106 is "L" for the count value "0", and therefore, as a result of the calibration process, the count value of the counter circuit 112 is set to "0". After the calibration process, the offset generator 110 generates an extrinsic input offset corresponding to the count value "0" and applies it to the differential input terminal of the receiver 106. Figure 17C illustrates an exemplary output of receiver 106 after the calibration process, which at least partially compensates for the intrinsic input offset of receiver 106.

[0096] Thus, the calibration process effectively performs calibration for any of the receivers 106 whose intrinsic input offsets are Va, Vb, and Vc. Figure 19 illustrates an exemplary distribution of the input offset of the receiver 106 before and after the calibration process in one or more embodiments. The illustrated distribution was obtained by Monte Carlo simulation. According to the Monte Carlo simulation, it was found that the calibration process effectively narrows the range of the final input offset of the receiver 106 to near 0V.

[0097] Figure 20 illustrates exemplary uses of the integrated circuit 100 described above in one or more embodiments. In the illustrated embodiments, the integrated circuit 100 is integrated into a display driver 200 configured to drive a display panel 300 based on image data received from a controller 400. Image data may be transmitted to the display driver 200 according to the MIPI D-PHY protocol or the MIPI C-PHY protocol. The display driver 200 comprises an interface (I / F) circuit 210, an image processing circuit 220, and a drive circuit 230. The interface circuit 210 incorporates the integrated circuit 100 described in the embodiments above and receives image data from the controller 400 via a receiver 106 (shown in Figure 1). The output of the receiver 106 includes image data, and the drive circuit 230 is configured to update the display panel 300 based on the output of the receiver 106.

[0098] In one implementation, the interface circuit 210 may be configured to transfer image data to the image processing circuit 220. In another embodiment, the interface circuit 210 may be configured to process the image data and transfer the processed image data to the image processing circuit 220. The image processing circuit 220 may be configured to apply one or more desired image processing operations (e.g., gamma conversion, color adjustment, scaling, subpixel rendering, and other image processing operations) to the image data and to supply the processed image data to the drive circuit 230. The drive circuit 230 may be configured to update the display panel 300 based on the processed image data received from the image processing circuit 220. In one implementation, the drive circuit 230 may be configured to drive the source lines (sometimes called data lines) of the display panel 300 based on the processed image data to display the image corresponding to the image data.

[0099] Method 2100 in Figure 21 illustrates the steps for operating an integrated circuit (e.g., integrated circuit 100 shown in Figures 1 and 3). Note that one or more of the steps shown in Figure 21 may be omitted, repeated, and / or performed in an order different from that shown in Figure 21. Also note that two or more steps may be performed simultaneously.

[0100] Method 2100 includes, in step 2102, using an input switch circuit (e.g., switch circuit 104 as shown in Figures 1 and 2A) to switch the electrical connection between a plurality of signal inputs (e.g., signal input 102) and the differential input terminals of a receiver (e.g., receiver 106) based on a communication protocol to which the transmission signals are sent to the plurality of signal inputs. Method 2100 further includes, in step 2104, using the input switch circuit to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver during the calibration process. Method 2100 further includes, in step 2106, performing calibration of the input offset between the differential input terminals of the receiver during the calibration process. The differential input terminals of the receiver may be short-circuited during the calibration process.

[0101] Although many embodiments have been described, those skilled in the art who benefit from this disclosure will understand that other embodiments can be devised that do not deviate from the technical scope. Accordingly, the technical scope of the invention should be limited only by the appended claims.

Claims

1. 1. An integrated circuit comprising: A plurality of signal inputs; a receiver having a differential input terminal; a calibration circuit configured to calibrate an input offset between the differential input terminals of the receiver in response to the integrated circuit being set to a calibration mode; switching electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the integrated circuit being set to a mode different from a calibration mode; an input switch circuit configured to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the integrated circuit being set to a calibration mode; Equipped with Integrated circuit.

2. a short-circuit switch circuit configured to short-circuit the differential input terminals of the receiver in the calibration mode; 10. The integrated circuit of claim 1.

3. Switching the electrical connections between the plurality of signal inputs and the differential input terminals of the receiver includes: electrically connecting two of the plurality of signal inputs to the differential input terminals of the receiver based on a communication protocol in which a transmit signal is transmitted to the plurality of signal inputs.

10. The integrated circuit of claim 1.

4. Switching the electrical connections between the plurality of signal inputs and the differential input terminals of the receiver includes: electrically connecting two of a first combination of the plurality of signal inputs to the differential input terminals of the receiver for data transmission according to a first protocol; electrically connecting two of a second combination of the plurality of signal inputs to the differential input terminals of the receiver for data transmission according to a second protocol; Including, The second combination is different from the first combination.

10. The integrated circuit of claim 1.

5. A display driver, an interface circuit section including: a receiver having a plurality of signal inputs and differential input terminals; a calibration circuit section configured to calibrate input offsets of the differential input terminals of the receiver in response to the display driver being set to a calibration mode; and an input switch circuit section configured to switch electrical connections between the plurality of signal inputs and the differential input terminals of the receiver in response to the display driver being set to a mode different from the calibration mode, and to electrically disconnect the plurality of signal inputs from the differential input terminals of the receiver in response to the display driver being set to the calibration mode; driver circuitry configured to update a display panel based on the output of the receiver; Equipped with Display driver.

6. The receiver further includes a short-circuit switch circuit configured to short-circuit the differential input terminals of the receiver in the calibration mode.

6. The display driver according to claim 5.

7. switching electrical connections between the plurality of signal inputs and the differential input terminals of the receiver; electrically connecting two of a first combination of the plurality of signal inputs to the differential input terminals of the receiver for data transmission according to a first protocol; electrically connecting two of a second combination of the plurality of signal inputs to the differential input terminals of the receiver for data transmission according to a second protocol; Including, The second combination is different from the first combination.

6. The display driver according to claim 5.

8. switching, by an input switch circuit, electrical connections between a plurality of signal inputs and differential input terminals of a receiver based on a communication protocol in which a transmission signal is transmitted to the plurality of signal inputs; electrically disconnecting the plurality of signal inputs from the differential input terminals of the receiver by the input switch circuit unit in a calibration step; calibrating an input offset between the differential input terminals of the receiver in the calibration step; Contains method.

9. The calibration step further includes short-circuiting the differential input terminals of the receiver. The method of claim 8.

10. Switching the electrical connections between the plurality of signal inputs and the differential input terminals of the receiver includes: electrically connecting two of a first combination of the plurality of signal inputs to the differential input terminals of the receiver for data transmission according to a first protocol; electrically connecting two of a second combination of the plurality of signal inputs to the differential input terminals of the receiver for data transmission according to a second protocol; Including, The second combination is different from the first combination. The method of claim 8.

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