Semiconductor device with passivated magnetic concentrator

Abstract

To provide a semiconductor device having a hall sensor, and provide a manufacturing method of them.SOLUTION: A semiconductor device 500 contains hole sensors 506 and 507 arranged to a first plan surface which is parallel to a divice side front surface of a semiconductor die, and contains: a semiconductor die 505 that includes a bond pad on the device side front surface which is separated from a magnetic concentrator; a passivated magnetic concentrator 512 containing a magnetic alloy layer 515 formed on the device side front surface of the semiconductor die; a bond wire 513 that is mounted onto the die side front surface of the die pad 502 on a package substrate, and bonds a back side front surface of the semiconductor die opposite to the device side front surface and the bond pad of the semiconductor die with a lead 501 of the package substrate; and a mold chemical compound 503 that covers the passivated magnetic concentrator 512, the semiconductor die, the bonding wire, one part of the lead, and the die side front surface of the die pad. An upper side front surface of the magnetic alloy layer is covered with a protection layer 517 of a polymer material.SELECTED DRAWING: Figure 5C

Description

[Technical Field]

[0001] This application relates generally to semiconductor devices that sense magnetic fields, and more particularly to semiconductor devices that include Hall sensors. [Background technology]

[0002] Semiconductor devices for magnetic sensing include Hall effect sensors with circuit elements. Magnetic sensing can be used for motor control, position sensing, automation, current sensing, and other applications. Hall effect sensors integrated into silicon semiconductor devices can be formed by doping regions to contain carriers that are sensitive to magnetic fields. A voltage proportional to the magnetic field is output, while a constant current is applied to the Hall sensor. Hall sensors are most sensitive to magnetic fields perpendicular to the plane of the sensor. In applications using Hall sensors with directional sensitivity, semiconductor device position is important for magnetic field sensing to ensure that the magnetic field is perpendicular to the sensor within the semiconductor device. Alignment and system position are important for sensor performance.

[0003] The performance for sensing magnetic fields when the magnetic field is "in plane" with the plane in which the Hall sensor lies can be improved by incorporating a magnetic concentrator into the semiconductor device. The magnetic concentrator can be a ferromagnetic material formed over the sensor in the semiconductor device. The magnetic concentrator can focus and bend the magnetic field so that when the sensor is exposed to an in-plane magnetic field, a local magnetic field perpendicular to the Hall sensor is formed within the semiconductor device, thereby improving sensitivity to in-plane magnetic fields.

[0004] Magnetic concentrator materials for use in semiconductor processes include magnetic alloy materials. These materials can be deposited, for example, by electroless or electroplating. Magnetic alloy materials are particularly sensitive to semiconductor etching and cleaning chemicals often used, making it difficult to fabricate magnetic concentrators using these materials in semiconductor processes. Chemicals used in photolithography and post-plating processes can damage the magnetic alloy materials, so modified chemistries may be specified, increasing costs. A reliable and robust integrated magnetic concentrator and method for its fabrication are needed. Summary of the Invention

[0005] An example described includes a semiconductor die including a Hall sensor disposed in a first plane parallel to a device-side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed on the device-side surface of the semiconductor die, wherein an upper surface of the magnetic alloy layer is covered by a layer of polymer material; a back-side surface of the semiconductor die opposite the device-side surface mounted to the die-side surface of a die pad on a package substrate, the back-side surface being mounted to the die-side surface of a die pad on a package substrate, the semiconductor die having bond pads on the device-side surface spaced apart from the magnetic concentrator; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; and a mold compound covering the magnetic concentrator, the semiconductor die, the electrical connections, portions of the leads, and the die-side surface of the die pad. [Brief explanation of the drawings]

[0006] [Figure 1] 1 illustrates a Hall sensor semiconductor device in a small outline transistor (SOT) package sensing in perspective view.

[0007] [Figure 2] 1 illustrates a semiconductor die with a Hall sensor and a magnetic concentrator in an applied magnetic field.

[0008] [Figure 3A] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3B] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3C] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3D] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3E] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3F] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3G] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3GG] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3H] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration. [Figure 3HH] A series of cross-sectional views illustrate selected steps for forming a semiconductor die and passivated magnetic concentrator in a particular configuration.

[0009] [Figure 4A] Semiconductor dies on a semiconductor wafer are illustrated in perspective view.

[0010] [Figure 4B] The individual semiconductor dies are illustrated in close-up view.

[0011] [Figure 5A] A packaged semiconductor device in the above arrangement is illustrated in plan view. [Figure 5B] A packaged semiconductor device in the above arrangement is illustrated in perspective view. [Figure 5C] A packaged semiconductor device in the above arrangement is illustrated in cross section.

[0012] [Figure 6A] Selected steps of a method for forming the above arrangement are illustrated in a flow chart. [Figure 6B] Selected steps of a method for forming the above arrangement are illustrated in a flow chart. DETAILED DESCRIPTION OF THE INVENTION

[0013] Corresponding numbers and symbols in the different drawings generally refer to corresponding parts unless otherwise noted. The drawings are not necessarily drawn to scale.

[0014] Elements are described herein as being "coupled." The term "coupled" includes elements that are directly connected and elements that are indirectly connected, and also includes elements that are electrically connected using intervening coupled elements or wiring.

[0015] The term "semiconductor die" is used herein. A semiconductor die may be a discrete semiconductor device such as a bipolar transistor, two or three discrete devices such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die may be an integrated circuit comprising multiple semiconductor devices such as multiple capacitors in an A / D converter. A semiconductor die may include passive devices such as resistors, inductors, filters, sensors, or active devices such as transistors. A semiconductor die may be an integrated circuit comprising hundreds or thousands of transistors combined to form a functional circuit, such as a microprocessor or memory device.

[0016] The term "semiconductor device package" is used herein. A semiconductor device package includes at least one semiconductor die electrically coupled to terminals and a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies may be packaged together. For example, a power metal-oxide-semiconductor (MOS) field-effect transistor (FET) semiconductor die and a logic semiconductor die (such as a gate driver die or controller die) may be packaged together to form a single packaged electronic device. Additional components, such as passive elements, may be included in the packaged electronic device. The semiconductor die is mounted to a package substrate that provides conductive leads, some of which form terminals for the packaged device. The semiconductor die may be mounted to a package substrate with its device-side surface facing away from the substrate and its backside surface facing and mounted on the die pads of the package substrate. In wire-bonded semiconductor device packages, bond wires couple the conductive leads of the package substrate to the bond pads on the semiconductor die. The semiconductor device package may have a package body formed by a thermosetting epoxy resin in a molding process or by the use of an epoxy, plastic, or resin that is liquid at room temperature and then hardened. The package body may provide a hermetic package for the packaged device. The package body may be formed into a mold using an encapsulation process, but some of the leads of the package substrate are not covered during encapsulation, and these exposed lead portions provide terminals for the semiconductor device package.

[0017] The term "package substrate" is used herein. A package substrate is a substrate configured to receive a semiconductor die and support the semiconductor die in a completed semiconductor device package. Package substrates useful for this configuration include conductive lead frames, which may be formed from copper, aluminum, stainless steel, steel, or alloys such as alloy 42 or copper alloys. The lead frame may include a die pad with a die-side surface for mounting the semiconductor die, and conductive leads positioned near and spaced from the die pad for coupling to the bond pads on the semiconductor die using wire bonds, ribbon bonds, or other conductors. The lead frame may be provided in a strip or array. The conductive lead frame may be provided as a panel with a strip or array of unit device portions in rows and columns. A semiconductor die may be placed on each unit device portion within the strip or array. The semiconductor die may be placed on a die pad for each packaged device, and a die attach or die adhesive may be used to mount the semiconductor die to the lead frame die pad. In wire-bonded packages, bond wires may couple the bond pads on the semiconductor die to the leads of the lead frame. The lead frame may have plated portions in areas designated for wire bonding, for example, silver plating may be used. After the bond wires are in place, a portion of the package substrate, the semiconductor die, and at least a portion of the die pad may be covered with a protective material such as a mold compound.

[0018] A package substrate, such as a leadframe, has conductive portions on its die-facing surface. The leads of a metal leadframe are conductive all along its surface, while other substrate types have conductive lands in the dielectric substrate material for connection to the semiconductor die. Plating may be used on the leads of a conductive leadframe to improve bond wire adhesion, prevent corrosion and tarnishing, and increase reliability. Spot plating or overall plating may be used.

[0019] In packaging semiconductor devices, molding compounds can be used to partially cover the package substrate, to cover the semiconductor die, and to cover the electrical connections from the semiconductor die to the package substrate. This is sometimes called an “encapsulation” process, except that some portions of the package substrate are not covered within the molding compound during encapsulation, e.g., terminals and leads are exposed through the molding compound. Encapsulation is often a compression molding process, in which case a thermosetting molding compound such as a resin epoxy can be used. Room-temperature solid or powder molding compounds can be heated to a liquid state, after which molding can occur by pressing the liquid molding compound into a mold. Transfer molding can also be used. Unit molds can be used that are molded to enclose individual devices, or block molding can be used to simultaneously form packages for several devices from the molding compound. Devices can be provided in arrays of hundreds or even thousands of devices molded together in rows and columns. After molding, the individual packaged devices are severed from one another in a sawing operation by cutting through the mold compound and package substrate at saw streets formed between the devices, leaving portions of the package substrate leads exposed from the mold compound package to form terminals for the packaged semiconductor devices.

[0020] The term "scribe lane" is used in this application. A scribe lane is a portion of a semiconductor wafer between semiconductor dies. In related literature, the term "scribe street" is sometimes used. Once semiconductor processing is complete and the semiconductor device is completed, the semiconductor device is separated into individual semiconductor dies by cutting the semiconductor wafer along the scribe lanes. The separated dies are then removed and handled individually for further processing. This process of removing the dies from the wafer is called "singulation" or sometimes "dicing." The scribe lanes are located on four sides of the semiconductor die, and when the dies are singulated from each other, rectangular semiconductor dies are formed.

[0021] The term "saw street" is used herein. Saw streets are areas between molded electronic devices that are used to allow a cutting tool, such as a mechanical blade, laser, or other cutting tool, to pass between the molded electronic devices and separate the devices from one another. This process is another form of singulation. When the molded electronic devices are provided in a strip, with one device adjacent to another along the strip, the saw streets are parallel and perpendicular to the length of the strip. When the molded electronic devices are provided in an array of devices in rows and columns, the saw streets include two groups of parallel saw streets that are perpendicular to each other, and the cutting tool traverses the molded electronic devices in two different directions to cut the packaged electronic devices in the array from one another.

[0022] The term "quad flat no-lead" or "QFN" is used herein for a type of electronic device package. QFN packages have conductive leads that are coextensive with the sides of the molded package body, while quad packages have leads on four sides. Alternative flat no-lead packages may have leads on two sides or only one side. These are sometimes called "small outline no-lead" or "SON" packages. Electronic devices in no-lead packages may be surface-mounted to a substrate. Leaded packages may be used with this arrangement, in which the leads extend away from the package body and are molded to form portions for soldering to the substrate. Dual in-line packages (DIPs) may be used with this arrangement. Small outline packages (SOPs) may be used with this arrangement. Small outline no-lead (SON) packages may be used, and small outline transistor (SOT) packages are leaded packages that may be used with this arrangement. The leads for leaded packages are arranged for solder mounting to the substrate. The leads may be shaped to extend toward the substrate and form a mounting surface. Gull-wing leads, J-leads, and other lead shapes may be used. In DIP packages, the leads terminate in pin-shaped portions that can be inserted into conductive holes formed in the circuit board, and solder is used to bond the leads to the conductors within the holes.

[0023] The term "magnetic alloy" is used herein. A magnetic alloy is a material that is ferromagnetic. Useful examples of such configurations include nickel-iron alloy (NiFe), cobalt-iron alloy (CoFe), and cobalt- or nickel-based ternary and quaternary alloys, such as CoFeB, CoNiFe, and CoNiFeCr. In such configurations, a magnetic concentrator is formed by using a magnetic alloy formed on a semiconductor die containing one or more Hall sensors. The magnetic concentrator generates a localized magnetic field in response to an applied magnetic field. The applied magnetic field can be in the same plane as the one or more Hall sensors or can be "in-plane." The magnetic concentrator generates a localized magnetic field that is out-of-plane at an angle relative to the plane of the one or more Hall sensors. The magnetic concentrator also focuses magnetic flux in the localized magnetic field, increasing the sensitivity of the one or more Hall sensors to the applied magnetic field.

[0024] The term "in-plane" is used herein to describe the magnetic field. In such an arrangement, the semiconductor die includes the Hall sensor. In one example, a silicon semiconductor die includes a Hall sensor formed by creating an area with a carrier within the semiconductor die, and the Hall sensor outputs a voltage proportional to the strength of the magnetic field in the presence of an applied magnetic field while a constant current is applied to the Hall sensor. One or more Hall sensors are arranged along a plane, e.g., a plane parallel to the device side of the semiconductor die. The Hall sensor is sensitive to magnetic fields with flux lines that are "out-of-plane," that is, at an angle to the plane of the Hall sensor, preferably perpendicular to the plane in which the Hall sensor lies. The Hall sensor is insensitive to magnetic fields with flux lines that are "in-plane," or that generate magnetic flux parallel to the plane in which the Hall sensor lies.

[0025] The term "magnetic concentrator" is used herein. A magnetic concentrator is a magnetic element that generates a localized magnetic field and focuses magnetic flux in response to an applied magnetic field. In such an arrangement, the magnetic concentrator is formed from a magnetic alloy layer, and a nickel-iron (NiFe) magnetic alloy or other magnetic alloys may be used. When an in-plane magnetic field is applied to the magnetic concentrator, a localized magnetic field is generated with magnetic flux lines that are out-of-plane with respect to the Hall sensors in the semiconductor die. The magnetic concentrator also enhances the magnetic field for an in-plane applied magnetic field, increasing the signal-to-noise ratio and thereby increasing the sensitivity of one or more Hall sensors in the semiconductor die. The term "passivated magnetic concentrator" is used herein. A passivated magnetic concentrator is a magnetic concentrator that is at least partially covered with a polyimide layer. In an exemplary arrangement, the magnetic concentrator is formed from a magnetic alloy layer and then passivated by covering at least a portion of the magnetic alloy layer with a polyimide layer. The passivated magnetic concentrator is then protected from chemicals, such as etchants and cleaning chemicals, used in subsequent processing steps in forming the semiconductor die that includes the magnetic concentrator. By forming a passivated magnetic concentrator, use of such an arrangement allows for the use of conventional semiconductor processing, including conventional chemicals, without damaging the magnetic alloy layer in the passivated magnetic concentrator.

[0026] In such an arrangement, a semiconductor die includes one or more Hall sensors. A first passivation layer, such as a polyimide layer, is formed on the surface of the semiconductor die. A seed layer is deposited on the polyimide layer. Photoresist is deposited and patterned to form areas for plating. The magnetic concentrator is formed on the semiconductor die by depositing a magnetic alloy layer in the areas patterned in the photoresist for plating. The deposition can be done using electroplating or electroless plating. The magnetic alloy layer material is plated on the seed layer in the patterned areas. After the plating process, the photoresist is stripped or otherwise removed, for example, by ashing. A protective layer is formed on the magnetic alloy layer and patterned using photolithography to form a passivated magnetic concentrator. In one arrangement, the sides and top of the magnetic concentrator are covered. By passivating the magnetic alloy layer, the remaining seed layer and any other layers used in the plating process are removed by conventional seed layer etching and cleaning processes. Etchants and cleaning solutions such as sulfuric acid, peroxide, ammonia, and combinations thereof, such as piranha solution, can be used. Because the magnetic alloy layer is passivated by the protective layer, conventional semiconductor chemicals can be used without damaging the magnetic alloy layer. The magnetic alloy layer and the protective layer form a magnetic concentrator. In operation, the magnetic concentrator increases the sensitivity of the Hall sensor to in-plane magnetic fields. The materials and methods used in such an arrangement are often used in semiconductor processing, and no new materials are required. The use of such an arrangement is cost-effective and easy to implement.

[0027] FIG. 1 illustrates, in cross section, a semiconductor die 105 including a Hall sensor 106 in a semiconductor device package 100, shown in an example as a small outline transistor (SOT) package. The SOT package is one type of semiconductor device package useful for such placement. SOT packages are used for low terminal count devices that include passive components, transistors, and analog circuitry. The semiconductor device package 100 has a body formed from a molding compound 103, e.g., a thermosetting epoxy resin. Other molding compounds, including resins, epoxies, or plastics, may also be used. The leads 101 are part of a package substrate, such as a metal lead frame, that supports the semiconductor die 105 (not visible in FIG. 1 because it is obscured by the package body; see FIG. 2) within the package 100, and the leads 101 are exposed from the molding compound 103 and from electrical terminals for the packaged electronic device. In the exemplary SOT package shown, the leads 101 of Figure 1 are formed to extend alongside the body of the packaged semiconductor device 100 and provide gull-wing shaped terminals with legs at their ends. The packaged electronic device 100 can be mounted to a circuit board or module using surface mount technology (SMT).

[0028] 1, semiconductor device 100 is shown in a sensing application for a magnetic field 112 resulting from a source 110. The magnetic flux density 112 for the magnetic field is perpendicular to the plane of the Hall sensor, where sensitivity is greatest. However, Hall sensor 106 is relatively insensitive to magnetic fields that are in-plane with respect to the plane of the Hall sensor.

[0029] FIG. 2 illustrates the addition of a magnetic concentrator to a semiconductor die containing Hall sensors. In FIG. 2, a semiconductor die 205 includes two Hall sensors 206, 207. In an alternative arrangement, a single Hall sensor, such as in FIG. 1, may be used. Using two spaced-apart Hall sensors 206, 207 enables a differential flux sensing approach, where inherent voltage offsets and common-mode noise in the signal can be reduced by taking the difference between the outputs of two similar Hall sensors 206, 207 using a differential signal to sense the strength of the magnetic field. The Hall sensors 206 and 207 lie in a plane P1 that is parallel to the device side 210 of the semiconductor die 205. In FIG. 2, a magnetic concentrator 221 is shown formed on the semiconductor die 205 over the Hall sensors 206, 207.

[0030] When a magnetic field having magnetic flux density 212 is applied in an in-plane direction relative to the Hall sensors 206 and 207, the magnetic concentrator 221 becomes magnetized and generates a second magnetic field in the semiconductor die 205 around the Hall sensors 206 and 207, with magnetic flux lines 223 having a concentrated magnetic flux intensity, the magnetic flux being in an out-of-plane direction relative to the Hall sensors. In this example, the magnetic flux from the magnetic field 223 is perpendicular to the plane P1 in which the Hall sensors lie, so the Hall sensors are sensitive to and sense the magnetic flux of the magnetic field 223, which is proportional to the magnetic flux of the applied magnetic field 212. By adding the magnetic concentrator 221, the semiconductor device 200 can sense in-plane magnetic fields. In one example arrangement, the magnetic concentrator 221 can be formed from a magnetic alloy layer deposited on the surface of the semiconductor die 205 and aligned with the Hall sensors 206 and 207. In one particular example, a nickel-iron (NiFe) alloy layer is used. Other magnetic alloy materials may also be used, including CoFe, CoFeB, CoNiFe, or CoNiFeCr.

[0031] FIGS. 3A-3HH illustrate selected processes used to form the arrangement in a series of cross-sectional views. In FIG. 3A, a semiconductor die 305 is shown in cross-section, with a pair of Hall sensor devices 306, 307 formed spaced apart within the semiconductor die 305. In one example, a silicon semiconductor die is used, and the Hall sensors are formed by doping to form areas with carriers. The Hall sensors are subjected to an applied magnetic field while a constant current flows through them, outputting a voltage proportional to the magnetic field. While some arrangements can use a single Hall sensor, the exemplary arrangements shown in FIGS. 2 and 3A-3GG use two Hall sensors, allowing for differential sensing. A layer of polyimide 308 is shown deposited on the device side of the semiconductor die 305, acting as a passivation layer. Additional passivation layers, such as nitride, oxide, and oxynitride layers, can be used between the semiconductor die 305 and the polyimide layer 308. Hall sensors 306 and 307 lie in a plane P1 that is parallel to the device side of semiconductor die 305.

[0032] FIG. 3B illustrates the semiconductor die 305 in FIG. 3A after additional processing. In FIG. 3B, an adhesion layer 309 is formed on the polyimide layer 308 to prepare for plating operations. The adhesion layer 309 can be a TiW layer in one example process. Other materials, including chromium (Cr), titanium (Ti), tungsten (W), and nickel (Ni), can also be used to form the adhesion layer. The adhesion layer enhances the adhesion of metals deposited on the structure subsequent to the polyimide layer 308. In an alternative approach, the adhesion layer 309 can be omitted.

[0033] 3C illustrates the semiconductor die 305 shown in FIG. 3B after additional processing. In FIG. 3C, a seed layer 311 is shown deposited on the adhesion layer 309. In one example process, a copper (Cu) seed layer is formed. The seed layer 311 may be, for example, sputter deposited on the surface of the semiconductor die 305. Vapor deposition, such as CVD, plasma-enhanced vapor deposition (PVD), and atomic layer deposition (ALD), may be used to form the seed layer 311. In an alternative arrangement, a sputtered layer of NiFe may be used as the seed layer 311.

[0034] 3D illustrates, in another cross-sectional view, the semiconductor die 305 of FIG. 3C after additional processing. In FIG. 3D, a photoresist layer 313 is shown after a deposition and patterning step. The photoresist layer 313 defines areas of the seed layer 311 that are exposed for plating.

[0035] FIG. 3E illustrates the element of FIG. 3D after additional processing in another cross-sectional view. In FIG. 3E, the layer of magnetic alloy material 315 is shown after plating in the open areas defined by the patterned photoresist layer 313. In one exemplary arrangement, the magnetic alloy layer 315 is of nickel-iron (NiFe) composition. In an alternative arrangement, a magnetic alloy layer including CoFe, CoFeB, CoNiFe, or CoNiFeCr may be used. In one exemplary process, the magnetic alloy layer 315 has a thickness T1 that is between 10 and 90 microns thick. The magnetic alloy layer may be formed using a seed layer 311 in a plating process such as electroplating or by electroless plating. In one exemplary process, electroplating is performed using a NiFe bath plating chemistry. A Ni anode is used, and an electroplating current is applied to the seed layer 311 to form the NiFe layer 315.

[0036] 3F illustrates, in another cross-sectional view, the elements of FIG. 3E after additional processing. In FIG. 3F, magnetic alloy layer 315 is shown after photoresist layer 313 (see FIG. 3E) has been removed. The photoresist layer may be removed by a chemical stripping or plasma ashing process, or a combination thereof. Magnetic alloy layer 315 now has an outer surface and a top surface facing away from the device-side surface of semiconductor die 305.

[0037] 3G and 3GG illustrate, in cross-sectional views, two alternative configurations resulting from additional processing of the elements shown in FIG. 3F. In FIG. 3G, another protective layer 317 is deposited on the magnetic alloy layer 315. In FIG. 3G, the protective layer 317 is patterned to cover the top and outer surfaces of the magnetic alloy layer 315. The protective layer 317 then passivates the magnetic alloy layer 315, thereby protecting it from additional processing. Useful examples for the protective layer 317 include any patternable protective polymer. In some examples, the protective layer 317 is photopatternable. In some examples, a polyimide is used for the protective layer 317. In one particular example, polyimide HD4100 is used, which is commercially available from HD Microsystems, LLC, of ​​Pearl, New Jersey, USA.

[0038] Figure 3GG illustrates an alternative approach in another cross-sectional view. In Figure 3GG, following the processing that results in the structure shown in Figure 3F, protective layer 317 is deposited and patterned to cover only the top surface of magnetic alloy layer 315. The top of magnetic alloy layer 315 is then protected from further processing by the passivation of protective layer 317.

[0039] FIG. 3H illustrates the element of FIG. 3G in another cross-sectional view after additional processing. In FIG. 3H, the seed layer 311 and adhesion layer 309, which are outside the magnetic alloy layer 315 and are no longer needed, are removed by chemical etching, dry etching, or other processes. A chemical wet etchant, such as sulfuric acid, peroxide, or ammonia, or a combination thereof, can be used. A mixture such as piranha etchant can also be used. Layer 317 protects the magnetic alloy layer 315 from damage that might otherwise occur during the etching process. The use of an arrangement that includes protective layer 317 over magnetic alloy layer 315 allows the use of conventional etching chemistries and materials without damaging the magnetic alloy layer, which is sensitive to these etching processes. A passivated magnetic concentrator 312 is formed on the semiconductor die 305 by protective layer 317 and magnetic alloy layer 315. In operation, the passivated magnetic concentrator 312 enables the Hall sensors 306, 307 to sense an applied magnetic field that is an in-plane magnetic field relative to the plane P1 in which the Hall sensors 306, 307 lie.

[0040] Figure 3HH illustrates, in another cross-sectional view, the alternative arrangement of Figure 3GG after additional processing. In Figure 3HH, seed layer 311 and adhesion layer 309 have been removed from areas outside magnetic alloy layer 315, where these layers are no longer needed. Passivated magnetic concentrator 314 is formed by protective layer 317 over magnetic alloy layer 315 formed on semiconductor die 305. Magnetic concentrator 314 enables Hall sensors 306, 307 to sense applied magnetic fields that are in-plane with respect to plane P1 in which the Hall sensors lie.

[0041] 3A-3HH illustrate, as an example, steps for forming an arrangement using a single semiconductor die 305. However, in manufacturing, these steps are performed on a semiconductor wafer with many semiconductor dies formed simultaneously. After the semiconductor dies are formed, additional steps are performed to separate the dies and package the dies to form semiconductor devices.

[0042] 4A and 4B illustrate processes used in forming semiconductor dies, such as those used in conjunction with wire bonding arrangements. In FIG. 4A, a semiconductor wafer 401 is shown with an array of semiconductor dies 405 arranged in rows and columns. The semiconductor dies 405 are formed in a semiconductor fabrication facility using fabrication processes, including ion implantation for carrier doping, annealing, oxidation, dielectric and conductor deposition, photolithography, patterning, etching, chemical-mechanical polishing (CMP), electroplating, and other processes to create semiconductor devices. Devices are formed on the device side surfaces of the semiconductor dies. Scribe lanes 403 and 404 are perpendicular to each other and extend across the wafer 401 in parallel groups to separate the rows and columns of completed semiconductor dies 405 and provide areas for dicing the wafer to separate the semiconductor dies 405 from one another.

[0043] FIG. 4B illustrates a single semiconductor die 405 with bond pads 408, which are conductive pads that are electrically coupled to devices (not shown for simplicity) formed on the semiconductor die 405. The semiconductor dies 405 are separated from the wafer 401 by wafer dicing or singulated from one another using scribe lanes 403, 404 (see FIG. 4A). Wafer dicing can be done by mechanical sawing along the scribe lanes or by laser cutting. The semiconductor die 405 shown in FIG. 4B includes a passivated magnetic concentrator 412 formed on the device-side surface of the semiconductor die. The passivated magnetic concentrator 412 can be formed from a magnetic alloy layer and a protective layer as shown in FIGS. 3A-3HH.

[0044] FIGS. 5A-5C illustrate a packaged semiconductor device incorporating a certain arrangement in plan, perspective, and cross-sectional views, respectively. FIG. 5A illustrates, in plan view, a packaged semiconductor device 500 with a semiconductor die 505 in an arrangement including a passivated magnetic concentrator 512. FIG. 5A illustrates the packaged semiconductor device after molding compound 503 has been formed. A metal lead frame is shown with leads 501 and a die pad 502. See FIG. 5B, which illustrates the completed semiconductor device package; note that leads 501 have not yet been formed in the lead formation process. Semiconductor die 505 has a backside surface (not visible in this view) that mounts to die pad 502; the device-side surface of semiconductor die 505 faces the reader in the drawings. Semiconductor die 505 is electrically connected to leads 501 by wire bonds 513, which couple bond pads on semiconductor die 505 to leads 501. Mold compound 503 is shown (shown as transparent in FIG. 5A for purposes of illustration) covering die pad 502, semiconductor die 505, and portions of leads 501, with leads 501 extending through and exposed from mold compound 503 to form terminals. As described further below, the portions of leads 501 exposed from mold compound 503 are shaped to form terminals for a semiconductor device package that includes semiconductor die 505. Passivated magnetic concentrator 512 is shown over a portion of semiconductor die 505, which includes one or more Hall sensors formed therein.

[0045] FIG. 5A illustrates the elements after molding has formed mold compound 503 and after a trimming process has removed dam bars and unused leads from package substrate 519, but before the forming process to shape leads 501.

[0046] A wire bonding process is used to form the bond wire 513. In wire bonding, a wire bonding tool is used that includes a capillary through which the bond wire passes. In useful examples, the bond wire can be copper, palladium-coated copper (PCC), gold, silver, or aluminum. To initiate the wire bond, a "free-air" ball is formed on one end of the bond wire so that the bond wire extends from the capillary. The ball can be formed by a flame or other heating device directed at the end of the wire. The ball is placed on a conductive bond pad of the semiconductor die, and the ball is bonded to the bond pad. Heat, mechanical pressure, and / or sonic energy can be applied to bond the ball to the bond pad. As the capillary moves away from the ball bond on the bond pad, the bond wire extends from the capillary in an arc or curved shape. The capillary moves over a point on a conductive portion of the package substrate, such as a lead of a lead frame. A capillary in a wire bonder is used to connect a bond wire to a conductive lead; for example, a stitch bond may be formed between the bond wire and the lead. After the stitch bond is formed to the conductive lead, the wire extending from the stitch bond is cut or severed at the end of the capillary, and the process begins again by forming another ball on the wire. Automated wire bonders can repeat this process very rapidly, many times per second, to form bond wires for packaged semiconductor devices. This process is called "ball-and-stitch" bonding. In one alternative, a ball is first bonded to a package substrate lead or other conductive surface. A second ball is formed on the end of the bond wire and bonded to a bond pad on the semiconductor die. The bond wire is then extended to the first ball and bonded to the first ball using a stitch bond on the ball, which is sometimes called "ball-stitch-on-ball" or "BSOB" bonding.In some exemplary processes, the ball bonds are more reliable than the stitch bonds made to the package substrate, and the use of extra ball bonds can increase the reliability of the wire bonds.

[0047] FIG. 5B illustrates the packaged semiconductor device of FIG. 5A in a perspective view. In this example, a SOT package is shown. The packaged semiconductor device 500 includes a molding compound 503 covering a semiconductor die 505, a die pad 502 of a metal lead frame, and a portion of the leads 501. The leads 501 extend from the molding compound 503, and the exposed portions are shaped to form terminals for the packaged device with feet 504 arranged for surface mounting the packaged semiconductor device 500 to a circuit board. In alternative arrangements, a no-lead package, such as a small outline no-lead (SON) package, or a quad flat no-lead (QFN) package, may be used. In a no-lead package, the terminals do not extend beyond the package outline, and therefore the leads 501 are not as shown in FIG. 5B; instead, portions of the leads may terminate with the package body and have bottom surfaces exposed from the molding compound for mounting to a circuit board.

[0048] FIG. 5C illustrates, in a cross-sectional view, the packaged semiconductor device of FIGS. 5A and 5B illustrating an example arrangement. In FIG. 5C, the packaged semiconductor device 500 includes a semiconductor die 505 having two Hall sensors 506 and 507 formed on the semiconductor die 505. As shown, the two Hall sensors are formed in a plane P1, which is oriented horizontally as the elements are oriented in FIG. 5C and is parallel to the device-side surface of the semiconductor die 505. A polyimide layer 508 is shown deposited on the device-side surface of the semiconductor die 505. A seed layer 511 is shown deposited on the polyimide layer 508. Also in this example arrangement, an adhesion layer 509 is deposited on the polyimide layer 508 and between the seed layer 511 and the polyimide layer 508. In one exemplary process, the adhesion layer may be a TiW layer, although other materials used for adhesion layers in semiconductor processes, such as titanium (Ti), tungsten (W), and nickel (Ni), may be used. In an alternative approach, the adhesion layer 509 may be omitted. In one exemplary process, the seed layer 511 is copper. The seed layer may be deposited by sputter deposition or by atomic layer deposition (ALD). A magnetic alloy layer 515 is formed on the seed layer using a plating process, such as an electroless or electroplating process using photoresist and photolithography. A protective layer 517 is formed on the magnetic alloy layer 515. As described above, the protective layer 517 may be any patternable polymer, polyimide, or photopatternable polymer. The use of the protective layer 517 in this arrangement may protect the magnetic alloy layer 515 from other processing steps and chemicals used after the plating operation without damaging the magnetic alloy layer 515. The magnetic alloy layer 515 and the protective layer 517 form a passivated magnetic concentrator 512, which, as described above, enables the Hall sensors 506, 507 to sense an applied magnetic field that is in-plane with respect to the plane P1 in operation of the packaged semiconductor device 500, and the magnetic alloy layer 515 responds to the applied magnetic field by creating a local magnetic field and bending the magnetic field lines of this local magnetic field to become an out-of-plane magnetic field with respect to the plane P1.When such an arrangement is used, as described above and illustrated in FIG. 2, the Hall sensors in the packaged semiconductor device 500 can sense an in-plane applied magnetic field.

[0049] 6A and 6B illustrate, in a flow chart, the steps for forming a semiconductor device package of this configuration. In the flow chart of FIG. 6A, processing for a single semiconductor die is described for illustrative purposes. In some manufacturing processes, a package substrate has many semiconductor dies mounted on unit leadframe portions, and wire bonding and molding operations are performed simultaneously on all unit devices to improve yield and reduce manufacturing costs.

[0050] Figure 6A illustrates the steps taken to form the arrangement in wafer-level processing, and Figure 6B illustrates the steps taken to form the arrangement after the semiconductor die have been removed from the wafer and packaged.

[0051] In step 601 in FIG. 6A, the method begins with forming a semiconductor die on a semiconductor wafer, the semiconductor die including at least one Hall sensor, and alternatively, may include two or more Hall sensors.

[0052] The method transitions to step 603 in Figure 6A where a first polyimide layer is formed over the device side surface of the semiconductor die.

[0053] The method then transitions to step 605 in Figure 6A, where a seed layer is formed on the first polyimide layer over the semiconductor die. In one exemplary process, an adhesion layer, such as a TiW layer, is formed between the seed layer and the first polyimide layer. In an alternative process, the adhesion layer is omitted. The seed layer may be made of, for example, copper.

[0054] The method then transitions to step 607 where a photoresist layer is formed over the seed layer and the photoresist layer is patterned to form openings for plating.

[0055] 6A then transitions to step 609, where a magnetic concentrator is formed by plating a magnetic alloy layer using the seed layer. The magnetic alloy layer can be plated by electroplating or an electroless plating process. The magnetic alloy layer can be a nickel-iron NiFe layer. In additional useful examples, the magnetic alloy layer can be a cobalt-iron CoFe layer, a cobalt-nickel-iron CoNiFe layer, and a magnetic alloy including CoFeB and CoNiFeCr.

[0056] 6A then transitions to step 611 where a photoresist stripping process removes the photoresist layer. A plasma ashing process or other stripping process may be used.

[0057] The method of FIG. 6A then transitions to step 613, where a protective layer is formed on the magnetic alloy layer. The protective layer is patterned to cover a portion of the magnetic alloy layer. The protective layer can be a patternable polymer, a photopatternable polymer, or a polyimide. In one example, the upper surface of the magnetic alloy layer is coated. In an alternative example, the upper surface of the magnetic alloy layer is coated and is covered on the outside by the protective layer. The protective layer is then processed by removing unwanted portions of the seed layer and, if a bonding layer is used, the adhesion layer.

[0058] In step 615, the semiconductor wafer is singulated and the individual semiconductor dies are detached from one another. An example is shown in Figures 4A and 4B. This completes the wafer-level process for placement, after which the method transitions to the die packaging operation shown in Figure 6B, where the method transitions from step 615 in Figure 6A to step 617 in Figure 6B.

[0059] The die packaging operation is shown in Figure 6B. The method transitions from step 615 in Figure 6A to step 617 in Figure 6B. In step 617, semiconductor die are mounted on die pads of a package substrate, with the package substrate having leads for each semiconductor die spaced from the die pads. In step 619 in Figure 6B, electrical connections are made between bond pads on the semiconductor die and leads spaced from the semiconductor die on the package substrate. The electrical connections can be bond wires as shown in Figure 5A, or in some alternative arrangements, ribbon bonds can be used.

[0060] The method continues at step 621. At step 621, a molding operation covers the semiconductor die, the die pad, the magnetic concentrator, and a portion of the leads with a molding compound to form a packaged semiconductor device.

[0061] In step 623, the packaged semiconductor devices are removed from the package substrate and separated from one another by a sawing operation. The mechanical saw cuts the package substrate, which may be a metal lead frame and mold compound, at the saw streets between the packaged semiconductor devices to separate the packaged semiconductor devices from one another.

[0062] Using such an arrangement, a packaged semiconductor device is provided that includes one or more Hall sensors with a passivated magnetic concentrator. The packaged semiconductor device is a sensor that is sensitive to magnetic fields, including in-plane magnetic fields. Such an arrangement is cost-effective, being formed using existing methods, materials, and tools for fabricating devices. By providing a passivated magnetic concentrator on the semiconductor device die using materials that are compatible with typical semiconductor process chemistries and methods, use of such an arrangement provides an economical Hall sensor device that is sensitive to in-plane magnetic fields. The packaged semiconductor device can be used with a variety of semiconductor package types, including SOT and SON packages.

[0063] Modifications in the described arrangements are possible, and other alternative arrangements are possible, within the scope of the claims.

Claims

1. 1. An apparatus comprising: a package substrate including a die pad; a semiconductor die having a device-side surface and a backside surface opposite the device-side surface mounted to the die-side surface of the die pad, the semiconductor die including bond pads on the device-side surface of the semiconductor die and a Hall sensor disposed in a first plane parallel to the device-side surface of the semiconductor die; a passivated magnetic concentrator including a magnetic alloy layer formed on a device-side surface of the semiconductor die and having an upper surface facing away from the device-side surface of the semiconductor die, the passivated magnetic concentrator being spaced from the bond pad, the upper surface of the magnetic alloy layer being covered by a layer of polymer material; electrical connections coupling the bond pads of the semiconductor die to leads of the package substrate; a molding compound covering the magnetic concentrator, the semiconductor die, the electrical connections, a portion of the leads, and a die-side surface of the die pad; Including, the device-side surface of the semiconductor die includes an area that is not covered by the footprint of the layer of polymer material.

2. 10. The apparatus of claim 1, The apparatus wherein the magnetic alloy layer in the passivated magnetic concentrator comprises nickel-iron.

3. 10. The apparatus of claim 1, The apparatus, wherein the magnetic alloy layer in the passivated magnetic concentrator comprises nickel-iron, cobalt-iron, cobalt-iron-boron, cobalt-nickel-iron, cobalt-nickel-iron-chromium, or a combination thereof.

4. 10. The apparatus of claim 1, The device wherein the layer of polymeric material overlies the magnetic alloy layer.

5. 10. The apparatus of claim 1, the semiconductor die further comprising a seed layer disposed between a device side surface of the semiconductor die and the passivated magnetic concentrator.

6. 6. The apparatus of claim 5, The device, wherein the seed layer comprises copper or nickel-iron.

7. 10. The apparatus of claim 1, The layer of polymer material covers an upper surface of the magnetic alloy layer and a portion of a device-side surface of the semiconductor die.

8. 8. The apparatus of claim 7, The device wherein the magnetic alloy layer is nickel-iron or cobalt-iron.

9. 9. The apparatus of claim 8, The magnetic alloy layer has a thickness between 10 and 90 microns.

10. 1. An apparatus comprising: a semiconductor die including at least one Hall sensor formed within the semiconductor die, the at least one Hall sensor disposed along a first plane parallel to a device side surface of the semiconductor die; a passivated magnetic concentrator on a device-side surface of the semiconductor die and on the at least one Hall sensor, the magnetic concentrator including a magnetic alloy layer and a layer of polymer material on at least an upper surface of the magnetic alloy layer, the upper surface of the magnetic alloy layer facing away from the device-side surface of the semiconductor die; Including, the device-side surface of the semiconductor die includes an area not covered by the layer of polymer material.

11. 11. The apparatus of claim 10, The apparatus, wherein the passivated magnetic concentrator comprises a magnetic alloy layer that is nickel-iron, cobalt-iron, cobalt-iron-boron, cobalt-nickel-iron, cobalt-nickel-iron-chromium, or a combination thereof.

12. 11. The apparatus of claim 10, the layer of polymer material overlies between a top surface of the magnetic alloy layer and an opposing bottom surface disposed over a device side surface of the semiconductor die; The layer of polymer material further covers a portion of the device-side surface of the semiconductor die adjacent an outer side of the magnetic alloy layer.

13. 11. The apparatus of claim 10, The device, wherein the magnetic alloy layer comprises nickel-iron.

14. 11. The apparatus of claim 10, The magnetic alloy layer has a thickness between 10 and 90 microns.

15. 1. A method comprising: forming a semiconductor die on a semiconductor wafer, the semiconductor die including at least one Hall sensor, the at least one Hall sensor disposed along a plane parallel to a device side surface of the semiconductor die; depositing a layer of polyimide material over a device side surface of the semiconductor die; depositing a seed layer over the layer of polyimide material; depositing a photoresist layer over the seed layer; patterning the photoresist layer to form an opening exposing the seed layer over a device side surface of the semiconductor die; forming a passivated magnetic concentrator on a device side surface of the semiconductor die; plating a layer of magnetic alloy in said opening; removing the photoresist layer, wherein the magnetic alloy layer has a top surface facing away from the device-side surface of the semiconductor die and an outer side extending from the top surface to an opposing bottom surface above the device-side surface of the semiconductor die; forming a layer of a second polymer material over the layer of magnetic alloy, the layer of second polymer material covering at least the upper surface of the layer of magnetic alloy; said forming being formed by performing A method comprising:

16. 16. The method of claim 15, The method, wherein forming a layer of a second polymer material on the layer of magnetic alloy includes covering the outside of the layer of magnetic alloy with the layer of second polymer material.

17. 16. The method of claim 15, The method, wherein plating the layer of magnetic alloy comprises plating nickel-iron, cobalt-iron, cobalt-iron-boron, cobalt-nickel-iron, cobalt-nickel-iron-chromium, or a combination thereof.

18. 16. The method of claim 15, The method wherein plating the layer of magnetic alloy comprises plating nickel iron.

19. 16. The method of claim 15, 11. The method of claim 10, further comprising, after forming the layer of second polymer material, removing from a device side surface of the semiconductor die using a chemical etch a portion of the seed layer that is not covered by the layer of second polymer material.

20. 20. The method of claim 19, separating the semiconductor die from the semiconductor wafer; mounting at least one of the semiconductor dies to a die pad of a package substrate, the package substrate including leads spaced apart from the die pad; forming electrical connections between bond pads on a device side surface of the at least one semiconductor die and the leads; covering the at least one semiconductor die, the passivated magnetic concentrator, the electrical connections, and the die pad with a molding compound, wherein a portion of the leads are exposed from the molding compound; The method further comprises:

21. 1. A method for sensing a magnetic field, comprising: placing a packaged semiconductor device including a semiconductor die including at least one Hall sensor in a plane within an applied magnetic field, the applied magnetic field being an in-plane magnetic field with respect to a plane in which the at least one Hall sensor device is; sensing the applied magnetic field at the packaged semiconductor device with a passivated magnetic concentrator, the passivated magnetic concentrator including a magnetic alloy layer on a device-side surface of the semiconductor die, the magnetic alloy layer being at least partially covered by a polymer layer; Including, The method, wherein the device side surface of the semiconductor die includes an area that is not covered by the footprint of the polymer layer.

22. 22. The method of claim 21, The method, wherein the magnetic alloy layer comprises nickel-iron, cobalt-iron, cobalt-iron-boron, cobalt-nickel-iron, cobalt-nickel-iron-chromium, or a combination thereof.

Images