Analog-to-digital converting circuit for optimizing power consumption of dual conversion gain operation, and operation method of the same

Abstract

To provide an image sensor that comprises an analog-to-digital converting circuit capable of optimizing and reducing power consumption of a dual conversion gain operation.SOLUTION: An ADC circuit 150 included in an image sensor comprises: a comparator 151 configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal; and a counter 152 configured to determine whether or not outputting of a second digital signal corresponding to the second conversion gain is required on the basis of counting pulses of the first conversion gain output signal. When it is determined that outputting of the second digital signal is not required, the counter 152 controls the comparator 151 so as not to generate the second conversion gain output signal.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital conversion circuit and method for optimizing power consumption in dual conversion gain operation. [Background technology]

[0002] There are several types of image sensors, including CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide Semiconductor) image sensors (CIS). CMOS image sensors contain pixels made of CMOS transistors, and convert light energy into electrical signals using the photoelectric conversion elements contained in each pixel. CMOS image sensors obtain information about the captured image using the electrical signals generated from each pixel.

[0003] An analog-to-digital converter (ADC) receives an analog input voltage generated by a pixel and converts it into a digital signal. The converted digital signal can be transferred to other devices. ADCs are used in various signal processing devices. As the performance of signal processing devices improves in recent years, improved resolution for analog signals is required. Therefore, ADCs that can process many signals in the same time and provide improved resolution for each signal are used, but they have the problem of increased power consumption. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 10,431,608 [Patent Document 2] U.S. Pat. No. 10,194,106 [Patent Document 3] U.S. Patent No. 9,363,450 [Patent Document 4] U.S. Pat. No. 10,735,676 [Patent Document 5] U.S. Patent No. 10,615,190 [Patent Document 6] U.S. Patent No. 10,397,500 [Patent Document 7] U.S. Patent No. 10,170,514 [Patent Document 8] U.S. Patent No. 6,498,576 [Patent Document 9] US Patent Application Publication No. 2020 / 0236318 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide an analog-to-digital conversion circuit that optimizes power consumption in dual conversion gain operation to reduce power consumption, an operating method thereof, and an image sensor including the same. [Means for solving the problem]

[0006] A circuit according to an embodiment of the present invention includes a comparator that compares a first pixel signal corresponding to a first conversion gain with a first ramp signal to generate a first conversion gain output signal, and a second pixel signal corresponding to a second conversion gain with a second ramp signal to generate a second conversion gain output signal, and a counter that counts pulses of the first conversion gain output signal, outputs the counting result as a first digital signal, and determines whether or not it is necessary to output a second digital signal corresponding to the second conversion gain based on the first digital signal. If the first conversion gain is a conversion gain higher than the second conversion gain and it is determined that it is unnecessary to output the second digital signal, the counter controls the comparator not to generate the second conversion gain output signal.

[0007] An operating method of an analog-to-digital conversion circuit according to an embodiment of the present invention includes the steps of: generating a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generating a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, counting pulses of the first conversion gain output signal and outputting the counting result as a first digital signal, determining whether or not it is necessary to output a second digital signal corresponding to the second conversion gain based on the first digital signal, and controlling not to generate the second conversion gain output signal when it is determined that it is not necessary to output the second digital signal. The first conversion gain is a conversion gain higher than the second conversion gain.

[0008] According to an embodiment of the present invention, an image sensor includes a pixel array for outputting a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain from pixels sharing a floating diffusion region, and an analog-to-digital conversion circuit for converting the first pixel signal into a first digital signal and determining whether the second pixel signal needs to be converted into a second digital signal based on the first digital signal, where the first conversion gain is higher than the second conversion gain. Effect of the Invention

[0009] According to an embodiment of the present invention, the power consumption of the dual conversion gain operation can be optimized by determining whether a low conversion gain operation is required based on the output feedback of the counter, and the power consumption of the analog-to-digital conversion circuit can be reduced. [Brief description of the drawings]

[0010] [Figure 1] 2 shows an example of a configuration of an image processing block according to an embodiment of the present invention. [Diagram 2] 2 shows an example of the configuration of the image sensor of FIG. 1. [Diagram 3] FIG. 3 is a circuit diagram illustrating an example of one of the pixel groups in the pixel array of FIG. 2. [Figure 4a] FIG. 4 is a circuit diagram showing the floating diffusion region under high conversion gain conditions in which the dual conversion transistor of FIG. 3 is turned off. [Figure 4b] FIG. 4 is a circuit diagram showing the floating diffusion region under a low conversion gain condition in which the dual conversion transistor of FIG. 3 is turned on. [Diagram 5] 3 shows an example of the configuration of the analog-to-digital conversion (ADC) circuit of FIG. 2. [Figure 6a]6 is a timing diagram illustrating the process in which the ADC circuit of FIG. 5 processes pixel signals according to a Reset-Sig-Sig-Reset (RSSR) method. [Figure 6b] 6 is a timing diagram illustrating the process in which the ADC circuit of FIG. 5 processes pixel signals according to a Reset-Reset-Sig-Sig (RRSS) method. [Figure 7] 1 shows an example of a high conversion gain digital signal. [Figure 8] 13 shows the weights of high conversion gain pixel signals and low conversion gain pixel signals in image data according to the value of a high conversion gain digital signal. [Figure 9] 4 is a flow chart illustrating a method of operating an analog-to-digital conversion (ADC) circuit for power consumption optimization of dual conversion gain operation in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, embodiments of the present invention are described clearly and in detail so that those skilled in the art can easily practice the present invention.

[0012] Components described with reference to terms such as unit, module, block, or, er used in the detailed description and functional blocks illustrated in the drawings may be implemented in the form of software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive elements, or a combination thereof.

[0013] 1 shows an example of a configuration of an image processing block 10 according to an embodiment of the present invention. The image processing block 10 may be implemented as part of various electronic devices such as a smartphone, a digital camera, a laptop, a desktop, etc. The image processing block 10 may include a lens 12, an image sensor 14, an ISP front end block (Image Signal Processor front end block) 16, and an image signal processor 18.

[0014] The light is reflected by an object to be photographed, a scene, etc., and the lens 12 can receive the reflected light signal. The image sensor 14 can generate an electrical signal based on the light received through the lens 12. For example, the image sensor 14 may be implemented as a complementary metal oxide semiconductor (CMOS) image sensor, etc. For example, the image sensor 14 may be a multi-pixel image sensor having a dual pixel structure or a tetracell structure.

[0015] The image sensor 14 may include a pixel array. The pixels of the pixel array may convert optical signals into electrical signals to generate pixel values. The ratio at which the optical signals are converted into electrical signals (e.g., voltages) may be defined as a conversion gain. In particular, the pixel array may generate pixel signals under low conversion gain and high conversion gain conditions using a dual conversion gain that varies the conversion gain.

[0016] Additionally, image sensor 14 may include an Analog-to-Digital Converting (ADC) Circuit for performing Correlation Double Sampling (CDS) on pixel values. The configuration of image sensor 14 is described in further detail with reference to FIG.

[0017] The ISP front-end block 16 performs pre-processing on the electrical signal output from the image sensor 14, and processes the electrical signal into a form suitable for processing by the image signal processor 18. The ISP front-end block 16 of the present invention can selectively perform pre-processing on the electrical signal corresponding to a low conversion gain condition and pre-processing on the electrical signal corresponding to a high conversion gain condition, based on the output of the image sensor 14.

[0018] The image signal processor 18 can appropriately process the electrical signals processed by the ISP front-end block 16 to generate image data related to a photographed object, scene, etc. To this end, the image signal processor 18 can perform various processes such as color correction, auto white correction, gamma correction, color saturation correction, bad pixel correction, and hue correction.

[0019] 1 shows one lens 12 and one image sensor 14. However, in other embodiments, the image processing block 10 may include multiple lenses, multiple image sensors, and multiple ISP front-end blocks. In this case, the multiple lenses may each have a different angle of view. Furthermore, the multiple image sensors may have different functions, performance, and / or characteristics, and may include pixel arrays with different configurations.

[0020] Fig. 2 shows an example of the configuration of the image sensor 14 in Fig. 1. The image sensor 100 may include a pixel array 110, a row driver 120, a ramp signal generator 130, a voltage buffer 140, an ADC circuit 150, a timing controller 160, and a buffer 170.

[0021] The pixel array 110 may include a plurality of pixels arranged in a matrix along rows and columns. Each of the plurality of pixels may include a photoelectric conversion element. For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0022] The pixel array 110 may include multiple pixel groups PG. Each pixel group PG may include two or more pixels. The pixels that make up a pixel group may share a floating diffusion region or multiple floating diffusion regions. Although the pixel array 110 of FIG. 2 is shown to include four rows and four columns (i.e., 4×4) of pixel groups PG, the invention is not so limited.

[0023] A pixel group PG may include pixels of the same color. For example, a pixel group PG may include red pixels that convert light in the red spectral region into an electrical signal, green pixels that convert light in the green spectral region into an electrical signal, or blue pixels that convert light in the blue spectral region into an electrical signal. For example, the pixels that make up the pixel array 110 may be arranged in the form of a Tetra-Bayer Pattern.

[0024] Each of the pixels in the pixel array 110 can output a pixel signal along the column lines CL1 to CL4 according to the intensity or amount of light received from the outside. For example, the pixel signal can be an analog signal corresponding to the intensity or amount of light received from the outside.

[0025] As described with reference to FIG. 1, the pixel array 110 may generate pixel signals under low conversion gain conditions and high conversion gain conditions depending on the illuminance around the object. Hereinafter, a pixel signal generated under a low conversion gain condition will be referred to as a low conversion gain pixel signal, and a pixel signal generated under a high conversion gain condition will be referred to as a high conversion pixel signal. For example, the pixel array 110 may first generate a high conversion gain pixel signal and then generate a low conversion gain pixel signal. The pixel signals may pass through a voltage buffer (e.g., a source follower) and be provided to the ADC circuit 150 via the column lines CL1 to CL4. The pixel array 110 may change the conversion gain by turning on or off the dual conversion transistor, which will be described in detail with reference to FIGS. 3, 4a, and 4b.

[0026] The row driver 120 may select and drive rows of the pixel array 110. The row driver 120 may decode addresses and / or control signals generated by the timing controller 160 to generate control signals for selecting and driving rows of the pixel array 110. For example, the control signals may include signals for selecting pixels or signals for resetting floating diffusion regions.

[0027] The ramp signal generator 130 can generate the ramp signal RAMP under the control of the timing controller 160. For example, the ramp signal generator 130 can operate under a control signal such as a ramp enable signal. When the ramp enable signal is activated, the ramp signal generator 130 can generate the ramp signal RAMP according to a predetermined value (e.g., a start level, an end level, a slope, etc.). In other words, the ramp signal RAMP can be a signal that increases or decreases according to a predetermined slope over a certain time. The ramp signal RAMP can be provided to the ADC circuit 150 through the voltage buffer 140.

[0028] The ADC circuit 150 may receive pixel signals from a plurality of pixels of the pixel array 110 via column lines CL1-CL4, and may receive a ramp signal RAMP from the ramp signal generator 130 via a voltage buffer 140. The ADC circuit 150 may operate based on a correlated double sampling (CDS) technique that obtains a reset signal and an image signal for the received pixel signal and extracts a useful signal component from the difference. If the high conversion gain pixel signal is generated before the low conversion gain pixel signal, the ADC circuit 150 may generate the high conversion gain digital signal before the low conversion gain digital signal. The ADC circuit 150 may include a plurality of comparators COMP and a counter CNT.

[0029] Specifically, the comparator COMP can compare the reset signal of the pixel signal with the ramp signal RAMP, and can compare the image signal of the pixel signal with the ramp signal RAMP to perform correlated double sampling CDS. The counter CNT can count pulses of the correlated double sampled signal and output it as a digital signal. The counter CNT of the present invention can determine whether or not it is necessary to output a low conversion gain digital signal based on the high conversion gain digital signal.

[0030] For example, when it is determined that the output of the low conversion gain digital signal is not necessary, the counter CNT may generate a power down signal that causes the comparator COMP to not perform a comparison operation on the low conversion gain pixel signal, thereby reducing the power consumption of the ADC circuit 150. Although the ADC circuit 150 of FIG. 2 is shown to include four comparators COMP and four counters CNT, the present invention is not limited thereto.

[0031] The timing controller 160 may generate control signals and / or clocks for controlling the operation and / or timing of each of the row driver 120, the ramp signal generator 130, and the ADC circuit 150.

[0032] The buffer 170 may include a memory MEM and a sense amplifier SA. The memory MEM may store a digital signal output from a corresponding counter CNT of the ADC circuit 150. The sense amplifier SA may sense and amplify the stored digital signal. The sense amplifier SA may output the amplified digital signal as image data IDAT, which may be transferred to the ISP front-end block 16 of FIG. 1.

[0033] Fig. 3 is a circuit diagram showing an example of one of the pixel groups PG of the pixel array 110 of Fig. 2. Fig. 4a is a circuit diagram showing a floating diffusion region FD1 under a high conversion gain condition in which the dual conversion transistor DC of Fig. 3 is turned off. Fig. 4b is a circuit diagram showing the floating diffusion regions FD1 and FD2 under a low conversion gain condition in which the dual conversion transistor DC of Fig. 3 is turned on.

[0034] For example, the pixel group PG may include pixels PX1-PX4, photoelectric conversion elements PD1-PD4, transfer transistors Tx1-Tx4, reset transistors RST, dual conversion transistors DC, drive transistors Dx, and selection transistors SEL. Although the pixel group PG in Fig. 3 is shown as having a tetracell structure in which four pixels PX1-PX4 each include a photoelectric conversion element PD1-PD4, the present invention is not limited thereto, and the pixel group PG may be implemented to have a variety of other structures.

[0035] The first pixel PX1 may include a first photoelectric conversion element PD1 and a first transfer transistor Tx1, and the other pixels PX2, PX3, and PX4 may each include similar components. Each of the pixels PX1 to PX4 may share a reset transistor RST, a dual conversion transistor DC, a driving transistor Dx, and a selection transistor SEL. Each of the pixels PX1 to PX4 may share a first floating diffusion region FD1.

[0036] The first floating diffusion region FD1 or the second floating diffusion region FD2 can accumulate charges corresponding to the amount of incident light. While the transfer transistors Tx1 to Tx4 are turned on by the transfer signals VT1 to VT4, respectively, the first floating diffusion region FD1 or the second floating diffusion region FD2 can receive and accumulate charges from the photoelectric conversion elements PD1 to PD4. The first floating diffusion region FD1 can be connected to the gate terminal of the drive transistor Dx operated as a source follower amplifier, so that a voltage corresponding to the charges accumulated in the first floating diffusion region FD1 can be formed. For example, the capacitance of the first floating diffusion region FD1 can be represented as a first capacitance CFD1.

[0037] The dual conversion transistor DC is driven by a dual conversion signal VDC. When the dual conversion transistor DC is turned off, the capacitance of the first floating diffusion region FD1 may correspond to a first capacitance CFD1. In a typical environment, since the first floating diffusion region FD1 is not easily saturated, the need to increase the capacitance of the first floating diffusion region FD1 (i.e., CFD1) may not be required, and the dual conversion transistor DC may be turned off.

[0038] However, in a high-illumination environment, the first floating diffusion region FD1 can easily become saturated. To prevent such saturation, the dual conversion transistor DC can be turned on, and the first floating diffusion region FD1 is electrically connected to the second floating diffusion region FD2, so that the capacitance of the floating diffusion regions FD1 and FD2 can be expanded to the sum of the first capacitance CFD1 and the second capacitance CFD2.

[0039] The transfer transistors Tx1 to Tx4 are driven by transfer signals VT1 to VT4, respectively, and can transfer charges generated by the photoelectric conversion elements PD1 to PD4 to the first floating diffusion region FD1 or the second floating diffusion region FD2. For example, one end of each of the transfer transistors Tx1 to Tx4 can be connected to the photoelectric conversion elements PD1 to PD4, respectively, and the other end can be connected to the first floating diffusion region FD1.

[0040] The reset transistor RST is driven by a reset signal VRST and can provide a power supply voltage VDD to the first floating diffusion region FD1 or the second floating diffusion region FD2, so that the charge stored in the first floating diffusion region FD1 or the second extended floating diffusion region FD2 can be transferred to the power supply voltage VDD terminal, and the voltage of the first floating diffusion region FD1 or the second floating diffusion region FD2 can be reset.

[0041] The driving transistor Dx amplifies the voltage of the first floating diffusion region FD1 or the second floating diffusion region FD2 to generate a pixel signal PIX. The selection transistor SEL is driven by a selection signal VSEL and can select pixels to be read row by row. When the selection transistor SEL is turned on, the pixel signal PIX is output to the ADC circuit 150 of FIG. 2 via a column line CL.

[0042] Fig. 5 shows an example of the configuration of the analog-to-digital conversion ADC circuit 150 of Fig. 2. The ADC circuit 150 may include a comparator 151 and a counter 152. The ADC circuit 150 can convert a pixel signal PIX, which is an analog signal output from the pixel array 110, into a digital signal DS and output the digital signal DS. For clear explanation and simplicity of the drawings, the pixel array 110 of Fig. 5 is shown for only one pixel, and the configuration and function of the pixel array 110 are as described with reference to Figs. 3, 4a, and 4b.

[0043] Specifically, as described with reference to Fig. 2, the comparator 151 may compare a reset signal of a pixel signal with the ramp signal RAMP and may compare an image signal of the pixel signal with the ramp signal RAMP to perform correlated double sampling CDS, and the counter 152 may count pulses of the correlated double sampled signal and output the counted signal as a digital signal. Hereinafter, the description will be made with reference to Figs. 2, 3, 4a and 4b as well as Fig. 5.

[0044] For example, the comparator 151 may have a two-stage structure including two amplifiers (a first amplifier 151_1 and a second amplifier 151_2), and the first amplifier 151_1 and the second amplifier 151_2 may be implemented as an operational transconductance amplifier (OTA), but the present invention is not limited thereto. For example, the comparator 151 may have a structure including more amplifiers. Note that the ADC circuit 150 may include multiple comparators and counters, but for clarity, FIG. 5 shows one comparator 151 and one counter 152.

[0045] The first amplifier 151_1 may receive the pixel signal PIX from the pixel array 110 via the column line CL, and may receive the ramp signal RAMP from the ramp signal generator 130 via the voltage buffer 140. The first amplifier 151_1 may output a first output signal OTA1_OUT based on the received signal. For example, the first amplifier 151_1 may output the first output signal OTA1_OUT having a high level during a period in which the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, and may output the first output signal OTA1_OUT having a low level during a period in which the level of the ramp signal RAMP is lower than the level of the pixel signal PIX. The comparison operation of the first amplifier 151_1 described above is performed between the reset signal of the pixel signal PIX and the ramp signal RAMP, and between the image signal of the pixel signal PIX and the ramp signal RAMP.

[0046] The second amplifier 151_2 may amplify the first output signal OTA1_OUT to output a second output signal OTA2_OUT, which is a comparison signal. For example, the second output signal OTA2_OUT may be an inverted signal of the first output signal OTA1_OUT. In other words, the second amplifier 151_2 may be implemented to output the second output signal OTA2_OUT having a low level while the first output signal OTA1_OUT has a high level, and to output the second output signal OTA2_OUT having a high level while the first output signal OTA1_OUT has a low level.

[0047] In the following description, the comparator 151 performs a comparison operation, and the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT changes from a high level to a low level or from a low level to a high level, which is referred to as a decision of the ADC circuit 150. In other words, "after the decision of the circuit 150 is completed" may mean "after the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT changes from a high level to a low level or from a low level to a high level." The comparator 151 may be initialized in response to an auto-zero signal in an auto-zero section before the comparison operation is performed, and may perform the comparison operation again.

[0048] The counter 152 can operate under the control of the timing controller 160, and can count the pulses of the corresponding second output signal OTA2_OUT and output it as a digital signal DS. For example, the counter 152 can operate under control signals such as a counter clock signal CNT_CLK and an inversion signal CONV that inverts an internal bit of the counter 152.

[0049] For example, the counter 152 may include an up / down counter and a bit-wise inversion counter. The bit-wise inversion counter can perform the same operation as the up / down counter. For example, the bit-wise inversion counter can perform only an up count function and a function of inverting all bits in the counter to 1's complement when a specific signal is received. The bit-wise inversion counter can perform a reset count and then invert the result to convert it to a 1's complement (i.e., a negative number).

[0050] Furthermore, the counter 152 of the present invention can determine whether it is necessary to output a low-conversion gain digital signal based on the high-conversion gain digital signal. If it is determined that it is not necessary to output a low-conversion gain digital signal, the counter 152 can generate a power-down signal PD that prevents the comparator 151 from performing a comparison operation on the low-conversion gain pixel signal.

[0051] The counter 152 can send a power-down signal PD to the comparator 151 (i.e., the first amplifier 151_1 or the second amplifier 151_2). In response to the power-down signal PD, the first amplifier 151_1 or the second amplifier 151_2 may not generate the first output signal OTA1_OUT or the second output signal OTA2_OUT corresponding to the low conversion gain condition. This can reduce power consumption of the pixel array 110 or the ADC circuit 150. For example, the first amplifier 151_1 and the second amplifier 151_2 may include a power-down switch (e.g., an NMOS transistor or a PMOS transistor) that operates in response to the power-down signal PD.

[0052] Figure 6a is a timing diagram showing a process in which the ADC circuit 150 of Figure 5 processes the pixel signal PIX according to a Reset-Sig-Sig-Reset (RSSR) method, and Figure 6b is a timing diagram showing a process in which the ADC circuit 150 of Figure 5 processes the pixel signal PIX according to a Reset-Reset-Sig-Sig (RRSS) method, which will be described below with reference to Figure 5 together with Figures 6a-6b.

[0053] 6a and 6b, a 1H time period is shown. The 1H time period may be a time period that must be guaranteed to drive a plurality of pixels of the pixel array 110 in units of rows. For example, the 1H time period may include a high conversion gain reset signal period HRST, a high conversion gain image signal period HSIG, a low conversion gain reset signal period LRST, and a low conversion gain image signal period LSIG.

[0054] Referring to FIG. 6a, a high conversion gain reset signal section HRST, a high conversion gain image signal section HSIG, a low conversion gain image signal section LSIG, and a low conversion gain reset signal section LRST are sequentially performed in RSSR.

[0055] In each of the multiple sections (HRST, HSIG, LSIG, and LRST), a high conversion gain reset signal VHRST, a high conversion gain image signal VHSIG, a low conversion gain image signal VLSIG, and a low conversion gain reset signal VLRST are output as components of a pixel signal PIX and converted into digital signals in order.

[0056] First, a reset signal VRST of a logic high level is applied to the gate of the reset transistor RST, and then a reset signal VRST of a logic low level is applied to the gate of the reset transistor RST. Then, in response to the auto-zero signal AZ, an adjustment can be made between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX. Next, a dual conversion signal VDC of a logic low level is applied to the gate of the dual conversion transistor DC, and a high conversion gain reset signal VHRST can be output in the HRST period. Then, a transfer signal VT of a logic high level is applied to the gate of the transfer transistor Tx, and a high conversion gain image signal VHSIG is output in the HSIG period.

[0057] Then, the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX can be adjusted again in response to the auto-zero signal AZ. Next, a reset signal VRST of a logic low level is applied to the gate of the reset transistor RST, a dual conversion signal VDC of a logic high level is applied to the gate of the dual conversion transistor DC, a transfer signal VT of a logic high level is applied to the gate of the transfer transistor Tx, and a low conversion gain image signal VLSIG is output in the LSIG period. Then, a reset signal VRST of a logic high level is applied to the gate of the reset transistor RST, and a low conversion gain reset signal VLRST is output in the LRST period.

[0058] When the ADC circuit 150 processes the pixel signal PIX according to the RSSR method as shown in FIG. 6a, if the counter 152 determines that it is not necessary to output a low conversion gain digital signal, the operation of the comparator 151 is stopped in response to the power down signal PD after the HSIG period ends, so that the LSIG period and the LRST period are omitted, and the power consumption of the ADC circuit 150 can be reduced.

[0059] Referring to FIG. 6b, a low conversion gain reset signal section LRST, a high conversion gain reset signal section HRST, a high conversion gain image signal section HSIG, and a low conversion gain image signal section LSIG are sequentially progressed RRSS (Reset-Reset-Sig-Sig).

[0060] First, a reset signal VRST of a logic high level is applied to the gate of the reset transistor RST, and then a reset signal VRST of a logic low level is applied to the gate of the reset transistor RST. Then, an adjustment between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX can be performed in response to the auto-zero signal AZ. Next, a dual conversion signal VDC of a logic high level is applied to the gate of the dual conversion transistor DC, and a low conversion gain reset signal VLRST can be output in the LRST period. Then, an adjustment between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX is performed again in response to the auto-zero signal AZ, and then a dual conversion signal VDC of a logic low level is applied to the gate of the dual conversion transistor DC, and a high conversion gain reset signal VHRST can be output in the HRST period.

[0061] Next, a transfer signal VT of a logic high level is applied to the gate of the transfer transistor Tx, and a high conversion gain image signal VHSIG is output in the HSIG section. Then, a dual conversion signal VDC of a logic high level is applied to the gate of the dual conversion transistor DC, a transfer signal VT of a logic high level is applied to the gate of the transfer transistor Tx, and a low conversion gain image signal VLSIG is output in the LSIG section.

[0062] When the ADC circuit 150 processes the pixel signal PIX according to the RRSS method as shown in FIG. 6b, if the counter 152 determines that it is not necessary to output a low conversion gain digital signal, the operation of the comparator 151 is stopped in response to the power down signal PD after the HSIG period ends, thereby omitting the LSIG period and reducing the power consumption of the ADC circuit 150.

[0063] 7 shows an example of the high conversion gain digital signal DS, which will be described below with reference to FIG.

[0064] Referring to FIG. 7, the digital signal DS may be 10 bits (DS[0] to DS[9]). Here, DS[0] is the most significant bit (MSB) and DS[9] is the least significant bit (LSB). The counter 152 can monitor the digital signal DS to calculate the value X of the upper bits. For example, the counter 152 can calculate the value of only the most significant bit DS[0], or can calculate the values ​​of the 0th to 2nd bits (DS[0] to DS[2]). However, the present invention is not limited thereto, and the counter 152 can also calculate the value X of the upper bits in a manner different from that described above.

[0065] Thereafter, the counter 152 may compare the value X of the most significant bit with a value of a predetermined threshold code. If the value X of the most significant bit is less than or equal to the value of the threshold code (X≦Threshold code), the counter 152 may determine that output of the low conversion gain digital signal is not necessary, and may generate a power-down signal PD. As described with reference to FIG. 5, the power-down signal PD may be provided to the comparator 151 (i.e., the first amplifier 151_1 or the second amplifier 151_2). In this case, the comparator 151 may not perform a comparison operation (e.g., an operation in the LSIG section or the LRST section in FIG. 6a to FIG. 6b) on the low conversion gain pixel signal, and power consumption of the ADC circuit 150 may be reduced.

[0066] On the other hand, if the value X of the most significant bit is greater than the value of the threshold code (X>Threshold code), the counter 152 may determine that a low conversion gain digital signal needs to be generated and may not generate the power-down signal PD. In this case, the comparator 151 may continue to perform a comparison operation (for example, an operation in the LSIG section and the LRST section in FIG. 6a-6b) on the low conversion gain pixel signal.

[0067] FIG. 8 shows the weights of high conversion gain pixel signals and low conversion gain pixel signals in image data according to the value of the high conversion gain digital signal DS. For example, assume that the value of the digital signal DS is expressed through the value of the most significant bit as described with reference to FIG. 7. TH represents the value of the threshold code, and HC_MAX represents the maximum value that the high conversion gain digital signal DS can have. The following description will be made with reference to FIG. 5 and FIG. 7 as well as FIG. 8.

[0068] 8, when generating image data, the region in which both the high conversion gain pixel signal and the low conversion gain pixel signal are involved is only the section where the value of the digital signal DS is between TH and HC_MAX. For example, this section may correspond to an intermediate illumination region between low illumination and high illumination. When the illumination is higher than this region (i.e., when the value of the digital signal DS reaches HC_MAX), only the low conversion gain pixel signal can be used, and when the illumination is lower (i.e., when the value of the digital signal DS is less than or equal to TH), only the high conversion gain pixel signal can be used.

[0069] In other words, when the value of the high conversion gain digital signal DS is smaller than or equal to TH, the low conversion gain pixel signal does not contribute to the generation of image data, so that it may be determined by the counter 152 that it is not necessary to output the low conversion gain digital signal. In this case, the power down signal PD is supplied to the comparator 151 (i.e., the first amplifier 151_1 or the second amplifier 151_2) to stop the comparison operation of the low conversion gain pixel signal (for example, stop the operation in the LRST section and the LSIG section in Figs. 6A to 6b), thereby reducing the power consumption of the ADC circuit 150.

[0070] That is, the counter 152 can grasp the value of the high conversion gain digital signal DS in real time to determine whether or not a low conversion gain digital signal is necessary, and based on the determination result, can control the operation of the comparator 151. Alternatively, in some cases, the comparison operation of the low conversion gain pixel signal cannot be stopped, and even if a low conversion gain digital signal is generated, pre-processing of the low conversion gain digital signal may not be performed in the ISP front-end block 16 of FIG.

[0071] 9 is a flow chart illustrating a method of operating an analog-to-digital conversion (ADC) circuit for optimizing power consumption in dual conversion gain operation according to an embodiment of the present invention, which will now be described with reference to FIG. 5 in conjunction with FIG.

[0072] In step S110, the comparator 151 can compare the high conversion gain pixel signal with the ramp signal to generate an output signal corresponding to a high conversion gain condition (hereinafter, high conversion gain output signal), and can compare the low conversion gain pixel signal with the ramp signal to generate an output signal corresponding to a low conversion gain condition (hereinafter, low conversion gain output signal). In step S120, the counter 152 can count pulses of the high conversion gain output signal and output the counted result as a high conversion gain digital signal.

[0073] In step S130, the counter 152 can determine whether or not it is necessary to output a low-conversion gain digital signal based on the high-conversion gain digital signal. Specifically, the counter 152 can compare the value of the high-conversion gain digital signal (e.g., the value of the most significant bit of the high-conversion gain digital signal) with the value of a predetermined threshold code. In step S140, if it is determined that it is not necessary to output a low-conversion gain digital signal, the counter 152 can control the comparator 151 not to generate a low-conversion gain output signal.

[0074] The above is a specific embodiment for carrying out the present invention. The present invention includes not only the above-mentioned embodiment, but also an embodiment that is simply modified or easily modified. The present invention also includes a technique that can be easily modified and carried out using the embodiment. Therefore, the scope of the present invention should not be limited to the above-mentioned embodiment, but should be determined not only by the claims described below, but also by equivalents to the claims of the present invention. [Explanation of symbols]

[0075] 100: Image sensor 110: Pixel array 120: Low Driver 130: Ramp signal generator 140: Voltage buffer 150:ADC circuit 151: Comparator 152: Counter 160: Timing controller 170: Buffer

Claims

1. A pixel array configured to output a first pixel signal corresponding to a first conversion gain from a first pixel and to output a second pixel signal corresponding to a second conversion gain from the first pixel; an analog-to-digital conversion circuit configured to output a first digital signal corresponding to the first pixel signal; and the analog-to-digital conversion circuit is configured to output a second digital signal corresponding to the second pixel signal based on a value of the first digital signal; the first conversion gain is higher than the second conversion gain; Image sensor.

2. The image sensor of claim 1, wherein the analog-to-digital conversion circuit is configured to output the second digital signal based on a comparison result between the value of at least some of the bits of the first digital signal and a threshold value.

3. The pixel array has a floating diffusion region connected to the first pixel, and a plurality of pixels connected to the floating diffusion region; the floating diffusion region has a first capacitance value when the pixel array outputs the first pixel signal; the floating diffusion region has a second capacitance value greater than the first capacitance value when the pixel array outputs the second pixel signal; 3. The image sensor according to claim 2.

4. An image sensor as described in Claim 3, wherein the analog-to-digital conversion circuit is configured to output the second digital signal when the value of at least some of the bits of the first digital signal is greater than the threshold value.

5. The image sensor of claim 4, wherein the analog-to-digital conversion circuit is configured not to generate the second digital signal when the value of at least some of the bits of the first digital signal is below the threshold value.

6. The pixel array further comprising: a dual conversion transistor connected to the floating diffusion region; and a reset transistor connected to the dual conversion transistor; the dual conversion transistor and the reset transistor are connected in series; 5. The image sensor according to claim 4.

7. The image sensor of claim 4, wherein the analog-to-digital conversion circuit is configured to output a first reset digital signal corresponding to a reset signal of the first pixel signal and the first digital signal before outputting the second digital signal.

8. The image sensor of claim 6, wherein the analog-to-digital conversion circuit is configured to output a first reset digital signal corresponding to the reset signal of the second pixel signal, and a second reset digital signal corresponding to the reset signal of the first pixel signal, before outputting the first digital signal.

9. An image sensor as described in claim 6, wherein at least a portion of the bits of the first digital signal include the most significant bit of the first digital signal.

10. A pixel array configured to output a first pixel signal corresponding to a first conversion gain from a first pixel and to output a second pixel signal corresponding to a second conversion gain from the first pixel; an analog-to-digital conversion circuit configured to output a first digital signal corresponding to the first pixel signal; and the analog-to-digital conversion circuit is configured to output a second digital signal corresponding to the second pixel signal based on a value of a most significant bit (MSB) of the first digital signal; the first conversion gain is higher than the second conversion gain; Image sensor.

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