Circuit including analog-to-digital converter using auto-zero period optimization, and operation method of the same

Abstract

To provide an analog-to-digital converter capable of reducing power consumption by utilizing auto-zero period optimization, and to provide an operation method thereof, and an image sensor including the analog-to-digital converter.SOLUTION: A circuit includes: a first amplifier that adjusts and equalizes voltage levels of an input node and an output node in response to a first auto-zero signal in a first auto-zero period, compares a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, compares the ramp signal and an image signal of the pixel signal in a second operation period, and generates a first output signal; and a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, and generates a second output signal on the basis of the first output signal in the first operation period and the second operation period. An operation of the second amplifier is stopped from a time point at which the second auto-zero period ends to a time point at which the first operation period starts.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter using auto-zero section optimization and a method of operating the same. [Background technology]

[0002] There are several types of image sensors, including CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide Semiconductor) image sensors (CIS). CMOS image sensors contain pixels made up of CMOS transistors, and convert light energy into electrical signals using the photoelectric conversion elements contained in each pixel. CMOS image sensors obtain information about the captured image using the electrical signals generated from each pixel.

[0003] An analog-to-digital converter (ADC) receives an analog input voltage generated by a pixel and converts it into a digital signal. The converted digital signal is then transferred to another device. ADCs are used in a variety of signal processing devices. As the performance of modern signal processing devices improves, improved resolution for analog signals is required. Therefore, ADCs are used that can process many signals in the same time and provide improved resolution for each signal, but they have the problem of increased power consumption. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,491,845 [Patent Document 2] U.S. Pat. No. 10,616,518 [Patent Document 3] U.S. Pat. No. 9,554,072 [Patent Document 4] U.S. Pat. No. 10,840,936 [Patent Document 5] U.S. Pat. No. 10,594,333 [Patent Document 6] US Patent Application Publication No. 2021 / 0134854 [Patent Document 7] US Patent Application Publication No. 2020 / 0228740 [Patent Document 8] US Patent Application Publication No. 2020 / 0266785 [Patent Document 9] JP 2019-146016 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide an analog-to-digital converter that reduces power consumption by utilizing auto-zero section optimization, an operating method thereof, and an image sensor including the same. [Means for solving the problem]

[0006] A circuit according to an embodiment of the present invention includes a first amplifier that adjusts the voltage levels of an input node and an output node to be equal in response to a first auto-zero signal during a first auto-zero period, compares a reset signal of a pixel signal output from a pixel array with a ramp signal during a first operating period, and compares an image signal of the pixel signal with the ramp signal during a second operating period to generate a first output signal, and a second amplifier that charges a capacitor in response to a second auto-zero signal during a second auto-zero period and generates a second output signal based on the first output signal during the first operating period and the second operating period. After the second auto-zero period ends, the second amplifier is stopped operating until the first operating period begins.

[0007] A method for operating an analog-to-digital converter circuit according to an embodiment of the present invention includes the steps of: adjusting voltage levels of an input node and an output node of a first amplifier to be equal in response to a first auto-zero signal during a first auto-zero period; charging a capacitor of a second amplifier in response to a second auto-zero signal during a second auto-zero period; stopping operation of the second amplifier from the end of the second auto-zero period until a first operating period begins; comparing a reset signal and a ramp signal of a pixel signal output from a pixel array during the first operating period, and comparing an image signal of the pixel signal and the ramp signal during a second operating period to generate a first output signal; and generating a second output signal based on the first output signal.

[0008] An image sensor according to an embodiment of the present invention includes a pixel array that converts light into an electrical signal to generate a pixel signal, a ramp signal generator that generates a ramp signal, and an analog-to-digital converter that converts the pixel signal into a digital signal. The analog-to-digital converter includes a first amplifier that adjusts voltage levels of an input node and an output node to be equal in response to a first auto-zero signal in a first auto-zero period, compares a reset signal of a pixel signal output from the pixel array with the ramp signal in a first operating period, and compares an image signal of the pixel signal with the ramp signal in a second operating period to generate a first output signal, a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, and generates a second output signal based on the first output signal in the first operating period and the second operating period, and a counter that counts pulses of the second output signal and outputs the counted result as a digital signal. After the second auto-zero period ends, the second amplifier stops operating before the first operating period begins.

[0009] A converter circuit according to an embodiment of the present invention includes a first transistor that charges a capacitor in response to an auto-zero signal during an auto-zero period, generates an output signal during an operation period, and provides a power supply voltage to a first output node to which the output signal is output; a second transistor that is turned on in response to the auto-zero signal and is connected to the capacitor via a bias node; a current source that is connected to the first transistor via the first output node, is connected to the capacitor and the second transistor via the bias node, and generates a power supply current based on the voltage level of the bias node held by the capacitor; and a third transistor that stops operation of the circuit by turning off in response to a power down signal. Effect of the Invention

[0010] According to an embodiment of the present invention, the power consumption of an analog-to-digital converter can be reduced by optimizing the auto-zero interval. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram showing an example of a configuration of an image processing block according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram illustrating an example of the configuration of an image sensor in FIG. [Diagram 3] FIG. 3 is a circuit diagram illustrating an example of one of the pixel groups in the pixel array of FIG. 2. [Figure 4] 3 is a diagram illustrating an example of the configuration of an analog-to-digital converter ADC in FIG. 2. [Diagram 5] FIG. 5 is a circuit diagram showing an example of a first amplifier in FIG. [Figure 6] FIG. 5 is a circuit diagram showing an example of the second amplifier of FIG. 4. [Figure 7] 5 is an example of a timing diagram illustrating the operation of the circuit of the analog-to-digital converter ADC of FIG. 4. [Figure 8]3 is a diagram illustrating another example of the circuit configuration of the analog-to-digital converter ADC in FIG. 2. [Figure 9] 9 is a circuit diagram showing another example of the second amplifier of FIG. 8. [Figure 10a] 10 is an example of a timing diagram showing the operation of the ADC circuit of FIG. 4 due to the operation of the feedback circuit of FIG. [Figure 10b] 10 is an example timing diagram illustrating operation of the ADC circuit of FIG. 4 with the auto-zero section optimization and feedback circuit operation of FIG. 9. [Figure 11] 9 is a circuit diagram showing another example of the second amplifier of FIG. 8. [Figure 12] 4 is a flowchart illustrating a circuit operation method of an analog-to-digital converter ADC using auto-zero interval optimization according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, embodiments of the present invention are described clearly and in detail so that those skilled in the art can easily practice the present invention.

[0013] Components described with reference to terms such as unit, module, block, or, or er in the detailed description and functional blocks illustrated in the drawings may be implemented in the form of software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive elements, or a combination thereof.

[0014] 1 shows an example of a configuration of an image processing block 10 according to an embodiment of the present invention. The image processing block 10 may be implemented as part of a variety of electronic devices such as a smartphone, a digital camera, a laptop, a desktop, etc. The image processing block 10 may include a lens 12, an image sensor 14, an ISP front end block (Image Signal Processor front end block) 16, and an image signal processor 18.

[0015] Light is reflected by an object, a scene, etc. to be photographed, and the lens 12 can receive the reflected light. The image sensor 14 can generate an electrical signal based on the light received through the lens 12. For example, the image sensor 14 may be realized by a complementary metal oxide semiconductor (CMOS) image sensor, etc. For example, the image sensor 14 may be a multi-pixel image sensor having a dual pixel structure or a tetracell structure.

[0016] The image sensor 14 may include a pixel array. The pixels of the pixel array may convert light into electrical signals to generate pixel values. Additionally, the image sensor 14 may include Analog-to-Digital Converter (ADC) circuitry for performing Correlation Double Sampling (CDS) on the pixel values. The configuration of the image sensor 14 will be described in more detail with reference to FIG. 2.

[0017] The ISP front-end block 16 can pre-process the electrical signals output from the image sensor 14 and process them into a form suitable for processing by the image signal processor 18 .

[0018] The image signal processor 18 can appropriately process the electrical signals processed by the ISP front-end block 16 to generate image data related to the photographed object, scene, etc. To this end, the image signal processor 18 can perform various processes such as color correction, auto white correction, gamma correction, color saturation correction, bad pixel correction, and hue correction.

[0019] 1 shows one lens 12 and one image sensor 14. However, in other embodiments, the image processing block 10 may include multiple lenses, multiple image sensors, and multiple ISP front-end blocks. In this case, the multiple lenses may each have a different angle of view. Furthermore, the multiple image sensors may have different functions, performance, and / or characteristics, and may include pixel arrays with different configurations.

[0020] Fig. 2 shows an example of the configuration of the image sensor 14 in Fig. 1. The image sensor 100 may include a pixel array 110, a row driver 120, a ramp signal generator 130, a voltage buffer 140, an ADC circuit 150, a timing controller 160, and a buffer 170.

[0021] The pixel array 110 may include a plurality of pixels arranged in a matrix along rows and columns. Each of the plurality of pixels may include a photoelectric conversion element. For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0022] The pixel array 110 may include multiple pixel groups PG. Each pixel group PG may include two or more pixels. The pixels that make up a pixel group may share a floating diffusion region or multiple floating diffusion regions. Although the pixel array 110 of FIG. 2 is shown to include four rows and four columns (i.e., 4×4) of pixel groups PG, the invention is not so limited.

[0023] A pixel group PG may include pixels of the same color. For example, a pixel group PG may include red pixels that convert light in the red spectral region into an electrical signal, green pixels that convert light in the green spectral region into an electrical signal, or blue pixels that convert light in the blue spectral region into an electrical signal. For example, the pixels that make up the pixel array 110 may be arranged in the form of a Tetra-Bayer Pattern.

[0024] Each of the pixels of the pixel array 110 can output a pixel signal along the column lines CL1-CL4 according to the intensity or amount of light received from the outside. For example, the pixel signal can be an analog signal corresponding to the intensity or amount of light received from the outside. The pixel signal may pass through a voltage buffer (e.g., a source follower) and be provided to the ADC circuit 150 via the column lines CL1-CL4.

[0025] The row driver 120 may select and drive rows of the pixel array 110. The row driver 120 may decode addresses and / or control signals generated by the timing controller 160 to generate control signals for selecting and driving rows of the pixel array 110. For example, the control signals may include signals for selecting pixels or signals for resetting floating diffusion regions.

[0026] The ramp signal generator 130 can generate the ramp signal RAMP under the control of the timing controller 160. For example, the ramp signal generator 130 can operate under a control signal such as a ramp enable signal. When the ramp enable signal is activated, the ramp signal generator 130 can generate the ramp signal RAMP according to a predetermined value (e.g., a start level, an end level, a slope, etc.). In other words, the ramp signal RAMP can be a signal that increases or decreases according to a predetermined slope over a certain time. The ramp signal RAMP can be provided to the ADC circuit 150 through the voltage buffer 140.

[0027] The ADC circuit 150 can receive pixel signals from a plurality of pixels of the pixel array 110 via column lines CL1-CL4, and can receive a ramp signal RAMP from the ramp signal generator 130 via a voltage buffer 140. The ADC circuit 150 can operate based on a correlated double sampling CDS technique that obtains a reset signal and an image signal for the received pixel signal and extracts the difference into a useful signal component. The ADC circuit 150 can include a plurality of comparators COMP and a counter CNT.

[0028] Specifically, the comparator COMP may compare a reset signal of the pixel signal with the ramp signal RAMP, and may compare an image signal of the pixel signal with the ramp signal RAMP to perform correlated double sampling CDS. The counter CNT may count pulses of the correlated double sampled signal and output the result as a digital signal. The ADC circuit 150 of the present invention may be implemented to reduce power consumption using auto-zero section optimization and / or output feedback. Although the ADC circuit 150 of FIG. 2 is shown to include four comparators COMP and four counters CNT, the present invention is not limited thereto.

[0029] The timing controller 160 may generate control signals and / or clocks for controlling the operation and / or timing of each of the row driver 120, the ramp signal generator 130, and the ADC circuit 150.

[0030] The buffer 170 may include a memory MEM and a sense amplifier SA. The memory MEM may store a digital signal output from a corresponding counter CNT of the ADC circuit 150. The sense amplifier SA may sense and amplify the stored digital signal. The sense amplifier SA may output the amplified digital signal as image data IDAT, which may be transferred to the ISP front-end block 16 of FIG. 1.

[0031] Fig. 3 is a circuit diagram showing an example of one of the pixel groups PG of the pixel array 110 of Fig. 2. For example, the pixel group PG may include pixels PX1-PX4, photoelectric conversion elements PD1-PD4, transfer transistors Tx1-Tx4, reset transistors RST, dual conversion transistor DC, drive transistor Dx, and selection transistor SEL. Although the pixel group PG of Fig. 3 is shown as having a tetracell structure in which four pixels PX1-PX4 each include a photoelectric conversion element PD1-PD4, the present invention is not limited thereto, and the pixel group PG may be implemented to have various other structures.

[0032] The first pixel PX1 may include a first photoelectric conversion element PD1 and a first transfer transistor Tx1, and the other pixels PX2, PX3, and PX4 may each include similar components. Each of the pixels PX1 to PX4 may share a reset transistor RST, a dual conversion transistor DC, a drive transistor Dx, and a selection transistor SEL. Each of the pixels PX1 to PX4 may share a first floating diffusion region FD1. The reset transistor RST and the dual conversion transistor DC may share a second floating diffusion region.

[0033] The first floating diffusion region FD1 or the second floating diffusion region FD2 can accumulate charges corresponding to the amount of incident light. While the transfer transistors Tx1 to Tx4 are turned on by the transfer signals VT1 to VT4, respectively, the first floating diffusion region FD1 or the second floating diffusion region FD2 can receive and accumulate charges from the photoelectric conversion elements PD1 to PD4. The first floating diffusion region FD1 may be connected to the gate terminal of the drive transistor Dx driven as a source follower amplifier, so that a voltage corresponding to the charges accumulated in the first floating diffusion region FD1 may be formed. For example, the capacitance of the first floating diffusion region FD1 may be represented by a first capacitance CFD1.

[0034] The dual conversion transistor DC is driven by a dual conversion signal VDC. When the dual conversion transistor DC is turned off, the capacitance of the first floating diffusion region FD1 may correspond to a first capacitance CFD1. In a typical environment, since the first floating diffusion region FD1 is not easily saturated, the need to increase the capacitance of the first floating diffusion region FD1 (i.e., CFD1) may not be required, and the dual conversion transistor DC may be turned off.

[0035] However, in a high-illumination environment, the first floating diffusion region FD1 can easily become saturated. To prevent such saturation, the dual conversion transistor DC can be turned on, and the first floating diffusion region FD1 is electrically coupled to the second floating diffusion region FD2, so that the capacitance of the floating diffusion regions FD1 and FD2 can be expanded to the sum of the first capacitance CFD1 and the second capacitance CFD2.

[0036] The transfer transistors Tx1 to Tx4 are driven by transfer signals VT1 to VT4, respectively, and can transfer the charges generated by the photoelectric conversion elements PD1 to PD4 to the first floating diffusion region FD1 or the second floating diffusion region FD2. For example, one end of each of the transfer transistors Tx1 to Tx4 can be connected to the photoelectric conversion elements PD1 to PD4, respectively, and the other end can be connected to the first floating diffusion region FD1.

[0037] The reset transistor RST is driven by a reset signal VRST and can provide a power supply voltage VDD to the first floating diffusion region FD1 or the second floating diffusion region FD2, so that the charge stored in the first floating diffusion region FD1 or the second extended floating diffusion region FD2 can be transferred to the power supply voltage VDD terminal, and the voltage of the first floating diffusion region FD1 or the second floating diffusion region FD2 may be reset.

[0038] The driving transistor Dx can amplify the voltage of the first floating diffusion region FD1 or the second floating diffusion region FD2 to generate a pixel signal PIX. The selection transistor SEL is driven by a selection signal VSEL and can select pixels to be read row by row. When the selection transistor SEL is turned on, the pixel signal PIX is output to the ADC circuit 150 of FIG. 2 via a column line CL.

[0039] 4 shows an example of the configuration of the circuit 150 of the analog-to-digital converter ADC of FIG. 2. The ADC circuit 150 may include a comparator 151 and a counter 152. The ADC circuit 150 can convert a pixel signal PIX, which is an analog signal output from the pixel array 110, into a digital signal DS and output the digital signal DS. For clear explanation and simplicity of the drawings, the pixel array 110 of FIG. 4 is shown for only one pixel, and the configuration and function of the pixel array 110 are the same as those described with reference to FIG. 3.

[0040] Specifically, as described with reference to Fig. 2, the comparator 151 may compare a reset signal of a pixel signal with the ramp signal RAMP and may compare an image signal of the pixel signal with the ramp signal RAMP to perform correlated double sampling CDS, and the counter 152 may count pulses of the correlated double sampled signal and output the counted signal as a digital signal. Hereinafter, the description will be made with reference to Figs. 2 and 3 as well as Fig. 4.

[0041] For example, the comparator 151 may have a two-stage structure including two amplifiers (a first amplifier 151_1 and a second amplifier 151_2), and the first amplifier 151_1 and the second amplifier 151_2 may be implemented as an operational transconductance amplifier (OTA), but the present invention is not limited thereto. For example, the comparator 151 may have a structure including more amplifiers. Note that the ADC circuit 150 may include multiple comparators and counters, but for clarity, FIG. 5 shows one comparator 151 and one counter 152.

[0042] The first amplifier 151_1 may receive the pixel signal PIX from the pixel array 110 via the column line CL, and may receive the ramp signal RAMP from the ramp signal generator 130 via the voltage buffer 140. The first amplifier 151_1 may output a first output signal OTA1_OUT based on the received signal. For example, the first amplifier 151_1 may output a first output signal OTA1_OUT having a high level during a period in which the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, and may output a first output signal OTA1_OUT having a low level during a period in which the level of the ramp signal RAMP is lower than the level of the pixel signal PIX. The comparison operation of the first amplifier 151_1 described above is performed between the reset signal of the pixel signal PIX and the ramp signal RAMP, and between the image signal of the pixel signal PIX and the ramp signal RAMP.

[0043] The second amplifier 151_2 may amplify the first output signal OTA1_OUT to output a second output signal OTA2_OUT, which is a comparison signal. For example, the second output signal OTA2_OUT may be an inverted signal of the first output signal OTA1_OUT. In other words, the second amplifier 151_2 may be implemented to output the second output signal OTA2_OUT having a low level while the first output signal OTA1_OUT has a high level, and to output the second output signal OTA2_OUT having a high level while the first output signal OTA1_OUT has a low level.

[0044] In the following description, the comparison operation of the comparator 151 and the change in the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT from a high level to a low level or from a low level to a high level will be referred to as a decision of the ADC circuit 150. In other words, "after the decision of the circuit 150 is completed" can mean "after the voltage level of the first output signal OTA1_OUT or the second output signal OTA2_OUT changes from a high level to a low level or from a low level to a high level."

[0045] The comparator 151 may be initialized in response to an auto-zero signal in an auto-zero section before a comparison operation is performed, and may perform the comparison operation again. Specifically, the first amplifier 151_1 is initialized in response to a first auto-zero signal AZ_OTA1, and the second amplifier 151_2 is initialized in response to a second auto-zero signal AZ_OTA2.

[0046] In the following description, the auto-zero section of the first amplifier 151_1 will be referred to as the first auto-zero section, and the auto-zero section of the second amplifier 151_2 will be referred to as the second auto-zero section. For example, during the first auto-zero section and the second auto-zero section, the voltage levels of the input node and / or the output node of the first amplifier 151_1 and the second amplifier 151_2 may be equal.

[0047] It should be noted that the time it takes for the first amplifier 151_1 to be initialized and the time it takes for the second amplifier 151_2 to be initialized may be different from each other. For example, the time it takes for the first amplifier 151_1 to be initialized may be longer than the time it takes for the second amplifier 151_2 to be initialized. In this case, when the initialization of the second amplifier 151_2 is completed, the corresponding second auto-zero signal AZ_OTA2 may no longer be applied to the second amplifier 151_2.

[0048] In other words, if the initialization of the second amplifier 151_2 is completed earlier than the initialization of the first amplifier 151_1, the second auto-zero section may be adjusted to end regardless of the remaining length of the first auto-zero section. That is, the second auto-zero section of the present invention may be optimized to end when the initialization of the second amplifier 151_2 is completed. For example, when the second auto-zero section ends, the second amplifier 151_2 may be realized not to consume power until the comparison operation of the first amplifier 151_1 is performed. For this purpose, the second amplifier 151_2 may include a switch for temporarily stopping power consumption in response to the end of the second auto-zero section. Such auto-zero section optimization can reduce the power consumption of the ADC circuit 150.

[0049] The counter 152 can operate under the control of the timing controller 160, and can count the pulses of the corresponding second output signal OTA2_OUT and output it as a digital signal DS. For example, the counter 152 can operate under control signals such as a counter clock signal CNT_CLK and an inversion signal CONV that inverts an internal bit of the counter 152.

[0050] For example, the counter 152 may include an up / down counter and a bit-wise inversion counter. The bit-wise inversion counter can perform the same operation as the up / down counter. For example, the bit-wise inversion counter can perform only an up count function and a function of inverting all bits in the counter to 1's complement when a specific signal is input. The bit-wise inversion counter can perform a reset count and then invert the result to convert it to a 1's complement (i.e., a negative number).

[0051] Fig. 5 is a circuit diagram showing an example of the first amplifier 151_1 of Fig. 4. The first amplifier 200 may include a plurality of transistors TR11 to TR16, a plurality of switches SW1 to SW2, and a first current source 210. For example, the first transistor TR11, the second transistor TR12, the fifth transistor TR15, and the sixth transistor TR16 may be NMOS transistors, and the third transistor TR13 and the fourth transistor TR14 may be PMOS transistors. However, the present invention is not limited thereto, and the first to sixth transistors TR11 to TR16 may be transistors of different types from those shown in Fig. 5.

[0052] 5, a ramp signal RAMP is input to a gate terminal of a first transistor TR11, and a pixel signal PIX is input to a gate terminal of a second transistor TR12. Source terminals of the first and second transistors TR11 and TR12 are connected to a first current source 210 at a common node COMM. For example, the third and fourth transistors TR13 and TR14 may be connected in the form of a current mirror. The sum of the currents flowing through the first and second transistors TR11 and TR12 may be equal to a first power supply current ISS1.

[0053] The gate terminal and the drain terminal of the third transistor TR13 and the drain terminal of the first transistor TR11 are commonly coupled to the second output node OUT12, and the drain terminal of the fourth transistor TR14 and the drain terminal of the second transistor TR12 are commonly coupled to the first output node OUT11. The fifth transistor TR15 may be coupled between the first output node OUT11 and the second output node OUT12. For example, the fifth transistor TR15 may limit the voltage level of the signal output from the first output node OUT11.

[0054] A first output signal OTA1_OUT is output from a first output node OUT11, and an inverted first output signal OTA1_OUT` is output from a second output node OUT12. For example, the first output signal OTA1_OUT may have a high level during an interval in which the level of the ramp signal RAMP is higher than the level of the pixel signal PIX, and may have a low level during an interval in which the level of the ramp signal RAMP is lower than the level of the pixel signal PIX. The first output signal OTA1_OUT may be provided to the second amplifier 151_2 of FIG. 4.

[0055] The first current source 210 may include a sixth transistor TR16. The sixth transistor TR16 is coupled to a ground voltage VSS and may generate a first power supply current ISS1 based on a first bias signal BIAS1.

[0056] Meanwhile, during the first auto-zero period, the switches SW1 and SW2 may be turned on in response to the first auto-zero signal AZ_OTA1. When the switches SW1 and SW2 are turned on, the second input node IN12 and the first output node OUT11 are connected to each other, and the first input node IN11 and the second output node OUT12 are connected to each other. Therefore, during the first auto-zero period, the levels of the first input node IN11, the second input node IN12, the first output node OUT11, and the second output node OUT12 may be equal to each other. Although not shown, the first capacitor connected to the first input node IN11 may receive the ramp signal RAMP, and the second capacitor connected to the second input node IN12 may receive the pixel signal PIX. For example, the first and second capacitors may operate as auto-zero level sampling capacitors.

[0057] Fig. 6 is a circuit diagram showing an example of the second amplifier 151_2 of Fig. 4. The second amplifier 300 may include a plurality of transistors TR21-TR24, a capacitor C1, a switching circuit 310, and a current source 320. For example, the seventh and tenth transistors TR21, TR24 may be PMOS transistors, and the eighth to ninth transistors TR22, TR23 may be NMOS transistors. However, the present invention is not limited thereto, and the seventh to tenth transistors TR21-TR24 may be transistors of different types from those shown in Fig. 6.

[0058] The seventh transistor TR21 may receive the first output signal OTA1_OUT from the first amplifier 151_1 of FIG. 4 as an input, and may operate in response to the first output signal OTA1_OUT. For example, when the voltage level of the first output signal OTA1_OUT is high, the seventh transistor TR21 is turned off, and no current flows to the third output node OUT21, so that the voltage level of the second output signal OTA2_OUT can be low. Conversely, when the voltage level of the first output signal OTA1_OUT is low, the seventh transistor TR21 is turned on, and a current flows to the third output node OUT21, so that the voltage level of the second output signal OTA2_OUT can be high. In other words, the second amplifier 300 may operate as an inverting amplifier. That is, when the voltage level of the first output signal OTA1_OUT increases, the voltage level of the second output signal OTA2_OUT may decrease.

[0059] The switching circuit 310 may include an eighth transistor TR22 coupled between the third output node OUT21 and a bias node BN. During the second auto-zero period, the eighth transistor TR22 may operate in response to the second auto-zero signal AZ_OTA2 and may be turned on in response to the activated second auto-zero signal AZ_OTA2. When the eighth transistor TR22 is turned on, the voltage level of the bias node BN may become equal to the voltage level of the third output node OUT21, and a charge may be charged in the capacitor C1 coupled to the bias node BN.

[0060] When the capacitor C1 is fully charged, the second amplifier 300 is initialized and the second auto-zero section can be terminated. That is, the length of the second auto-zero section is optimized based on the time it takes for the capacitor C1 coupled to the bias node BN to be charged. As described with reference to FIG. 4, the optimized length of the second auto-zero section can be shorter than the length of the first auto-zero section.

[0061] On the other hand, while the ADC circuit 150 of FIG. 4 is performing a comparison operation, when the second auto-zero signal AZ_OTA2 is inactivated and the eighth transistor TR22 is turned off, the voltage level of the bias node BN, which becomes equal to the voltage level of the third output node OUT21, is maintained by the capacitor C1, thereby allowing the current source 320 to operate.

[0062] The current source 320 may include a ninth transistor TR23 coupled to the third output node OUT21. The ninth transistor TR23 may generate a power supply current ISS2 based on the voltage of the bias node BN, i.e., the voltage of one end of the capacitor C1.

[0063] As described above, when the capacitor C1 connected to the bias node BN is fully charged, the second auto-zero signal AZ_OTA2 is deactivated and the second auto-zero period ends. At this time, the tenth transistor TR24 is turned off in response to the activated power-down signal PD, so that the operation of the second amplifier 300 can be temporarily stopped (i.e., temporarily powered down). That is, the tenth transistor TR24 can operate as a power-down switch for the second amplifier 300.

[0064] The operation of the second amplifier 300 may be stopped before the first amplifier 200 performs the comparison operation. In other words, when the first auto-zero interval of the first amplifier 200 ends (i.e., when the first auto-zero signal AZ_OTA1 is deactivated), the power-down signal PD is deactivated, the tenth transistor TR24 is turned on, and the second amplifier 300 starts operating again.

[0065] In other words, the tenth transistor TR24 may be turned on in response to the power down signal PD of a low level during the second auto-zero period and the comparison operation period, and may be turned off in response to the power down signal PD of a high level during the second auto-zero period and the comparison operation period. Due to such an operation of the tenth transistor TR24, the second amplifier 300 may reduce power consumption during the second auto-zero period and the comparison operation period.

[0066] Fig. 7 is an example of a timing diagram showing the operation of the circuit 150 of the analog-to-digital converter ADC of Fig. 4. Referring to Fig. 7, the time from t0 to t2 is defined as an auto-zero section (including a first auto-zero section and a second auto-zero section), and the time from t2 to t11 is defined as a comparison operation section. More specifically, the time from t3 or t4 to t6 is defined as a first operation section, the time from t6 or t9 to t10 is defined as a second operation section, the time from t0 to t2 is defined as a first auto-zero section, and the time from t0 to t1 is defined as a second auto-zero section. And the time from t1 to t2 is defined as a power-down section.

[0067] Before time t0, a selection signal VSEL is activated, and pixel signals PIX are output from a plurality of pixel groups (for example, pixel groups as shown in FIG. 3) of the pixel array of FIG. 2. A power supply voltage can be provided by a reset signal VRST activated before time t0. In the embodiment, the level of the pixel signal PIX and the level of the ramp signal RAMP can be determined by a circuit (not shown) before time t0 and after time t11. Hereinafter, a description will be given with reference to FIG. 7 as well as FIG. 4 to FIG. 6.

[0068] The first auto-zero signal AZ_OTA1 is activated from time t0 to time t2. The second auto-zero signal AZ_OTA2 is activated from time t0 to time t1 and deactivated from time t1 to time t2. The first amplifier 151_1 may be initialized in response to the first auto-zero signal AZ_OTA1 during the first auto-zero interval (from time t0 to time t2), and the second amplifier 151_2 is initialized in response to the second auto-zero signal AZ_OTA2 during the second auto-zero interval (from time t0 to time t1).

[0069] As described with reference to Fig. 6, the length of the second auto-zero section is determined based on the time it takes to fully charge a capacitor (e.g., C1 in Fig. 6) included in the second amplifier 151_2. When the initialization of the second amplifier 151_2 is completed, the second auto-zero signal AZ_OTA2 is deactivated and the second auto-zero section can end.

[0070] At this time, the power-down signal PD is activated to turn off a power-down switch (for example, TR24 in FIG. 6) of the second amplifier 151_2, thereby temporarily stopping the operation of the second amplifier 151_2 from time t1 to time t2. This makes it possible to reduce the power consumption of the second amplifier 151_2 from time t1 to time t2, and also to reduce the power consumption of the entire ADC circuit 150. The power-down signal PD is deactivated again when the first auto-zero period ends and the comparison operation period begins.

[0071] In order to digitally convert the reset signal of the pixel signal PIX, an offset can be added to the ramp signal RAMP at time t3, and the ramp signal RAMP can decrease from time t4. The counter 152 can count the counting clock signal CNT_CLK from time t4 to time t5 when the polarity of the second output signal OTA2_OUT, which is the output of the second amplifier 151_2, changes.

[0072] When the digital conversion of the reset signal is completed, an offset is again added to the ramp signal RAMP at time t6 to convert the image signal of the pixel signal PIX into a digital signal at time t6, and the bit of the counter 152 is inverted in response to the inversion signal CONV at time t7. At time t8, the transfer signal VT is activated, and the voltage level of the input node of the first amplifier 151_1, which receives the pixel signal PIX, may change due to the charge accumulated by the photoelectric conversion element PD during that time.

[0073] For digital conversion of the image signal, the level of the ramp signal RAMP may decrease at time t9. The counter 152 may count the count clock signal CNT_CLK from time t9 to time t10 at which the polarity of the second output signal OTA2_OUT, which is the output of the second amplifier 151_2, changes. For example, the counter 152 in FIG. 4 may output the digital signal DS at time t10. When the digital conversion of the image signal is completed, the ADC circuit 150 may be initialized for the next comparison operation (i.e., correlated double sampling).

[0074] Although the operation timing of the ADC circuit 150 has been described with reference to FIG. 7, the present invention is not limited thereto, and the timing of the signals can be changed depending on the implementation method of the ADC circuit 150 (e.g., the structures of the first amplifier 151_1 and the second amplifier 151_2, etc.).

[0075] 8 shows another example of the configuration of the circuit 150 of the analog-to-digital converter ADC of FIG. 2. Referring to FIG. 8, the second output signal OTA2_OUT may be fed back to the second amplifier 151_2. The second output signal OTA2_OUT fed back to the second amplifier 151_2 may control the power supply (e.g., a current source) of the second amplifier 151_2, and may reduce the power consumption of the ADC circuit 150. Such an output feedback operation of the second amplifier 151_2 may be performed when the first amplifier 151_1 performs a comparison operation between the reset signal of the pixel signal PIX and the ramp signal RAMP, and when the first amplifier 151_1 performs a comparison operation between the image signal of the pixel signal PIX and the ramp signal RAMP.

[0076] That is, the ADC circuit 150 of Figure 8 performs not only the auto-zero section optimization but also an output feedback operation, thereby further reducing power consumption compared to the ADC circuit 150 of Figure 4. The ADC circuit 150 of Figure 8 can perform the same functions as those described with reference to Figure 4 except for the output feedback operation described above, and therefore a duplicated description will be omitted.

[0077] FIG. 9 is a circuit diagram showing another example of the second amplifier 151_2 of FIG. 8. The second amplifier 300a may further include an eleventh transistor TR25 and a feedback circuit 330. For example, the eleventh transistor TR25 may be an NMOS transistor. However, the present invention is not limited thereto, and the eleventh transistor TR25 may be a different type of transistor from that shown in FIG. 9. Referring to FIG. 9, when the seventh transistor TR21 is turned on, a current may also flow through the eleventh transistor TR25. The second output signal OTA2_OUT may be transferred to the feedback circuit 330.

[0078] The feedback circuit 330 may control the current source 320 based on the second output signal OTA2_OUT and the feedback active signal FB_EN. To perform such an output feedback operation, the feedback circuit 330 may include a logic gate 331. For example, the logic gate 331 may be a NAND gate.

[0079] The logic gate 331 may output the feedback signal FB in response to the second output signal OTA2_OUT and the feedback active signal FB_EN. For example, the logic gate 331 may be implemented such that when the voltage level of the feedback active signal FB_EN and the voltage level of the second output signal OTA2_OUT are both at a high level, the voltage level of the feedback signal FB can be at a low level.

[0080] When the voltage level of the feedback signal FB is high, the eleventh transistor TR25 is turned on and the power supply current ISS2 can flow through the eleventh transistor TR25. However, when the voltage level of the feedback signal FB is low, the eleventh transistor TR25 is turned off and the power supply current ISS2 cannot flow through the eleventh transistor TR25.

[0081] Specifically, after the comparison operation between the ramp signal RAMP and the pixel signal PIX is completed, the voltage level of the first output signal OTA1_OUT may be a low level, and the voltage level of the second output signal OTA2_OUT may be a high level. At this time, before the feedback activation signal FB_EN is activated, the feedback signal FB may be a high level, the eleventh transistor TR25 may be in a turned-on state, and the power supply current ISS2 may flow through the eleventh transistor TR25.

[0082] On the other hand, when the feedback activation signal FB_EN is activated (i.e., the voltage level of the feedback activation signal FB_EN becomes high), the feedback signal FB becomes low and the eleventh transistor TR25 is turned off, so that the power supply current ISS2 cannot flow through the eleventh transistor TR25. As a result, by utilizing the output feedback after the comparison operation is completed, the power consumption of the second amplifier 300 can be reduced, and the power consumption of the ADC circuit 150 can also be reduced.

[0083] As the difference in power consumption before and after the comparison operation continues, the performance of the image sensor (e.g., the performance of the ADC circuit that converts pixel signals into digital signals) may deteriorate. After the comparison operation is performed by the operation of the feedback circuit 330 described above, when the power supply current ISS2 cannot flow through the output nodes OUT21 and OUT22, the difference in power consumption before and after the comparison operation can be reduced. Therefore, the problem of performance deterioration of the image sensor can be improved by the operation of the feedback circuit 330.

[0084] On the other hand, although the logic gate 331 in FIG. 9 is shown as a NAND gate, the present invention is not so limited and the feedback circuit 330 may be implemented as any other configuration (e.g., as a NOR gate and an inverting amplifier) ​​that enables the voltage level of the feedback signal FB to go to a low level when the voltage level of the second output signal OTA2_OUT goes to a high level.

[0085] Although the feedback circuit 330 of FIG. 9 is shown to directly receive the second output signal OTA2_OUT, the present invention is not limited thereto. For example, the feedback circuit 330 of FIG. 9 may receive another signal based on the second output signal OTA2_OUT. For example, the second amplifier 300a may further include a transistor, a switch, an inverter, or a logic gate coupled between the seventh transistor TR21 and the third output node OUT21. In this case, the logic gate 331 of the feedback circuit 330 may receive a signal obtained by passing the second output signal OTA2_OUT through a transistor, a switch, an inverter, or a logic gate coupled between the seventh transistor TR21 and the third output node OUT21, and may perform the comparison operation as described above.

[0086] In other words, the feedback circuit 330 can receive the second output signal OTA2_OUT as is, or the second output signal OTA2_OUT passed through a transistor, switch, inverter or logic gate between the seventh transistor TR21 and the third output node OUT21.

[0087] In conclusion, the second amplifier 300a in Fig. 9 may further reduce power consumption compared to the second amplifier 300 in Fig. 6 by using both the operation of the tenth transistor TR24 due to optimization of the second auto-zero section and the operation of the feedback circuit 330. The configuration and function of the second amplifier 300a shown in Fig. 9 are the same as those of the second amplifier 300 in Fig. 6, except for the operation of the feedback circuit 330 described above, so a duplicated description will be omitted.

[0088] 10a is an example of a timing diagram showing the operation of the ADC circuit 150 of FIG. 4 according to the operation of the feedback circuit 330 of FIG. 9, and FIG. 10b is an example of a timing diagram showing the operation of the ADC circuit 150 of FIG. 4 according to the operation of the auto-zero section optimization and feedback circuit 330 of FIG. 9. That is, FIG. 10a corresponds to the case where the second amplifier 300a of FIG. 9 uses only the output feedback operation, and FIG. 10b corresponds to the case where the second amplifier 300a of FIG. 9 uses both the auto-zero section optimization and the output feedback operation. In addition, in the case of FIG. 10a, it is assumed that the length of the second auto-zero section is not optimized and is similar to the length of the first auto-zero section, and that the power-down signal PD is not activated.

[0089] 10a and 10b, the section T0 may correspond to an auto-zero section, the sections T1 to T3 may correspond to sections in which the comparator 151 compares the reset signal of the pixel signal PIX with the ramp signal RAMP, and the sections T4 to T6 may correspond to sections in which the comparator 151 compares the image signal of the pixel signal PIX with the ramp signal RAMP. The feedback activation signal FB_EN is activated when the determination of the ADC circuit 150 ends (i.e., when the sections T2 and T5 end). For example, the voltage level of the feedback activation signal FB_EN is maintained at a high level during the sections T2 to T3 and / or the sections T5 to T6 in which the ramp signal RAMP is ramped.

[0090] Based on the feedback enable signal FB_EN and the second output signal OTA2_OUT, the feedback circuit 330 can output a feedback signal FB. In response to the feedback signal FB at a low level, a transistor (e.g., the eleventh transistor TR25 in FIG. 9) between the current source 320 and the output node can be turned off, and the power supply current ISS2 can not flow.

[0091] Therefore, the level of the power supply current ISS2 is maintained approximately equal in the intervals T1 to T3 and T4 to T6 by the operation of the feedback circuit 330. For example, the level of the power supply current ISS2 may be close to zero in the intervals T1 to T3 and T4 to T6. This allows the power consumption of the ADC circuit 150 to be reduced.

[0092] 10b, the auto-zero period T0 is divided into a first auto-zero period in which the first auto-zero signal AZ_OTA1 is activated and a second auto-zero period in which the second auto-zero signal AZ_OTA2 is activated. As described with reference to FIGS. 4 and 6, the second auto-zero period ends after the capacitor (e.g., capacitor C1 in FIG. 6) included in the second amplifier 151_2 is fully charged.

[0093] Then, when the second auto-zero period ends, the power-down signal PD is activated, and the operation of the second amplifier 151_2 can be temporarily stopped before the comparison operation period begins. Therefore, the power supply current ISS2 cannot flow while the power-down signal PD is activated, and the power consumption of the ADC circuit 150 can be reduced. In conclusion, referring to FIG. 10b, the second amplifier 151_2 is initialized through the optimization of the auto-zero period, and the level of the power supply current ISS2 approaches 0 before the comparison operation period begins, so that the power consumption of the ADC circuit 150 can be further reduced compared to FIG. 10a.

[0094] 11 is a circuit diagram showing another example of the second amplifier 151_2 of FIG. 8. The second amplifier 300b may further include a control circuit 340. The control circuit 340 may adjust the output of the control current ICN to reduce a difference in power consumption of the second amplifier 300b before and after performing the comparison operation. The control circuit 340 may include twelfth and thirteenth transistors TR26 and TR27 connected between the power supply voltage VDD and the third output node OUT21 and connected in parallel with the seventh transistor TR21 and the tenth transistor TR24.

[0095] The twelfth transistor TR26 can operate in response to a control signal CN, and the thirteenth transistor TR27 can operate in response to a second bias signal BIAS2. Here, the control signal CN is generated from the timing controller 160 of FIG. 2. In the embodiment, the gate of the thirteenth transistor TR27 is coupled to a bias node BN. For example, the twelfth to thirteenth transistors TR26 and TR27 can be NMOS transistors. However, the present invention is not limited thereto, and the twelfth to thirteenth transistors TR26 and TR27 can be transistors of different types from those shown in FIG. 11.

[0096] When the control signal CN is inactivated, the twelfth transistor TR26 is turned off and the control current ICN may not flow through the thirteenth transistor TR27. On the other hand, when the control signal CN is activated to turn on the twelfth transistor TR26 and the second bias signal BIAS2 is applied to turn on the thirteenth transistor TR27, the control current ICN can flow to the output nodes OUT21 and OUT22 through the twelfth transistor TR26 and the thirteenth transistor TR27.

[0097] After the magnitude relationship between the level of the ramp signal RAMP and the level of the pixel signal PIX is determined, the level of the power supply current ISS2 may become high, and power may continue to be consumed even after the comparison operation is performed. As described above, as the difference in power consumption before and after the comparison operation continues, the performance of the image sensor may be degraded.

[0098] The control circuit 340 can operate to prevent such degradation of the image sensor performance. After the ramp signal RAMP starts to ramp, as the control signal CN and the second bias signal BIAS2 are activated, the control current ICN can flow to the output nodes OUT21 and OUT22 via the twelfth and thirteenth transistors TR26 and TR27 as described above, and the level of the power supply current ISS2 can increase by the level of the control current ICN.

[0099] For example, after the ramp signal RAMP starts to ramp, the level of the power supply current ISS2 (hereinafter referred to as the second level), which has increased by the level of the control current ICN, may be higher than the level of the power supply current ISS2 before the comparison operation is performed (hereinafter referred to as the first level), and lower than the level of the power supply current ISS2 after the comparison operation is performed (i.e., after the determination of the magnitude relationship between the voltage level of the ramp signal RAMP and the voltage level of the pixel signal PIX is completed) (hereinafter referred to as the third level).

[0100] By such an operation of the control circuit 340, the difference between the first level and the second level and the difference between the second level and the third level may both be smaller than the difference between the first level and the third level. This makes it possible to reduce the difference in power consumption before and after the comparison operation of the second amplifier 300 and improve the performance degradation of the image sensor. Therefore, the performance degradation of the image sensor caused by the difference in power consumption before and after performing the comparison operation may be improved by the operation of the feedback circuit 330 or the operation of the control circuit 340 described above.

[0101] In conclusion, the second amplifier 300b in Fig. 11 can further reduce power consumption compared to the second amplifier 300 in Fig. 6 by using not only the operation of the tenth transistor TR24 by optimizing the second auto-zero section, but also one of the operation of the feedback circuit 330 or the operation of the control circuit 340. The configuration and function of the second amplifier 300b shown in Fig. 11 are the same as those of the second amplifier 300 in Fig. 6 and the second amplifier 300a in Fig. 9, except for the operation of the control circuit 340 described above, and therefore a duplicated description will be omitted.

[0102] 12 is a flowchart showing a method of operating a circuit of an analog-to-digital converter ADC using auto-zero section optimization according to an embodiment of the present invention, which will be described below with reference to FIG.

[0103] In step S110, the first amplifier 151_1 can adjust the voltage levels of the input node and the output node to be equal in response to the first auto-zero signal AZ_OTA1. In step S120, the second amplifier 151_2 can charge the capacitor in response to the second auto-zero signal AZ_OTA2. In step S130, after the second auto-zero interval ends, the operation of the second amplifier 151_2 can be temporarily stopped before the comparison operation interval begins.

[0104] In step S140, the first amplifier 151_1 may generate a first output signal OTA1_OUT by comparing a pixel signal PIX output from the pixel array 110 with a ramp signal RAMP during a comparison operation period. Specifically, the first amplifier 151_1 may perform correlated double sampling (CDS) by comparing a reset signal of the pixel signal PIX with the ramp signal RAMP during a first operation period and comparing an image signal of the pixel signal PIX with the ramp signal RAMP during a second operation period.

[0105] In step S150, the second amplifier 151_2 may generate a second output signal OTA2_OUT based on the first output signal OTA1_OUT. For example, the second output signal OTA2_OUT may be an inverted signal of the first output signal OTA1_OUT.

[0106] The above is a specific embodiment for carrying out the present invention. The present invention includes not only the above-described embodiment, but also embodiments that can be simply modified or easily modified. The present invention also includes techniques that can be easily modified and carried out using the embodiment. Therefore, the scope of the present invention should not be limited to the above-described embodiment, but should be determined not only by the claims described below, but also by equivalents to the claims of the present invention. [Explanation of symbols]

[0107] 10 Image Processing Block 12 Lenses 14 Image Sensor 16 ISP Front-end Blocks 18 Image Signal Processor 100 Image Sensor 110 pixel array 120 Low Driver 130 Ramp Signal Generator 140 Voltage Buffer 150 ADC circuit 151 Comparator 151_1 First amplifier 151_2 Second amplifier 152 Counter 160 Timing Controller 170 buffers 200 First Amplifier 210 First current source 300, 300a, 300b Second amplifier 310 Switching Circuits 320 current source 330 Feedback Circuit 331 Logic Gates 340 Control circuit

Claims

1. The first amplifier comprises: adjusting the voltage levels of the input node and the output node to be equal in response to the first auto-zero signal during the first auto-zero interval; a ramp signal is received at a first input node of the input node, and pixel signals output from a pixel array are received at a second input node of the input node via column lines of the pixel array, the column lines being connected to second input nodes of the first amplifier; a reset signal of a pixel signal output from a pixel array during a first operating period is compared with a ramp signal, and an image signal of the pixel signal is compared with the ramp signal during a second operating period to generate a first output signal; a second amplifier including an input node connected to the output node of the first amplifier; charging the capacitor in response to a second autozero signal different from the first autozero signal during a second autozero interval; the second amplifier is stopped from operating after the second auto-zero interval ends and before the first operation interval begins; receiving the first output signal from the first amplifier at an input node of the second amplifier; generating a second output signal based on the first output signal from the first amplifier during the first operating interval and the second operating interval; the second auto-zero interval overlaps with the first auto-zero interval, and when operation of the second amplifier is stopped, the second amplifier is configured to stop supplying a power supply voltage from the time the second auto-zero interval ends to the time the first operating interval begins.

2. 2. The circuit of claim 1, wherein the length of the second auto-zero interval is determined based on the time it takes for the capacitor to fully charge, and is shorter than the length of the first auto-zero interval.

3. The second amplifier comprises: a first transistor for supplying a power supply voltage to a first output node from which a second output signal is output in response to the first output signal; a second transistor that is turned on in response to the second auto-zero signal and that is coupled to the capacitor through a bias node; a current source coupled to the first transistor via the first output node and to the capacitor and the second transistor via the bias node, the current source generating a power supply current based on a voltage level of the bias node held by the capacitor; a third transistor connected to the first transistor, supplying a power supply voltage to the first transistor, and turned off in response to a power down signal to disable operation of the second amplifier.

4. The circuit described in claim 3, characterized in that the third transistor is configured to turn off in response to the power down signal being activated when the second auto-zero interval ends, and to turn on in response to the power down signal being deactivated when the first operating interval begins.

5. 4. The circuit of claim 3, wherein the first transistor and the third transistor are PMOS transistors and the second transistor is an NMOS transistor.

6. The second amplifier comprises: a feedback circuit connected to the first output node, receiving the second output signal and outputting a feedback signal for controlling the power supply current; 4. The circuit of claim 3, further comprising: a fourth transistor coupled to the current source through a second output node, the fourth transistor responsive to the feedback signal to couple the first output node to the second output node.

7. the feedback circuit includes a logic gate that outputs the feedback signal based on the second output signal and a feedback activation signal; 7. The circuit of claim 6, wherein the fourth transistor is turned off in response to the feedback signal.

8. 8. The circuit of claim 7, wherein the fourth transistor is an NMOS transistor and the logic gate is a NAND gate.

9. the second amplifier further includes a control circuit that outputs a control current in response to a control signal; The control circuit a fifth transistor that generates the control current based on the power supply voltage in response to the control signal; a sixth transistor responsive to a bias signal to provide said control current to said first output node.

10. 10. The circuit of claim 9, wherein the control circuit outputs the control current to the current source via the first output node and the second output node when the ramp signal begins to ramp during the first operating interval or the second operating interval.

11. A circuit operation method for an analog-to-digital converter, comprising: adjusting the voltage levels of the input node and the output node of the first amplifier to be equal in response to a first auto-zero signal during a first auto-zero interval; charging a capacitor of a second amplifier in response to a second autozero signal during a second autozero interval overlapping the first autozero interval; stopping the operation of the second amplifier after the second auto-zero interval ends and before the first operation interval begins; receiving pixel signals output from a pixel array at an input node of the first amplifier via a column line of the pixel array, the column line being connected to the input node of the first amplifier; comparing a reset signal of a pixel signal output from a pixel array with a ramp signal during the first operating period, and comparing an image signal of the pixel signal with the ramp signal during a second operating period after the first operating period to generate a first output signal; receiving the first output signal from the first amplifier at an input node of the second amplifier, the input node of the second amplifier being connected to an output node of the first amplifier; generating a second output signal based on the first output signal from the first amplifier during the first and second operating intervals; wherein stopping the operation of the second amplifier includes cutting off the supply of a power supply voltage to the second amplifier from the time when the second auto-zero interval ends to the time when the first operation interval begins.

12. the length of the second auto-zero section is determined based on the time it takes for the capacitor of the second amplifier to be fully charged, and is shorter than the length of the first auto-zero section; The step of stopping the operation of the second amplifier comprises:

12. The method of claim 11, further comprising: stopping operation of the second amplifier in response to a power-down signal being activated when the second auto-zero interval ends and being deactivated when the first operating interval begins.

13. and controlling a power supply current of the analog-to-digital converter using the second output signal; 12. The method of claim 11, wherein controlling the power supply current is performed during at least one of the first operating interval and the second operating interval.

14. The step of controlling the power supply current comprises: outputting a feedback signal based on the second output signal and a feedback activation signal; and controlling the power supply current to not flow in response to the feedback signal.

15. A circuit that charges a capacitor in response to an auto-zero signal during an auto-zero period and generates an output signal during an operation period, The circuit comprises: a first transistor that supplies a power supply voltage to a first output node from which the output signal is output; a second transistor that is turned on in response to the auto-zero signal and that is coupled to the capacitor through a bias node; a current source coupled to the first transistor via the first output node and to the capacitor and the second transistor via the bias node, the current source generating a power supply current based on a voltage level of the bias node held by the capacitor; a third transistor connected to the first transistor, supplying a power supply voltage to the first transistor, and turning off in response to a power-down signal to stop operation of the circuit; When the operation of the circuit is stopped, the circuit is configured such that the third transistor cuts off the supply of power supply voltage to the first transistor in response to the power down signal.

16. the third transistor is turned off in response to the power-down signal being activated when the auto-zero interval ends; When the operation period starts, the power-down signal is deactivated, and the power-down signal is turned on. The length of the auto-zero interval is determined based on the time it takes for the capacitor to be fully charged; 16. The circuit of claim 15, wherein operation of the circuit is suspended after the auto-zero interval ends and before the operating interval begins.

17. 16. The circuit of claim 15, wherein the first transistor and the third transistor are PMOS transistors and the second transistor is an NMOS transistor.

18. a feedback circuit connected to the first output node, receiving the output signal or a signal based on the output signal, and outputting a feedback signal for controlling the power supply current; 16. The circuit of claim 15, further comprising: a fourth transistor coupled to the current source through a second output node, the fourth transistor responsive to the feedback signal to couple the first output node to the second output node.

19. the feedback circuit includes a logic gate that outputs the feedback signal based on the output signal and a feedback activation signal; 20. The circuit of claim 18, wherein the fourth transistor is turned off in response to the feedback signal.

20. 20. The circuit of claim 19, wherein the fourth transistor is an NMOS transistor and the logic gate is a NAND gate.

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