A signal sampling method, system and device of a digital-to-analog converter and a storage medium

Abstract

The application discloses a signal sampling method, system and device of a digital-to-analog converter and a storage medium, and the method comprises the following steps: obtaining a first sampling result and a second sampling result of the low-power consumption prediction ADC; the first sampling result is used for representing a quantization result of an input ADC signal in a previous sampling period after analog-to-digital conversion; the second sampling result is used for representing a quantization result of an input ADC signal in a current sampling period after analog-to-digital conversion; determining that the first sampling result is not equal to the second sampling result, and switching the connection between a group of differential capacitor digital-to-analog converters of the main ADC and a reference voltage. The method can reduce the power consumption of signal sampling of the digital-to-analog converter. The application can be widely applied in the technical field of signal sampling.

Description

Technical Field

[0001] This application relates to the field of signal sampling technology, and in particular to a signal sampling method, system, device and storage medium for a digital-to-analog converter. Background Technology

[0002] Analog-to-digital converters (ADCs) in wireless sensors or portable devices generally require low power consumption. ADCs convert analog signals to digital signals through two processes: sampling and quantization. In existing technologies, the quality factor is used to measure quantization efficiency, and its power consumption consists of two parts: the front-end input signal driver and the quantizer. The input signal driver dominates the quantization quality factor, therefore its power consumption has significant room for optimization. Therefore, a new signal sampling method for digital-to-analog converters is urgently needed. Summary of the Invention

[0003] The purpose of this application is to at least partially solve one of the technical problems existing in the prior art.

[0004] Therefore, one objective of the embodiments of this application is to provide a signal sampling method, system, apparatus and storage medium for a digital-to-analog converter, which can reduce power consumption during sampling.

[0005] To achieve the above technical objectives, the technical solution adopted in this application includes: acquiring a first sampling result and a second sampling result of the low-power predictive ADC; the first sampling result is used to characterize the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the previous sampling period; the second sampling result is used to characterize the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the current sampling period.

[0006] In addition, the signal sampling method for a digital-to-analog converter according to the above embodiments of the present invention may also have the following additional technical features:

[0007] Furthermore, in this embodiment of the application, it is determined that the first sampling result is equal to the second sampling result, and the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage is maintained.

[0008] Further, in this embodiment of the application, the main ADC includes a negative capacitor digital-to-analog converter and a positive capacitor digital-to-analog converter. The step of determining that the first sampling result is not equal to the second sampling result and switching the connection of the plates of a set of differential capacitor digital-to-analog converters of the main ADC to the reference voltage specifically includes: determining that the first sampling result is not equal to the second sampling result, switching the connection of the capacitor plates of the negative capacitor digital-to-analog converter from the negative reference voltage to the positive reference voltage, and switching the connection of the capacitor plates of the positive capacitor digital-to-analog converter from the positive reference voltage to the negative reference voltage.

[0009] Further, in this embodiment of the application, the step of determining that the first sampling result is not equal to the second sampling result, switching the connection of the capacitor plate of the negative capacitor digital-to-analog converter to the negative reference voltage to the positive reference voltage, and switching the connection of the capacitor plate of the positive capacitor digital-to-analog converter to the negative reference voltage, specifically includes: determining that the first sampling result is not equal to the second sampling result, switching the connection of the plates of the two parallel capacitors in the negative capacitor digital-to-analog converter to the negative reference voltage to the positive reference voltage, and switching the connection of the plates of the two parallel capacitors in the positive capacitor digital-to-analog converter to the negative reference voltage.

[0010] Further, in this embodiment of the application, the step of determining that the first sampling result is not equal to the second sampling result, switching the connection of the plates of the two parallel capacitors in the negative capacitor digital-to-analog converter to the negative reference voltage, and switching the connection of the plates of the two parallel capacitors in the positive capacitor digital-to-analog converter to the positive reference voltage, specifically includes: determining that the first sampling result is not equal to the second sampling result, switching the connection of the lower plates of the two parallel capacitors in the negative capacitor digital-to-analog converter to the negative reference voltage, and switching the connection of the lower plates of the two parallel capacitors in the positive capacitor digital-to-analog converter to the positive reference voltage; the upper plates of the two parallel capacitors in the negative capacitor digital-to-analog converter remain unchanged, and the upper plates of the two parallel capacitors in the positive capacitor digital-to-analog converter remain unchanged.

[0011] Furthermore, in this embodiment of the application, the main ADC includes a negative capacitor digital-to-analog converter and a positive capacitor digital-to-analog converter. The step of determining that the first sampling result is equal to the second sampling result and maintaining the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage specifically includes: determining that the first sampling result is equal to the second sampling result, maintaining the connection between the capacitor plates of the negative capacitor digital-to-analog converter and the reference voltage after the end of the previous sampling cycle, and maintaining the connection between the capacitor plates of the positive capacitor digital-to-analog converter and the reference voltage.

[0012] On the other hand, embodiments of this application also provide a signal sampling system for a digital-to-analog converter, comprising:

[0013] The acquisition unit is used to acquire the first sampling result and the second sampling result of the low-power predictive ADC;

[0014] The processing unit is used to determine that the first sampling result is not equal to the second sampling result, and to switch the connection between the plates of a set of differential capacitive digital-to-analog converters of the main ADC and the reference voltage.

[0015] Furthermore, in this embodiment of the application, it further includes: a fixing unit, used to determine that the first sampling result is equal to the second sampling result, and to maintain the connection between the plates of a set of differential capacitive digital-to-analog converters of the main ADC and the reference voltage.

[0016] On the other hand, this application also provides a signal sampling device for a digital-to-analog converter, comprising:

[0017] At least one processor;

[0018] At least one memory for storing at least one program;

[0019] When the at least one program is executed by the at least one processor, the at least one processor implements a signal sampling method for a digital-to-analog converter as described in any one of the claims of the invention.

[0020] In addition, this application also provides a storage medium storing processor-executable instructions, which, when executed by a processor, are used to perform a signal sampling method for a digital-to-analog converter as described in any of the preceding claims.

[0021] The advantages and beneficial effects of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application:

[0022] This application can determine whether to switch the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage based on the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the previous sampling cycle of the low-power predictive ADC and the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the current sampling cycle; this scheme can reduce the power consumption of the digital-to-analog converter sampling. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating the steps of a signal sampling method for a digital-to-analog converter in a specific embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the structure of a digital-to-analog converter in a specific embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of plate switching during the signal sampling process of a digital-to-analog converter in a specific embodiment of the present invention;

[0026] Figure 4This is a schematic diagram illustrating the power consumption calculation process of a digital-to-analog converter during signal sampling, according to a specific embodiment of the prior art.

[0027] Figure 5 This is a schematic diagram illustrating the calculation process for reducing power consumption during the signal sampling process of a digital-to-analog converter in a specific embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of the signal sampling system of a digital-to-analog converter in a specific embodiment of the present invention;

[0029] Figure 7 This is a schematic diagram of the structure of a signal sampling device for a digital-to-analog converter in a specific embodiment of the present invention. Detailed Implementation

[0030] The following detailed description, in conjunction with the accompanying drawings, illustrates the principles and processes of the signal sampling method, system, device, and storage medium of the digital-to-analog converter in the embodiments of the present invention.

[0031] Reference Figure 1 This invention provides a signal sampling method for a digital-to-analog converter. The method may include the following steps:

[0032] S1. Obtain the first sampling result and the second sampling result of the low-power predictive ADC;

[0033] In this step, the first sampling result can be used to characterize the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the previous sampling period; the second sampling result can be used to characterize the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the current sampling period; in practical applications, the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the previous sampling period can be 11, 10, 01 or 00, and similarly, the quantization result obtained by analog-to-digital conversion of the signal input to the ADC in the current sampling period.

[0034] S2. Determine that the first sampling result is not equal to the second sampling result, and switch the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage.

[0035] In this step, it can be determined whether the first sampling result and the second sampling result are equal. If the first sampling result is not equal to the second sampling result, the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage can be switched.

[0036] Furthermore, the signal sampling method also includes: S3, determining that the first sampling result is equal to the second sampling result, and maintaining the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage;

[0037] In this step, if it is determined that the first sampling result is equal to the second sampling result, the connection method between the plates of the differential capacitor digital-to-analog converter of the main ADC in the previous sampling cycle and the reference voltage can be maintained, that is, the first sampling result D... PE1 00 and the second sampling result D PE2 If they are equal to 00, then the original connection method is maintained.

[0038] Furthermore, the main ADC includes a negative capacitor digital-to-analog converter and a positive capacitor digital-to-analog converter. The step of determining that the first sampling result is not equal to the second sampling result and switching the connection of the plates of a set of differential capacitor digital-to-analog converters of the main ADC to the reference voltage specifically includes: determining that the first sampling result is not equal to the second sampling result, switching the connection of the capacitor plates of the negative capacitor digital-to-analog converter from the negative reference voltage to the positive reference voltage, and switching the connection of the capacitor plates of the positive capacitor digital-to-analog converter from the positive reference voltage to the negative reference voltage;

[0039] In this step, the main ADC may include a negative capacitor digital-to-analog converter and a positive capacitor digital-to-analog converter. When it is determined that the first sampling result is not equal to the second sampling result, the connection of the capacitor plate of the negative capacitor digital-to-analog converter to the negative reference voltage can be switched to the connection of the capacitor plate to the positive reference voltage. At the same time, the connection of the capacitor plate of the positive capacitor digital-to-analog converter to the positive reference voltage can be switched to the connection of the capacitor plate to the negative reference voltage.

[0040] Further, the step of determining that the first sampling result is not equal to the second sampling result, switching the connection of the capacitor plate of the negative capacitor digital-to-analog converter from the negative reference voltage to the positive reference voltage, and switching the connection of the capacitor plate of the positive capacitor digital-to-analog converter from the positive reference voltage to the negative reference voltage, may specifically include:

[0041] If the first sampling result is determined to be different from the second sampling result, the connection between the plates of the two parallel capacitors in the negative capacitor digital-to-analog converter and the negative reference voltage is switched to the connection between the plates of the two parallel capacitors and the positive reference voltage. If the connection between the plates of the two parallel capacitors in the positive capacitor digital-to-analog converter and the positive reference voltage is switched to the connection between the plates of the two parallel capacitors and the negative reference voltage, the connection between the plates of the two parallel capacitors and the positive reference voltage is switched.

[0042] Further, determining that the first sampling result is not equal to the second sampling result, the step of switching the connection of the plates of the two parallel capacitors in the negative capacitor digital-to-analog converter to the negative reference voltage and the connection of the plates of the two parallel capacitors to the positive reference voltage, and switching the connection of the plates of the two parallel capacitors in the positive capacitor digital-to-analog converter to the negative reference voltage, can specifically include:

[0043] If the first sampling result is determined to be different from the second sampling result, the connection between the lower plates of the two parallel capacitors in the negative capacitor-to-analog converter and the negative reference voltage is switched to the connection between the lower plates of the two parallel capacitors and the positive reference voltage. Conversely, the connection between the lower plates of the two parallel capacitors in the positive capacitor-to-analog converter and the positive reference voltage is switched to the connection between the lower plates of the two parallel capacitors and the negative reference voltage. The upper plates of the two parallel capacitors in the negative capacitor-to-analog converter remain unchanged, as do the upper plates of the two parallel capacitors in the positive capacitor-to-analog converter.

[0044] Furthermore, the main ADC includes a negative capacitor digital-to-analog converter and a positive capacitor digital-to-analog converter. The step of determining that the first sampling result is equal to the second sampling result and maintaining the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage may specifically include:

[0045] The first sampling result is determined to be equal to the second sampling result. The connection between the capacitor plate of the negative capacitor digital-to-analog converter and the reference voltage is maintained after the end of the previous sampling cycle, and the connection between the capacitor plate of the positive capacitor digital-to-analog converter and the reference voltage is maintained.

[0046] The sampling method of this application will be described below with reference to the accompanying drawings and specific embodiments:

[0047] The input signal from the previous sampling period is converted into the highest two quantized bits (D) by analog-to-digital conversion. PE The value is 11. The input signal in the current sampling period undergoes analog-to-digital conversion to obtain the highest two quantized bits, D. PE For example, let's take 00 as an example.

[0048] like Figure 2 When this sampling technique is applied to an ADC, the overall circuit consists of a low-power predictive ADC and a main ADC. First, the low-power predictive ADC samples and quantizes the input signal, providing a two-bit plate reversal control signal; this process is called the pre-estimation stage. During the plate polarity reversal stage, the main ADC changes the connection of the two most significant plates according to the plate reversal control signal. Finally, the main ADC samples and quantizes the signal.

[0049] Combination Figure 2 as well as Figure 3The input signal from the previous sampling period undergoes analog-to-digital conversion to obtain the highest two quantized bits, D. PE The value is 11. Based on this quantization result, after the previous digital-to-analog conversion operation, the main ADC has a set of differential capacitive digital-to-analog converters (CDACs), namely a negative capacitor digital-to-analog converter and a positive capacitor digital-to-analog converter. The lower plate of the positive capacitor digital-to-analog converter is connected to two parallel capacitors 1C and 2C, and the upper plate is connected to V. CM The lower electrode is connected to the positive reference voltage +V. REF The upper plates of the two parallel capacitors 1C and 2C in the negative capacitance digital-to-analog converter are connected to V. CM The lower electrode is connected to the negative reference voltage -V REF V REF Indicates the reference voltage.

[0050] During the polarity reversal phase, the current input signal is in region 4, i.e., the polarity reversal control signal D. PE The value is 00. Therefore, before the next sampling begins, the lower plate of the positive capacitance digital-to-analog converter should be connected to -V. REF The upper plate remains unchanged, while the lower plate of the negative capacitor digital-to-analog converter should be connected to +V. REF The upper plate remains unchanged. This can be achieved by swapping the upper plates of the P-side and N-side capacitors.

[0051] During the sampling phase, refer to Figures 4-5 The main ADC completes sampling of the current signal. ΔV is determined by ΔV1(V in (m)-V in (m-1) becomes ΔV2(ε) q,p ), where (ε q,p The quantization error is generated by the low-power predictive ADC and is limited to 1 / 4 of the input swing, so it will be reduced by at least 75% at most.

[0052] like Figure 4 As shown, for a traditional design, the base plate is connected to the corresponding reference voltage at the end of the previous sampling period (m-1). At the start of the next input sampling (m), the output voltage (V) on the base plate... B (This corresponds to the previous numeric input D) m-1 It can be represented as V(D) m-1 ) = V in (m-1)+ε q , where ε q This is a quantization error. Therefore, the voltage change ΔV1(m) of the load capacitor can be calculated as V. in (m)-V in (m-1)+ε q Due to ε qIt is very small and can be simplified to V. in (m)-V in (m-1).

[0053] like Figure 5 For the sampling method of this invention, based on the pre-estimated digital output of the ADC, after swapping the capacitor plates, the lower plate of the capacitor is connected to the reference voltage -V. REF The initial voltage is V B For V in (m)+ε q,p Instead of the V in traditional design in (m-1)+ε q , where ε q,p This is due to the quantization error from the pre-estimated ADC. Therefore, the load capacitor voltage change ΔV2(m) = V in this method. in (m)+ε q,p -V in (m)=ε q,p .

[0054] Furthermore, if the sampled signal is located in the same region in two consecutive sampling cycles, that is, if the input signal in the previous sampling cycle is converted into the highest two quantized bits D by analog-to-digital conversion in two consecutive sampling cycles, then... PE The value is 11. The input signal in the current sampling period undergoes analog-to-digital conversion to obtain the highest two quantized bits, D. PE If it is also 11, then the polarity exchange stage of the plates is skipped, thus ensuring the optimal value.

[0055] In addition, refer to Figure 6 ,and Figure 1 Corresponding to the method, the embodiments of this application also provide a signal sampling system for a digital-to-analog converter, which may include: an acquisition unit 101, used to acquire a first sampling result and a second sampling result of a low-power predictive ADC; and a processing unit 102, used to determine that the first sampling result is not equal to the second sampling result, and switch the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage.

[0056] Furthermore, a signal sampling system for a digital-to-analog converter may also include a fixing unit 103, used to determine that the first sampling result is equal to the second sampling result, and to maintain the connection between the plates of a set of differential capacitor digital-to-analog converters of the main ADC and the reference voltage.

[0057] and Figure 1 Corresponding to the method described herein, embodiments of this application also provide a signal sampling device for a digital-to-analog converter, the specific structure of which can be referred to... Figure 7 ,include:

[0058] At least one processor 1001;

[0059] At least one memory 1002 is used to store at least one program;

[0060] When the at least one program is executed by the at least one processor, the at least one processor implements the signal sampling method of the digital-to-analog converter.

[0061] The content of the above method embodiments is applicable to the device embodiments. The specific functions implemented by the device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0062] and Figure 1 Corresponding to the method described above, this application also provides a storage medium storing processor-executable instructions, which, when executed by a processor, are used to perform the signal sampling method of the digital-to-analog converter.

[0063] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0064] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional technology for an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0065] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several programs to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0066] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequential list of executable programs for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, a program execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can retrieve and execute a program from or in conjunction with such a program execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit a program for use by or in conjunction with a program execution system, apparatus, or device.

[0067] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0068] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable program execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0069] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0070] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0071] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A method of signal sampling for a digital-to-analog converter, the method comprising: The digital-to-analog converter comprises a main ADC and a low-power prediction ADC, and the signal sampling method comprises the following steps: obtaining a first sampling result and a second sampling result of the low-power prediction ADC; the first sampling result is used to represent a quantization result of an input ADC signal in a previous sampling period after analog-to-digital conversion; and the second sampling result is used to represent a quantization result of an input ADC signal in a current sampling period after analog-to-digital conversion; determining that the first sampling result is not equal to the second sampling result, and switching a connection between a plate of a group of differential capacitor digital-to-analog converters of the main ADC and a reference voltage.

2. The method of claim 1, wherein The signal sampling method further comprises: determining that the first sampling result is equal to the second sampling result, and maintaining the connection between the plate of the group of differential capacitor digital-to-analog converters of the main ADC and the reference voltage.

3. The method of claim 1, wherein the step of sampling the analog signal comprises the step of: The main ADC comprises a negative capacitor digital-to-analog converter and a positive capacitor digital-to-analog converter, and the step of determining that the first sampling result is not equal to the second sampling result and switching the connection between the plate of the group of differential capacitor digital-to-analog converters of the main ADC and the reference voltage specifically comprises: ​ determining that the first sampling result is not equal to the second sampling result, switching a connection between a plate of the negative capacitor digital-to-analog converter and a negative reference voltage to a connection between the plate and a positive reference voltage, and switching a connection between a plate of the positive capacitor digital-to-analog converter and the positive reference voltage to a connection between the plate and the negative reference voltage.

4. The method of claim 3, wherein the step of sampling the analog signal comprises the step of: The step of determining that the first sampling result is not equal to the second sampling result, switching the connection between the plate of the negative capacitor digital-to-analog converter and the negative reference voltage to the connection between the plate and the positive reference voltage, and switching the connection between the plate of the positive capacitor digital-to-analog converter and the positive reference voltage to the connection between the plate and the negative reference voltage specifically comprises: determining that the first sampling result is not equal to the second sampling result, switching a connection between plates of two parallel capacitors in the negative capacitor digital-to-analog converter and the negative reference voltage to a connection between the plates and the positive reference voltage, and switching a connection between plates of two parallel capacitors in the positive capacitor digital-to-analog converter and the positive reference voltage to a connection between the plates and the negative reference voltage.

5. The method of claim 4, wherein the step of sampling the signal comprises the step of: The step of determining that the first sampling result is not equal to the second sampling result, switching the connection between the plates of the two parallel capacitors in the negative capacitor digital-to-analog converter and the negative reference voltage to the connection between the plates and the positive reference voltage, and switching the connection between the plates of the two parallel capacitors in the positive capacitor digital-to-analog converter and the positive reference voltage to the connection between the plates and the negative reference voltage specifically comprises: determining that the first sampling result is not equal to the second sampling result, switching the lower plate of the two parallel capacitors in the negative capacitive digital-to-analog converter from being connected to a negative reference voltage to being connected to a positive reference voltage, switching the lower plate of the two parallel capacitors in the positive capacitive digital-to-analog converter from being connected to a positive reference voltage to being connected to a negative reference voltage, keeping the upper plate of the two parallel capacitors in the negative capacitive digital-to-analog converter unchanged, and keeping the upper plate of the two parallel capacitors in the positive capacitive digital-to-analog converter unchanged.

6. The method of claim 2, wherein the step of sampling the analog signal comprises the step of: sampling the analog signal at a sampling rate of 2.4 GHz. The main ADC includes a negative capacitive digital-to-analog converter and a positive capacitive digital-to-analog converter, and the step of determining that the first sampling result is equal to the second sampling result and keeping the connection of the plates of a group of differential capacitive digital-to-analog converters of the main ADC to a reference voltage specifically includes: determining that the first sampling result is equal to the second sampling result, keeping the connection of the plates of the capacitors of the negative capacitive digital-to-analog converter to a reference voltage after the end of the previous sampling period, and keeping the connection of the plates of the capacitors of the positive capacitive digital-to-analog converter to a reference voltage.

7. A signal sampling system for a digital-to-analog converter, comprising: The system is applied to the method of any one of claims 1-6, and includes: an acquisition unit configured to acquire a first sampling result and a second sampling result of the low-power consumption prediction ADC; a processing unit configured to determine that the first sampling result is not equal to the second sampling result, and switch the connection of the plates of a group of differential capacitive digital-to-analog converters of the main ADC to a reference voltage.

8. A signal sampling system for a digital to analog converter as recited in claim 7, wherein, Further comprising: a fixing unit configured to determine that the first sampling result is equal to the second sampling result, and keep the connection of the plates of a group of differential capacitive digital-to-analog converters of the main ADC to a reference voltage.

9. A signal sampling device for a digital-to-analog converter, characterized in that... comprising: at least one processor; at least one memory configured to store at least one program; when the at least one program is executed by the at least one processor, the at least one processor is caused to implement the signal sampling method of the digital-to-analog converter according to any one of claims 1-6.

10. A storage medium having stored therein instructions executable by a processor, the instructions causing the processor to perform the method of claim 1. The processor-executable instructions, when executed by the processor, perform the signal sampling method of the digital-to-analog converter according to any one of claims 1-6.

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