Semiconductor device, photoelectric conversion system, and mobile entity

Abstract

To suppress a decrease in wiring reliability or breakdown of a pn junction and optimize a circuit area at the same time.SOLUTION: Provided is a semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate which is stacked on the first semiconductor substrate; a first pad to which a first power supply voltage for driving elements formed on the first semiconductor substrate is inputted; a second pad to which a second power supply voltage for driving elements formed on the second semiconductor substrate is inputted; a first protective circuit which is disposed on the first semiconductor substrate; and a second protective circuit which is disposed on the second semiconductor substrate. The first power supply voltage is higher than the second power supply voltage. The first protective circuit is connected to the first pad, and the second protective circuit is connected to the second pad.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a photoelectric conversion system, and a mobile object. [Background technology]

[0002] In semiconductor devices in which multiple substrates are stacked, a configuration has been proposed that makes them less susceptible to failure by forming a protection circuit on the substrate and dissipating external noise such as static electricity applied from the outside through an appropriate path.

[0003] A semiconductor device may be constructed by stacking a substrate on which elements driven by a high voltage (hereinafter also referred to as a high-voltage substrate) are arranged and a substrate on which elements driven by a low voltage (hereinafter also referred to as a low-voltage substrate) are arranged. Patent Document 1 proposes a device configuration in which an electrostatic protection circuit is formed on only one of the stacked substrates. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-182941 Summary of the Invention [Problem to be solved by the invention]

[0005] In a semiconductor device in which a high-voltage substrate and a low-voltage substrate are stacked, if a protection circuit is formed only on the low-voltage substrate according to the configuration of Patent Document 1, the electrostatic protection circuit for the high-voltage substrate is also formed on the low-voltage substrate. As a result, a high voltage that drives elements driven by a high voltage is applied to the low-voltage substrate and the wiring provided on the low-voltage substrate, raising concerns about reduced wiring reliability and the occurrence of pn junction breakdown. On the other hand, if a protection circuit is formed only on the high-voltage substrate, there is a possibility that the circuit area will increase. [Means for solving the problem]

[0006] One aspect of the present invention is a semiconductor device comprising: a first semiconductor substrate; a second semiconductor substrate stacked on the first semiconductor substrate; a first pad to which a first power supply voltage for driving elements formed on the first semiconductor substrate is input from outside; a second pad to which a second power supply voltage for driving elements formed on the second semiconductor substrate is input from outside; a first protection circuit disposed on the first semiconductor substrate; and a second protection circuit disposed on the second semiconductor substrate, wherein the first power supply voltage is higher than the second power supply voltage, the first protection circuit is electrically connected to the first pad, and the second protection circuit is electrically connected to the second pad. [Effects of the Invention]

[0007] According to the present invention, in a semiconductor device in which substrates having elements with different drive voltages are stacked, it is possible to provide a protection circuit suitable for the elements arranged on each substrate. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 5] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 6] FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 7] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 8] FIG. 10 is a circuit diagram of a pixel of a semiconductor device according to a third embodiment. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 10]FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 11] FIG. 10 is a circuit diagram of a pixel of a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 14] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 17] FIG. 10 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 18] FIG. 10 is a plan view of a semiconductor device according to a sixth embodiment. [Figure 19] FIG. 10 is a cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 20] FIG. 13 is a plan view of a semiconductor device according to a seventh embodiment. [Figure 21] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh embodiment. [Figure 22] FIG. 13 is a plan view of a semiconductor device according to an eighth embodiment. [Figure 23] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth embodiment. [Figure 24] FIG. 13 is a functional block diagram of a photoelectric conversion system according to a ninth embodiment. [Figure 25] FIG. 20 is a functional block diagram of a photoelectric conversion system according to a tenth embodiment. [Figure 26] FIG. 22 is a functional block diagram of a photoelectric conversion system according to an eleventh embodiment. [Figure 27] FIG. 22 is a functional block diagram of a photoelectric conversion system according to a twelfth embodiment. [Figure 28] FIG. 22 is a functional block diagram of a photoelectric conversion system according to a thirteenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0012] In this specification, when the term "impurity concentration" is used simply, it means the net impurity concentration minus the amount compensated for by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET doping concentration. A region where the P-type doped impurity concentration is higher than the N-type doped impurity concentration is a P-type semiconductor region. Conversely, a region where the N-type doped impurity concentration is higher than the P-type doped impurity concentration is an N-type semiconductor region.

[0013] Furthermore, in this specification, when it is stated that "component A and component B are electrically connected," it is not limited to the case where component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is sufficient that they are electrically connected.

[0014] (First embodiment) The structure of a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

[0015] 1 is a schematic diagram of a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment has a first pad 101A, a second pad 101B, a first protection circuit 102A, a second protection circuit 102B, a first reference potential line 103A, a second reference potential line 103B, a first internal circuit 104A, and a second internal circuit 104B.

[0016] The first pad 101A and the second pad 101B are pads for outputting signals generated within the semiconductor device to the outside, and for inputting voltages supplied from the outside to drive the circuits of the semiconductor device, etc. For example, a first power supply voltage is input to the first pad, and a second power supply voltage is input to the second pad.

[0017] The first protection circuit 102A is a circuit for protecting the internal circuit from external noise such as static electricity and surge voltage input from the first pad 101A, and the second protection circuit 102B is a circuit for protecting the internal circuit from external noise input from the second pad 101B. Each protection circuit is configured, for example, by a diode, a GAte Grounded MOS, an RC Trigger MOS, or a combination of these elements.

[0018] The first reference potential line 103A and the second reference potential line 103B are wirings to which a reference potential is applied, such as a power supply wiring or a ground wiring. Here, the first reference potential line 103A and the second reference potential line 103B may be separate wirings or may be the same wiring. The configuration of the reference potential lines will be described in detail later.

[0019] The first internal circuit 104A and the second internal circuit 104B are circuits provided within the semiconductor device, and are configured to include, for example, a driver circuit for amplifying an external signal.

[0020] The first protection circuit 102A is connected between the first pad 101A and the first reference potential line 103A, and the first internal circuit 104A is connected to the first pad 101A. Similarly, the second protection circuit 102B is connected between the second pad 101B and the second reference potential line 103B, and the second internal circuit 104B is connected to the second pad 101B.

[0021] When external noise such as static electricity is applied to the first pad 101A, a current flows to the first reference potential line 103A via the protection circuit, clamping the voltage applied to the first internal circuit 104A within a predetermined range. This makes it possible to prevent element destruction or failure due to application of a large voltage to the first internal circuit 104A. Similarly, when external noise such as static electricity is applied to the second pad 101B, a current flows to the second reference potential line 103B via the protection circuit, making it possible to prevent failure of the second internal circuit 104B.

[0022] The first protection circuit 102A and the second protection circuit 102B may be connected to circuit elements such as resistors and capacitors in addition to the circuit elements shown in Fig. 1. For example, by connecting a resistor between the first pad 101A and the first protection circuit 102A or between the first protection circuit 102A and the first internal circuit 104A, the voltage input from the first pad 104A can be dropped, and the absolute value of the voltage applied to the subsequent circuit can be reduced.

[0023] 2 and 3 are schematic diagrams showing the planar layout of the protection circuit according to the first embodiment.

[0024] The semiconductor device according to this embodiment includes a first member 105A shown in Fig. 2(A) and a second member 105B shown in Fig. 2(B). In this embodiment, the first pad 101A, the second pad 101B, the first protection circuit 102A, and the first internal circuit 104A are formed on the first member 105A, and the second protection circuit 102B and the second internal circuit 104B are formed on the second member 105B. The first member 105A and the second member 105B are stacked.

[0025] 2A, the first protection circuit 102A on the first member 105A is disposed between the first pad 101A and the first internal circuit 104A in a plan view. In FIG. 2B, the second protection circuit 102B on the second member 105B is disposed between the second pad 101B on the first member 105A and the second internal circuit 104B on the second member 105B in a plan view.

[0026] The circuit arrangement is not limited to this, and for example, the first protection circuit 102A and the second protection circuit 102B may be arranged so that they are each disposed between the first pad 101A and the second pad 101B in a plan view, as shown in Fig. 3. Furthermore, the first protection circuit 102A disposed on the first member 105A and the second protection circuit 102B disposed on the second member 105B may be arranged so that they overlap in a plan view.

[0027] FIG. 4 is a cross-sectional view of the semiconductor device taken along dashed line AA′ shown in FIG.

[0028] The semiconductor device according to this embodiment is constructed by bonding together a first member 105A having a first semiconductor substrate 100A and a first wiring structure 130A, and a second semiconductor substrate 100B and a first member 105B having a second wiring structure 130B. The first wiring structure 130A has wires 107, 108, 109, and 114 and vias 110, 111, 112, 113, and 115. The first wiring structure 130B has wires 117, 118, and 119 and vias 116, 120, 121, 122, and 123.

[0029] The first semiconductor substrate 100A and the second semiconductor substrate 100B are, for example, silicon substrates, and circuit elements such as MOS transistors, resistors, capacitors, and photoelectric conversion elements that constitute internal circuits are formed on each substrate.

[0030] The first member 105A and the second member 105B are electrically connected via a substrate bonding portion 106. The first wiring structure 130A included in the first member 105A and the second wiring structure 130B included in the second member 105B each include multiple wiring layers and via layers. The wiring 108 and the wiring 109 are provided in a wiring layer different from the first wiring layer in which the wiring 107 and the wiring 114 are provided. The wiring 118 and the wiring 119 are provided in a third wiring layer different from the second wiring layer in which the wiring 117 is provided. Similarly, the vias 110 and 112 are provided in the same via layer different from the via layer in which the vias 111 and 113 are provided, and the vias 120 and 122 are provided in the same via layer different from the via layer in which the vias 121 and 123 are provided.

[0031] 4, the first member 105A and the second member 105B each have two wiring layers, but the number of wiring layers and the number of via layers included in the wiring structure of each member are not limited to this and can be set arbitrarily. Furthermore, the wiring included in the wiring layer and the via included in the via layer are made of metal such as copper, aluminum, tungsten, or titanium. Between each wiring layer, an insulating layer is formed, made of, for example, a silicon oxide film, a silicon nitride film, or a silicon carbide film.

[0032] In this embodiment, the first pad 101A and the second pad 101B are provided in the same wiring layer. Therefore, the first pad 101A and the second pad 101B can be formed in the same process. The first pad 101A is configured by exposing the wiring 107 in the first member through a first opening formed by opening the semiconductor substrate from the first semiconductor substrate 105A side. Similarly, the second pad 101B is configured by exposing the wiring 114 provided in the same wiring layer as the wiring 107 through a second opening formed by opening the semiconductor substrate from the first semiconductor substrate 100A side. The pad structure is not limited to this. For example, an opening formed by opening the semiconductor substrate from the first semiconductor substrate 100A side may penetrate the first member 105A, exposing the wiring layer included in the second wiring structure 130B of the second member 105B to the outside. Alternatively, the opening may be formed from the second semiconductor substrate 100B side.

[0033] A first protection circuit 102A is formed on the first semiconductor substrate 100A of the first member 105A, and a second protection circuit 102B is formed on the second semiconductor substrate 100B of the second member 105B. While each of the protection circuits 102A and 102B is depicted as a diode in FIG. 4, the elements constituting the protection circuits are not limited to this. Furthermore, a silicide structure (not shown) may be provided on the first semiconductor substrate 100A and the second semiconductor substrate 100B.

[0034] The first protection circuit 102A is connected to the first pad 101A through wiring 107 and 108 and vias 110 and 111. Of the terminals of the first protection circuit 102A, only the terminal connected to the first pad 101A is shown in Fig. 4, but the other terminal of the first protection circuit 102A is connected to a reference potential wiring 103A (not shown).

[0035] The first internal circuit 104A is connected to the first pad 101A through wirings 107 and 109 and vias 112 and 113. The first internal circuit 104A may be electrically connected to the second member 105B through a substrate joint .

[0036] The second protection circuit 102B is connected to the second pad 101B through wiring 114, 117, and 118, vias 115, 116, 120, and 121, and the substrate joint 106. Of the terminals of the second protection circuit 102B, only the terminal connected to the second pad 101B is shown in Fig. 4, but the other terminal of the second protection circuit 102B is connected to a reference potential wiring 103B (not shown).

[0037] The second internal circuit 104B is connected to the second pad 101B through the wirings 114, 117, and 119, vias 115, 116, 122, and 123, and the substrate joint .

[0038] The substrate bonding portion 106 may be formed by, for example, TSV (Through Silicon Via) bonding or CCB (Cu-Cu-Bonding) bonding. Furthermore, microbump bonding is also acceptable. In the case of CCB bonding, a contact portion between the first insulating layer of the first wiring structure and the second insulating layer of the second wiring structure and a contact portion between the first metal member of the first wiring structure and the second metal member of the second wiring structure are formed on the bonding surface.

[0039] Consider a semiconductor device in which multiple semiconductor substrates are stacked, with each substrate supplied with a different power supply voltage. Generally, the higher the power supply voltage, the greater the current flowing through the circuit, increasing the risk of reduced wiring reliability due to electromigration and pn junction breakdown. To reduce this risk, it is effective to increase the wiring width, the spacing between wirings, and the spacing between impurity regions. Therefore, when stacking multiple substrates with different power supply voltages to drive the elements arranged on each substrate, optimal design rules may be set for each substrate according to the operating voltage of the elements arranged on each substrate. In this specification, a high voltage refers to a voltage that is relatively high in absolute value relative to the ground potential, and a low voltage refers to a voltage that is relatively low in absolute value relative to the ground potential.

[0040] Prior literature has proposed a device configuration in which a protection circuit is formed only on one of the stacked semiconductor substrates. For example, in a semiconductor device in which substrates with different power supply voltages for driving the elements are stacked, a protection circuit is formed on the substrate (low-voltage substrate) on which elements driven at a low voltage are arranged according to the configuration described in the prior literature. In this case, a protection circuit for protecting elements on the substrate (high-voltage substrate) on which elements driven at a high voltage are arranged is also formed only on the low-voltage substrate. This results in high voltage being applied to the low-voltage substrate and the wiring arranged on the low-voltage substrate. This raises concerns about reduced wiring reliability and the occurrence of pn junction breakdown. On the other hand, if a protection circuit is formed only on the high-voltage substrate, the protection circuit for protecting the elements on the low-voltage substrate must be designed in accordance with the design rules for the high-voltage substrate. In this case, the wiring width, the space between the wiring, and the space between the impurity regions increase, resulting in an increase in circuit area.

[0041] Therefore, in the semiconductor device according to the present invention, a protection circuit to which a high voltage is applied is formed on a substrate on which elements driven by a high voltage are disposed, and a protection circuit to which a low voltage is applied is formed on a substrate on which elements driven by a low voltage are disposed. In this case, the protection circuit to which a high voltage is applied is formed according to the process rule of the high-voltage substrate, and the protection circuit disposed on the low-voltage substrate is formed according to the process rule of the low-voltage substrate. Therefore, for example, the gate oxide film of the protection circuit to which a high voltage is applied is thicker than that of the protection circuit to which a low voltage is applied to improve the breakdown voltage. Furthermore, the protection circuit disposed on the high-voltage substrate has thicker contacts to the source and drain and plugs connected to the gate than the protection circuit disposed on the low-voltage substrate. Furthermore, the size of the isolation surrounding the protection circuit is larger in the protection circuit disposed on the high-voltage substrate than in the protection circuit disposed on the low-voltage substrate. This makes it possible to simultaneously suppress deterioration of wiring reliability and pn junction breakdown while optimizing the circuit area.

[0042] The concept of this embodiment is not limited to semiconductor devices having a stacked structure of two semiconductor substrates, but can also be applied to semiconductor devices having a stacked structure of three or more semiconductor substrates, for example.

[0043] (Second embodiment) The structure of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.

[0044] FIG. 5 is a planar layout diagram of a protection circuit according to a second embodiment. In this embodiment, the semiconductor device includes a first member 205A shown in FIG. 5A and a second member 205B shown in FIG. 5B. In this embodiment, a first pad 201A, a first protection circuit 202A, and a first internal circuit 204A are formed on the first member 205A. A second protection circuit 202B and a second internal circuit 204B are formed on the second member 205B. In FIG. 5, the first protection circuit 202A is disposed between the first pad 201A and the first internal circuit 203A in a planar view, and the second protection circuit 202B is disposed between the second pad 201B and the second internal circuit 203B in a planar view. The circuit arrangement is not limited to this, and each protection circuit may be disposed between the first pad 201A and the second pad 201B, as in FIG. 3. Furthermore, the first protection circuit 202A and the second protection circuit 202B may be arranged so as to overlap each other in a plan view.

[0045] Fig. 6 is a cross-sectional view of the semiconductor device taken along dashed line BB' in Fig. 5. The semiconductor device of this embodiment is configured by bonding together a first member 205A having a first semiconductor substrate 200A and a first wiring structure 230A and a second member 205B having a second semiconductor substrate 200B and a second wiring structure 230B. The semiconductor device of this embodiment differs from the first embodiment in that the wiring layer on which the wiring that forms the first pad 201A is arranged is different from the wiring layer on which the wiring that forms the second pad 201B is arranged.

[0046] In this embodiment, the first pad 201A is configured by opening the semiconductor substrate from the first semiconductor substrate 200A side and exposing the wiring 207 in the first wiring structure 230A of the first member 205A. On the other hand, the second pad 201B is configured by opening the semiconductor substrate from the second semiconductor substrate 200A side and penetrating the first member 205A, exposing the wiring 217 included in the second wiring structure 230B of the second member 205B.

[0047] In the first embodiment, the first pad 101A and the second pad 101B are wires included in the same wiring layer, which has the advantage of allowing multiple pads to be formed in the same process. Meanwhile, the second pad 101B and the second internal circuit 104B are connected via the wires 114, 117, and 119, the vias 115, 116, 122, and 123, and the substrate joint 106, which increases the distance from the pad to the internal circuit. This can result in increased wiring resistance, which can cause a drop in power supply voltage and signal delays. Meanwhile, in the semiconductor device structure according to the second embodiment, the second pad 201B is wire included in a wiring layer within the second wiring structure 230B, which reduces the wiring resistance from the pad to the internal circuit, thereby reducing the drop in power supply voltage and signal delays.

[0048] (Third embodiment) The structure of a semiconductor device according to a third embodiment of the present invention will be described with reference to Figures 7 to 9. The semiconductor device according to the third embodiment has a CMOS sensor as part of its internal circuitry. Figure 7 is a schematic diagram of the planar layout of a protection circuit according to the third embodiment.

[0049] In this embodiment, the semiconductor device is constructed by bonding together a first member 305A shown in Fig. 7(A) and a second member 305B shown in Fig. 7(B). In this embodiment, a first pad 301A, a first protection circuit 302A, and a CMOS sensor 311 are formed on the first member 305A. Furthermore, a second protection circuit 302B and an internal circuit 304 are formed on the second member 305B. The internal circuit 304 is, for example, a processing circuit that processes signal charges generated by the CMOS sensor 311.

[0050] 7, first protection circuit 302A is arranged between first pad 301A and CMOS sensor 311, and second protection circuit 302B is arranged between second pad 301B and internal circuit 304. The circuit arrangement is not limited to this, and each protection circuit may be arranged between first pad 301A and second pad 301B as in Fig. 3. Also, first protection circuit 302A and second protection circuit 302B may be arranged so as to overlap in a plan view.

[0051] Fig. 8 shows an example of a pixel 315 that constitutes the CMOS sensor 311 shown in Fig. 7. The CMOS sensor 311 includes pixels 315 arranged in an array.

[0052] Each pixel 315 includes a photodiode 306, a transfer transistor 307, a reset transistor 308, an amplification transistor 309, and a row selection transistor 310. The output terminal of the photodiode 306 is connected to one of the source or drain of the transfer transistor 307, and the other terminal is connected to one of the source or drain of the reset transistor 308 and the gate of the amplification transistor 309. One of the source or drain of the amplification transistor is connected to one of the source or drain of the row selection transistor 310. The reset transistor 308 and the amplification transistor 309 are connected to a common power supply, which is supplied from a first pad 301A. The row selection transistor 310 is connected to a vertical output line and transmits a signal obtained by the photodiode 306 to an internal circuit composed of an AD conversion circuit, a horizontal output circuit, etc. (not shown).

[0053] Pixels 315 constituting the CMOS sensor 311 are arranged in an array on the first semiconductor substrate 300A, and a signal obtained from a sensor selected by a row selection transistor 310 is transmitted to an internal circuit 304 on the second semiconductor substrate 300B. All of the components 306 to 310 of the CMOS sensor 311 may be formed on the semiconductor substrate 300A, or some of them may be formed on the semiconductor substrate 300B.

[0054] FIG. 9 is a cross-sectional view of the semiconductor device taken along dashed line CC′ in FIG. 7 . The semiconductor device of this embodiment is configured by bonding together a first member 305A having a first semiconductor substrate 300A and a first wiring structure 330A and a second member 305B having a second semiconductor substrate 300B and a second wiring structure 330B. Here, the first pad 301A is configured by opening the semiconductor substrate from the first semiconductor substrate 300A side, exposing the wiring 313 of the first wiring structure 330A in the first member 305A. On the other hand, the second pad 301B is configured by forming an opening penetrating the first member 305A from the first semiconductor substrate 300A side, exposing the wiring 320 of the second wiring structure 330B in the second member 305B. The pad configuration is not limited to this; for example, as shown in the first embodiment, the first pad 301A and the second pad 301B may be provided in the same wiring layer.

[0055] In this embodiment, a CMOS sensor 311 is formed as an example of the internal circuits 104A and 204A in FIGS. 4 and 6 . An n-type semiconductor region 327 constituting a photodiode 306, an n-type semiconductor region 328 serving as the drain of a transfer transistor 307, and an element isolation structure 329 are arranged within a first semiconductor substrate 300A. The transfer transistor 307 is composed of n-type semiconductor regions 327 and 328 and a gate electrode 330, and charges generated and accumulated in the n-type semiconductor region 327 are transferred to the n-type semiconductor region 328 by the gate electrode 330. A color filter layer 332 including color filters corresponding to the pixels 315 and a microlens layer 331 including microlenses are arranged on the back side of the CMOS sensor 311. While FIG. 9 illustrates a so-called back-illuminated CMOS sensor in which light is incident from the microlens layer 331 side, the configuration of the CMOS sensor 311 is not limited to this.

[0056] Here, the operating voltage of the circuits may be different between the first semiconductor substrate 301A on which the CMOS sensor 311 is formed and the second semiconductor substrate 301B on which the internal circuit is formed. For example, a high voltage may be applied to the first semiconductor substrate 301A to improve the sensitivity of the CMOS sensor 311, and a low voltage may be applied to the second semiconductor substrate 301B to enable high-speed operation of the internal circuit.

[0057] According to the present invention, first protection circuit 302A connected to first pad 301A, which supplies a power supply voltage for operating CMOS sensor 311, is formed on first semiconductor substrate 300A. Meanwhile, second protection circuit 302B connected to second pad 301B, which supplies a voltage for driving the internal circuit, is formed on second semiconductor substrate 400B. This configuration makes it possible to suppress a decrease in wiring reliability and pn junction breakdown due to a high voltage power supply for sensor operation, while also optimizing the circuit area.

[0058] (Fourth embodiment) The structure of a semiconductor device according to a fourth embodiment of the present invention will be described with reference to Figures 10 to 12. This embodiment is characterized in that a SPAD (Single Photon Avalanche Diode) 410 is formed instead of the CMOS sensor 305 described in Figure 7.

[0059] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and a signal is extracted from the cathode side. Therefore, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is an N-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is a P-type semiconductor region. The present invention also applies when the cathode of the APD is set to a fixed potential and a signal is extracted from the anode side. In this case, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is a P-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is an N-type semiconductor region. While the following description focuses on a case where one node of the APD is set to a fixed potential, the potentials of both nodes may fluctuate.

[0060] Fig. 10 is a planar layout image of a protection circuit according to the fourth embodiment. In this embodiment, the semiconductor device is formed by bonding together a first member 405A shown in Fig. 10(A) and a second member 405B shown in Fig. 10(B). The first member 405A includes a first semiconductor substrate 400A and a first wiring structure 430A, and the second member 405B includes a second semiconductor substrate 400B and a second wiring structure 430B.

[0061] In this embodiment, the first pad 401A, the first protection circuit 402A, and the SPAD sensor 410 are formed on the first member 405A. The second protection circuit 402B and the internal circuit 404 are formed on the second member 405B. In FIG. 10, the first protection circuit 402A is disposed between the first pad 401A and the SPAD sensor 410, and the second protection circuit 402B is disposed between the second pad 401B and the internal circuit 404. The circuit arrangement is not limited to this, and each protection circuit may be disposed between the first pad 401A and the second pad 401B, as in FIG. 3. The first protection circuit 402A and the second protection circuit 402B may be disposed so as to overlap in a plan view.

[0062] FIG. 11 shows an example of the outline of the SPAD sensor 410 shown in FIG. 10. The SPAD sensor 410 is an avalanche photodiode and includes a photodiode 406, a quench element 407, an inverter circuit 408, and a counter circuit 409. A negative high-voltage power supply is supplied to the first pad 401A, and electrons generated by photoelectric conversion in the photodiode 406 are avalanche-multiplied. The amplified electrons are shaped into pulses via the inverter circuit 408 and transmitted to the counter circuit 409. One counter circuit 409 may be connected to one photodiode 406, or one counter circuit 409 may be connected to multiple photodiodes 406. All of these circuit elements 406 to 409 may be formed on the first semiconductor substrate 400A, or some of the elements may be formed on the second semiconductor substrate 400B. The quench element 407 may be a resistor or a transistor. The resistance value of the quench element may be variable, for example, it may be an element whose resistance value changes periodically.

[0063] FIG. 12 is a cross-sectional view of the semiconductor device taken along dashed line DD′ in FIG. 10 . The semiconductor device of this embodiment is configured by bonding together a first member 405A having a first semiconductor substrate 400A and a first wiring structure 430A and a second member 405B having a second semiconductor substrate 400B and a second wiring structure 430B. Here, the first pad 401A is configured by opening the semiconductor substrate from the first semiconductor substrate 400A side, exposing the wiring 412 of the first wiring structure 430A in the first member 410A. On the other hand, the second pad 401B is configured by providing an opening penetrating the first member 405A, exposing the wiring 419 in the second wiring structure 430B of the second member 405B. As shown in the first embodiment, the first pad 401A and the second pad 401B may be provided in the same wiring layer.

[0064] In this embodiment, a SPAD sensor 410 is formed as an example of the internal circuits 104A and 204A in FIGS. 4 and 6, or instead of the CMOS sensor in FIG. 9. In FIG. 12, only the photodiode 406 and first protection circuit 402A shown in FIG. 11 are formed on the first semiconductor substrate 400A. The arrangement of elements is not limited to this, and circuit elements 407 to 409 may also be formed on the first semiconductor substrate 400A. In addition, a color filter layer 428 including a plurality of color filters and a microlens layer 429 including a plurality of microlenses are arranged on the light incident surface side of the SPAD sensor 410. Although FIG. 12 describes a so-called back-illuminated SPAD sensor, the configuration of the SPAD sensor described in this embodiment is merely an example and is not limited thereto.

[0065] In the SPAD sensor 410, a negative high voltage is applied to the photodiode 406 to avalanche-multiply the charge obtained by photoelectric conversion. Therefore, a high voltage is applied to the first semiconductor substrate 400A. According to the configuration of the present invention, a first protection circuit 402A connected to a first pad 401A to which a negative high voltage for avalanche multiplication is applied is formed on the first semiconductor substrate 400A. On the other hand, a second protection circuit 402B connected to a second pad 401B to which a lower voltage is applied compared to the first pad 401A is formed on the second semiconductor substrate 400B. This configuration makes it possible to suppress deterioration of wiring reliability and breakdown of pn junctions while optimizing the circuit area.

[0066] (Fifth embodiment) The structure of a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS.

[0067] In the first to fourth embodiments, a protection element is disposed on each of the low-voltage substrate and the high-voltage substrate. Each of the protection circuits disposed on each substrate connects one terminal to the internal circuit of the substrate and the other terminal to a reference potential line. Placing the reference potential line on each substrate may reduce area efficiency. Therefore, this embodiment is characterized in that the reference potential lines connected to the protection circuits disposed on the low-voltage substrate and the protection circuits disposed on the high-voltage substrate are formed on one of the stacked substrates.

[0068] Variations in the arrangement of the reference potential line will be described with reference to FIGS.

[0069] 13 is a cross-sectional view of the semiconductor device according to the first embodiment. A first pad 101A on the high-voltage substrate and a second pad 101B on the low-voltage substrate are provided on a common wiring layer on the high-voltage substrate side. One terminal of a first protection circuit 102A on the high-voltage substrate and one terminal of a second protection circuit 102B on the low-voltage substrate are connected to a common reference potential line 103 provided on the low-voltage substrate side. By providing the reference line 103 on the low-voltage substrate, which has a high degree of freedom in wiring layout, it is possible to improve area efficiency.

[0070] 14 is a cross-sectional view of a semiconductor device according to the second embodiment. The first pad 201A of the high-voltage substrate is provided in a wiring layer on the high-voltage substrate side, and the second pad 201B of the low-voltage substrate is provided in a wiring layer on the low-voltage substrate side. One terminal of the first protection circuit 202A of the high-voltage substrate and one terminal of the second protection circuit 202B of the low-voltage substrate are connected to a common reference potential line 233 provided on the low-voltage substrate side. In this configuration, by providing the first pad 201A and the second pad 201B on each substrate, the wiring resistance from the pads to the internal circuit can be reduced, and power supply voltage drops and signal delays can be suppressed. Furthermore, by providing the reference wiring 103 on the low-voltage substrate, which has a high degree of freedom in wiring layout, area efficiency can be improved.

[0071] 15 is a cross-sectional view of a semiconductor device according to the second embodiment. As in FIG. 14, the first pad 201A of the high-voltage substrate is provided in a wiring layer on the high-voltage substrate side, and the second pad 201B of the low-voltage substrate is provided in a wiring layer on the low-voltage substrate side. This differs from FIG. 14 in that one terminal of the first protection circuit 202A of the high-voltage substrate and one terminal of the second protection circuit 202B of the low-voltage substrate are connected to a common reference potential line 243 provided on the high-voltage substrate side. By providing the reference potential line 243 on the high-voltage substrate, it is possible to reduce the possibility that potential fluctuations in the first pad 201A and the first internal circuit 204A connected to the reference potential line 243 will propagate to the low-voltage substrate.

[0072] 16 is a cross-sectional view of a semiconductor device according to the second embodiment. As in FIGS. 14 and 15, a first pad 201A on the high-voltage substrate is provided in a wiring layer on the high-voltage substrate side, and a second pad 201B on the low-voltage substrate is provided in a wiring layer on the low-voltage substrate side. One terminal of the first protection circuit 202A on the high-voltage substrate and one terminal of the second protection circuit 202B on the low-voltage substrate are connected to a common reference potential line 253 arranged on the low-voltage substrate side. Furthermore, a third protection circuit 202C is connected to the second pad 201B on the low-voltage substrate side and arranged on the high-voltage substrate.

[0073] 17 is a plan view of a semiconductor device according to this embodiment, which corresponds to the case where the reference potential line shown in FIGS. 14 and 16 is provided on the low-voltage substrate side.

[0074] Figure 17(a) shows a high-voltage substrate on which pixels such as a CMOS sensor 311 and a SPAD 410 are arranged, and Figure 17(b) shows a low-voltage substrate on which peripheral circuits are arranged, for example. Around the pixel area of ​​the high-voltage substrate, pads (PAD1) for the high-voltage substrate and pads (PAD2) for the low-voltage substrate are arranged alternately. On the low-voltage substrate, reference potential wiring is formed to surround the peripheral area, and pads for the low-voltage substrate are arranged around that.

[0075] As described above, the high-voltage substrate and the low-voltage substrate are connected via a wiring structure including multiple wiring layers. The shared potential wiring is formed using at least three wiring layers, and the wiring width is secured to be, for example, about 50 to 100 μm. By securing the wiring width, multiple vias can be connected to the common potential wiring.

[0076] (Sixth embodiment) The structure of a semiconductor device according to a sixth embodiment of the present invention will be described using Figures 18 and 19. In the first to fifth embodiments described above, the method of arranging a protection circuit in a semiconductor device having two members has been described. The sixth embodiment is characterized by having three members (first member 1701, second member 1702, and third member 1703). Explanations common to the first to fifth embodiments will be omitted, and the description will focus on the characteristic parts of the sixth embodiment.

[0077] 18A and 18B are schematic diagrams including a plan view of a semiconductor device according to the sixth embodiment. As shown in Fig. 18A, the semiconductor device shown in this embodiment is configured by stacking three members: a first member 1701, a second member 1702, and a third member 1703.

[0078] 18(b) shows the arrangement of elements on the first member 1701. A first pad 1704, a first protection circuit 1707, and a first internal circuit 1710 are arranged on the first member 1701. Furthermore, openings are provided that penetrate the first member 1701 toward a second pad 1705 arranged on the second member 1702 and a third pad 1706 arranged on the third member 1703.

[0079] 18(c) shows the arrangement of elements on the second member 1702. A second pad 1705, a second protection circuit 1708, and a second internal circuit 1711 are arranged on the second member 1702. Furthermore, an opening is provided that penetrates the second member 1702 toward a third pad 1706 arranged on a third member 1703.

[0080] 18(d) shows the arrangement of elements on the third member 1703. A third pad 1706, a third protection circuit 1709, and a third internal circuit 1712 are arranged on the third member 1703.

[0081] First pad 1704, second pad 1705, and third pad 1706 are pads that output signals generated within the semiconductor device to the outside, and pads that input voltages supplied from the outside to drive circuits in the semiconductor device. For example, a first power supply voltage is input to first pad 1704, a second power supply voltage is input to second pad 1705, and a third power supply voltage is input to third pad 1706. Furthermore, first protection circuit 1707 is connected to first pad 1704, second protection circuit 1708 is connected to second pad 1705, and third protection circuit 1709 is connected to third pad 1706.

[0082] Here, first protection circuit 1707 is arranged in a region between first pad 1704 and first internal circuit 1710 in a plan view, and first pad 1704 and first internal circuit 1710 are connected via first protection circuit 1707. Second protection circuit 1708 is arranged in a region between second pad 1705 and second internal circuit 1711, and second pad 1705 and second internal circuit 1711 are connected via second protection circuit 1708. Third protection circuit 1709 is arranged in a region between third pad 1706 and third internal circuit 1712, and third pad 1706 and third internal circuit 1712 are connected via third protection circuit 1709.

[0083] The position of each protection circuit is not limited to the region between the pad and the internal circuit, and may be, for example, between pads, etc. Furthermore, each protection circuit may be arranged in a region where they overlap each other in a plan view.

[0084] FIG. 19 is a cross-sectional view of the semiconductor device taken along dashed line EE' in FIG.

[0085] The first member 1701 includes a first semiconductor substrate 1701A and a first wiring layer 1701B. The second member 1702 includes a second semiconductor substrate 1702A and a second wiring layer 1702B. The third member 1703 includes a third semiconductor substrate 1703A and a third wiring layer 1703B.

[0086] In this embodiment, first wiring layer 1701B and second semiconductor substrate 1702A are bonded together, and second wiring layer 1702B and third wiring layer 1703A are bonded together. Therefore, the semiconductor device according to the sixth embodiment is configured by stacking first semiconductor substrate 1701A, first wiring layer 1701B, second semiconductor substrate 1702A, second wiring layer 1702B, third wiring layer 1703B, and third wiring layer 1703A in this order from the top of FIG. 19 . Here, first wiring layer 1701B and second wiring layer 1702B may be electrically connected via contact portion 1713 penetrating the substrate, and second wiring layer 1702B and third wiring layer 1703B may be electrically connected via substrate bonding portion 1714. Contact portion 1713 is configured to mainly contain a metal such as tungsten or copper. Furthermore, the substrate bond 1714 typically contains mainly copper, and is formed to further contain a barrier metal (titanium, nickel, etc.) to suppress the diffusion of copper.

[0087] The first protection circuit 1707 is disposed on the first semiconductor substrate 1701A, and the second protection circuit 1708 is disposed on the second semiconductor substrate 1702A. Furthermore, the third protection circuit 1709 is disposed on the third semiconductor substrate 1703A. In other words, each protection element is disposed on a semiconductor substrate adjacent to a wiring layer provided with a pad to which a voltage corresponding to the respective substrate is applied, and the wiring layer provided with the pad and the semiconductor substrate provided with the protection element constitute a single component. Furthermore, by disposing a reference potential wiring (not shown) on one of the substrates, the wiring area can be reduced.

[0088] Now, consider a case where the SPAD sensor described in the fourth embodiment is applied to the semiconductor device of this embodiment. In this case, for example, a configuration is possible in which the avalanche photodiode 410 shown in FIG. 11 is arranged as the first internal circuit 1710, the quench element 407, the inverter circuit 408, etc. are arranged as the second internal circuit 1711, and the counter circuit 409 and other peripheral circuits are arranged as the third internal circuit 1712. By using a structure in which three components are stacked, it is possible to increase the sizes of the quench element 407, the inverter circuit 408, etc. that make up the SPAD compared to a semiconductor device in which two components are stacked, and this is expected to have the effects of reducing manufacturing variations in the elements, reducing noise, etc.

[0089] In this configuration, a negative high-voltage power supply is supplied to the first semiconductor substrate 1701A to avalanche-multiply electrons generated by photoelectric conversion. On the other hand, elements arranged on the second semiconductor substrate 170A are generally operated at a higher voltage than elements arranged on the third semiconductor substrate 1703A. Therefore, the absolute values ​​of the voltages supplied to each substrate have the following relationship: |First power supply voltage|>>|Second power supply voltage|>|Third power supply voltage|

[0090] The magnitude relationship of the voltages supplied to the respective substrates can also be expressed as follows. |First power supply voltage - Second power supply voltage|>|Second power supply voltage - Third power supply voltage| |First power supply voltage - Third power supply voltage|>|Second power supply voltage - Third power supply voltage|

[0091] Therefore, according to this embodiment, even when different power supply voltages are supplied to the three components, the protection circuit can be designed using the optimal design rules set for each component, making it possible to simultaneously suppress deterioration of wiring reliability and pn junction breakdown while optimizing the circuit area.

[0092] This configuration is merely an example, and the relationship between the types of elements arranged on each substrate and the voltages supplied is not limited to this. For example, a configuration in which elements other than the avalanche photodiode are arranged on the first member 1701, or a configuration in which the quench element 407 or part of the inverter circuit 408 is arranged on the third member 1703 may be used.

[0093] (Seventh embodiment) The structure of a semiconductor device according to a seventh embodiment of the present invention will be described using Figures 20 and 21. The seventh embodiment is a semiconductor device having three substrates, similar to the sixth embodiment, and the method of bonding the components is also similar to the sixth embodiment. This embodiment will be described mainly focusing on the differences from the sixth embodiment. This embodiment is characterized in that the second protection circuit and the third protection circuit are arranged in the same component.

[0094] FIG. 20 is a plan view of a semiconductor device according to the seventh embodiment. As shown in FIG. 20(a), the semiconductor device according to this embodiment is formed by stacking a first member 1801, a second member 1802, and a third member 1803 in this order. FIG. 20(b) shows the arrangement of elements on the first member 1801. A first pad 1804, a first protection circuit 1807, and a first internal circuit 1810 are arranged on the first member 1801. Furthermore, openings are provided through the first member 1801 toward the second pad 1805 and the third pad 1806 arranged on the third member 1803. FIG. 20(c) shows the arrangement of elements on the second member 1802. Openings are provided through the second member 1802 toward the second pad 1805 and the third pad 1806 arranged on the third member 1803. FIG. 20(c) shows the arrangement of elements on the third member 1803. A second pad 1805 , a third pad 1806 , a second protection circuit 1808 , a third protection circuit 1809 and a third internal circuit 1812 are disposed on a third member 1803 .

[0095] Fig. 21 is a cross-sectional view of the semiconductor device taken along dashed line FF' in Fig. 20. As described above, the method of bonding the various components is the same as in the sixth embodiment, but differs from the sixth embodiment in that the second pad 1805 and the second protection circuit 1808 are disposed on the third component 1803. Although both the second pad 1805 and the second protection circuit 1808 are disposed on the third component 1803 in Fig. 21, for example, the second protection circuit 1808 may be disposed on the second component 1802 and the second pad 1805 may be disposed on the third component 1803.

[0096] As in the explanation for the sixth embodiment, when a SPAD sensor is applied to the semiconductor device of this embodiment, an example of the relationship between the voltages applied to each member is shown below. There is a large difference in the absolute value of the voltages applied between the first member 1801 and the second member 1802, or between the first member 1801 and the third member 1803. |First power supply voltage|>>|Second power supply voltage|>|Third power supply voltage|

[0097] The magnitude relationship of the voltages supplied to the respective substrates can also be expressed as follows. |First power supply voltage - Second power supply voltage|>|Second power supply voltage - Third power supply voltage| |First power supply voltage - Third power supply voltage|>|Second power supply voltage - Third power supply voltage|

[0098] For example, assume that the voltage supplied to the first pad 1804 is approximately −30 V, the voltage supplied to the second pad 1805 is approximately 3.3 V, and the voltage supplied to the third pad 1806 is approximately 1.1 V. There is no significant difference in the voltages supplied to the second pad 1805 and the third pad 1806, and it is believed that there will be no significant differences in the design rules for the wiring process of the second member 1802 and the third member 1803 to which voltages are supplied from each pad, or in the withstand voltage of the p-n junction. Therefore, if both the second pad 1805 and the second protection circuit 1808 are disposed on the same substrate, there are disadvantages such as the inability to optimize the p-n junction and wiring width and space, but these impacts are small. On the other hand, the second pad 1805 and the third pad 1806 can be manufactured in the same process. Furthermore, because the second protection circuit 1808 and the third protection circuit 1809 can be manufactured in the same process, the semiconductor device according to the seventh embodiment can be manufactured with fewer process steps than the sixth embodiment.

[0099] (Eighth embodiment) The structure of a semiconductor device according to an eighth embodiment of the present invention will be described with reference to Figures 22 and 23. The eighth embodiment is a semiconductor device composed of three members, similar to the sixth and seventh embodiments, but is characterized by a different method of stacking the members.

[0100] FIG. 22 is a plan view of a semiconductor device according to the eighth embodiment.

[0101] In this embodiment, as shown in FIG. 22(a), a first member 1901, a second member 1902, and a third member 1903 are laminated in this order. FIG. 22(b) shows the arrangement of elements on the first member 1901. A first pad 1904, a first protective circuit 1907, and a first internal circuit 1910 are arranged on the first member 1901. Furthermore, openings are provided that penetrate the second member 1902 toward second pads 1905 and third pads 1906 arranged on the second member 1902. FIG. 22(c) shows the arrangement of elements on the second member 1902. A second pad 1905, a third pad 1906, and a second internal circuit 1911 are arranged on the second member 1902. As shown in FIG. 22(d), no pads or protective elements are arranged on the third member 1903, and only a third internal circuit 1912 is arranged thereon.

[0102] FIG. 23 is a cross-sectional view of the semiconductor device taken along dashed line GG' in FIG.

[0103] In this embodiment, first wiring layer 1901B and second wiring layer 1902B are bonded together, and second semiconductor substrate 1901A and third wiring layer 1903B are bonded together. In the semiconductor device according to the eighth embodiment, from the top of FIG. 23, first semiconductor substrate 1901A, first wiring layer 1901B, second wiring layer 1902B, second semiconductor substrate 1902A, third wiring layer 1903B, and third wiring layer 1903A are arranged in this order. Here, first wiring layer 1901B and second wiring layer 1902B are electrically connected via substrate bonding portion 1913, for example, and second semiconductor substrate 1902A and third wiring layer 1903B are electrically connected via through-substrate contact portion 1914, for example.

[0104] In this embodiment, the first protection circuit 1907 is disposed on the first semiconductor substrate 1901A, and the second protection circuit 1908 and the third protection circuit 1909 are disposed on the second semiconductor substrate 1902A. In Figures 22 and 23, the second pad 1905 and the second protection circuit 1907, and the third pad 1906 and the third protection circuit 1909 are disposed in regions that do not overlap when viewed from above the main surface of the first semiconductor substrate 1901A, but they may also be disposed in regions that overlap.

[0105] In the sixth and seventh embodiments, it was necessary to form deep pad openings that penetrate the semiconductor substrate at least twice, but the semiconductor device shown in this embodiment only requires a relatively shallow pad opening that penetrates the semiconductor substrate once, which makes it possible to simplify the pad opening process and bonding process and to achieve high reliability.

[0106] (Ninth embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 24. Fig. 24 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0107] The photoelectric conversion devices described in the first to sixth embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Also included in the photoelectric conversion system is a camera module equipped with an optical system such as a lens and an imaging device. Fig. 24 illustrates a block diagram of a digital still camera as an example of such systems.

[0108] 24 includes an image pickup device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the image pickup device 1004. The system further includes an aperture 1003 that adjusts the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0109] The photoelectric conversion system also includes a signal processing unit 1007, which is an image generation unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compressions as necessary to output image data. The signal processing unit 1007 may be formed on the same semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004.

[0110] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data from the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system or may be detachable.

[0111] The photoelectric conversion system further includes an overall control and calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0112] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004 and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0113] As described above, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0114] (Tenth embodiment) The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 25. Fig. 25 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0115] FIG. 25A shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 1300 includes an image capture device 1310. The image capture device 1310 is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 1300 includes an image processing unit 1312 that performs image processing on multiple pieces of image data acquired by the image capture device 1310, and a parallax acquisition unit 1314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 1300. The photoelectric conversion system 1300 also includes a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 1318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, or may be realized by a software module. Furthermore, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or may be realized by a combination of these.

[0116] The photoelectric conversion system 1300 is connected to a vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 1300 is also connected to a control ECU 1330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 1318. The photoelectric conversion system 1300 is also connected to an alarm device 1340 that issues an alarm to the driver based on the determination result of the collision determination unit 1318. For example, if the determination result of the collision determination unit 1318 indicates a high possibility of a collision, the control ECU 1330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0117] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 1300. Fig. 25(B) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 1350). A vehicle information acquisition device 1320 sends instructions to the photoelectric conversion system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0118] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0119] (Eleventh embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 26. Fig. 26 is a block diagram showing an example of the configuration of a range image sensor which is the photoelectric conversion system of this embodiment.

[0120] 26, the range image sensor 1401 is configured to include an optical system 1407, a photoelectric conversion device 1408, an image processing circuit 1404, a monitor 1405, and a memory 1406. The range image sensor 1401 can obtain a range image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected toward the subject from a light source device 1409 and reflected from the surface of the subject.

[0121] The optical system 1407 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photoelectric conversion device 1408, forming an image on the light receiving surface (sensor section) of the photoelectric conversion device 1408.

[0122] The photoelectric conversion device 1408 is one of the photoelectric conversion devices according to the above-described embodiments, and a distance signal indicating a distance determined from a light reception signal output from the photoelectric conversion device 1408 is supplied to the image processing circuit 1404 .

[0123] The image processing circuit 1404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 1408. The distance image (image data) obtained by this image processing is then supplied to a monitor 1405 for display, or supplied to a memory 1406 for storage (recording).

[0124] In the range image sensor 1401 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0125] (Twelfth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 27. Fig. 27 is a diagram showing an example of a schematic configuration of an endoscopic surgery system, which is the photoelectric conversion system of this embodiment.

[0126] 27 shows a state in which an operator (doctor) 1131 is performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1150. As shown in the figure, the endoscopic surgery system 1150 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0127] The endoscope 1100 is composed of a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. In the example shown, the endoscope 1100 is configured as a so-called rigid lens barrel having a rigid lens barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0128] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 1132. The endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0129] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and light reflected from an observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is sent to a camera control unit (CCU: CAmerA Control Unit) 1135 as RAW data.

[0130] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0131] Under the control of the CCU 1135 , the display device 1136 displays an image based on the image signal that has been subjected to image processing by the CCU 1135 .

[0132] The light source device 1203 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 1100 with irradiation light when photographing an operation site or the like.

[0133] The input device 1137 is an input interface for the endoscopic surgery system 1150. A user can input various information and instructions to the endoscopic surgery system 1150 via the input device 1137.

[0134] The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0135] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical site, can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 1203. In this case, it is also possible to capture images corresponding to each RGB color in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0136] Furthermore, the light source device 1203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0137] The light source device 1203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, specific tissue, such as blood vessels on the surface of the mucous membrane, can be photographed with high contrast by irradiating light with a narrower band than the light (i.e., white light) used in normal observation. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 1203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0138] (Thirteenth embodiment) The photoelectric conversion system of this embodiment will be described with reference to FIGS. 28(A) and (B). FIG. 28(A) illustrates glasses 1600 (smart glasses) which are the photoelectric conversion system of this embodiment. The glasses 1600 have a photoelectric conversion device 1602. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the above embodiments. A display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 1601. There may be one or more photoelectric conversion devices 1602. A combination of multiple types of photoelectric conversion devices may also be used. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 28(A).

[0139] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device. The control device 1603 also controls the operations of the photoelectric conversion device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the photoelectric conversion device 1602.

[0140] FIG. 28B illustrates glasses 1610 (smart glasses) according to one application example. The glasses 1610 include a control device 1612, which includes a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. A lens 1611 includes an optical system for projecting light emitted from the photoelectric conversion device and the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light-receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitter to the display unit in a planar view reduces degradation of image quality.

[0141] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0142] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0143] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0144] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0145] The display area may include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first and second field-of-view areas may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0146] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0147] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0148] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0149] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present invention.

[0150] Furthermore, the photoelectric conversion systems shown in the ninth and tenth embodiments are examples of photoelectric conversion systems to which a photoelectric conversion device can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 24 and 25. The same applies to the ToF system shown in the eleventh embodiment, the endoscope shown in the twelfth embodiment, and the smart glasses shown in the thirteenth embodiment.

[0151] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0152] The present disclosure has the following configuration.

[0153] (Configuration 1) a first pad to which a first power supply voltage for driving elements formed on the first semiconductor substrate is input from an external device; a second pad to which a second power supply voltage for driving elements formed on the second semiconductor substrate is input from an external device; a first protection circuit disposed on the first semiconductor substrate; and a second protection circuit disposed on the second semiconductor substrate, wherein the first power supply voltage is higher than the second power supply voltage, the first protection circuit is electrically connected to the first pad, and the second protection circuit is electrically connected to the second pad.

[0154] (Configuration 2) 2. The semiconductor device according to configuration 1, wherein the circuit area of ​​the first protection circuit is larger than the circuit area of ​​the second protection circuit.

[0155] (Configuration 3) 3. The semiconductor device according to claim 1, wherein a gate oxide film of a transistor included in the first protection circuit is thicker than a gate oxide film of a transistor included in the second protection circuit.

[0156] (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein the first protection circuit and the second protection circuit do not overlap in a plan view.

[0157] (Configuration 5) 5. The semiconductor device according to any one of structures 1 to 4, comprising: a first wiring structure disposed between the first semiconductor substrate and the second semiconductor substrate; a second wiring structure disposed between the first wiring structure and the second semiconductor substrate; a first wiring layer included in the first wiring structure; and a second wiring layer included in the second wiring structure.

[0158] (Configuration 6) 6. The semiconductor device according to claim 5, wherein the first pad and the second pad are arranged in the same layer as the first wiring layer.

[0159] (Configuration 7) 6. The semiconductor device according to claim 5, wherein the first pad is arranged in the same layer as the first wiring layer, and the second pad is arranged in the same layer as the second wiring layer.

[0160] (Configuration 8) 8. The semiconductor device of claim 6, further comprising a second opening formed above a portion of the second wiring layer.

[0161] (Configuration 9) The semiconductor device according to any one of structures 5 to 8, characterized in that the first wiring structure includes a first insulating layer, the second wiring structure includes a second insulating layer, and the first wiring structure and the second wiring structure are joined so that the first insulating layer and the second insulating layer are in contact with each other.

[0162] (Configuration 10) 10. The semiconductor device according to any one of configurations 5 to 9, wherein the first wiring included in the first wiring layer is electrically connected to an element formed on the first semiconductor substrate.

[0163] (Configuration 11) 11. The semiconductor device according to any one of configurations 5 to 10, wherein the second wiring included in the second wiring layer is electrically connected to an element formed on the second semiconductor substrate.

[0164] (Configuration 12) the first protection circuit is electrically connected between the first pad and a reference potential wiring; 12. The semiconductor device according to any one of configurations 1 to 11, wherein the second protection circuit is electrically connected between the second pad and the reference potential wiring.

[0165] (Configuration 13) 13. The semiconductor device according to claim 12, wherein the reference potential wiring is a ground wiring.

[0166] (Configuration 14) 14. The semiconductor device according to claim 12, wherein the reference potential wiring is formed on either the first semiconductor substrate or the second semiconductor substrate.

[0167] (Configuration 15) 15. The semiconductor device according to any one of configurations 1 to 14, wherein the elements formed on the first semiconductor substrate include photoelectric conversion elements.

[0168] (Configuration 16) 16. The semiconductor device according to claim 15, wherein the first semiconductor substrate has at least a part of a circuit for reading out a signal based on the charge of the photoelectric conversion element.

[0169] (Configuration 17) 16. The semiconductor device according to configuration 15, wherein the photoelectric conversion element is an avalanche photodiode to which the first power supply voltage is input.

[0170] (Configuration 18) 18. The semiconductor device according to any one of configurations 1 to 17, wherein the thickness of the first semiconductor substrate is thinner than the thickness of the second semiconductor substrate.

[0171] (Configuration 19) The semiconductor device of configuration 5, wherein the number of wiring layers arranged between the wiring layer on which the first pad is arranged and the first protection circuit is less than or equal to the number of wiring layers arranged between the wiring on which the second pad is arranged and the second protection circuit.

[0172] (Configuration 20) The semiconductor device according to configuration 1, further comprising: a third semiconductor substrate stacked on the second semiconductor substrate; a third pad to which a third power supply voltage for driving an element formed on the third semiconductor substrate is input from outside; and a third protection circuit electrically connected to the third pad, wherein the absolute value of the first power supply voltage is greater than the absolute value of the third power supply voltage.

[0173] (Configuration 21) 21. The semiconductor device of configuration 20, comprising: a first wiring structure stacked on the first semiconductor substrate; a second wiring structure stacked on the second semiconductor substrate; a third wiring structure stacked on the third semiconductor substrate; a first wiring layer included in the first wiring structure; a second wiring layer included in the second wiring structure; and a third wiring layer included in the third wiring structure, wherein the first pad is arranged in the same layer as the first wiring layer, the second pad is arranged in the same layer as the second wiring layer, and the third pad is arranged in the same layer as the third wiring layer.

[0174] (Configuration 22) 21. The semiconductor device of configuration 20, comprising: a first wiring structure stacked on the first semiconductor substrate; a second wiring structure stacked on the second semiconductor substrate; a third wiring structure stacked on the third semiconductor substrate; a first wiring layer included in the first wiring structure; a second wiring layer included in the second wiring structure; and a third wiring layer included in the third wiring structure, wherein the first pad is arranged on the same layer as the first wiring layer, and the second pad and the third pad are arranged on the same layer as the second wiring layer.

[0175] (Configuration 23) 23. A photoelectric conversion system comprising: a semiconductor device according to any one of configurations 1 to 22; and a signal processing unit that generates an image using a signal output by the semiconductor device.

[0176] (Configuration 24) 23. A moving body including the semiconductor device according to any one of configurations 1 to 22, characterized in that the moving body has a control unit that controls the movement of the moving body using a signal output by the semiconductor device. [Explanation of symbols]

[0177] 100A First semiconductor substrate 100B Second semiconductor substrate 101A 1st Pad 101B 2nd pad 102A 1st protection circuit 102B 2nd protection circuit

Claims

1. a first semiconductor substrate; a second semiconductor substrate stacked on the first semiconductor substrate; a first pad to which a first power supply voltage for driving elements formed on the first semiconductor substrate is input from an external source; a second pad to which a second power supply voltage for driving elements formed on the second semiconductor substrate is input from an external source; a first protection circuit disposed on the first semiconductor substrate; a second protection circuit disposed on the second semiconductor substrate; the absolute value of the first power supply voltage is higher than the absolute value of the second power supply voltage; the first protection circuit is electrically connected to the first pad; The semiconductor device, wherein the second protection circuit is electrically connected to the second pad.

2. 2. The semiconductor device according to claim 1, wherein the circuit area of ​​the first protection circuit is larger than the circuit area of ​​the second protection circuit.

3. 2. The semiconductor device according to claim 1, wherein a gate oxide film of a transistor included in the first protection circuit is thicker than a gate oxide film of a transistor included in the second protection circuit.

4. The semiconductor device according to claim 1 , wherein the first protection circuit and the second protection circuit do not overlap in a plan view.

5. a first wiring structure disposed between the first semiconductor substrate and the second semiconductor substrate; a second wiring structure disposed between the first wiring structure and the second semiconductor substrate; a first wiring layer included in the first wiring structure; 2. The semiconductor device according to claim 1, further comprising: a second wiring layer included in the second wiring structure.

6. 6. The semiconductor device according to claim 5, wherein the first pad and the second pad are arranged in the same layer as the first wiring layer.

7. the first pad is disposed in the same layer as the first wiring layer, 6. The semiconductor device according to claim 5, wherein the second pad is disposed in the same layer as the second wiring layer.

8. 8. The semiconductor device according to claim 6, wherein a second opening is formed on a part of the second wiring layer.

9. the first wiring structure includes a first insulating layer; the second wiring structure includes a second insulating layer; 6. The semiconductor device according to claim 5, wherein the first wiring structure and the second wiring structure are bonded together so that the first insulating layer and the second insulating layer are in contact with each other.

10. 6. The semiconductor device according to claim 5, wherein the first wiring included in the first wiring layer is electrically connected to an element formed on the first semiconductor substrate.

11. 6. The semiconductor device according to claim 5, wherein the second wiring included in the second wiring layer is electrically connected to an element formed on the second semiconductor substrate.

12. the first protection circuit is electrically connected between the first pad and a reference potential wiring; 2. The semiconductor device according to claim 1, wherein the second protection circuit is electrically connected between the second pad and the reference potential wiring.

13. 13. The semiconductor device according to claim 12, wherein the reference potential wiring is a ground wiring.

14. 13. The semiconductor device according to claim 12, wherein the reference potential wiring is formed on either the first semiconductor substrate or the second semiconductor substrate.

15. 2. The semiconductor device according to claim 1, wherein the elements formed on the first semiconductor substrate include photoelectric conversion elements.

16. 16. The semiconductor device according to claim 15, wherein the first semiconductor substrate has at least a part of a circuit for reading out a signal based on the charge of the photoelectric conversion element.

17. 16. The semiconductor device according to claim 15, wherein the photoelectric conversion element is an avalanche photodiode to which the first power supply voltage is input.

18. 2. The semiconductor device according to claim 1, wherein the thickness of the first semiconductor substrate is thinner than the thickness of the second semiconductor substrate.

19. 6. The semiconductor device according to claim 5, wherein the number of wiring layers arranged between the wiring layer in which the first pad is arranged and the first protection circuit is equal to or less than the number of wiring layers arranged between the wiring in which the second pad is arranged and the second protection circuit.

20. a third semiconductor substrate stacked on the second semiconductor substrate; a third pad to which a third power supply voltage for driving an element formed on the third semiconductor substrate is input from an external source, and a third protection circuit electrically connected to the third pad; 2. The semiconductor device according to claim 1, wherein the absolute value of said first power supply voltage is greater than the absolute value of said third power supply voltage.

21. a first wiring structure stacked on the first semiconductor substrate; a second wiring structure stacked on the second semiconductor substrate; a third wiring structure stacked on the third semiconductor substrate; a first wiring layer included in the first wiring structure; a second wiring layer included in the second wiring structure; a third wiring layer included in the third wiring structure, the first pad is disposed in the same layer as the first wiring layer, the second pad is disposed in the same layer as the second wiring layer, 21. The semiconductor device according to claim 20, wherein the third pad is disposed in the same layer as the third wiring layer.

22. a first wiring structure stacked on the first semiconductor substrate; a second wiring structure stacked on the second semiconductor substrate; a third wiring structure stacked on the third semiconductor substrate; a first wiring layer included in the first wiring structure; a second wiring layer included in the second wiring structure; a third wiring layer included in the third wiring structure, the first pad is disposed in the same layer as the first wiring layer, 21. The semiconductor device according to claim 20, wherein the second pad and the third pad are arranged in the same layer as the second wiring layer.

23. The semiconductor device of claim 1 ; a signal processing unit that generates an image using a signal output from the semiconductor device.

24. A moving object including the semiconductor device according to claim 1, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the semiconductor device.

Images