Method and device for reducing voltage load of semiconductor component of inverter

JP2023106341A5Pending Publication Date: 2026-01-16ROBERT BOSCH GMBH
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Patent Information

Application Number
JP2023006283
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2022-01-20
Filing Date
2023-01-19
Publication Date
2026-01-16

AI Technical Summary

Technical Problem

Existing inverters in electrically drivable vehicles face high voltage loads on semiconductor components during charging and reverse energy flow due to the absence of additional switches, leading to increased wear and manufacturing costs.

Method used

A method and device that adjust the gate voltage of semiconductor elements in series circuits to block current flow and match voltage loads, using evaluation units and gate drivers to reduce leakage currents and distribute load evenly across components.

Benefits of technology

Reduces semiconductor component wear and manufacturing costs by minimizing voltage loads during charging, extending component lifespan and optimizing manufacturing tolerances.

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Abstract

To provide a method and a device for reducing voltage loads of semiconductor components of an inverter and, in particular, of a three-phase inverter.SOLUTION: A device includes one or more series circuits comprising at least one first semiconductor component 10 and a second semiconductor component 20 which are MOSFETs, SiC-MOSFETs and / or power semiconductors, the device converting a direct voltage into an alternating voltage suitable for an electric machine. In the device, an inverter 30 converts a direct voltage Ubat supplied from a battery 40 into an alternating voltage Uac suitable for an electric machine 50, supplies the alternating voltage to the electric machine 50, and adapts a gate voltage of the first semiconductor component and / or a gate voltage of the second semiconductor component to approximately interrupt a current flow between the battery and the electric machine during charging of the battery. A voltage load of a gate oxide layer of each of the first and second semiconductor components is reduced by decreasing the gate voltage of each semiconductor component, and / or voltage loads of drain-source paths of the semiconductor components are matched to one another.SELECTED DRAWING: Figure 1
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Description

Technical Field

[0001] The present invention relates to a method and a device for reducing the voltage load of semiconductor elements of an inverter, particularly a three-phase inverter.

Background Art

[0002] In the charging mode of a battery of an electrically drivable vehicle having an electrical system including a battery, a driving inverter, and an electric motor, usually, the driving inverter is in a non-operating state. Basically, two system concepts are known for connecting the driving inverter. The driving inverter is either disconnected by an additional switch or set to a non-operating mode and left in this mode.

[0003] Due to cost reasons, such additional switches are often omitted, so the semiconductors used in the inverter are loaded by the application of a negative gate-source voltage and a part of the so-called DC link voltage during the charging mode.

[0004] Furthermore, in the prior art, vehicles are known that enable a bi-directional charging mode in which the electrical energy stored in the vehicle's battery can also flow in the reverse direction to an external charging station. That is, the semiconductors of the driving inverter are loaded as described above even during the period when energy flows backward unless they are galvanically insulated from the battery by an additional switch.

Summary of the Invention

Means for Solving the Problems

[0005] According to a first aspect of the present invention, a method for reducing the voltage load of semiconductor elements of an inverter, for example, a driving inverter of an electric drive vehicle, is proposed. In a first step of the method according to the present invention, a requirement is identified for charging a battery in an electrical system having at least one battery, an inverter, and an electromechanism. If the electrical system is a component of an electrically driven vehicle, the electromechanism is, for example, an electric motor in the vehicle's drive system, and the electrical system is not limited to such applications and is not limited to applications in vehicles.

[0006] Battery charging requests are generated, for example, in the vehicle charging process, by a charging device electrically connected to the vehicle. The inverter is configured based on at least one series circuit comprising at least one first semiconductor element and a second semiconductor element, and converts a DC voltage supplied from a battery into an AC voltage suitable for an electromechanical device and supplies it to the electromechanical device. The semiconductor elements are configured as, for example, MOSFETs (metal-oxide-semiconductor field-effect transistors), SiC-MOSFETs, and / or power semiconductors. Furthermore, it is also possible to connect another semiconductor element in parallel to the first semiconductor element and / or the second semiconductor element, for example, to switch high load currents. In such cases, it is preferable that all semiconductor elements in each parallel circuit are controlled similarly and simultaneously. It is preferable that each semiconductor element is controlled by an evaluation unit according to the present invention and / or by a separate gate driver that can be connected to such an evaluation unit using information processing technology.

[0007] In a second step of the method according to the present invention, the gate voltage of the first semiconductor element (abbreviated as "gate-source voltage") and / or the gate voltage of the second semiconductor element are adjusted to substantially interrupt the flow of current between the battery and the electromechanical device during battery charging. Here, "substantially" refers to the normally present leakage current that may flow through the source-drain path of the semiconductor element even when the semiconductor element is off. Thus, interrupting the flow of current here means the off state of the first semiconductor element and / or the second semiconductor element.

[0008] The gate voltage of the first semiconductor element and / or the gate voltage of the second semiconductor element are adjusted by lowering the gate voltages of the first and second semiconductor elements, thereby reducing the voltage load on the gate oxide film of each semiconductor element.

[0009] Alternatively, gate voltage adjustment is performed so that the voltage loads in the drain-source paths of each semiconductor element are matched to each other. Because the conductance values ​​of the drain-source paths of each semiconductor element differ, different voltage loads can occur in two semiconductor elements, which in turn results in different voltage drops across the two semiconductor elements.

[0010] To match the voltage load in the drain-source path of each semiconductor element, voltage measurements are performed using appropriate voltage sensors, and the deviations in the voltage load are identified based on these measurements. For this purpose, each voltage sensor is connected to the evaluation unit according to the present invention, for example, using information processing technology.

[0011] If there is no switch to galvanically isolate the inverter in charging mode for reasons such as cost and / or space, this method can advantageously achieve a longer inverter lifespan because the voltage load on the semiconductor elements is reduced and / or matched. Furthermore, since the manufacturing tolerances of the semiconductor elements can be compensated by the method according to the present invention, the tolerance requirements of the semiconductor elements can be reduced, and thereby the manufacturing cost of the semiconductor elements can also be reduced accordingly.

[0012] These advantages are particularly evident when the semiconductor elements used operate primarily in an off state throughout their entire service life. In particular, the aforementioned electrically driven vehicles typically have a significantly shorter service life than their charging period, making these applications applicable to such vehicles.

[0013] The cited claims illustrate preferred further improvements to the present invention. In an advantageous embodiment of the present invention, the drain-source voltages of the first semiconductor element and the second semiconductor element are consistently set to approximately the same value during battery charging. That is, not only are the drain-source voltages approximate each other, but identical drain-source voltage characteristics are obtained.

[0014] Alternatively, the first and second semiconductor elements are alternately switched between conductive and non-conductive modes during battery charging, with only one of the two semiconductor elements in conductive mode while the other is in non-conductive mode, and the total time spent in conductive mode for each of the two semiconductor elements during battery charging being approximately the same. In other words, this achieves the equalization of the voltage load on the two semiconductor elements over time. In particular, the multiphase inverter configuration described later has the special advantage of reducing the individual load on each semiconductor because the load on each semiconductor can be sequentially distributed to semiconductors of different phases.

[0015] It is particularly preferable to set the gate voltages of the first and second semiconductor elements to 0V or close to 0V to reduce the voltage load on the gate oxide films of the semiconductor elements.

[0016] Advantageously, the gate voltages of the first and second semiconductor elements are adjusted to match the voltage load of each drain-source path of the semiconductor elements within a voltage range that ranges exclusively from a negative gate voltage value to a predetermined threshold, where the predetermined threshold is below the threshold voltage of each semiconductor element. The predetermined threshold is at least 1V below the threshold voltage of the semiconductor element, so that leakage current can be kept low and / or, preferably, each semiconductor does not unintentionally turn on. Since the voltage load reduction control of the semiconductor elements according to the present invention is performed during the battery charging mode in which power loss due to leakage current does not burden the battery but burdens the charging device, the level of leakage current is usually not a problem even if the gate voltage approaches the threshold.

[0017] In a further advantageous embodiment of the present invention, the inverter has a plurality of series circuits (e.g., two or more half-bridge or full-bridge circuits) each consisting of at least one first semiconductor element and a second semiconductor element, each series circuit configured to control a phase of a polyphase electromachine (e.g., a three-phase motor), and the voltage load of all these semiconductor elements is reduced and / or matched during battery charging. Preferably, the matching adjustment results in a voltage difference of 0V across each phase.

[0018] Advantageously, each gate voltage is adjusted based on a first voltage measurement representing the total voltage drop across at least one series circuit consisting of at least two semiconductor elements, and a second voltage measurement representing the voltage drop across the semiconductor element on the lower potential side of the series circuit (i.e., the "low-side" semiconductor element). In a drive inverter, there are typically three parallel phases short-circuited by the leakage inductance of the motor's stator. This allows for a first-order approximation that the voltages of all three phases are the same. Therefore, using the single phase voltage sensor described above is sufficient to measure the voltage across all semiconductors. This enables particularly cost-effective embodiments of the present invention, as only one phase voltage sensor is required despite the inverter being configured for multiple phases.

[0019] In a further advantageous embodiment of the present invention, the voltage drop across a semiconductor element on the low-potential side is determined based on a measurement of a negative temperature coefficient (NTC) resistor provided for temperature detection of the semiconductor element, and based on the estimated temperature of the semiconductor element. Therefore, since voltage measurements across an NTC resistor to determine the temperature of the semiconductor element are often already performed, there is an advantage in that there is no need to place an additional voltage sensor for voltage measurement across the semiconductor element. By connecting the NTC resistor to the drain terminal of the semiconductor element via a high resistance, a particularly simple and cost-effective voltage measurement of the semiconductor element can be performed based on the voltage divider thus constructed.

[0020] Furthermore, the voltage load matching adjustment for each semiconductor element is performed taking into account the existing degradation of each semiconductor element, particularly identified by the gate voltage fluctuation. For this reason, a gate voltage fluctuation value for the semiconductor element is set within a voltage range below the semiconductor element's threshold voltage (also known as the "subthreshold" region) to understand the changes in the semiconductor element's characteristic curve. Any observed changes in the characteristic curve are advantageous when considered when reducing the voltage load on the semiconductor element.

[0021] According to a second aspect of the present invention, an apparatus for reducing the voltage load on semiconductor elements of an inverter is proposed. This apparatus comprises a first semiconductor element, a second semiconductor element, and an evaluation unit. The evaluation unit is preferably configured as, for example, an ASIC (Application Specific Integrated Circuit), an FPGA (field-programmable grid array), a processor, a digital signal processor, a microcontroller, etc., and is connected to a first gate driver and a second gate driver, respectively, connected to the control inputs (gates) of the two semiconductor elements, using information processing technology. The first gate driver and the second gate driver are, for example, integrated into the evaluation unit and / or configured as separate components. The evaluation unit is configured to identify the battery charge request of an electrical system having at least one battery, an inverter, and an electromechanism (e.g., an electric motor), and the inverter is configured based on at least one series circuit consisting of at least a first semiconductor element and a second semiconductor element (e.g., each MOSFET), which converts the DC voltage supplied by the battery into an AC voltage suitable for the electromechanism and supplies it to the electromechanism. The evaluation unit is configured to adjust the gate voltage of the first semiconductor element (preferably by a first gate driver) and / or the gate voltage of the second semiconductor element (preferably by a second gate driver) to substantially interrupt the current flow between the battery and the electromechanical device during battery charging, thereby reducing the voltage load on the gate oxide film of each semiconductor element and / or matching the voltage load on the drain-source path of each semiconductor element by lowering the gate voltages of the first and second semiconductor elements. Features, combinations of features, and the resulting advantages correspond to those described in relation to the embodiments stated at the beginning of the invention, refer to the above description to avoid repetition. [Brief explanation of the drawing]

[0022] Embodiments of the present invention will be described in detail below with reference to the attached drawings. [Figure 1]This is a circuit diagram of an embodiment of the apparatus according to the present invention. [Figure 2] This is a circuit diagram for explaining exemplary phase voltage measurement according to the present invention. Embodiments for Carrying Out the Invention

[0023] FIG. 1 is a circuit diagram showing an embodiment of the apparatus according to the present invention. The apparatus has an inverter 30 configured to convert the DC voltage of a battery 40 into a three-phase AC voltage Uac. The circuits of the three phases P1, P2, and P3 are each represented by a dashed rectangle for reasons of simplification, and only the circuit of the first phase P1 is shown in detail as representative of all three phases P1, P2, and P3. The other phases P2 and P3 are configured in the same manner as the first phase P1.

[0024] The circuit of the first phase P1 has two first MOSFETs 10 connected in parallel and two second MOSFETs 20 connected in series, which are in parallel connection. Here, the MOSFETs 10 and 20 are simplified as controllable resistors, and it should be noted that each represents the resistance value of the drain-source path of the semiconductor elements 10 and 20. Since each midpoint terminal 35 of the circuits of the three phases P1, P2, and P3 is electrically connected to the motor 50, the inverter 30 is configured to supply the three-phase AC voltage Uac to the motor 50 in this way.

[0025] The apparatus according to the present invention is here configured as an ASIC and further includes an evaluation unit 60 connected to a first gate driver 70 and a second gate driver 75 using information processing technology. The gate drivers 70 and 75 are each electrically connected to the corresponding semiconductor elements 10 and 20. It should be noted that the circuits of the second phase P2 and the third phase P3 are configured in the same manner, but their gate drivers and each electrical connection are omitted for reasons of clarity.

[0026] The inverter 30 according to the invention is not continuously electrically connected to the battery 40, and the battery 40 is configured to supply a DC voltage Ubat to the inverter 30. The evaluation unit 60 is configured to connect with an external charging device 80 using information processing technology as soon as the charging device 80 is electrically connected to the battery 40 via a charging cable (not shown).

[0027] Based on the above configuration, the evaluation unit 60 is configured to identify a charge request for the battery 40 output in the form of a signal from the charging device 80, and, if there is a charge request for the battery 40, to adjust the gate voltage of the first semiconductor element 10 by the first gate driver 10 and / or the gate voltage of the second semiconductor element 20 by the second gate driver 20 so as to substantially interrupt the flow of current between the battery 40 and the electromachine 50 during the charging of the battery 40.

[0028] To reduce the voltage load on the drain-source paths of semiconductor elements 10 and 20, the adjusted gate voltages are set so that the resistance values ​​(or the drain-source voltages dropping through these paths) of the drain-source path of the first semiconductor element 10 are matched with respect to the second semiconductor element 20 as closely as possible, while simultaneously reducing the voltage load on the gate oxide films of semiconductor elements 10 and 20 by approximating each gate voltage to 0V as closely as possible.

[0029] Voltage measurements are performed to determine the basis for adjusting each gate voltage, and the voltage deviation between the first semiconductor switch 10 and the second semiconductor switch 20 is identified. For this purpose, a first voltage applied across the series circuit of the inverter 30 is identified on the one hand, and a second voltage representing the voltage of the first phase P1 is identified on the other hand. The individual voltage sensors are not shown here for the sake of clarity of the display.

[0030] Advantageously, since the semiconductor elements 10 and 20 are alternately controlled for opening and closing, the voltage load on each individual semiconductor element 10 and 20 decreases over time. To match the drain-source voltage, the range in which each gate voltage is adjusted is limited to a negative range up to a predetermined threshold, where the threshold voltage of semiconductor elements 10 and 20 is 1V below.

[0031] Figure 2 is a circuit diagram illustrating an exemplary phase voltage measurement according to the present invention. For clarity, only the first semiconductor element 10 of the inverter 30 according to the present invention is shown in Figure 2, but the inverter 30 further includes a second semiconductor element 20 arranged in series with the first semiconductor element 10.

[0032] Furthermore, a known configuration is shown in which the temperature of the first semiconductor element 10 is measured by an NTC resistor 100 that is thermally coupled to the first semiconductor element 10. The NTC resistor 100 is usually powered for this purpose by a current source 110, so that the voltage drop across the NTC resistor 100 can be detected by an analog-to-digital converter 90.

[0033] The capacitor 120, connected in parallel with the NTC resistor 100, is provided exemplarily for voltage filtering and overvoltage protection. According to the present invention, the known configuration described above is extended by a high resistance 130 (e.g., at the level of 1 megaohm), which, together with the NTC resistor 100, constitutes a voltage divider connected in parallel with the first semiconductor element 10 (in this case, a MOSFET), thus configured to perform DC link voltage measurement of the inverter 30.

[0034] Furthermore, according to the present invention, an evaluation unit 60 is provided which receives voltage values ​​detected by the analog-to-digital converter 90 and controls the semiconductor elements 10 and 20 according to the present invention based on these voltage values ​​and information regarding the current temperature of the NTC resistor 100. Information regarding the current temperature of the NTC resistor 100 can be determined, for example, based on temperature sensors of adjacent phases and / or based on temperature sensors that measure the temperature of the cooling water circuit for cooling the semiconductor elements 10 and 20. Furthermore, the evaluation unit 60 is configured to deactivate the power supply 110 during the charging mode of the battery 40 coupled to the inverter 30 and to measure the phase voltage using the NTC resistor 100.

Claims

1. A method for reducing voltage loads on semiconductor devices (10, 20) of an inverter (30), comprising: - determining the requirements for charging a battery (40) of an electrical system comprising at least one battery (40), an inverter (30) and an electric machine (50), said inverter (30) being based on at least one series circuit made up of at least one first semiconductor element (10) and a second semiconductor element (20) and converting a DC voltage (Ubat) supplied by said battery (40) into an AC voltage (Uac) suitable for said electric machine (50) and supplying said electric machine (50); adjusting the gate voltage of the first semiconductor element (10) and / or the gate voltage of the second semiconductor element (20) so as to substantially interrupt the flow of current between the battery (40) and the electric machine (50) during charging of the battery (40), - by lowering the gate voltages of the first semiconductor element (10) and the second semiconductor element (20), the voltage load on the gate oxide of each of the semiconductor elements (10, 20) is reduced; and / or - the voltage loads of the drain-source paths of each of said semiconductor elements (10, 20) are matched to one another; A method comprising:

2. 2. The method of claim 1, wherein the drain-source voltages of the first semiconductor device (10) and the second semiconductor device (20) are consistently set to approximately the same value during charging of the battery (40).

3. the first semiconductor element (10) and the second semiconductor element (20) are each alternately switched between a conductive mode and a non-conductive mode during charging of the battery (40); - only one of said two semiconductor elements (10, 20), respectively, is in a conductive mode, while the other of said two semiconductor elements (10, 20), respectively, is in a non-conductive mode; the total time of each of the two semiconductor elements (10, 20) in the conduction mode during charging of the battery (40) is approximately the same; The method of claim 1.

4. 2. The method of claim 1, wherein the gate voltages of the first semiconductor element (10) and the second semiconductor element (20) are set to or close to 0V to reduce the voltage load on the gate oxides of the semiconductor elements (10, 20).

5. 2. The method of claim 1, wherein the gate voltages of the first semiconductor element (10) and the second semiconductor element (20) are adjusted to match the voltage load of the drain-source path of each of the semiconductor elements (10, 20) within a voltage range extending exclusively from a negative gate voltage value up to a predetermined threshold value, the predetermined threshold value being below a threshold voltage of each of the semiconductor elements (10, 20).

6. 2. The method of claim 1, wherein the inverter (30) comprises a plurality of series circuits of at least one first semiconductor device (10) and a second semiconductor device (20), each series circuit configured to control a respective phase of a polyphase electric machine (50), and wherein the voltage loads of all of the semiconductor devices (10, 20) are reduced and / or matched during charging of the battery (40).

7. 2. The method of claim 1, wherein each gate voltage is adjusted based on a first voltage measurement representative of a total voltage drop across the at least one series circuit of at least two semiconductor elements (10, 20) and based on a second voltage measurement representative of a voltage drop across the semiconductor element (10, 20) on a low potential side of the series circuit.

8. 8. The method according to claim 7, wherein the voltage drop across the semiconductor element (10, 20) on the low potential side is determined based on a measurement of an NTC resistor provided for temperature detection of the semiconductor element (10, 20) and on an estimated temperature of the semiconductor element (10, 20).

9. 2. The method of claim 1, wherein the matching of the voltage load of each semiconductor element (10, 20) is performed taking into account existing degradation of each semiconductor element (10, 20) identified based on variations in gate voltage.

10. A device for reducing the voltage load of semiconductor elements (10, 20) of an inverter (30), comprising: a first semiconductor element (10), a second semiconductor element (20), an evaluation unit (60), The evaluation unit (60) - identifying a requirement for charging the battery (40) of an electrical system having at least one battery (40), the inverter (30) and an electric machine (50), the inverter (30) being based on at least one series circuit consisting of at least one first semiconductor element (10) and a second semiconductor element (20), converting a DC voltage (Ubat) supplied from the battery (40) into an AC voltage (Uac) suitable for the electric machine (50) and supplying it to the electric machine (50); - adjusting the gate voltage of the first semiconductor element (10) and / or the gate voltage of the second semiconductor element (20) so as to substantially interrupt the flow of current between the battery (40) and the electric machine (50) during charging of the battery (40); - by lowering the gate voltages of the first semiconductor element (10) and the second semiconductor element (20), the voltage load on the gate oxide of each of the semiconductor elements (10, 20) is reduced; and / or the voltage loads of the drain-source paths of each of said semiconductor elements (10, 20) are matched to one another; The apparatus is configured to: