X-ray image acquisition device and x-ray image acquisition system

Abstract

To provide an X-ray image acquisition device and system configured to simplify the configuration and reduce circuit scale while implementing TDI operation even when the number of pixel portions is increased.SOLUTION: An X-ray image acquisition device comprises: a pixel unit comprising M pixel arrays each including N pixel portions (N and M are integers of two or more); M circuit units; and a control unit. Each of the circuit units comprises: T (T is an integer of N or more) adders for sequentially adding electric signals corresponding to output signals from the N pixel portions; and a switch portion for switching a connection state between the N pixel portions and the T adders. The control unit switches the connection state in synchronism with the transfer of an object along a first direction so that the electric signals corresponding to the output signals output from the pixel portions in response to detection of an X-ray that has passed through the same region of the object are added in the same adder.SELECTED DRAWING: Figure 32

Description

Technical Field

[0001] One aspect of the present disclosure relates to an X-ray image acquisition device and an X-ray image acquisition system.

Background Art

[0002] An X-ray image acquisition device for acquiring an X-ray image of an object being conveyed is known (see, for example, Patent Document 1). For example, in the inspection device described in Patent Document 1, a TDI (Time Delay Integration) operation that was conventionally realized using a CCD (Charge Coupled Device) sensor is now realized using a CMOS (Complementary Metal Oxide Semiconductor) sensor. This X-ray image acquisition device includes detection means configured by arranging a plurality of line sensors each including a plurality of detection elements, and storage means for storing digital signals output from each detection element, and realizes the TDI operation by performing an addition operation in the storage means.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the inspection device described in Patent Document 1, depending on the number of detection elements, the speed of the addition operation in the storage means may not meet the requirements, and there is a risk that the TDI operation cannot be realized. In addition, for the X-ray image acquisition device as described above, simplification of the configuration and reduction of the circuit scale are required.

[0005] Therefore, one aspect of this disclosure is to provide an X-ray image acquisition apparatus and an X-ray image acquisition system that can achieve TDI operation even when the number of pixels increases, while also simplifying the configuration and reducing the circuit size. [Means for solving the problem]

[0006] An X-ray image acquisition apparatus according to one aspect of the present disclosure is an X-ray image acquisition apparatus for acquiring an X-ray image of an object being transported along a first direction, comprising: a pixel unit having M (M is an integer of 2 or more) pixel arrays, each containing N (N is an integer of 2 or more) pixel units for detecting X-rays, the N pixel units being arranged along a first direction, and the M pixel arrays being arranged along a second direction orthogonal to the first direction; M circuit units provided corresponding to the M pixel arrays; and a control unit for controlling the M circuit units. Each unit has T (T is an integer greater than or equal to N) summing units that sequentially add electrical signals corresponding to the output signals from N pixel units of a corresponding pixel array, and a switch unit that switches the connection state between the N pixel units and the T summing units. The control unit switches the connection state between the N pixel units and the T summing units in synchronization with the transport of the object along a first direction, so that for each of the M circuit units, the electrical signals corresponding to the output signals output from the pixel units when X-rays that have passed through the same area of ​​the object are detected are added in the same summing unit.

[0007] In this X-ray image acquisition device, each of the M circuit units has T adders and a switch unit. In each of the M circuit units, the connection state between N pixel units and T adders is switched in synchronization with the transport of the object along a first direction, so that the electrical signals corresponding to the output signals output from the pixel units when X-rays transmitted through the same area of ​​the object are detected are added in the same adder unit, thereby realizing TDI operation. By realizing TDI operation through addition processing in the circuit units in this way, the problem of the speed of addition calculations in the storage means described above can be avoided, and TDI operation can be realized even when the number of pixel units increases. In addition, memory such as the storage means described above can be omitted, and the configuration can be simplified. Furthermore, in this X-ray image acquisition device, TDI operation is realized by switching the connection state between the pixel units and adders using a switch unit. This reduces the size of the circuit compared to, for example, the case where a memory for simply adding signals is provided in the circuit unit. Therefore, with this X-ray image acquisition device, TDI operation can be realized even when the number of pixel units increases, and the configuration can be simplified and the size of the circuit can be reduced.

[0008] An X-ray image acquisition apparatus according to one aspect of this disclosure further comprises at least one scintillator that converts X-rays transmitted through an object into scintillation light, and N pixel units may receive the scintillation light converted by at least one scintillator. In this case, X-rays can be converted into scintillation light and detected.

[0009] Each of the T summing units may be an analog-to-digital converter (A / D converter). In this case, TDI operation can be achieved using the A / D converter.

[0010] Each of the T summing units may be a charge amplifier. In this case, TDI operation can be achieved using charge amplifiers.

[0011] A gap of at least twice the width of the pixel may be left between the pixel unit and the M circuit units. In this case, the incidence of X-rays on the circuit units, which have lower X-ray resistance compared to the pixel unit, can be suppressed.

[0012] An X-ray image acquisition apparatus according to one aspect of this disclosure further comprises a shielding member that is impermeable to X-rays, the shielding member having an opening, the pixel unit facing the opening, and the M circuit units may face portions of the shielding member other than the opening. In this case, it is possible to allow X-rays to enter the pixel unit while suppressing the entry of X-rays into the circuit unit.

[0013] The X-ray image acquisition apparatus of the present invention further comprises N × M wires electrically connected to N pixel portions of each of M pixel arrays and M circuit units, and each of the N × M wires may extend so as to pass over the N pixel portions. In this case, the N wires are not concentrated between the M pixel arrays arranged in the second direction, and the localization of dead zones can be avoided.

[0014] Each of the N×M wirings has a main body extending from the circuit unit to the pixel section, and an extension extending from the connection point between the main body and the pixel section toward the opposite side of the circuit unit, and the extension may be electrically isolated from the main body. In this case, the aperture ratio of the N pixel sections can be made uniform, and the generation of parasitic capacitance caused by the extension can be suppressed.

[0015] The control unit controls M circuit units such that the electrical signals corresponding to the output signals from L pixel units arranged in a first direction are added in the adder unit, and then the electrical signals are read out from the adder unit. The value of L may be selectable from an integer between 1 and N. In this case, the number of pixel units to be added can be selected according to, for example, the amount of X-ray leakage or the thickness of the object.

[0016] The control unit controls the M circuit units such that an electrical signal is read out from the addition unit after electrical signals corresponding to output signals from the pixel units from the P-th to the Q-th (P < Q) in the first direction are added in the addition unit, and the values of P and Q may be selectable from integers between 1 and N. In this case, for example, it can correspond to variations in the positional relationship between the X-ray source and the pixel unit.

[0017] The addition unit has a first addition unit and a second addition unit. The control unit controls the M circuit units such that an electrical signal is read out from the first addition unit after electrical signals corresponding to output signals from the pixel units located in the first region in the first direction are added in the addition unit, and an electrical signal is read out from the addition unit after electrical signals corresponding to output signals from the pixel units located in the second region aligned with the first region in the first direction are added in the second addition unit. In this case, for example, a dual mode can be realized, and multiple X-ray images can be acquired in one process.

[0018] In the first direction, when the side where the first addition unit is located with respect to the second addition unit is the first side, and the side where the second addition unit is located with respect to the first addition unit is the second side, the first addition unit may be arranged on the first side with respect to the first region, and the second addition unit may be arranged on the second side with respect to the second region. In this case, the lengths of the wirings connecting the pixel units located in the first region and the first addition unit, and the wirings connecting the pixel units located in the second region and the second addition unit can be reduced.

[0019] The exposure time of each of the N pixel units may be controlled independently of the conveyance of the object. The external signal used for synchronization with the conveyance of the object may include jitter (fluctuation), and if the exposure time of the pixel unit is associated with such an external signal, there is a concern that variations will occur in the exposure time. On the other hand, by controlling the exposure time of each of the N pixel units independently of the conveyance of the object, the exposure times of the N pixel units can be made uniform.

[0020] The on / off of the line delay function can be changed. When the line delay function is on, the exposure start timings of the N pixel units may be shifted by a predetermined time according to the order of the N pixel units in the first direction. In this case, the line delay function can be realized and the synchronization position in the height direction can be changed.

[0021] N may be an integer of 8 or more. According to this X-ray image acquisition device, even when the number of pixel units is large in this way, the TDI operation can be realized, and the configuration can be simplified and the circuit scale can be reduced.

[0022] The X-ray image acquisition system according to one aspect of the present disclosure includes the above X-ray image acquisition device, an X-ray source that outputs X-rays, and a transport unit that transports an object along the first direction. According to this X-ray image acquisition system, for the reasons described above, even when the number of pixel units increases, the TDI operation can be realized, and the configuration can be simplified and the circuit scale can be reduced.

Effect of the Invention

[0023] According to one aspect of the present disclosure, it is possible to provide an X-ray image acquisition device and an X-ray image acquisition system that can realize the TDI operation even when the number of pixel units increases, and can simplify the configuration and reduce the circuit scale.

Brief Description of the Drawings

[0024] [Figure 1] It is a plan view of the image sensor of the embodiment. [Figure 2] It is a diagram showing the circuit configuration of the pixel array and the circuit unit. [Figure 3] It is a diagram showing the circuit configuration of the amplifier array. [Figure 4] It is a diagram showing the circuit configuration of the switch array. [Figure 5] It is a diagram showing the circuit configuration of the memory array. [Figure 6] It is a diagram showing the circuit configuration of the ADC array. [Figure 7] This is a timing chart showing the operation of the image sensor in the embodiment. [Figure 8] This is a timing chart showing the operation of the image sensor in the embodiment. [Figure 9] This is a timing chart showing the operation of the image sensor in the embodiment. [Figure 10] This diagram illustrates the operation of TDI (Transmission Distributed Initiative). [Figure 11] This diagram illustrates the operation of TDI (Transmission Distributed Initiative). [Figure 12] This is a circuit diagram illustrating charge transfer in a comparative example. [Figure 13] This is a circuit diagram illustrating charge transfer in an embodiment. [Figure 14] This figure shows the circuit configuration of the pixel array and circuit unit of the first modified example. [Figure 15] This figure shows the circuit configuration of the pixel array and amplifier array in the second modified example. [Figure 16] This figure shows the circuit configuration of the switch array in the second modified example. [Figure 17] This is a timing chart showing the operation of the image sensor in the second modified example. [Figure 18] This is a timing chart showing the operation of the image sensor in the second modified example. [Figure 19] This figure shows the circuit configuration of the pixel array and circuit unit of the third modified example. [Figure 20] This figure shows the circuit configuration of the switch array in the third modified example. [Figure 21] This figure shows the circuit configuration of the amplifier array in the third modified example. [Figure 22] This figure shows the circuit configuration of the switch array in the third modified example. [Figure 23] This is a timing chart showing the operation of the image sensor in the third modified example. [Figure 24] This is a timing chart showing the operation of the image sensor in the third modified example. [Figure 25]This is a timing chart showing the operation of the image sensor in the third modified example. [Figure 26] This is a diagram illustrating the TDI operation of the third modified example. [Figure 27] This is a diagram illustrating the TDI operation of the third modified example. [Figure 28] This figure shows the circuit configuration of the pixel array and circuit unit of the fourth modified example. [Figure 29] This is a timing chart showing the operation of the image sensor in the fourth modified example. [Figure 30] This is a timing chart showing the operation of the image sensor in the fourth modified example. [Figure 31] This is a configuration diagram of the X-ray image acquisition device according to the second embodiment. [Figure 32] This is a plan view of the image sensor of the second embodiment. [Figure 33] This is a diagram illustrating the TDI operation of the second embodiment. [Figure 34] This is a diagram illustrating the TDI operation of the second embodiment. [Figure 35] This diagram illustrates the TDI operation when switching the number of added frames. [Figure 36] (a) and (b) are diagrams illustrating the function for switching the number of added frames. [Figure 37] (a) and (b) are diagrams illustrating the function for switching the number of added frames. [Figure 38] This diagram illustrates the TDI operation when switching the addition range. [Figure 39] This diagram illustrates the TDI operation when switching the addition range. [Figure 40] (a) and (b) are diagrams illustrating the function of switching the addition range. [Figure 41] This is a diagram to explain dual mode. [Figure 42] This diagram illustrates TDI operation in dual mode. [Figure 43] This diagram illustrates TDI operation in dual mode. [Figure 44] This is a diagram illustrating other configuration examples for dual mode. [Figure 45] This diagram illustrates the TDI operation when the addition direction is reversed. [Figure 46] This diagram illustrates the TDI operation when the addition direction is reversed. [Figure 47] This diagram illustrates another example of TDI operation when the addition direction is reversed. [Figure 48] This diagram illustrates the independent control of exposure time. [Figure 49] This is a diagram to explain the line delay function. [Figure 50] This is a diagram to explain the line delay function. [Modes for carrying out the invention]

[0025] Embodiments of this disclosure will be described in detail below with reference to the drawings. In the following description, the same or equivalent elements will be denoted by the same reference numerals, and redundant descriptions will be omitted. [First Embodiment] [Image sensor configuration]

[0026] The image sensor 1 shown in Figure 1 is a solid-state image sensor used, for example, in an X-ray imaging device for acquiring an X-ray image of an object being transported along the transport direction. In an X-ray imaging device, for example, X-rays transmitted through the object are converted into scintillation light by a scintillator, and the X-ray image of the object is acquired by detecting this scintillation light with the image sensor 1. In this process, a TDI (Time Delay Integration) operation is performed using the image sensor 1 to improve the signal-to-noise ratio in the acquired image. The TDI operation will be described later.

[0027] As shown in Figure 1, the image sensor 1 comprises a pixel unit 2, a circuit unit 3, and a decoder 4. The pixel unit 2, the circuit unit 3, and the decoder 4 are formed on a single chip and are integrated with each other. The pixel unit 2 has M pixel arrays 12, each containing N pixel units 11 (where N is an integer of 2 or more) that perform photoelectric conversion. Each pixel unit 11 is formed, for example, in a rectangular shape in a plan view. The N pixel units 11 are arranged in a row adjacent to each other along a first direction X1. The M pixel arrays 12 are arranged adjacent to each other along a second direction X2 that is orthogonal to the first direction X1. The A-th pixel unit 11 (where A is any integer between 1 and N) of the M pixel arrays 12 is arranged along the second direction X2. In other words, in the pixel unit 2, N × M pixel units 11 are arranged in a matrix.

[0028] As described above, when used in an X-ray image acquisition device, the image sensor 1 is positioned so that the first direction X1 coincides with the transport direction of the object. N may be an integer of 8 or more, or an integer of 16 or more. The larger N is, the better the signal-to-noise ratio can be improved by TDI operation. The following explanation will use the case where N is 4 as an example, but the same applies to other values ​​of N.

[0029] Each pixel 11 is composed of, for example, a photodetector capable of detecting scintillation light. In this example, the photodetector is a photodiode made of silicon, but it may also be a photodiode made of a compound semiconductor such as InGaAs or CdTe. In this example, the photodetector is a surface-type photodiode with the PN junction exposed on the surface, but it may also be an embedded-type photodiode with the PN junction embedded inside.

[0030] The circuit section 3 comprises M circuit units 5, each corresponding to one of the M pixel arrays 12. In this example, the M circuit units 5 are each electrically connected to one of the M pixel arrays 12. Specifically, the N pixel sections 11 of each of the M pixel arrays 12 and the M circuit units 5 are electrically connected by N × M wirings 6. That is, the N pixel sections 11 of one pixel array 12 are electrically connected to the corresponding circuit unit 5 by N wirings 6. Each wiring 6 extends linearly along a first direction X1, for example, passing over the pixel section 11.

[0031] As shown in Figure 2, each circuit unit 5 includes an amplifier array 30, a switch array (switch circuit, switch section) 40, a memory array 50, and an ADC (Analog-to-Digital converter) array 60. The configuration and operation of one circuit unit 5 and the corresponding pixel array 12 will be described below, but the configuration and operation of other circuit units 5 and pixel arrays 12 are similar. The four pixel sections 11 of the pixel array 12 will also be referred to as pixel sections PD1, PD2, PD3, and PD4, in order from furthest from the circuit unit 5.

[0032] As shown in Figure 3, the amplifier array 30 includes N (four in this example) charge amplifiers 31. Each charge amplifier 31 has an operational amplifier 32, a capacitance unit 33, and a reset switch 34. The capacitance unit 33 is a feedback capacitance and is connected between the inverting input terminal 32a and the output terminal 32c of the operational amplifier 32. The charge signal output from the pixel unit 11 is stored in the capacitance unit 33. The non-inverting input terminal 32b of the operational amplifier 32 is connected to a reference voltage Vref. The reset switch 34 is connected in parallel with the capacitance unit 33 between the inverting input terminal 32a and the output terminal 32c. The reset switch 34 is turned on and off according to the reset signal RS_A to reset the charge stored in the capacitance unit 33.

[0033] Each of the four charge amplifiers 31 is connected to one of the four pixel units 11 of the corresponding pixel array 12. More specifically, the charge signal from the pixel unit 11 is input to the inverting input terminal 32a of the operational amplifier 32. The charge amplifier 31 converts the charge signal output from the corresponding pixel unit 11 of the pixel array 12 into a voltage signal. Hereinafter, the charge amplifiers 31 that receive signals from the pixel units PD1, PD2, PD3, and PD4 will also be referred to as charge amplifiers CA1, CA2, CA3, and CA4, respectively. The voltage signal from the charge amplifiers 31 is output to the switch units SU1 to SU4, which will be described later, via the output terminal 32c.

[0034] As shown in Figure 4, the switch array 40 includes N (4 in this example) switch units 41. Each switch unit 41 includes four switches 42a, 42b, 42c, and 42d, each connected to one of the four charge amplifiers 31. The output signals from the switch units 41 are output to the memory units MR1 ​​to MR4, which will be described later. The switch array 40 is configured such that the connection state between the charge amplifiers CA1 to CA4 and the memory units MR1 ​​to MR4 switches according to the on / off state of switches 42a to 42d.

[0035] More specifically, in each switch unit 41, switch 42a is turned on and off according to switching signal SW1, switch 42b is turned on and off according to switching signal SW2, switch 42c is turned on and off according to switching signal SW3, and switch 42d is turned on and off according to switching signal SW4. The switch units 41 connected to memory units MR1, MR2, MR3, and MR4 are denoted as switch units SU1, SU2, SU3, and SU4, respectively. Figure 4 shows the output nodes SU1_OUT, SU2_OUT, SU3_OUT, and SU4_OUT of switch units SU1, SU2, SU3, and SU4.

[0036] When switching signal SW1 is ON and switching signals SW2~SW4 are OFF, charge amplifiers CA1, CA4, CA3, and CA2 are connected to memory units MR1, MR2, MR3, and MR4, respectively. When switching signal SW2 is ON and switching signals SW1, SW3, and SW4 are OFF, charge amplifiers CA2, CA1, CA4, and CA3 are connected to memory units MR1, MR2, MR3, and MR4, respectively. When switching signal SW3 is ON and switching signals SW1, SW2, and SW4 are OFF, charge amplifiers CA3, CA2, CA1, and CA4 are connected to memory units MR1, MR2, MR3, and MR4, respectively. When switching signal SW4 is ON and switching signals SW1~SW3 are OFF, charge amplifiers CA4, CA3, CA2, and CA1 are connected to memory units MR1, MR2, MR3, and MR4, respectively.

[0037] As shown in Figure 5, the memory array 50 contains N (4 in this example) memory units 51. The memory array 50 may also contain T (T is an integer greater than or equal to N) memory units 51. Each memory unit 51 has capacitors 52N, 52S, switches 53N, 53S, 54N, 54S, and a reset switch 55. Capacitor 52N holds the reference voltage (N level) in the voltage signal from the charge amplifier 31, and capacitor 52S holds the signal voltage (S level) in the voltage signal from the charge amplifier 31. The difference between the signal voltage and the reference voltage becomes the effective signal.

[0038] Switches 53N and 53S are used to switch the connection state between capacitors 52N and 52S and switch units SU1 to SU4, while switches 54N and 54S are used to switch the connection state between capacitors 52N and 52S and A / D converters AD1 to AD4, which will be described later. Switches 53N and 53S are turned on and off according to switching signals SETN1 and SETS1, and switches 54N and 54S are turned on and off according to switching signals SETN2 and SETS2.

[0039] The reset switch 55 is turned on and off according to the reset signal RS_M. When the reset switch 55 is turned on, the reset voltage VRS is supplied, and the voltages at the input terminals of the A / D converters AD1 to AD4 are reset. The memory array 50 is provided to reverse the signal transfer order because the voltage signals from the charge amplifier 31 are held in capacitors 52N and 52S in the order of S level, then N level, while the AD conversion by the ADC array 60 is in the order of N level, then S level. Hereinafter, the memory units 51 connected to the switch units SU1, SU2, SU3, SU4 (A / D converters AD1, AD2, AD3, AD4) will also be referred to as memory units MR1, MR2, MR3, and MR4, respectively. Figure 5 shows the output nodes MR1_OUT, MR2_OUT, MR3_OUT, and MR4_OUT of memory units MR1, MR2, MR3, and MR4.

[0040] As shown in Figure 6, the ADC array 60 includes N (4 in this example) A / D converters (adders) 61. The ADC array 60 may also include T (T is an integer greater than or equal to N) A / D converters 61. In this example, each A / D converter 61 is configured as a single-slope type and includes a comparator 62, a counter 63 with B bits (B is an integer greater than or equal to 1), B latch switches 64, and B capacitors 65. The comparator 62 compares the output signal from the memory unit 51 with the ramp wave VRAMP. The counter 63 outputs a count value in B bits corresponding to the output signal from the comparator 62. The latch switches 64 latch the counter value output from the counter 63. The capacitors 65 hold the count value output from the counter 63 according to the on / off state of the latch switches 64. The counter 63 operates based on the clock pulse CLK. The latch switches 64 operate according to the latch signal LS.

[0041] In the A / D converter 61, the output of the comparator 62 changes in accordance with the output signals from the memory units MR1 ​​to MR4 (charge signals from the pixel units PD1 to PD4 and voltage signals from the charge amplifiers CA1 to CA4), and the counter 63 counts in accordance with this change, thereby performing A / D conversion to convert the voltage signal into a digital value.

[0042] If the A / D converters 61 connected to memory units MR1, MR2, MR3, and MR4 are designated as A / D converters AD1, AD2, AD3, and AD4 respectively, then separate reset signals RS_C1, RS_C2, RS_C3, and RS_C4 are input to the counters 63 of A / D converters AD1, AD2, AD3, and AD4. This makes it possible to independently reset the counters 63 of A / D converters AD1 to AD4.

[0043] In each A / D converter 61, the counter 63 performs a count according to the received voltage signal and stores the count value. The counting performed by the counter 63 may be either count-up or count-down. Furthermore, the counter 63 uses the previously held count value as a reference and performs a count according to the next input voltage signal and stores that count value. In other words, each counter 63 performs a count sequentially each time a voltage signal is input and stores count values ​​corresponding to all input voltage signals (addition process).

[0044] The B capacitors 65 each hold a voltage signal (addition signal) corresponding to the holding state (addition state) of the count value in the corresponding counter 63. That is, whether the voltage signal in each capacitor 65 is held or not is determined according to the count value held in the corresponding counter 63. As a result, by reading the holding state of the voltage signals in the B capacitors 65, a digital signal corresponding to the count value held in the counter 63 can be obtained. Thus, in the A / D converter 61, the comparator 62 and the counter 63 function as an addition processing unit that performs addition processing of the voltage signals output from one of the charge amplifiers CA1 to CA4, and the B capacitors 65 function as a holding unit that holds an addition signal according to the addition state of the addition processing unit. The count value held in the counter 63 is reset by the input of reset signals RS_C1 to C4. The timing of reading the holding state of the voltage signals in the capacitors 65 is controlled by the decoder 4.

[0045] Referring again to Figure 1, the M circuit units 5 are arranged adjacent to (facing) the corresponding pixel array 12 in the first direction X1. Each circuit unit 5 has N arrangement regions R aligned in the second direction X2. Each of the arrangement regions R has one of the charge amplifiers 31, memory unit 51, and A / D converter 61 described above. The width of each arrangement region R in the second direction X2 is 1 / N or less of the width of the pixel section 11 in the second direction X2. That is, in the second direction X2, the combined width of the N arrangement regions R is less than or equal to the width of the pixel section 11. [TDI operation]

[0046] The TDI operation using the image sensor 1 will be explained with reference to Figures 7 to 9. In the timing chart of Figure 7, the time changes of the reset signal RS_A, the voltage signals from charge amplifiers CA1 to CA4, the switching signals SW1 to SW4, the switching signals SETN1, SETS1, SETN2, SETS2 and the reset signal RS_M, and the operating states of the A / D converters AD1 to AD4 are shown from top to bottom. In the operating states of the A / D converters AD1 to AD4, "A / D Convert: CA1" means that A / D conversion of the voltage signal from charge amplifier CA1 is being performed, and similarly, "A / D Convert: CA2 to CA4" means that A / D conversion of the voltage signals from charge amplifiers CA2 to CA4 is being performed. "H" means that the signal is held, and "0" means that the signal is reset. The waveforms of the voltage signals from charge amplifiers CA1 to CA4 are examples. These points are also the same for Figures 17, 18, 23, 24, 29, and 30 which will be described later. The timing chart in Figure 8 shows, from top to bottom, the operating states of A / D converters AD1 to AD4, as well as the time changes of the latch signal LS, reset signals RS_C1 to C4, and read signals D1 to D4. Read signals D1 to D4 are signals output from decoder 4 to control the timing of reading the voltage holding state at capacitor 65. When read signals D1, D2, D3, and D4 are turned on, the voltage holding state of capacitor 65 of A / D converters AD1, AD2, AD3, and AD4 is read out and converted into a digital value (digital signal) (Figure 2).

[0047] As shown in Figures 7 to 9, during the period between times T1 and T2, switching signal SW1 is turned on and switching signals SW2 to SW4 are turned off, and charge amplifiers CA1, CA4, CA3, and CA2 are connected to memory units MR1, MR2, MR3, and MR4, respectively. When voltage signals from charge amplifiers CA4, CA3, CA2, and CA1 (voltage signals corresponding to the charge signals output from pixel units PD4, PD3, PD2, and PD1) are input, counts are performed in A / D converters AD1, AD2, AD3, and AD4, respectively, and the count value is held. At time T2, read signal D1 is turned on, and the voltage state held in the capacitor 65 of A / D converter AD1 is read out and converted to a digital value. Before this readout, reset signal RS_C1 is input, and the counter 63 of A / D converter AD1 is reset.

[0048] During the period between times T2 and T3, the switching signal SW2 is turned on, while the switching signals SW1, SW3, and SW4 are turned off, and the charge amplifiers CA2, CA1, CA4, and CA3 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. Then, the voltage signals from the charge amplifiers CA1, CA4, CA3, and CA2 (voltage signals corresponding to the charge signals output from the pixel units PD1, PD4, PD3, and PD2) are input, and counts are performed in the A / D converters AD1, AD2, AD3, and AD4, respectively, and the count values ​​are held. At time T3, the read signal D2 is turned on, and the voltage state held in the capacitor 65 of the A / D converter AD2 is read out and converted to a digital value. Before this read out, the reset signal RS_C2 is input, and the counter 63 of the A / D converter AD2 is reset.

[0049] During the period between times T2 and T3, the voltage signals from the charge amplifiers 31, which were held in the capacities 52N and 52S of the memory unit 51 during the previous period between times T1 and T2, are transferred to the A / D converters AD1 to AD4 by switching the signals SETN1, SETS1, SETN2, and SETS2 on and off. Therefore, during the period between times T2 and T3, the A / D converters AD1, AD2, AD3, and AD4 perform counts corresponding to the voltage signals from the charge amplifiers CA1, CA4, CA3, and CA2 that were connected to the memory units MR1, MR2, MR3, and MR4 during the previous period between times T1 and T2, and perform A / D conversion. This is the same for other periods as well.

[0050] During the period between times T3 and T4, the switching signal SW3 is turned on, while the switching signals SW1, SW2, and SW4 are turned off, and the charge amplifiers CA3, CA2, CA1, and CA4 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. Then, the voltage signals from the charge amplifiers CA2, CA1, CA4, and CA3 (voltage signals corresponding to the charge signals output from the pixel units PD2, PD1, PD4, and PD3) are input, and counting is performed in the A / D converters AD1, AD2, AD3, and AD4, respectively. At time T4, the read signal D3 is turned on, and the voltage state held in the capacitor 65 of the A / D converter AD3 is read out and converted to a digital value. Before this readout, the reset signal RS_C3 is input, and the counter 63 of the A / D converter AD3 is reset.

[0051] During the period between times T4 and T5, the switching signal SW4 is turned on and the switching signals SW1 to SW3 are turned off, and the charge amplifiers CA4, CA3, CA2, and CA1 are connected to the memory units MR1, MR2, MR3, and MR4, respectively. Then, the voltage signals from the charge amplifiers CA3, CA2, CA1, and CA4 (voltage signals corresponding to the charge signals output from the pixel units PD3, PD2, PD1, and PD4) are input, and counting is performed in the A / D converters AD1, AD2, AD3, and AD4, respectively. At time T5, the read signal D4 is turned on, and the voltage state held in the capacitor 65 of the A / D converter AD4 is read out and converted to a digital value. Before this readout, the reset signal RS_C4 is input, and the counter 63 of the A / D converter AD4 is reset. The behavior during the periods T5 and T6, T6 and T7, T7 and T8, and T8 and T9 is the same as the behavior during the periods T1 and T2, T2 and T3, T3 and T4, and T4 and T5, respectively.

[0052] Through the above operation, the output signals from the N pixel units 11 are added together in a TDI manner. In the above example, continuous TDI-like addition is achieved by shifting the reset timing of the counters 63 in the A / D converters AD1 to AD4 by one frame each. One frame corresponds to the length of the period between times T1 and T2. In this addition process, the capacitors 65 (holding units) of the A / D converters AD1 to AD4, which hold the voltage signals corresponding to the charge signals output from the pixel units PD1 to PD4, are switched according to the order in which the pixel units PD1 to PD4 are arranged along the first direction X1. In other words, the switch array 40 switches the connection state between the charge amplifiers CA1 to CA4 and the capacitors 65 of the A / D converters AD1 to AD4 so that they switch in this manner.

[0053] Figures 10 and 11 are diagrams illustrating the addition process using TDI operation. Figures 10 and 11 show an example in which light (electromagnetic waves) from an object OJ being transported along the transport direction (first direction X1) is detected by the image sensor 1. When the object OJ is divided into regions a to j according to its position along the transport direction, as shown in Figures 10 and 11, the TDI operation detects light transmitted through the same region of the object OJ, and signals corresponding to the charge signals output from the pixel units PD1 to PD4 are input to the same A / D converters AD1 to AD4. For example, a signal based on the detection of light from region a is input to A / D converter AD1. Then, a voltage signal (4a) corresponding to the count value equivalent to the signal for 4 frames is held in the capacitor 65, and this voltage signal (4a) is read out as a digital value from the A / D converter AD1 at time T6. By obtaining a count value equivalent to the signal for N frames in this way, the signal-to-noise ratio in the acquired image can be improved. In TDI operation, the timing at which the switch array 40 switches the connection state between the charge amplifiers CA1-CA4 and the A / D converters AD1-AD4 is synchronized with the transport of the object OJ along the first direction X1 (e.g., transport speed). [Mechanism of Action and Effects]

[0054] In the image sensor 1, each of the M circuit units 5 has N charge amplifiers 31, N A / D converters 61, and a switch array 40 (switch circuit). In each circuit unit 5, the connection state between the charge amplifier 31 and the A / D converter 61's capacitor 65 (holding part), which holds the voltage signal (addition signal) corresponding to the charge signal output from the pixel unit 11, is switched according to the arrangement order of the N pixel units 11 along the first direction X1, thereby realizing TDI operation. By realizing TDI operation through addition processing using such A / D converters 61, it is possible to suppress the increase in circuit size compared to, for example, simply providing a memory for digitally adding signals in the circuit unit 5. Also, compared to, for example, outputting the signal outside the image sensor 1 and performing digital addition processing externally, the amount of output signal can be reduced. Furthermore, in the image sensor 1, the charge signal output from the pixel unit 11 is converted into a voltage signal by the charge amplifier 31, and this voltage signal is added by the A / D converter 61. This reduces the loss in the transfer of the charge signal from the pixel unit 11, enabling efficient TDI operation. Therefore, the image sensor 1 can achieve efficient TDI operation while suppressing an increase in circuit size and reducing the amount of output signal.

[0055] The reduction of loss in charge signal transfer from the pixel unit 11 will be explained with reference to Figures 12 and 13. Figure 12 is a circuit diagram illustrating charge transfer in a comparative example, and Figure 13 is a circuit diagram illustrating charge transfer in an embodiment. In the comparative example shown in Figure 12, the signal charge Q1 from the pixel unit is transferred to the integral capacitor C2 when the switch SW is turned on. In this case, if the capacitance on the pixel unit side (such as the capacitance of the photodiode) is C1, the voltage V2 at node 2 should be Q1 / C2 if the transfer is complete, but in reality it becomes Q1 / (C1+C2). Subsequently, even when the switch SW is turned off, the charge transferred to the integral capacitor C2 becomes Q1×C2 / (C1+C2), resulting in insufficient charge transfer (capacitance division).

[0056] On the other hand, as shown in Figure 13, when the charge amplifier 31 is connected to the pixel unit 11, the potential of node A does not change due to the signal charge Q from the pixel unit 11, and due to the effect of the virtual ground of the operational amplifier 32, the potential of node A remains at the same potential as the reference voltage Vref. Since the potential of node A does not change, the entire signal charge Q is stored in the capacitance unit 33, and the output voltage from the charge amplifier 31 becomes Q / Cf, which reduces the loss in the transfer of the charge signal. Cf is the capacitance of the capacitance unit 33.

[0057] Each A / D converter 61 is configured as a single-slope type. This enables efficient TDI operation with a simple configuration.

[0058] The switch array 40 is connected between the charge amplifier 31 and the comparator 62 (addition processing unit) of the A / D converter 61. This enables efficient TDI operation with a simple configuration.

[0059] The width of each arrangement region R in the second direction X2 is 1 / N or less of the width of the pixel portion 11 in the second direction X2. This allows for efficient arrangement of the circuit unit 5 and further suppresses the increase in circuit size.

[0060] Each pixel 11 includes a surface-type photodiode. This allows for a larger pixel area.

[0061] N is an integer greater than or equal to 8. When the number of pixels is large, the increase in circuit size and the increase in output signal amount tend to become problems, but with image sensor 1, even in such cases, it is possible to suppress the increase in circuit size and reduce the output signal amount while achieving efficient TDI operation. [Differentiation]

[0062] The image sensor 1 may be configured as in the first modified example shown in Figure 14. In the above embodiment, the entire image sensor 1 was formed on a single chip, but in the first modified example, the pixel unit 2, the circuit section 3, and the decoder 4 are formed on separate chips and are isolated from each other. During use, the pixel unit 2 is electrically connected to the circuit section 3 (amplifier array 30). Even with this first modified example, just like in the first embodiment, it is possible to achieve efficient TDI operation while suppressing an increase in circuit size and reducing the output signal amount.

[0063] The image sensor 1 may be configured as in the second modified example shown in Figures 15 to 18. In the second modified example, the light-receiving element of each pixel 11 is composed of an embedded photodiode. Each pixel 11 has a pixel amplifier 13 in addition to the light-receiving element. The pixel amplifier 13 has a capacitor 14, transistors 15 and 16, and a source follower amplifier 17. The capacitor 14 is, for example, a floating diffusion capacitor, which is a storage region formed on a semiconductor substrate. The signal charge from the light-receiving element is entirely transferred to the capacitor 14 and converted into a voltage. The transistor 15 is, for example, a MOS transistor, which controls the transfer of the signal from the light-receiving element to the capacitor 14. The transistor 16 is, for example, a MOS transistor, which controls the reset of the capacitor 14. The source follower amplifier 17 amplifies and outputs the voltage signal from the capacitor 14. The source follower amplifier 17 is connected to the charge amplifier 31 via a coupling capacitor 18. The output signal from the source follower amplifier 17 is converted into charge by the coupling capacitor 18, and then converted back into voltage by the charge amplifier 31. In Figure 15, Vr is the reset voltage of capacitor 14, Vb1 is the bias voltage, Vb2 is the reference voltage, TRAN is the transfer signal, and RS_P is the reset signal of capacitor 14.

[0064] In the second modification, as shown in Figure 16, the memory unit 51 has one capacitor 52 and one switch 53. In the second modification, the order in which the voltage signal from the charge amplifier 31 is held in the capacitor 52 is N level, then S level, which is the same as the order of AD conversion by the ADC array 60, so only one pair of capacitor 52 and switch 53 is provided. The switch 53 is turned on and off according to the switching signal SET.

[0065] Figures 17 and 18 are timing charts showing the operation of the image sensor 1 in the second modified example. In the second modified example as well, the switch array 40 switches the connection state between the charge amplifiers CA1 to CA4 and the capacitors 65 of the A / D converters AD1 to AD4 so that the capacitors 65 (holding part) of the A / D converters AD1 to AD4, which hold the voltage signals corresponding to the charge signals output from the pixel units PD1 to PD4, switch according to the arrangement of the pixel units PD1 to PD4 along the first direction X1.

[0066] This second modification, like the first embodiment described above, allows for efficient TDI operation while suppressing an increase in circuit size and reducing the output signal amount. Furthermore, since each pixel 11 includes an embedded photodiode, high sensitivity and low noise can be achieved.

[0067] The image sensor 1 may be configured as in the third modified example shown in Figures 19 to 27. In the third modified example, the light-receiving elements of each pixel section 11 are composed of surface-type photodiodes. As shown in Figure 19, each circuit unit 5 has a switch array (switch circuit) 40A, an amplifier array 30A, and a memory array 50A.

[0068] As shown in Figure 20, the switch array 40A is configured similarly to the switch array 40 of the first embodiment, except that it is connected between the pixel unit 11 and the amplifier array 30A. The switch array 40A is configured such that the connection state between the pixel units PD1 to PD4 and the capacitance unit 33 of the charge amplifiers CA1 to CA4 (adding unit) switches according to the on / off status of switches 42a to 42d.

[0069] As shown in Figure 21, the amplifier array 30A is connected between the switch units SU1 to SU4 and the memory units MR1 ​​to MR4. Separate reset signals RS_A1, RS_AC2, RS_A3, and RS_A4 are input to the reset switches 34 of the charge amplifiers CA1, CA2, CA3, and CA4. This makes it possible to independently reset the capacitive sections 33 of the charge amplifiers CA1 to CA. Except for these points, the amplifier array 30A is configured the same as the amplifier array 30 of the first embodiment described above.

[0070] As shown in Figure 22, voltage signals from charge amplifiers CA1 to CA4 are input to the memory array 50A. Output signals from memory units MR1 ​​to MR4 are read out using, for example, a differential amplifier. In memory unit MR1, switches 53N and 53S are turned on and off according to switching signals SETN1 and SETS1, and switches 54N and 54S are turned on and off according to read signal D1. In memory unit MR2, switches 53N and 53S are turned on and off according to switching signals SETN2 and SETS2, and switches 54N and 54S are turned on and off according to read signal D2. In memory unit MR3, switches 53N and 53S are turned on and off according to switching signals SETN3 and SETS3, and switches 54N and 54S are turned on and off according to read signal D3. In memory unit MR4, switches 53N and 53S are turned on and off according to switching signals SETN4 and SETS4, and switches 54N and 54S are turned on and off according to read signal D4. The memory array 50A does not have a reset switch 55 and is reset along with the reset of the differential amplifier described above. Except for these points, the memory array 50A is configured the same as the memory array 50 of the first embodiment described above.

[0071] In the third modified example, the M circuit units 5 are arranged adjacent to the corresponding pixel array 12 in the first direction X1, and each circuit unit 5 has N arrangement regions R aligned in the second direction X2. Each circuit unit 5 may also have T (where T is an integer greater than or equal to N) arrangement regions R. In the third modified example, one charge amplifier 31 and one memory unit 51 are arranged in each arrangement region R. The width of each arrangement region R in the second direction X2 is less than or equal to 1 / N of the width of the pixel portion 11 in the second direction X2.

[0072] Figures 23 to 25 are timing charts showing the operation of the image sensor 1 in the third modified example, and Figures 26 and 27 are diagrams for explaining the addition process by TDI operation in the third modified example. In the third modified example, the capacitance section 33 of the charge amplifiers CA1 to CA4, which store the charge signals output from the pixel sections PD1 to PD4, switches according to the arrangement of the pixel sections PD1 to PD4 along the first direction X1.

[0073] Specifically, as shown in Figures 23 and 24, the various components operate, and as shown in Figure 25, during the period between times T1 and T2, the charge signals output from the pixel units PD1, PD4, PD3, and PD2 are stored in the capacitance units 33 of the charge amplifiers CA1, CA2, CA3, and CA4, respectively. At time T2, the charge signals stored in the capacitance unit 33 of charge amplifier CA2 are read out. During the period between times T2 and T3, the charge signals output from the pixel units PD2, PD1, PD4, and PD3 are stored in the capacitance units 33 of the charge amplifiers CA1, CA2, CA3, and CA4, respectively. At time T3, the charge signals stored in the capacitance unit 33 of charge amplifier CA3 are read out. During the period between times T3 and T4, the charge signals output from the pixel units PD3, PD2, PD1, and PD4 are stored in the capacitance units 33 of the charge amplifiers CA1, CA2, CA3, and CA4, respectively. At time T4, the charge signal stored in the capacitance section 33 of charge amplifier CA4 is read out. During the period between times T4 and T5, the charge signals output from the pixel sections PD4, PD3, PD2, and PD1 are stored in the capacitance sections 33 of charge amplifiers CA1, CA2, CA3, and CA4, respectively. At time T5, the charge signal stored in the capacitance section 33 of charge amplifier CA1 is read out.

[0074] As shown in Figures 26 and 27, in the TDI operation of the third modified example, when light transmitted through the same region of object OJ is detected, the charge signals output from pixel units PD1 to PD4 are added (stored) as analog values ​​in the same charge amplifiers CA1 to CA4. For example, the signal based on the detection of light from region a is added in charge amplifier CA1. Then, the charge signal (4a) obtained by adding the signals for 4 frames is read out from charge amplifier CA1 at time T5.

[0075] This third modification also enables efficient TDI operation while suppressing an increase in circuit size and reducing the output signal amount. Specifically, in the image sensor 1 of the third modification, each of the M circuit units 5 has N charge amplifiers 31 and a switch array 40A (switch circuit). In each circuit unit 5, the connection state between the pixel unit 11 and the charge amplifier 31 is switched so that the capacitance unit 33 of the charge amplifier 31, where the charge signals output from the pixel unit 11 are accumulated (added as charge (analog value)), switches according to the arrangement order of the N pixel units 11 along the first direction X1, thereby realizing TDI operation. By realizing TDI operation through analog summing using such charge amplifiers 31, it is possible to suppress an increase in circuit size compared to, for example, the case where a memory for simply digitally summing signals is provided in the circuit unit 5. Furthermore, it is possible to reduce the output signal amount compared to, for example, the case where the signal is output outside the image sensor 1 and digital summing is performed externally. Furthermore, in the image sensor 1, the charge signal output from the pixel section 11 is stored in the capacitance section 33 of the charge amplifier 31, added together in an analog manner, and converted into a voltage signal by the charge amplifier 31. This reduces the loss in the transfer of the charge signal from the pixel section 11, enabling efficient TDI operation. Therefore, even with the third modified image sensor 1, efficient TDI operation can be achieved while suppressing an increase in circuit size and reducing the amount of output signal.

[0076] Furthermore, since the width of each arrangement region R in the second direction X2 is 1 / N or less of the width of the pixel portion 11 in the second direction X2, the circuit unit 5 can be efficiently arranged, and the increase in circuit size can be further suppressed. In the third modified example, a memory section having only one memory unit 51 may be provided instead of the memory array 50, and a shift register may be provided instead of the decoder 4. In this case as well, TDI operation can be realized. However, by using a memory array 50 having N memory units 51 as in the third modified example and performing reading with the decoder 4, it becomes possible to change the number of frames added.

[0077] As a fourth modification, in the third modification described above, the light-receiving elements of each pixel section 11 may be configured with embedded photodiodes. In the fourth modification, as shown in Figure 28, similar to the second modification, each pixel section 11 has a pixel amplifier 13 in addition to a light-receiving element. Each pixel section 11 is connected to a switch unit 41 via a coupling capacitor 18. A switch 19, which is turned on and off according to a reset signal RS_S, is provided between the coupling capacitor 18 and the switch unit 41. The charge signal generated by the light-receiving element is converted into a voltage signal by a source follower amplifier 17. This voltage signal is converted into a charge signal via the coupling capacitor 18. Figure 28 shows PD1, PD2, PD3, and PD4 as outputs from the pixel section 11. The image sensor 1 of the fourth modification operates according to the timing charts shown in Figures 29 and 30. With this fourth modification, as with the third modification described above, it is possible to achieve efficient TDI operation while suppressing an increase in circuit size and reducing the amount of output signal.

[0078] This disclosure is not limited to the first embodiment and its modifications described above. For example, the pixel unit 11 may be any unit that performs photoelectric conversion and may be used to detect infrared rays or X-rays, not just visible light. In the first embodiment, the A / D converter 61 is not limited to a single-slope type. The A / D converter 61 may convert an input voltage signal into a digital value and sequentially add the digital values. In the first embodiment, the switch array 40 may be connected between the comparator 62 and the counter 63 of the A / D converter 61. Even in this case, the switch array 40 can switch the connection state between the charge amplifiers CA1 to CA4 and the capacitors 65 of the A / D converters AD1 to AD4.

[0079] In the first embodiment described above, the count was calculated according to the signals for four frames and the count value was read out as a digital value. However, the number of frames to be added can be changed by changing the timing of the reset signals RS_C1~C4 input to the counters 63 of the A / D converters AD1~AD4 and the read signals D1~D4 from the decoder 4. In the third and fourth modified examples, as with the first modified example, the pixel unit 2, the circuit section 3, and the decoder 4 may be formed on separate chips. [Second Embodiment]

[0080] The X-ray image acquisition system 100 shown in Figure 31 is a system for acquiring an X-ray image of an object OJ being transported along a first direction X1. The X-ray image acquisition system 100 comprises an X-ray source 101, a transport unit 102, and an X-ray image acquisition device 110. The X-ray image acquisition device 110 comprises an image sensor 120 and a control unit 130.

[0081] The X-ray source 101 emits X-rays. A slit member 103 is positioned in front of the X-ray source 101 to define the irradiation range of the X-rays from the X-ray source 101. The transport unit 102 is, for example, a belt conveyor, and the object OJ placed on the belt is transported along the first direction X1 by the rotation of the belt. The transport path by the transport unit 102 is set to pass through the irradiation range of the X-rays from the X-ray source 101. As an example, the object OJ is food, and the X-ray image acquisition system 100 is used to inspect whether or not foreign matter is mixed into the object OJ.

[0082] As shown in Figures 1 and 2, the image sensor 120 comprises a pixel unit 2 and a circuit unit 3. Although not shown, the image sensor 120 also comprises the decoder 4 described above. The circuit unit 3 comprises M circuit units 5, each corresponding to M pixel arrays 12. Each circuit unit 5 includes an amplifier array 30, a switch array (switch unit) 40, a memory array 50, and an ADC array 60. The image sensor 120 is configured similarly to the image sensor 1 of the first embodiment, except for the points described below.

[0083] In the image sensor 120, the width DS of the gap 105, which is the portion between the pixel unit 2 and the circuit unit 3 in the first direction X1, is at least twice the width of the pixel unit 11 in the first direction X1. In other words, there is a gap of at least twice the width of the pixel unit 11 between the pixel unit 2 and the M circuit units 5. The gap DS may be at least five times the width of the pixel unit 11. The gap DS is, for example, about 2 mm.

[0084] The X-ray image acquisition device 110 further includes a scintillator 104 positioned above the pixel unit 2 (between the pixel unit 2 and the transport unit 102). The scintillator 104 converts X-rays transmitted through the object OJ into scintillation light. Each pixel 11 of the image sensor 120 receives and detects the scintillation light converted by the scintillator 104.

[0085] The X-ray image acquisition apparatus 110 further includes a shielding member 106 positioned between the image sensor 120 and the transport unit 102. The shielding member 106 has a main body portion 106a made of, for example, lead, which is impermeable to X-rays (shielding). A slit (opening) 106b is formed in the main body portion 106a. The shielding member 106 is arranged such that the pixel unit 2 faces the slit 106b, and the M circuit units 5 face the main body portion 106a (the part of the shielding member 106 other than the slit 106b). As a result, X-rays output from the X-ray source 101 toward the pixel unit 2 pass through the slit 106b, and X-rays output from the X-ray source 101 toward the circuit unit 5 are shielded by the shielding member 106. The shielding member 106 may also cover the gap portion 105 in the image sensor 120. In other words, the gap 105 may face the main body 106a of the shielding member 106.

[0086] In the image sensor 120, the N pixel units 11 of each of the M pixel arrays 12 and the M circuit units 5 are electrically connected by N × M wires 6. Each wire 6 extends linearly along a first direction X1 so as to pass over the pixel units 11. Each wire 6 has a main body 6a that extends linearly from the circuit unit 5 to the pixel unit 11, and an extension 6b that extends linearly from the connection point CP between the main body 6a and the pixel unit 11 to the opposite side of the circuit unit 5 (the left side in Figure 32). In this example, the extension 6b is electrically isolated from the main body 6a. That is, the main body 6a electrically connects the pixel units 11 and the circuit units 5 to each other.

[0087] The control unit 130 is composed of, for example, a computer including a processor (CPU) and recording media such as RAM and ROM. The control unit 130 is electrically connected to the X-ray source 101, the transport unit 102, and the image sensor 120, and controls the operation of the X-ray source 101, the transport unit 102, and the image sensor 120. Note that separate control units may be provided to control the X-ray source 101, the transport unit 102, and the image sensor 120. [TDI operation]

[0088] The TDI operation in the X-ray image acquisition system 100 will be explained with reference to Figures 33 and 34. This TDI operation is realized by the control unit 130 controlling each part. The following explanation will use the case where N is 8 as an example, but the same applies when N is any other value. The eight pixel units 11 provided in one pixel array 12 are designated as pixel units PD1 to PD8 according to their arrangement in the first direction X1, and the A / D converters 61 that convert the voltage signals corresponding to the charge signals from the pixel units PD1, PD2, PD3, PD4, PD5, PD6, PD7, and PD8 into digital values ​​are designated as adders AN1, AN2, AN3, AN4, AN5, AN6, AN7, and AN8, respectively.

[0089] In this TDI operation, as in the first embodiment described above, the switch array 40 switches the connection state between the charge amplifier 31 and the A / D converter 61 (between the pixel units PD1-PD8 and the adders AN1-AN8) so that the adders AN1-AN8, which perform counting according to the electrical signals (voltage signals) corresponding to the output signals (charge signals) output from the pixel units PD1-PD8, switch according to the arrangement of the pixel units PD1-PD8 along the first direction X1. As a result, the electrical signals (voltage signals) corresponding to the output signals (charge signals) output from the pixel units PD1-PD8, which are detected when light transmitted through the same area of ​​the object OJ is detected, are added in the same adders AN1-AN8.

[0090] For example, as shown in Figure 34, during the period between times T2 and T3, the electrical signals corresponding to the output signals from the pixel unit PD1 are added together in the adder unit AN1. During the period between times T3 and T4, the electrical signals corresponding to the output signals from the pixel units PD1 and PD2 are added together in the adders units AN2 and AN1, respectively. During the period between times T4 and T5, the electrical signals corresponding to the output signals from the pixel units PD1, PD2, and PD3 are added together in the adders units AN3, AN2, and AN1, respectively. During the period between times T5 and T6, the electrical signals corresponding to the output signals from the pixel units PD1, PD2, PD3, and PD4 are added together in the adders units AN4, AN3, AN2, and AN1, respectively. The addition process continues sequentially at subsequent times, and at time T10, the voltage signal (8a) obtained by adding the signals for 8 frames is read out from the adder unit AN1 and converted into a digital value. Thus, in this example, the signals for 8 frames are added together and obtained. The data output from the X-ray image acquisition device 110 may be the digital signal itself converted to a digital value (addition), or it may be the average value obtained by dividing the sum of the digital values ​​by the number of frames (averaging). The calculation method may be selectable from addition and averaging.

[0091] In this TDI operation, the timing at which the switch array 40 switches the connection state between the pixel units PD1 to PD8 and the adder units AN1 to AN8 is synchronized with the transport of the object OJ along the first direction X1 (e.g., transport speed). For example, the control unit 130 may generate a periodic line signal synchronized with the transport of the object OJ. In this case, the control unit 130 controls the switching timing by the switch array 40 based on the line signal and causes the image sensor 120 to perform the TDI operation. Alternatively, the control unit 130 may receive an external synchronization signal generated by an element other than the control unit 130. In this case, the control unit 130 controls the switching timing by the switch array 40 based on the synchronization signal and causes the image sensor 120 to perform the TDI operation. Such a synchronization signal can be generated, for example, by an encoder provided in the transport unit 102. The transport speed is, for example, about 10 m / min to 60 m / min. [Mechanism of Action and Effects]

[0092] In the X-ray image acquisition device 110, each of the M circuit units 5 has N A / D converters 61 (adding units) and a switch array 40 (switching unit). In each circuit unit 5, the connection state between the N pixel units 11 and the N A / D converters 61 is switched in synchronization with the transport of the object OJ along the first direction X1, so that the electrical signals (voltage signals) corresponding to the output signals (charge signals) output from the pixel units 11 when X-rays that have passed through the same area of ​​the object OJ are detected are added in the same A / D converter 61. This realizes TDI operation. By realizing TDI operation through the addition process in the circuit unit 5 in this way, the problem of the speed of addition calculations in the storage means described above can be avoided, and TDI operation can be realized even when the number of pixel units 11 increases. In addition, memory such as the storage means described above can be omitted, and the configuration can be simplified. Furthermore, in the X-ray image acquisition device 110, TDI operation is realized by switching the connection state between the pixel units 11 and the A / D converters 61 using the switch array 40. This allows for a reduction in circuit size compared to, for example, simply providing a memory in the circuit unit 5 for digitally adding signals. Therefore, the X-ray image acquisition device 110 enables TDI operation even when the number of pixels 11 increases, while also simplifying the configuration and reducing the circuit size. Furthermore, by adding signals through TDI operation, the signal-to-noise ratio (S / N ratio) in the acquired image can be improved. Such TDI operation is particularly effective when the output of the X-ray source 101 is reduced to reduce X-ray leakage and extend the lifespan of the X-ray source 101. This is because when the output of the X-ray source 101 is reduced, the signal amount decreases, which can lead to a decrease in the S / N ratio. In addition, since the addition process is performed within the image sensor 120, the number of wires for external connections can be reduced, and as a result, it becomes possible to achieve a multi-row system with small pixels.Furthermore, in the case of digital addition operations in the storage means described above, data recording, calculation, and erasure must be repeatedly performed, placing a heavy load on the computer. In contrast, the X-ray image acquisition device 110 performs data storage in the addition unit by switching using the switch array 40, thus reducing the load on the computer (control unit 130). As mentioned above, the ADC array 60 may include T (T is an integer greater than or equal to N) A / D converters 61. That is, each circuit unit 5 may have T A / D converters 61 (adding units). Even in this case, TDI operation can be performed in the same manner as in the above embodiment.

[0093] N pixel units 11 receive scintillation light converted by the scintillator 104. This allows X-rays to be converted into scintillation light and detected.

[0094] The summing unit is comprised of an A / D converter 61. This allows TDI operation to be achieved using the A / D converter 61.

[0095] A gap DS of more than twice the width of the pixel section 11 is left between the pixel unit 2 and the M circuit units 5. This makes it possible to suppress the incidence of X-rays on the circuit units 5, which have lower X-ray resistance compared to the pixel unit 2.

[0096] The pixel unit 2 faces the slit 106b of the shielding member 106, and the M circuit units 5 face the main body portion 106a of the shielding member 106 (the portion of the shielding member 106 other than the slit 106b). This allows for the incidence of X-rays to the pixel unit 2 while suppressing the incidence of X-rays to the circuit units 5.

[0097] Each of the N×M wirings 6 extends over N pixel sections 11. This prevents the N wirings 6 from converging between M pixel arrays 12 aligned in the second direction X2, thus avoiding the localization of dead zones.

[0098] Each of the N x M wirings 6 has a main body 6a extending from the circuit unit 5 to the pixel section 11, and an extended portion 6b extending from the connection point CP between the main body 6a and the pixel section 11 toward the opposite side from the circuit unit 5, with the extended portion 6b being electrically isolated from the main body 6a. This makes it possible to equalize the aperture ratio of the N pixel sections 11 and to suppress the generation of parasitic capacitance caused by the extended portion.

[0099] N is an integer greater than or equal to 8. According to the X-ray image acquisition device 110, even when the number of pixel units 11 is large, TDI operation can be realized, and the configuration can be simplified and the circuit size reduced. [Differentiation]

[0100] As a fifth modification, the X-ray image acquisition device 110 may have a function to switch the number of summation frames (the number of pixel units 11 that perform the summation process). In the examples shown in Figures 33 and 34, signals for 8 frames (all frames) were added and acquired, meaning the number of summation frames was 8, but the number of summation frames may be selectable from 1 to N. More specifically, the control unit 130 may control each circuit unit 5 so that the electrical signals corresponding to the output signals from L pixel units 11 arranged in the first direction X1 are added in the A / D converter 61, and then converted into digital signals by the A / D converter 61 and read out. The value of L can be selected from an integer between 1 and N. The value of L may be set to 0. In other words, the X-ray image acquisition device 110 may have a mode in which no summation process is performed.

[0101] Figure 35 is a diagram illustrating the TDI operation when switching the number of summation frames. Figure 35 shows an example where L is 4. The "*" in Figure 35 indicates that any state is possible. That is, in the case of "*", it may be in a reset state, or it may not be connected to the summation units AN1 to AN8. Alternatively, it may be connected to the summation units AN1 to AN8, and if, for example, the signal has been read out, it may be in any state thereafter. This point is also true for Figures 38, 39, and 46 which will be described later.

[0102] As shown in Figure 35, during the period between times T5 and T6, the electrical signals corresponding to the output signals from pixel units PD1, PD2, PD3, and PD4 are added together in adders AN4, AN3, AN2, and AN1, respectively. During the period between times T6 and T7, the electrical signals corresponding to the output signals from pixel units PD1, PD2, PD3, and PD4 are added together in adders AN5, AN4, AN3, and AN2, respectively, and pixel unit PD5 is in a reset state. During the period between times T7 and T8, the electrical signals corresponding to the output signals from pixel units PD1, PD2, PD3, and PD4 are added together in adders AN6, AN5, AN4, and AN3, respectively, and pixel units PD5 and PD6 are in a reset state. At time T6, the voltage signal (4a) obtained by adding the signals from 4 frames is read out from adder AN1 and converted into a digital value. Thus, in this example, the signals from 4 frames are added together and obtained as a digital value.

[0103] This fifth modification also enables TDI operation even when the number of pixel units 11 increases, similar to the second embodiment described above, while also simplifying the configuration and reducing the circuit size. Furthermore, the number of pixel units 11 that perform the addition process can be selected according to, for example, the amount of X-ray leakage or the thickness of the object.

[0104] This will be described while referring to FIGS. 36 and 37. As shown in FIGS. 36(a) and 36(b), the irradiation of the object OJ with X-rays may be performed inside the shielding box 140 in order to suppress the leakage of X-rays. The wider the X-ray irradiation range is, the easier it is for X-rays to leak from the shielding box 140, and it is necessary to enhance the shielding property of the shielding box 140. In FIG. 36(b), the X-ray irradiation range is wider and the X-ray leakage amount is larger than in FIG. 36(a). Here, when the number of added frames is increased, the S / N ratio can be improved, but it is necessary to widen the X-ray irradiation range, resulting in an increase in the X-ray leakage amount. In this regard, according to the fifth modification example, by having the function of switching the number of added frames, it is possible to select the number of added frames in consideration of the balance between the improvement of the S / N ratio and the X-ray leakage amount.

[0105] As shown in FIGS. 37(a) and 37(b), when the X-ray source 101 is a point source, the X-rays are irradiated onto the object OJ with a spread in the transport direction (the first direction X1). In FIG. 37(b), the spread range of the X-rays is wider than in FIG. 37(a). Since the object OJ has a thickness, perspective occurs due to the difference in the incident angle of the X-rays, and for example, the position passing through the object OJ between the central pixel portion 11 and the end pixel portion 11 is different. When perspective occurs, blurring may occur in the image. When it is necessary to suppress such blurring, it is effective to reduce the number of added frames and narrow the X-ray irradiation range. Thus, according to the fifth modification example, it is possible to select the number of added frames according to the thickness of the object OJ.

[0106] As a sixth modification example, the X-ray image acquisition device 110 may have a function of switching the addition range (the range of the pixel portion 11 where addition processing is performed). More specifically, the control unit 130 may control each circuit unit 5 such that after the electrical signals corresponding to the output signals from the pixel portions 11 from the P-th to the Q-th (P < Q) in the first direction X1 are added in the A / D converter 61, they are read out as digital values from the A / D converter 61. The values of P and Q are selected from the integers from 1 to N.

[0107] 51>Figures 38 and 39 illustrate the TDI operation when switching the addition range. Figure 38 shows an example where P is 3 and Q is 6. The "-" in Figure 38 indicates a clear state. This is also true for Figures 39 and 44, which will be discussed later.

[0108] As shown in Figure 38, during the period between times T4 and T5, the electrical signals corresponding to the output signals from pixel unit PD3 are added in adder unit AN1, and pixel units PD1 and PD2 are in a reset state. During the period between times T5 and T6, the electrical signals corresponding to the output signals from pixel units PD3 and PD4 are added in adders AN2 and AN1, respectively, and pixel units PD1 and PD2 are in a reset state. During the period between times T6 and T7, the electrical signals corresponding to the output signals from pixel units PD3, PD4, and PD5 are added in adders AN3, AN2, and AN1, respectively, and pixel units PD1 and PD2 are in a reset state. During the period between times T7 and T8, the electrical signals corresponding to the output signals from pixel units PD3, PD4, PD5, and PD6 are added in adders AN4, AN3, AN2, and AN1, respectively, and pixel units PD1 and PD2 are in a reset state. During the period between times T8 and T9, the electrical signals corresponding to the output signals from pixel units PD3, PD4, PD5, and PD6 are added together in adders AN5, AN4, AN3, and AN2, respectively, while pixel units PD1, PD2, and PD7 are in a reset state. At time T8, the voltage signal (4a) obtained by adding the signals for 4 frames is read out as a digital value from adder AN1.

[0109] Figure 39 shows an example where P is 5 and Q is 8. As shown in Figure 38, during the period between times T6 and T7, the electrical signals corresponding to the output signals from pixel unit PD5 are added in adder unit AN1, and pixel units PD1 to PD4 are in a reset state. During the period between times T7 and T8, the electrical signals corresponding to the output signals from pixel units PD5 and PD6 are added in adders AN2 and AN1, respectively, and pixel units PD1 to PD4 are in a reset state. During the period between times T8 and T9, the electrical signals corresponding to the output signals from pixel units PD5, PD6, and PD7 are added in adders AN3, AN2, and AN1, respectively, and pixel units PD1 to PD4 are in a reset state. At time T10, the voltage signal (4a) obtained by adding the signals for 4 frames is read out as a digital value from adder unit AN1.

[0110] This sixth modification also enables TDI operation even when the number of pixel units 11 increases, similar to the second embodiment described above, while also simplifying the configuration and reducing the circuit size. Furthermore, it can accommodate variations in the positional relationship between the X-ray source 101 and the pixel unit 2, for example.

[0111] This point will be explained with reference to Figure 40. When the image sensor 120 is incorporated into the X-ray image acquisition system 100, variations may occur in the positional relationship between the X-ray source 101 and the image sensor 120 (pixel unit 2). Figures 40(a) and 40(b) show how this positional relationship differs. When this positional relationship differs, the X-ray irradiation range will differ. In contrast, according to the sixth modified example, variations in the positional relationship between the X-ray source 101 and the pixel unit 2 can be accommodated by switching the addition range. Adding signals from the pixel section 11 that is not irradiated with X-rays increases noise, but according to the X-ray image acquisition device 110 of the sixth modified example, by switching the addition range, it is possible to adjust the device to add signals only from the pixel section 11 that receives X-rays, thereby suppressing the increase in noise.

[0112] As a seventh modification, the X-ray image acquisition device 110 may include a dual mode in addition to the normal mode as an operating mode. In this case, for example, as shown in Figure 41, the X-ray image acquisition device 110 may include a scintillator 104A positioned above the pixel units PD1 to PD4 and a scintillator 104B positioned above the pixel units PD5 to PD8 as the scintillator 104.

[0113] Scintillator 104A converts high-energy (first energy) X-rays into scintillation light, and scintillator 104B converts low-energy (second energy, lower than the first energy) X-rays into scintillation light. Scintillators 104A and 104B may, for example, have different thicknesses or be made of different materials. Pixel portions PD1 to PD4 are pixel portions 11 located in the first region RG1 in the first direction X1, and detect scintillation light from scintillator 104A. Pixel portions PD5 to PD8 are pixel portions 11 located in the second region RG2, which is continuous with the first region RG1, in the first direction X1, and detect scintillation light from scintillator 104B. The electrical signals corresponding to the output signals from pixel units PD1 to PD4 are added in adders AN1 to AN4 (first adder), and the electrical signals corresponding to the output signals from pixel units PD5 to PD8 are added in adders AN5 to AN8 (second adder). In this case, the image output from the X-ray image acquisition device 110 is separated into two regions, for example, a first region RG1 and a second region RG2.

[0114] In dual mode, the control unit 130 controls M circuit units such that the electrical signals corresponding to the output signals from pixel units PD1 to PD4 located in the first region RG1 are added in the adders AN1 to AN4 and then read out from the adders AN1 to AN4, and the electrical signals corresponding to the output signals from pixel units PD5 to PD8 located in the second region RG2 are added in the adders AN5 to AN8 and then read out from the adders AN5 to AN8. This enables TDI operation in both the first region RG1 and the second region RG2.

[0115] Figures 42 and 43 illustrate the TDI operation in dual mode. As shown in Figure 43, during the period between times T6 and T7, the electrical signals corresponding to the output signals from the pixel units PD1, PD2, PD3, PD4, and PD5 are added together in the adders AN1, AN4, AN3, AN2, and AN5, respectively. During the period between times T7 and T8, the electrical signals corresponding to the output signals from the pixel units PD1, PD2, PD3, PD4, PD5, and PD6 are added together in the adders AN2, AN1, AN4, AN3, AN6, and AN5, respectively. During the period between times T8 and T9, the electrical signals corresponding to the output signals from the pixel units PD1, PD2, PD3, PD4, PD5, PD6, and PD7 are added together in the adders AN3, AN2, AN1, AN4, AN7, AN6, and AN5, respectively. At time T10, the voltage signals (4e, 4a) obtained by adding the signals from 4 frames are converted to digital values ​​by the adders AN1 and AN5, respectively, and read out. In this example, the signals from 4 frames are added and acquired for each of the first region RG1 and the second region RG2.

[0116] Even with this seventh modification, as with the second embodiment described above, TDI operation can be achieved even when the number of pixel units 11 increases, and the configuration can be simplified and the circuit size reduced. Furthermore, dual mode can be realized, and multiple X-ray images can be acquired in a single process. Dual mode (dual energy) also has the following advantages. In conventional non-destructive testing using X-rays, material and foreign objects are detected by the difference in density of the X-ray transmission image. However, actual objects have complex shapes with uneven surfaces, or various materials are densely packed inside, resulting in uneven X-ray transmission, making it difficult to distinguish foreign objects by density alone. In contrast, dual mode allows for the simultaneous acquisition of two images of high and low energy using a single X-ray source 101. Since different materials have different absorption rates depending on the energy intensity, it becomes possible to distinguish materials by processing these two images. Note that, not limited to the horizontal arrangement as in the example described above, a vertical arrangement in which the pixel units 2 (pixel units 11) are arranged vertically may also be adopted. In this case, for example, the upper pixel unit 2 detects scintillation light based on high-energy X-rays, and the lower pixel unit 2 detects scintillation light based on low-energy X-rays. Dual mode can also be achieved with this configuration.

[0117] In the example shown in Figure 41, the first region RG1 and the second region RG2 were continuous, but the first region RG1 and the second region RG2 only need to be aligned in the first direction X1, and there may be a gap between the first region RG1 and the second region RG2. In this case, there may be an air gap between the first region RG1 and the second region RG2, or a shielding member may be placed there. Alternatively, scintillators 104A may be placed above the pixel sections PD1 to PD3 (pixel sections 11 located in the first region), and scintillators 104B may be placed above the pixel sections PD6 to PD8 (pixel sections 11 located in the second region), and a shielding member may be placed or a gap may be formed above the pixel sections PD4 and PD5 (pixel sections 11 located in the region between the first and second regions). A dead zone wider than the width of the pixel section 11 may be provided between the pixel sections PD4 and PD5. In this case, signal interference can be suppressed.

[0118] In the seventh modified example, the adders AN1-AN4 (first adder) and AN5-AN8 (second adder) may be arranged as shown in Figure 44. In this example, if, in the first direction X1, the side on which adders AN1-AN4 are located relative to adders AN5-AN8 (the left side in Figure 44) is defined as the first side, and the side on which adders AN5-AN8 are located relative to adders AN1-AN4 (the right side in Figure 44) is defined as the second side, then adders AN1-AN4 are arranged on the first side with respect to the first region RG1, and adders AN5-AN8 are arranged on the second side with respect to the second region RG2. In this case, the length of the wiring connecting the pixel units PD1-PD4 located in the first region RG1 and adders AN1-AN4, and the length of the wiring connecting the pixel units PD5-PD8 located in the second region RG2 and adders AN4-AN8 can be reduced.

[0119] As an eighth modification, the X-ray image acquisition device 110 may have a function to reverse the addition direction. By having a function to reverse the addition direction, it is possible to handle cases where the object OJ is transported in the opposite direction to the transport direction in the second embodiment described above. Even when the addition direction is reversed, the connection state between the pixel units PD1 to PD8 and the adder units AN1 to AN8 is switched in synchronization with the transport of the object OJ along the first direction X1, so that the electrical signals corresponding to the output signals output from the pixel units PD1 to PD8 when X-rays that have passed through the same area of ​​the object OJ are detected are added in the same adder units AN1 to AN8.

[0120] Figures 45 and 46 illustrate the TDI operation when the addition direction is reversed. In the example shown in Figures 45 and 46, signals from 8 frames (all frames) are added together and acquired. During the period between times T2 and T3, the electrical signals corresponding to the output signals from the pixel unit PD8 are added in the adder AN1. During the period between times T3 and T4, the electrical signals corresponding to the output signals from the pixel units PD8 and PD7 are added in the adders AN2 and AN1, respectively. During the period between times T4 and T5, the electrical signals corresponding to the output signals from the pixel units PD8, PD7, and PD6 are added in the adders AN3, AN2, and AN1, respectively. During the period between times T5 and T6, the electrical signals corresponding to the output signals from the pixel units PD8, PD7, PD6, and PD5 are added in the adders AN4, AN3, AN2, and AN1, respectively. The addition process is carried out sequentially at subsequent time points, and at time T10, the voltage signal (8j) obtained by adding the signals for 8 frames is converted to a digital value by the adder AN1 and read out.

[0121] Figure 47 illustrates another example of TDI operation when the addition direction is reversed. In the example in Figure 47, signals from four frames are added together and acquired. Between times T5 and T6, the electrical signals corresponding to the output signals from pixel units PD8, PD7, PD6, and PD5 are added together in adders AN4, AN3, AN2, and AN1, respectively. Between times T6 and T7, the electrical signals corresponding to the output signals from pixel units PD8, PD7, PD6, and PD5 are added together in adders AN5, AN4, AN3, and AN2, respectively, and pixel unit PD4 is in a reset state. Between times T7 and T8, the electrical signals corresponding to the output signals from pixel units PD8, PD7, PD6, and PD5 are added together in adders AN6, AN5, AN4, and AN3, respectively, and pixel units PD3 and PD4 are in a reset state. At time T6, the voltage signal (4j) obtained by adding together the signals from four frames is converted to a digital value in adder AN1 and read out. In this example, the signals from four frames are added together and obtained.

[0122] As a ninth modification, the control unit 130 may control the exposure time of each pixel unit 11 independently of the transport of the object OJ. Figure 48 is a diagram illustrating the independent control of exposure time. As shown in Figure 48, the external synchronization signal used for synchronization with the transport of the object OJ may contain jitter (fluctuations). If the exposure time of the pixel unit 11 is associated with such a synchronization signal, variations in exposure time may occur. In contrast, by controlling the exposure time of each pixel unit 11 (each frame) independently of the transport of the object OJ, the exposure times of the N pixel units 11 can be made uniform. With this ninth modification, as with the second embodiment, TDI operation can be achieved even when the number of pixel units 11 increases, and the configuration can be simplified and the circuit size reduced. The exposure time can be controlled by a dedicated control signal or by setting in a sensor setting storage device.

[0123] As a tenth modification, the X-ray image acquisition device 110 may have a line delay function. Figure 49 is a diagram illustrating the line delay function. When the line delay function is on, the exposure start timing of the N pixel units 11 is shifted by a predetermined time TS × U (where U is an integer of 1 or more) according to the arrangement of the N pixel units 11 in the first direction X1. Figure 49 shows the case where U is 1. The predetermined time TS is set to a time that is sufficiently shorter than the exposure time of the pixel unit 11 (for example, 100 msec). With this tenth modification, as with the second embodiment described above, TDI operation can be achieved even when the number of pixel units 11 increases, and the configuration can be simplified and the circuit size reduced. In addition, by having a line delay function, the synchronization position in the height direction can be changed.

[0124] This point will be explained with reference to Figure 50. When the X-ray source 101 is a point source, the image of the object OJ is magnified and projected according to the magnification L2 / L1 = C2 / C1. C1 is the distance between the X-ray source 101 and the object OJ (FOD), and C2 is the distance between the X-ray source 101 and the image sensor 120 (FDD). L1 is the length along the transport direction (first direction X1) corresponding to the distance C1, and L2 is the length along the transport direction corresponding to the distance C2. The image acquisition speed to be set for the image sensor 120 is determined by the product of the transport speed and the magnification. In other words, strictly speaking, the image sensor 120 is only fully speed-synchronized and additively synchronized at one specific height position. The image acquisition speed to be set for the image sensor 120 differs strictly depending on the transport speed and the height position (magnification) to which synchronization is desired. This difference can be adjusted by the line delay function. For example, if it is controlled based on an external synchronization signal, the line rate cannot be changed, but the synchronization position can be changed by changing the predetermined time TS. When the line delay function is enabled, the exposure start timing is delayed for later frames, resulting in a later image acquisition timing compared to normal operation. This means that the image is synchronized to a state where the object OJ is moving faster (traveling a greater distance). A faster speed corresponds to a higher magnification. In other words, the larger the line delay amount (predetermined time TS × U), the higher the synchronization height plane.

[0125] This disclosure is not limited to the embodiments and modifications described above. For example, in the second embodiment or the fifth to tenth modifications, the image sensor 120 may be configured in the same manner as in the third modification. In this case, the summing units AN1 to AN8 are composed of charge amplifiers 31. That is, in the second embodiment, the summing units AN1 to AN8, which add electrical signals (voltage signals) corresponding to the output signals (charge signals) output from the pixel units PD1 to PD8, were A / D converters 61, but the summing units AN1 to AN8 may be charge amplifiers 31. In this case, the charge amplifiers 31 store (add) the output signals (charge signals) themselves output from the pixel units PD1 to PD8 in the capacitance unit 33. Thus, the "electrical signals corresponding to the output signals output from the pixel units" that are added in the summing unit may be the output signals themselves. When the summing unit is a charge amplifier 31, the signals are added in charge state, so readout noise that occurs when reading out the charge occurs only once, and readout noise can be reduced. Furthermore, since the configuration can be achieved by switching connections to the integrating capacitor and using a minimum number of A / D converters, power consumption can be reduced. In addition, some scintillators 104 are susceptible to high-temperature environments due to the constraints of their glass transition point, and the increase in heat generation when multiple rows are used can be a problem. However, by configuring the summing section with a charge amplifier 31, the amount of heat generated can be reduced, thus addressing this problem. The summing sections AN1 to AN8 may be integrating capacitors provided in the circuit unit 5. In this case, the circuit unit 5 does not need to be provided with a charge amplifier 31 and an A / D converter 61.

[0126] In the second embodiment described above, the extended portion 6b of each wiring 6 was electrically isolated from the main body 6a, but the extended portion 6b of each wiring 6 may be electrically connected to the main body 6a, for example, at the connection point CP. In this case, the wiring capacitance of the N wirings 6 connected to one circuit unit 5 can be made uniform. The scintillator 104 may be omitted. In this case, for example, the pixel portion 11 is configured as a direct conversion type detector that converts incident X-rays directly into electrical signals without converting them into light.

[0127] The X-ray image acquisition device 110 may have a non-additive mode that outputs a signal obtained by converting the electrical signals output from the pixel units PD1 to PD8 into digital values ​​without performing addition or averaging calculations. In this case, the data output from the X-ray image acquisition device 110 will be a two-dimensional image of N × M pixels. Such an X-ray image acquisition device 110 can be used for axial alignment with the light source or for checking the delay of the line delay function. [Explanation of symbols]

[0128] 1,120…Image sensor, 2…Pixel unit, 5…Circuit unit, 6…Wiring, 6a…Main unit, 6b…Extended unit, 11,PD1~PD8…Pixel unit, 12…Pixel array, 31,CA1~CA4…Charge amplifier (adding unit), 40,40A…Switch array (switching unit), 61,AD1~AD4…A / D converter (adding unit), 100…X-ray image acquisition system, 101…X-ray source, 102…Transport unit, 1 04, 104A, 104B...Scintillator, 106...Shielding member, 106a...Main body (parts other than the slit), 106b...Slit (opening), 110...X-ray image acquisition device, 120...Image sensor, 130...Control unit, AN1~AN8...Adding unit (first adding unit, second adding unit), CP...Connection point, DS...Spacing, OJ...Object, RG1...First region, RG2...Second region, X1...First direction, X2...Second direction.

Claims

1. 1. An X-ray image acquisition device for acquiring an X-ray image of an object transported along a first direction, comprising: a pixel unit including M pixel arrays (M is an integer of 2 or more) each including N pixel units (N is an integer of 2 or more) for detecting X-rays, the N pixel units being aligned along the first direction, and the M pixel arrays being aligned along a second direction perpendicular to the first direction; M circuit units provided corresponding to the M pixel arrays; A control unit that controls the M circuit units, Each of the M circuit units is T (T is an integer equal to or greater than N) adders that sequentially add electrical signals corresponding to output signals from the N pixel units of the corresponding pixel array; A switch unit that switches a connection state between the N pixel units and the T adder units, An X-ray image acquisition device, wherein each of the T adding units is an A / D converter.

2. 1. An X-ray image acquisition device for acquiring an X-ray image of an object transported along a first direction, comprising: a pixel unit including M pixel arrays (M is an integer of 2 or more) each including N pixel units (N is an integer of 2 or more) for detecting X-rays, the N pixel units being aligned along the first direction, and the M pixel arrays being aligned along a second direction perpendicular to the first direction; M circuit units provided corresponding to the M pixel arrays; A control unit that controls the M circuit units, Each of the M circuit units is T (T is an integer equal to or greater than N) adders that sequentially add electrical signals corresponding to output signals from the N pixel units of the corresponding pixel array; A switch unit that switches a connection state between the N pixel units and the T adder units, An X-ray image acquisition device, wherein each of the T adder units is a charge amplifier.

3. 3. The X-ray image acquisition device according to claim 1, wherein a distance equal to or greater than twice the width of the pixel portion is provided between the pixel unit and the M circuit units.

4. The pixel array further includes N×M wirings electrically connected to the N pixel units of each of the M pixel arrays and the M circuit units; 4. The X-ray image acquisition device according to claim 1, wherein each of the N×M wirings extends so as to pass over the N pixel units.

5. 5. The X-ray image acquisition device of claim 4, wherein each of the N×M wirings has a main body portion extending from the circuit unit to the pixel portion and an extension portion extending from a connection point between the main body portion and the pixel portion to the opposite side of the circuit unit, and the extension portion is electrically isolated from the main body portion.

6. the control unit controls the M circuit units such that the electrical signals corresponding to the output signals from the L pixel units arranged in the first direction are added in the adder unit and then the electrical signals are read out from the adder unit; 6. The X-ray image acquisition device according to claim 1, wherein the value of L can be selected from integers between 1 and N inclusive.

7. the control unit controls the M circuit units such that the electrical signals corresponding to the output signals from the P-th to Q-th pixel units (P<Q) in the first direction are added in the adder unit, and then the electrical signals are read out from the adder unit; 6. The X-ray image acquisition device according to claim 1, wherein the values ​​of P and Q can be selected from integers between 1 and N inclusive.

8. the adder unit includes a first adder unit and a second adder unit, The X-ray image acquisition device of any one of claims 1 to 5, wherein the control unit controls the M circuit units so that the electrical signals corresponding to the output signals from the pixel units located in a first region in the first direction are added in the first adder and then the electrical signals are read out from the first adder, and the electrical signals corresponding to the output signals from the pixel units located in a second region aligned with the first region in the first direction are added in the second adder and then the electrical signals are read out from the adder.

9. In the first direction, a side where the first adder is located relative to the second adder is defined as a first side, and a side where the second adder is located relative to the first adder is defined as a second side. The X-ray image acquisition device according to claim 8 , wherein the first adder is disposed on the first side with respect to the first region, and the second adder is disposed on the second side with respect to the second region.

10. 10. The X-ray image acquisition device according to claim 1, wherein an exposure time of each of the N pixel units is controlled independently of a transport of the object.

11. The line delay function can be turned on and off. An X-ray image acquisition device as described in any one of claims 1 to 10, wherein when the line delay function is on, the exposure start timing of the N pixel units is shifted by a predetermined time in accordance with the arrangement order of the N pixel units in the first direction.

12. The X-ray image acquisition device according to any one of claims 1 to 11, wherein N is an integer of 8 or more.

13. An X-ray image acquisition device according to any one of claims 1 to 12, An X-ray source that outputs X-rays; a conveying unit that conveys the object along the first direction.

Images