Thin-film transistor device and method of manufacturing the same

Abstract

To reduce a circuit area.SOLUTION: A first semiconductor layer includes a first channel region and first source / drain regions sandwiching the first channel region. A second semiconductor layer includes a second channel region and second source / drain regions sandwiching the second channel region. A metal contact part is located in a hole extending through one or more upper insulating layers and one or more lower insulating layers, and in contact with one of the first source / drain regions and one of the second source / drain regions. A diameter of the hole at the lowermost layer in the one or more upper insulating layers is larger than a diameter of the hole at the uppermost layer in the one or more lower insulating layers.The metal contact part is made of a same metal material as source / drain lines of a first thin-film transistor and a second thin-film transistor.SELECTED DRAWING: Figure 3

Description

Technical Field

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[0001] The present disclosure relates to a thin film transistor device and a method for manufacturing the same.

Background Art

[0002] A technique for incorporating a low-temperature polysilicon thin film transistor (LTPS TFT) and an oxide semiconductor TFT into one pixel circuit has been put into practical use in displays such as smart watches and smartphones. Hereinafter, this technique is referred to as HTD (Hybrid TFT Display) technology. For example, the HTD technology incorporates both a low-temperature polysilicon TFT with high mobility and an oxide semiconductor TFT with low leakage current into the pixel circuit, thereby realizing an improvement in display quality and a reduction in power consumption.

Prior Art Documents

Patent Documents

[0003] <​​​​​​​​​​​​​​​​​​​​​In the future, reducing the area of ​​each pixel will be crucial for achieving higher resolution displays. In HTD backplanes, TFTs containing semiconductor layers made of two different materials—LTPS and metal oxide (oxide semiconductor)—must be electrically connected, requiring numerous contact holes. These contact holes occupy a large area, hindering the improvement of display resolution. This issue is similar in circuits of devices other than display devices, including LTPS TFTs and oxide semiconductor TFTs. It is also similar in circuits of multiple TFTs containing semiconductor layers made of materials other than LTPS and oxide semiconductors. [Means for solving the problem]

[0005] A thin-film transistor device according to one aspect of the present disclosure includes a first thin-film transistor on a substrate, which includes a first semiconductor layer; a second thin-film transistor on the substrate, which includes a second semiconductor layer; one or more upper insulating layers on the substrate; one or more lower insulating layers on the substrate; and a metal contact portion in contact with the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are formed of different materials. As viewed from the substrate, the first semiconductor layer, the one or more lower insulating layers, the second semiconductor layer, and the one or more upper insulating layers are stacked in that order. The first semiconductor layer includes a first channel region and a first source / drain region sandwiching the first channel region. The second semiconductor layer includes a second channel region and a second source / drain region sandwiching the second channel region. The metal contact portion is located in a hole penetrating the one or more upper insulating layers and the one or more lower insulating layers, and is in contact with one of the first source / drain region and one of the second source / drain region. The diameter of the hole in the bottommost layer of the one or more upper insulating layers is greater than the diameter of the hole in the topmost layer of the one or more lower insulating layers. The metal contact portion is formed of the same metal material as the source / drain wires of the first thin-film transistor and the second thin-film transistor.

[0006] Another aspect of the present disclosure is a method for manufacturing a thin-film transistor device, comprising: forming a first semiconductor layer; forming one or more lower insulating layers on the first semiconductor layer; forming a second semiconductor layer made of a different material from the first semiconductor layer on the uppermost of the one or more lower insulating layers; forming one or more upper insulating layers on the second semiconductor layer; forming holes penetrating the one or more upper insulating layers and the one or more lower insulating layers, exposing a portion of the source / drain region of the first semiconductor layer and a portion of the source / drain region of the second semiconductor layer in the holes; and forming a metal pattern in the holes including a metal contact portion that contacts a portion of the first semiconductor layer and a portion of the second semiconductor layer, and source / drain wiring. [Effects of the Invention]

[0007] According to one aspect of this disclosure, the size of a circuit including multiple types of thin-film transistors, each containing semiconductor layers of different materials, can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic example of the configuration of an OLED display device is shown. [Figure 2A] An example of a pixel circuit configuration is shown. [Figure 2B] Other examples of pixel circuit configurations are shown. [Figure 2C] Other examples of pixel circuit configurations are shown. [Figure 3] This shows the cross-sectional structures of a low-temperature polysilicon TFT and an oxide semiconductor TFT, in which their low-resistance regions are interconnected by a single contact hole. [Figure 4A] A schematic diagram of the cross-sectional structure of the contact hole is shown. [Figure 4B] The planar structure of the contact hole is schematically shown. [Figure 5A] A schematic diagram shows the cross-sectional structure of the contact holes that interconnect the low-resistance regions of the oxide semiconductor layer and the polysilicon layer. [Figure 5B] A schematic diagram shows the planar structure of contact holes that interconnect the low-resistance regions of the oxide semiconductor layer and the polysilicon layer. [Figure 6] It is a flowchart showing an example of a manufacturing method. [Figure 7A] It is a diagram for explaining a method of forming a contact hole. [Figure 7B] It is a diagram for explaining a method of forming a contact hole. [Figure 7C] It is a diagram for explaining a method of forming a contact hole. [Figure 8A] It shows the same state as the state shown in FIG. 7A. [Figure 8B] It shows a state where the photoresist pattern is removed from the state shown in FIG. 8A and holes are formed using the newly formed photoresist pattern as a mask. [Figure 8C] It shows a state where the natural oxide film of the low-temperature polysilicon layer is removed from the state shown in FIG. 8B. [Figure 8D] It shows a state where an M4 metal layer is formed with respect to the state shown in FIG. 8C. [ [Figure 9A] It schematically shows an oxide semiconductor layer in which the inner end portion of the hole is removed by hydrofluoric acid. [Figure 9B] It shows a state where the photoresist is removed from the state of FIG. 9A and an M4 metal layer pattern is formed. [Figure 10] It shows another structural example of the contact hole. [Figure 11] It shows another structural example of the contact hole. [Figure 12] It shows an example of a part of a pixel circuit. [Figure 13] It schematically shows the planar structure of the pixel circuit shown in FIG. 12. [Figure 14] It schematically shows a cross-sectional structure of a part of the planar structure shown in FIG. 13. [Figure 15] It shows an example of a pixel circuit. [Figure 16] It schematically shows the planar structure of the pixel circuit shown in FIG. 15. [Figure 17] It schematically shows the cross-sectional structure along the cut line XVII-XVII´ in FIG. 16.

Embodiments for Carrying Out the Invention

[0009] Embodiments of the present invention will be described below with reference to the attached drawings. It should be noted that these embodiments are merely one example of how to realize the present invention and do not limit the technical scope of the present invention. Common components in each figure are denoted by the same reference numerals. For the sake of clarity, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0010] [overview] In the following, an OLED (Organic Light-Emitting Diode) display device will be described as an example of a thin-film transistor device. The OLED display device of this disclosure includes low-temperature polysilicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs in the pixel circuit and / or peripheral circuit.

[0011] The semiconductor layer of a low-temperature polysilicon TFT (low-temperature polysilicon layer) and the semiconductor layer of an oxide semiconductor TFT (oxide semiconductor layer) are formed at different layer positions. For example, the low-temperature polysilicon layer is located below the oxide semiconductor layer. One or more insulating layers exist between these semiconductor layers. In this specification, the layer closer to the substrate is referred to as the lower layer, and the layer further from the substrate is referred to as the upper layer.

[0012] Low-temperature polysilicon TFTs include source / drain regions (low-resistance regions) formed of low-resistance polysilicon, while oxide semiconductor TFTs include source / drain regions (low-resistance regions) formed of low-resistance oxide semiconductors (low-resistance oxide semiconductors).

[0013] The sheet resistance of the low-resistance source / drain region is generally in the range of 10Ω to 100kΩ, for example, in the range of several tens of ohms to several tens of kΩ. The sheet resistance of the non-low-resistance (high-resistance) channel is generally in the range of 1MΩ to 10GΩ, for example, in the range of several MΩ to several GΩ.

[0014] In one embodiment of this specification, a single contact hole interconnects the source / drain wiring layer, the oxide semiconductor layer, and the low-temperature polysilicon layer. This configuration reduces the number of contact holes required for interconnecting these three layers, thereby reducing the circuit area.

[0015] For example, the source / drain wiring layer is the uppermost layer, the low-temperature polysilicon layer is the lowermost layer, and the oxide semiconductor layer is located between them. There is one or more insulating layers (one or more upper insulating layers) between the source / drain wiring layer and the oxide semiconductor layer. Also, there is one or more insulating layers (one or more lower insulating layers) between the oxide semiconductor layer and the low-temperature polysilicon layer.

[0016] The contact hole includes a metal contact portion within the hole that penetrates the upper and lower insulating layers. The contact portion may be made of the same metal as the source / drain wiring and may be contained within the same metal layer.

[0017] The contact portion is formed to adhere to the inner surface of the hole. Therefore, the contact portion penetrates the upper insulating layer and the lower insulating layer. The contact portion contacts the source / drain regions of the two TFTs exposed within the hole, thereby conducting electricity to the source / drain wiring, the source / drain regions of the oxide semiconductor layer, and the source / drain regions of the low-temperature polysilicon layer.

[0018] As described above, by interconnecting the source / drain regions of two TFTs with a single contact hole, the circuit area can be reduced compared to a configuration using multiple contact holes. The contact hole may also penetrate the source / drain region of the oxide semiconductor layer. This can further reduce the circuit area and contribute to higher resolution.

[0019] The above connection structure can be applied to circuits of devices other than OLED display devices. It can also be applied to circuits containing TFTs made of semiconductor materials other than oxide semiconductors and low-temperature polysilicon.

[0020] [Display device configuration] Figure 1 schematically shows an example of the configuration of an OLED display device 1. The OLED display device 1 is composed of a TFT (Thin Film Transistor) substrate 10 on which OLED elements are formed, a sealing substrate 20 for sealing organic light-emitting elements, and a bonding portion (glass frit seal portion) 30 that joins the TFT substrate 10 and the sealing substrate 20. For example, dry nitrogen is sealed between the TFT substrate 10 and the sealing substrate 20, and the bonding portion 30 seals them together. The sealing substrate 20 and the bonding portion 30 are one type of sealing structure, and as another example, the sealing structure may have, for example, a thin film encapsulation (TFE) structure.

[0021] A scanning driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are arranged around the cathode electrode formation area 14 outside the display area 25 of the TFT substrate 10. The driver IC 34 is connected to external equipment via an FPC (Flexible Printed Circuit) 35. The scanning driver 31, emission driver 32, and protection circuit 33 are peripheral circuits formed on the TFT substrate 10.

[0022] The scanning driver 31 drives the scan lines of the TFT substrate 100. The emission driver 32 drives the emission control lines to control the light emission period of each pixel. The driver IC 34 is mounted using, for example, an anisotropic conductive film (ACF).

[0023] The driver IC 34 supplies power and timing signals (control signals) to the scan driver 31 and the emission driver 32. Furthermore, the driver IC 34 supplies power and data signals to the demultiplexer 36.

[0024] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (where d is an integer greater than or equal to 2). The demultiplexer 36 drives d times the number of data lines (the number of output pins of the driver IC 34) by switching the data line to which the data signal from the driver IC 34 is output d times within the scanning period.

[0025] [Pixel circuit configuration] Multiple pixel circuits are formed on the TFT substrate 10 to control the current supplied to the anode electrodes of multiple subpixels (also simply called pixels). Figure 2A shows an example of the configuration of a pixel circuit. Each pixel circuit includes a drive transistor P1, a selection transistor N2, an emission transistor N3, and a holding capacitor C1. The pixel circuit controls the light emission of the OLED element E1. The OLED element E1 is a light-emitting element, and the transistors are TFTs.

[0026] The selection transistor N2 is a switch that selects sub-pixels. The selection transistor N2 is an N-channel oxide semiconductor TFT, and its gate terminal is connected to scan line 16. Its source terminal is connected to data line 15. Its drain terminal is connected to the gate terminal of the drive transistor P1.

[0027] The drive transistor P1 is a drive transistor (driver TFT) for the OLED element E1. The drive transistor P1 is a P-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor N2. The source terminal of the drive transistor P1 is connected to the power line 18 (Vdd). The drain terminal is connected to the source terminal of the emission transistor N3. A retaining capacitance C1 is formed between the gate terminal and the source terminal of the drive transistor P1.

[0028] The emission transistor N3 is a switch that controls the supply and cessation of drive current to the OLED element E1. The emission transistor N3 is an N-channel oxide semiconductor TFT, and its gate terminal is connected to the emission control line 17. The source terminal of emission transistor N3 is connected to the drain terminal of drive transistor P1. The drain terminal of emission transistor N3 is connected to the OLED element E1.

[0029] Next, the operation of the pixel circuit will be explained. The scanning driver 31 outputs a selection pulse to the scanning line 16, turning on the selection transistor N2. The data voltage supplied from the driver IC 34 via the data line 15 is stored in the retention capacitor C1. The retention capacitor C1 holds the stored voltage throughout one frame period. The retention voltage causes the conductance of the drive transistor P1 to change analogously, and the drive transistor P1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

[0030] The emission transistor N3 is located on the drive current supply path. The emission driver 32 outputs a control signal to the emission control line 17 to control the on / off state of the emission transistor N3. When the emission transistor N3 is ON, drive current is supplied to the OLED element E1. When the emission transistor N3 is OFF, this supply is stopped. By controlling the on / off state of the emission transistor N3, the illumination period (duty cycle) within one frame period can be controlled.

[0031] Figure 2B shows another example of the pixel circuit configuration. This pixel circuit has a reset transistor N4 instead of the emission transistor N3 in Figure 2A. The reset transistor N4 is an N-channel oxide semiconductor TFT. The reset transistor N4 controls the electrical connection between the reference voltage supply line 11 and the anode of the OLED element E1. This control is performed by supplying a reset control signal from the reset control line 19 to the gate terminal of the reset transistor N4. The reset transistor N4 can be used for various purposes.

[0032] Figure 2C shows another example of a pixel circuit configuration. This pixel circuit includes transistors P11, P13, P15, N12, N14, and N16. The Vscan2 signal is input to the gate terminal of transistor N12. The Vscan1 signal is input to the gates of transistors N14 and N16. A data voltage is applied to the holding capacitor C1 via transistors N12, P11, and N16. Transistor N14 provides Vref to the anode of the OLED element E1. The signals Vem1 and Vem2 are input to the gates of transistors P13 and P15, respectively, to control the presence or absence of light emission from the OLED element E1.

[0033] For example, the driving transistors P11, P13, and P15 are low-temperature polysilicon TFTs, and the transistors N12, N14, and N16 are oxide semiconductor TFTs. The source / drain region of the driving transistor P11 is connected to the source / drain region of the transistor N16. Note that the pixel circuits in Figures 2A, 2B, and 2C are examples, and the pixel circuits may have other circuit configurations. Depending on the operation of the TFT, one of the low-resistance regions becomes the source region and the other becomes the drain region, and these can switch. Therefore, the low-resistance region is referred to as the source / drain region.

[0034] The pixel circuit described above includes a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain regions are connected to each other. The connection configuration described herein can reduce the number of contact holes and contribute to higher resolution.

[0035] [Connecting low-temperature polysilicon TFTs and oxide semiconductor TFTs] The following describes an example configuration of interconnected low-temperature polysilicon TFTs and oxide semiconductor TFTs. In the example described below, the oxide semiconductor is assumed to be IGZO (Indium Gallium Zinc Oxide). The configuration described herein can be applied to TFTs of other oxide semiconductors, such as zinc oxide and tin dioxide.

[0036] Figure 3 shows the cross-sectional structures of a low-temperature polysilicon TFT 210 and an oxide semiconductor TFT 260, in which their source / drain regions (low-resistance regions) are interconnected by a single contact hole. These are the first and second TFTs. The low-temperature polysilicon TFT 210 and oxide semiconductor TFT 260 are formed on a flexible or inflexible insulating substrate 101 made of resin or glass.

[0037] A silicon nitride layer 102 is laminated on an insulating substrate 101, and a low-temperature polysilicon layer (active layer) 108 of a low-temperature polysilicon TFT 210 is further laminated on top of it. The low-temperature polysilicon layer includes low-resistance regions 105 and 107 and a channel region 103.

[0038] The low-temperature polysilicon layer 108 includes low-resistance regions (low-resistance LTPS) 105 and 107, and a high-resistance channel region (LTPS) 103 between the low-resistance regions 105 and 107 in the in-plane direction. The low-resistance regions 105 and 107 are the source / drain regions, respectively.

[0039] Low-resistance regions 105 and 107 are formed of low-resistance low-temperature polysilicon that has been doped with high-concentration impurities. Channel region 103 is formed of low-temperature polysilicon that has not been doped with low resistance (high-resistance low-temperature polysilicon).

[0040] The low-temperature polysilicon TFT 210 further includes a gate electrode 113 and a gate insulating layer 111 located between the gate electrode 113 and the low-temperature polysilicon layer 108 in the stacking direction. The low-temperature polysilicon layer 108, the gate insulating layer 111, and the gate electrode 113 are stacked in this order from bottom to top (from the substrate side), and the gate insulating layer 111 is in direct contact with the low-temperature polysilicon layer and the gate electrode 113.

[0041] The gate electrode 113 is formed of metal and is contained within the M1 metal layer. The gate insulating layer 111 is formed of silicon oxide (SiOx) in this example. In the example in Figure 3, the low-temperature polysilicon TFT 210 has a top gate structure, but it may also have a bottom gate structure, for example, and may include both a top gate electrode and a bottom gate electrode.

[0042] The oxide semiconductor TFT 260 includes a bottom gate electrode 117, a top gate electrode 131, and an oxide semiconductor layer (active layer) 124 between them. The oxide semiconductor layer 124 includes low-resistance regions 123 and 125 (low-resistance IGZO) and a high-resistance channel region 127 between the low-resistance regions 123 and 125 in the in-plane direction. The low-resistance regions 123 and 125 are formed of low-resistance IGZO. The channel region 127 is formed of non-low-resistance IGZO (high-resistance IGZO).

[0043] An insulating layer 115 is laminated on top of the gate insulating layer 111 and the gate electrode 113 so as to cover them. The insulating layer 115 is made of silicon nitride (SiNx). The bottom gate electrode 117 is laminated on top of the insulating layer 115. The bottom gate electrode 117 is made of metal and is contained in the M2 metal layer.

[0044] A gate insulating layer is formed between the bottom gate electrode 117 and the oxide semiconductor layer. In the configuration example shown in Figure 3, the gate insulating layer is a stack of two insulating layers 119 and 121. Insulating layer 119 is made of silicon nitride, and insulating layer 121 is made of silicon oxide.

[0045] The bottom gate electrode 117, insulating layers 119 and 121, and oxide semiconductor layer 124 are stacked in this order from bottom to top (from the substrate side), with insulating layer 119 in direct contact with the bottom gate electrode 117 and insulating layer 121, and insulating layer 121 in direct contact with oxide semiconductor layer 124.

[0046] The oxide semiconductor layer 124 is laminated on the insulating layer 121. The gate insulating layer 129 is located between the oxide semiconductor layer 124 and the top gate electrode 131. The gate insulating layer 129 is made of silicon oxide. The oxide semiconductor layer 124, the insulating layer 129, and the top gate electrode 131 are laminated in this order from bottom to top (from the substrate side), and the insulating layer 129 is in direct contact with the top gate electrode 131 and the oxide semiconductor layer 124. The top gate electrode 131 is made of metal and is embedded in the M3 metal layer. Note that either the top gate electrode 131 or the bottom gate electrode 117 may be omitted.

[0047] An insulating layer 133 is laminated on top of the top gate electrode 131 and the insulating layer 129 so as to cover them. Furthermore, an insulating layer 135 is laminated on top of the insulating layer 133. The insulating layer 133 is made of silicon oxide, and the insulating layer 135 is made of silicon nitride.

[0048] Figure 3 shows three contact holes (CH) 140, 150, and 160. Contact hole 140 interconnects the low-resistance region 107 of the low-temperature polysilicon TFT 210 with the upper source / drain wiring 144. Contact hole 140 includes a metal contact portion 141.

[0049] The contact portion 141 penetrates the insulating layers 135, 133, 129, 121, 119, 115, and 111 and directly contacts the low-resistance region 107 of the low-temperature polysilicon layer 108. The laminate consisting of the insulating layers 135, 133, 129, 121, 119, 115, and 111 has a through-hole 147. The contact portion 141 is formed to adhere to the inner surface of the through-hole 147. The source / drain wiring 144 is laminated on the insulating layer 135. The contact portion 141 and the source / drain wiring 144 are formed of the same material, are continuous, and are included in the M4 metal layer.

[0050] The contact hole 150 interconnects the low-resistance region 105 of the low-temperature polysilicon TFT 210 and the low-resistance region 125 of the oxide semiconductor TFT 260. The layers are stacked from the bottom up, in the order of the low-resistance region 105 of the low-temperature polysilicon layer 108 and the low-resistance region 125 of the oxide semiconductor layer 124.

[0051] The contact hole 150 includes a metal contact portion 151. Insulating layers 135, 133, and 129 are present between the metal contact portion 151 layer and the oxide semiconductor layer 124. Insulating layers 121, 119, 115, and 111 are present between the oxide semiconductor layer 124 and the low-temperature polysilicon layer 108.

[0052] The low-resistance region 125 of the oxide semiconductor layer 124 and the low-resistance region 105 of the low-temperature polysilicon layer 108 overlap, at least partially, in the stacking direction. The stacking direction is the vertical direction in Figure 3.

[0053] The contact portion 151 penetrates the insulating layers 135, 133, 129, the oxide semiconductor layer 124, and the insulating layers 121, 119, 115, and 11, and directly contacts the low-resistance region 105 of the low-temperature polysilicon layer 108. The laminate consisting of insulating layers 135, 133, 129, the oxide semiconductor layer 124, and the insulating layers 121, 119, 115, and 111 has through holes 157. The inner diameter of the through holes 157 changes discontinuously above and below the oxide semiconductor layer 124. Specifically, the minimum inner diameter above the oxide semiconductor layer 124 is larger than the maximum inner diameter below the oxide semiconductor layer 124.

[0054] The contact portion 151 is formed to adhere to the inner surface of the through hole 157. The outer diameter of the contact portion 151 changes discontinuously above and below the oxide semiconductor layer 124. Specifically, the minimum outer diameter above the oxide semiconductor layer 124 is greater than the maximum outer diameter below the oxide semiconductor layer 124.

[0055] The through-hole 157 penetrates the low-resistance region 125 of the oxide semiconductor layer 124. The contact portion 151 penetrates the low-resistance region 125 and is in direct contact with the upper surface of the low-resistance region 125 and the inner surface (side surface) of the hole. The contact portion 151 is in direct contact with the upper surface of the low-resistance region 105 of the polysilicon layer. The contact portion 151 is included in the M4 metal layer. The contact portion 151 may also interconnect the source / drain wiring on the insulating layer 135 with the oxide semiconductor layer 124. This source / drain wiring is included in the pattern of the M4 metal layer.

[0056] The contact hole 160 includes a metal contact portion 161. The contact portion 161 penetrates the insulating layers 135, 133, and 129 and directly contacts the low-resistance region 123 of the oxide semiconductor layer 124. The laminate consisting of the insulating layers 135, 133, and 129 has a through hole 167. The contact portion 161 is formed to adhere to the inner surface of the through hole 167. The source / drain wiring 164 is laminated on the insulating layer 135. The contact portion 161 and the source / drain wiring 164 are formed of the same material, are continuous, and are included in the M4 metal layer.

[0057] Figure 4A schematically shows the cross-sectional structure of contact holes 150 and 160, and Figure 4B schematically shows the planar structure of contact holes 150 and 160. The M4 metal layer including the metal contact portions 151 and 161 can be composed of, for example, a single metal layer or a metal laminate, and each layer may be a single metal material or an alloy. For example, a Ti / Al / Ti laminate can be used.

[0058] The contact portion 151 includes an upper portion 152 above the upper surface of the oxide semiconductor layer 124 and a lower portion 153 that follows below it. The upper portion 152 penetrates the insulating lamination above the oxide semiconductor layer 124 and is in direct contact with the upper surface of the low-resistance region 125. The inner diameter of the insulating lamination above the oxide semiconductor layer 124 is indicated by W1. In the configuration example in Figure 4A, the inner diameter W1 of the through-hole above the oxide semiconductor layer 124 is substantially constant.

[0059] The lower portion 153 of the contact portion 151 penetrates the oxide semiconductor layer 124 and the insulating laminate beneath it, and directly contacts the inner surface of the hole in the low-resistance region 125 of the oxide semiconductor layer 124 and the upper surface of the low-resistance region 105 of the low-temperature polysilicon layer 108. The inner diameter of the lower insulating laminate is indicated by W2. In the configuration example in Figure 4A, the inner diameter W2 of the through hole 157 below the oxide semiconductor layer 124 is substantially constant. The inner diameter of the through hole 157 changes discontinuously above and below the oxide semiconductor layer 124, with the maximum value of the inner diameter W2 being smaller than the minimum value of the inner diameter W1. This allows for higher density mounting of other components in the layers below the oxide semiconductor layer 124.

[0060] As shown in Figures 4A and 4B, when viewing the hole 157 of a single contact hole from above, the oxide semiconductor layer 124 and the low-temperature polysilicon layer 108 are visible simultaneously. More specifically, the low-resistance region 125 of the oxide semiconductor layer 124 and the low-resistance region 105 of the low-temperature polysilicon layer 108 are visible simultaneously. Furthermore, in the through-hole 157, the low-resistance region 125 of the oxide semiconductor layer 124 and the low-resistance region 105 of the low-temperature polysilicon layer 108 overlap. The portion of the insulating layer (hole) above the oxide semiconductor layer 124 of the through-hole 157 lies within the outline of the low-resistance region 125. The portion of the insulating layer (hole) below the oxide semiconductor layer 124 of the through-hole 157 lies within the outline of the low-resistance region 155.

[0061] Figures 5A and 5B show other structural examples of contact holes that interconnect the low-resistance regions of the oxide semiconductor layer and the polysilicon layer. Figure 5A schematically shows the cross-sectional structure, and Figure 5B schematically shows the planar structure. In this configuration example, the oxide semiconductor layer 124 and the low-temperature polysilicon layer 108 do not overlap when viewed in the stacking direction and are separated. Note that the configuration of the oxide semiconductor layer 124 and the low-temperature polysilicon layer 108 themselves is the same as in the configuration examples in Figures 4A and 4B, and therefore they are denoted by the same reference numerals. The contact hole 250 interconnects the low-resistance region 105 of the low-temperature polysilicon TFT 210 and the low-resistance region 125 of the oxide semiconductor TFT 260.

[0062] The laminate, consisting of insulating layers 135, 133, 129, 121, 119, 115, and 111, has through-holes 257. The inner diameter of the through-holes 257 changes discontinuously above and below the oxide semiconductor layer 124. Specifically, the minimum inner diameter above the oxide semiconductor layer 124 is greater than the maximum inner diameter below the oxide semiconductor layer 124.

[0063] The contact portion 251 is formed to adhere to the inner surface of the through hole 257. The contact hole 250 includes the metal contact portion 251. The contact portion 251 penetrates the insulating layers 135, 133, 129, 121, 119, 115, and 111. The outer diameter of the contact portion 251 changes discontinuously above and below the oxide semiconductor layer 124. Specifically, the minimum outer diameter above the oxide semiconductor layer 124 is greater than the maximum outer diameter below the oxide semiconductor layer 124.

[0064] The through-hole 257 does not penetrate the oxide semiconductor layer 124, and a portion of the low-resistance region 125, including its outer edge, is exposed at the through-hole 257. Similarly, a portion of the low-resistance region 105 of the low-temperature polysilicon layer 108, including its outer edge, is exposed at the through-hole 257. The contact portion 251 is in direct contact with the upper surface and end face (side surface) of the low-resistance region 125. The contact portion 251 is in direct contact with the upper surface and end face (side surface) of the low-resistance region 105 of the polysilicon layer. The contact portion 251 is included in the M4 metal layer.

[0065] The contact portion 251 includes an upper portion 252 above the upper surface of the oxide semiconductor layer 124 and a lower portion 253 that follows below it. The upper portion 252 penetrates the insulating lamination above the oxide semiconductor layer 124 and directly contacts the upper surface of the low-resistance region 125. The inner diameter of the through-hole 257 in the insulating lamination above the upper surface of the oxide semiconductor layer 124 is indicated by W11. In the configuration example in Figure 5A, the inner diameter W11 of the through-hole above the oxide semiconductor layer 124 decreases from top to bottom.

[0066] The lower portion 253 of the contact portion 251 penetrates the insulating lamination below the oxide semiconductor layer 124 and directly contacts the end face of the low-resistance region 125 of the oxide semiconductor layer 124 and the upper and end faces of the low-resistance region 105 of the low-temperature polysilicon layer 108. The inner diameter of the through-hole 257 below the lower surface of the oxide semiconductor layer 124 is indicated by W12. In the configuration example in Figure 5A, the inner diameter W2 of the through-hole 257 below the oxide semiconductor layer 124 decreases from top to bottom. The inner diameter of the through-hole 157 changes discontinuously above and below the oxide semiconductor layer 124, with the maximum value of the inner diameter W12 being smaller than the minimum value of the inner diameter W11.

[0067] The upper portion 252 and the lower portion 253 of the contact portion 251 have a tapered shape in accordance with the change in the inner diameter of the through hole 257. As a result, the thickness of the contact portion 251 at the end face (side surface) of the oxide semiconductor layer 124 increases, preventing the contact portion 251 from breaking off in a stepped manner.

[0068] As shown in Figures 5A and 5B, when viewing the hole 257 of a single contact hole from above, the oxide semiconductor layer 124 and the low-temperature polysilicon layer 108 are visible simultaneously. More specifically, the low-resistance region 125 of the oxide semiconductor layer 124 and the low-resistance region 105 of the low-temperature polysilicon layer 108 are visible simultaneously. In the through-hole 257, the low-resistance region 125 of the oxide semiconductor layer 124 and the low-resistance region 105 of the low-temperature polysilicon layer 108 do not overlap and are separated.

[0069] [Manufacturing method] Next, the manufacturing methods for TFT210 and 260 shown in Figure 3 will be described. Figure 6 is a flowchart of an example of the manufacturing method. The manufacturing method involves forming a silicon nitride layer on an insulating substrate 101 by CVD or the like, and then forming a low-temperature polysilicon layer (S101). Specifically, for example, amorphous silicon is deposited by CVD, and crystallized by excimer laser annealing to form a (low-temperature) polysilicon film. The pattern of the polysilicon layer is formed by patterning using photolithography.

[0070] Next, the manufacturing method involves depositing a silicon oxide layer by CVD or the like (S102). Furthermore, an M1 metal layer is deposited by sputtering or the like, and the M1 metal layer is patterned by photolithography (S103). The material of the M1 metal layer is arbitrary, and for example, Mo, W, Nb, Al, etc. can be used. The M1 metal layer may have a single-layer structure or a multi-layer structure.

[0071] Next, the manufacturing method involves using the gate electrode 113 (M1 metal layer) as a mask to inject impurities into the source / drain region of the polysilicon layer and activate the impurities. Furthermore, the dangling bonds are terminated by hydrogenation (S104). As a result, the resistance of the source / drain region is reduced.

[0072] Next, the manufacturing method involves depositing a silicon nitride layer by CVD or the like (S105). Furthermore, an M2 metal layer is deposited by sputtering or the like, and the M1 metal layer is patterned by photolithography (S103). The material of the M2 metal layer is arbitrary; for example, Mo, W, Nb, Al, etc., can be used. The M2 metal layer may have a single-layer structure or a multi-layer structure.

[0073] Next, the manufacturing method involves depositing a silicon nitride layer and a silicon oxide layer using a CVD method or the like (S107). Furthermore, an IGZO layer is deposited using a sputtering method or the like, and patterning is performed using photolithography (S108). At this time, holes in the IGZO layer through which the contact holes 150 pass are also formed.

[0074] Next, the manufacturing method involves depositing a silicon oxide layer (S109). Then, the manufacturing method involves depositing an M3 metal layer by sputtering or the like, and patterning it by photolithography (S110). The material of the M3 metal layer is arbitrary; for example, Mo, W, Nb, Al, etc., can be used. The M3 metal layer may have a single-layer structure or a multi-layer structure.

[0075] Next, the manufacturing method involves using the gate electrode 131 (M1 metal layer) as a mask to reduce the resistance of the source / drain region of the IGZO layer (S111). Resistance reduction can be achieved, for example, by exposing the source / drain region of the IGZO layer to He plasma. Resistance reduction may also be performed by ion implantation of B, Ar, H, etc.

[0076] Next, the manufacturing method involves forming a silicon nitride layer and a silicon oxide layer using a CVD method or the like (S112). Next, the manufacturing method involves performing anisotropic etching in the lamination of the insulating layer to form holes for each contact hole (S113).

[0077] Next, the manufacturing method involves depositing an M4 metal layer by sputtering or the like, and then patterning it using photolithography (S112). The M4 metal layer includes the source / drain wiring and the contact portion of the contact hole. The M4 metal layer is formed, for example, by depositing a conductive film such as Ti / Al / Ti and then patterning it.

[0078] The details of the contact hole formation method are described below. Figures 7A to 7D are diagrams illustrating the formation method (S113, S114) for contact holes 150 and 160. Figures 7A to 7D show the planar structure and cross-sectional structure at different steps in the formation of the contact holes, respectively.

[0079] Figure 7A schematically shows the state in which the insulating layer above the oxide semiconductor layer 124 is etched using the photoresist pattern 320 as a mask. For example, plasma etching can be used. The photoresist pattern 320 is stacked on the insulating layer 135. As described above, the holes 352 in the oxide semiconductor layer 124 are already formed before the creation of the photoresist pattern 320.

[0080] A hole 351 is formed in the laminate consisting of insulating layers 129, 133, and 135. In hole 351, the low-resistance region 125 of the oxide semiconductor layer 124 and its hole 352 are exposed. That is, the top surface and edge surface (inner surface of the hole) of the low-resistance region are exposed. In addition, a hole 167 is formed in the laminate consisting of insulating layers 129, 133, and 135. In hole 167, the top surface of the low-resistance region 123 of the oxide semiconductor layer 124 is exposed.

[0081] Figure 7B shows a state where etching has progressed further from the state shown in Figure 7A. Hole 353, which is connected to hole 352, is formed in the laminate consisting of insulating layers 111, 115, 119, and 121. The diameter of hole 353 is smaller than the diameter of hole 351. Holes 351, 352, and 353 are continuous and constitute a single hole 157, as explained with reference to Figures 3 and 4A.

[0082] Within hole 351, the peripheral edge of hole 352 in the low-resistance region 125 of the oxide semiconductor layer 124 is over-etched, and a recess 355 is formed on the upper surface of the low-resistance region 125. Therefore, the thickness of the low-resistance region 125 inside hole 351 is thinner than the thickness outside hole 351. Similarly, within hole 167, the low-resistance region 123 is over-etched, and a recess 356 is formed on its upper surface. The thickness of the low-resistance region 123 inside hole 167 is thinner than the thickness outside hole 167.

[0083] Thus, more oxygen vacancies are formed due to damage during etching, resulting in lower resistance. As a result, the contact resistance with the metal contact area becomes lower. The low-resistance region 105 of the low-temperature polysilicon layer 108 is exposed at the pore 353, and a native oxide film 358 is formed on its surface by the etching process. In this example, the native oxide film 358 is left intact. The native oxide film 358 is part of the low-resistance region 105.

[0084] Figure 7C shows the state in which the M4 metal layer has been formed, compared to the state shown in Figure 7B. The contact portion 151 interconnects the low-resistance region 125 of the oxide semiconductor layer and the low-resistance region 105 of the low-temperature polysilicon layer. The contact portion 161 interconnects the source / drain wiring 164 and the low-resistance region 123 of the oxide semiconductor layer.

[0085] Next, other methods for forming contact holes will be described. The formation method described below removes the native oxide film of the low-temperature polysilicon layer. This further reduces the contact resistance between the metal contact area and the low-resistance region of the low-temperature polysilicon layer.

[0086] Figure 8A shows the same state as shown in Figure 7A. Figure 8B shows the state in which the photoresist pattern 320 is removed from the state shown in Figure 8A, and a newly formed second photoresist pattern 325 is used as a mask to form the holes 353. The photoresist pattern 325 covers the inner surface of the holes 167 and the upper surface of the low-resistance region 123 of the oxide semiconductor layer 124.

[0087] The photoresist pattern 325 covers the entire inner surface of the hole 351 and the upper surface (periphery of the hole 352) of the low-resistance region 125 of the oxide semiconductor layer within the hole 351. The photoresist pattern 325 has a hole 326 that coincides with the hole 352 of the low-resistance region 125. Before etching, the insulating layer 121 is exposed through the hole 326. Etching forms the hole 353 of the insulating laminate. At this time, the upper surfaces of the low-resistance regions 123 and 125 are covered by the resist pattern 325, and no depressions are formed due to over-etching. The low-resistance region 105 of the low-temperature polysilicon layer 108 is exposed to the etchant, and a native oxide film 358 is formed.

[0088] Figure 8C shows the state after removing the native oxide film 358 from the low-temperature polysilicon layer 108, compared to the state shown in Figure 8B. The manufacturing method allows for more effective removal of the native oxide film 358 using hydrofluoric acid (HF) while maintaining the photoresist pattern 325. The photoresist pattern 325 reduces the adverse effects of hydrofluoric acid on the oxide semiconductor layer 124.

[0089] Figure 8D shows the state in which the M4 metal layer has been formed, compared to the state shown in Figure 8C. The contact portion 151 interconnects the low-resistance region 125 of the oxide semiconductor layer and the low-resistance region 105 of the low-temperature polysilicon layer. The contact portion 161 interconnects the source / drain wiring 164 and the low-resistance region 123 of the oxide semiconductor layer. The native oxide film 358 has been removed by hydrofluoric acid treatment, and the contact portion 151 is in direct contact with the lower-resistance surface of the low-resistance region 105 of the polysilicon layer.

[0090] Hydrofluoric acid can slightly etch the silicon oxide layer, silicon nitride layer, and oxide semiconductor layer together with the native oxide film 358. The etching rate of the oxide semiconductor layer is faster than that of the silicon oxide layer and silicon nitride layer. Therefore, a portion of the oxide semiconductor layer may be etched together with the native oxide film 358 and recede on the insulating layer.

[0091] Figure 9A schematically shows the oxide semiconductor layer 124 in which the inner edge of the hole 352 has been removed by hydrofluoric acid. Figure 9A schematically shows the state in which a portion of the oxide semiconductor layer 124 has been removed in the state shown in Figure 8C. The end face 361 is recessed from the end face of the lower insulating layer 121 and is located on the upper surface of the insulating layer 121. The diameter of the holes in the low-resistance region 125 of the oxide semiconductor layer 124 is smaller than the diameter of the holes in the insulating layer 129 directly above it, and larger than the diameter of the holes in the insulating layer 121 directly below it.

[0092] Figure 9B shows the state after removing the photoresist pattern 325 from the state in Figure 9A and forming the M4 metal layer (pattern). As indicated by the dashed circle 363, the contact portion 151 includes a portion that fills the upper surface of the insulating layer 121 that protrudes from the end face (side surface) of the low-resistance region 125. This portion is thick, which reduces the damage that the end face of the low-resistance region receives in subsequent processes.

[0093] [Other configuration examples] Figure 10 shows another example of the contact hole structure. The example shown in Figure 10 includes contact holes 440, 450, and 460, replacing contact holes 140, 150, and 160 in Figure 3. Other components are the same. In Figure 10, some components and some reference numerals are omitted.

[0094] Contact holes 440, 450, and 460 each include metal contact portions 441, 451, and 461, respectively. Contact portion 441 interconnects the low-resistance region 107 of the low-temperature polysilicon layer 108 with the source / drain wiring 444. Contact portion 451 interconnects the low-resistance region 125 with the low-resistance region 105 of the low-temperature polysilicon layer 108. Contact portion 461 interconnects the low-resistance region 123 of the oxide semiconductor layer 124 with the source / drain wiring 464.

[0095] The thickness of the metal contact portions 441, 451, and 461 (thickness of the M4 metal layer) is greater than the thickness in the structural example shown in Figure 3. In the example shown in Figure 10, the metal contact portion 451 fills the holes 455 in the oxide semiconductor layer 124 and the holes in the insulating laminate below it (embedded structure). In this way, the edge (side) of the oxide semiconductor layer 124 is protected by a thick metal, which reduces the damage the edge of the oxide semiconductor layer receives in subsequent processes.

[0096] Figure 11 shows another example of the contact hole structure. The example shown in Figure 11 includes contact holes 540, 550, and 560, replacing contact holes 140, 150, and 160 in Figure 3. Other components are the same. Some components and some reference numerals are omitted in Figure 11.

[0097] Contact holes 540, 550, and 560 each include metal contact portions 541, 551, and 561, respectively. Contact portion 541 interconnects the low-resistance region 107 of the low-temperature polysilicon layer 108 with the source / drain wiring 544. Contact portion 551 interconnects the low-resistance region 125 with the low-resistance region 105 of the low-temperature polysilicon layer 108. Contact portion 561 interconnects the low-resistance region 123 of the oxide semiconductor layer 124 with the source / drain wiring 564.

[0098] The contact portions 541, 551, and 561 have a tapered shape. That is, their outer and inner diameters decrease from the upper layer to the lower layer. In particular, the tapered shape of contact portion 551 can effectively prevent step breakage at the edge of the oxide semiconductor layer of contact portion 551. This reduces the damage that the edge of the oxide semiconductor layer receives in subsequent processes.

[0099] Below, examples of pixel circuits and device structures corresponding to pixel circuits are described. Figure 12 shows an example of a part of a pixel circuit. The pixel circuit includes transistors T3 to T6 and an OLED element E1. Transistor T3 is a driving transistor, and the other transistors are switching transistors. Transistors T4 and T5 are N-type oxide semiconductor TFTs, and the other transistors are P-type low-temperature polysilicon TFTs.

[0100] Transistor T4 is connected between the drain region and the gate electrode of the drive transistor T3. Transistor T5 is connected between the reference potential Vref wiring and the gate electrode of the drive transistor T3.

[0101] Transistor T6 is connected between the drain region of the drive transistor T3 and the anode electrode of the OLED element E1. Transistor T6 is controlled by the control signal Em, transistor T4 is controlled by the control signal S2, and transistor T5 is controlled by the control signal S1. The control signal S2 may be the next pixel circuit row S1 signal.

[0102] Figure 13 schematically shows the planar structure of the circuit shown in Figure 12, and Figure 14 schematically shows a cross-sectional structure of a part of the planar structure of Figure 13. In Figure 14, the white layer is an insulating layer. Wiring VRE transmits the reference potential Vref. Wiring EMC transmits the control signal Em to the gate electrode of transistor T6. Gate wire S2NB transmits the gate signal of the bottom gate electrode of transistor T4, and gate wire S2NT transmits the gate signal of the top gate electrode of transistor T4. Gate wire S1NB transmits the gate signal of the bottom gate electrode of transistor T5, and gate wire S1NT transmits the gate signal of the top gate electrode of transistor T5.

[0103] The contact hole CHC interconnects the source / drain region of transistor T4 with the source / drain region of transistor T3 or T6. The semiconductor layer of transistor T4 is an oxide semiconductor layer OX, while the semiconductor layers of transistors T3 and T6 are low-temperature polysilicon layers PS. The contact hole CHC interconnects the oxide semiconductor layer and the low-temperature polysilicon layer.

[0104] Contact hole CHB interconnects the source / drain region of transistor T4 with the source / drain wiring. Contact hole CHD interconnects its source / drain wiring with the gate electrode G3 of transistor T3. Contact hole CHA interconnects the source / drain region of transistor T5 with wiring VRE.

[0105] Below, examples of pixel circuits and device structures corresponding to pixel circuits are described. Figure 15 shows an example of a pixel circuit. The pixel circuit includes transistors T1 to T7, an OLED element E1, a retaining capacitor Cst, and a capacitor Cd. Transistor T3 is a driving transistor, and the other transistors are switching transistors. Transistors T4 and T5 are N-type oxide semiconductor TFTs, and the other transistors are P-type low-temperature polysilicon TFTs.

[0106] Transistor T2 is connected between the source region of the drive transistor T3 and the data line that transmits the data signal (DATA). Transistor T1 is connected between the source region of the drive transistor T3 and the wiring that transmits the power supply potential VDD. Transistor T4 is connected between the drain region of the drive transistor T3 and the gate electrode. Transistor T5 is connected between the wiring of the reference potential Vref and the gate electrode of the drive transistor T3.

[0107] Transistor T6 is connected between the drain region of the drive transistor T3 and the anode electrode of the OLED element E1. Transistor T7 is connected between the anode electrode of the OLED element E1 and the wiring that transmits the reset potential Vrst. The retaining capacitance Cst is connected between the transmission line of the power supply potential VDD and the gate electrode of the drive transistor T3, and capacitance Cd is connected between transistor T3 and the shield electrode SE. Transistors T1 and T6 are controlled by the control signal Em, transistors T2, T4, and T7 are controlled by the control signal S2, and transistor T5 is controlled by the control signal S1.

[0108] Figure 16 schematically shows the planar structure of the pixel circuit shown in Figure 15, and Figure 17 schematically shows the cross-sectional structure at the XVII-XVII' cut line in Figure 16. In Figure 16, wiring M2D is a data line, wiring M2V transmits the power supply potential VDD, wiring VRS transmits the reset potential Vrst, and wiring VRE transmits the reference potential Vref.

[0109] The gate wire S2P2 transmits the gate signal of transistor T7. The wiring EMC transmits the control signal Em to the gate electrodes of transistors T1 and T6. The shield electrode SE includes one electrode of capacitance Cd, and the capacitive electrode CE includes one electrode of retaining capacitance Cs.

[0110] Gate line S2P1 transmits the gate signal of transistor T2. Gate line S2NB transmits the gate signal of the bottom gate electrode of transistor T4, and gate line S2NT transmits the gate signal of the top gate electrode of transistor T4. Gate line S1NB transmits the gate signal of the bottom gate electrode of transistor T5, and gate line S1NT transmits the gate signal of the top gate electrode of transistor T5.

[0111] Contact hole CH1 interconnects the source / drain region of transistor T7 with the wiring VRS. Contact hole CH2 interconnects the source / drain region of transistor T7 with the anode electrode of the OLED element. Contact hole CH3 interconnects the source / drain region of transistor T4 with the source / drain region of transistor T3 or T6. The semiconductor layer of transistor T4 is an oxide semiconductor layer OX, and the semiconductor layers of transistors T3 and T6 are low-temperature polysilicon layers PS. Contact hole CH3 interconnects the oxide semiconductor layer and the low-temperature polysilicon layer.

[0112] Contact hole CH4 interconnects the source / drain region of transistor T4 with the source / drain wiring, and this source / drain wiring is connected to the gate electrode of transistor T3. Contact hole CH5 interconnects the source / drain region of transistor T5 with wiring VRE.

[0113] Figure 17 schematically shows the cross-sectional structure along the XVII-XVII' line in Figure 16. The lamination of polyimide layer PI1, buffer layer BUF1, and polyimide layer PI2 constitutes an insulating substrate. A shield electrode SE is laminated on top of the buffer layer BUF2. An underlying insulating layer UC is laminated to cover the shield electrode SE.

[0114] A low-temperature polysilicon layer PS is laminated on the underlying insulating layer UC, and a gate insulating layer GI1 is laminated over it. Wiring VRS, S2P2, EMC, and VRE are formed on the gate insulating layer GI1. These are included in the same metal layer pattern. An interlayer insulating layer ILD1 is laminated over the wiring VRS, S2P2, EMC, and VRE.

[0115] Capacitive electrodes CE, wiring S2NB, and S1NB are laminated on the interlayer insulating layer ILD1. These are included in the same metal layer pattern. The interlayer insulating layer ILD2 is laminated over the capacitive electrodes CE, wiring S2NB, and S1NB. The gate insulating layer GI2 is laminated on the interlayer insulating layer ILD2.

[0116] The oxide semiconductor layer OX is laminated on the gate insulating layer GI2. The gate insulating layer GI3 is laminated so as to cover the oxide semiconductor layer OX. Wirings S2NT and S1NT are laminated on the gate insulating layer GI3. The planarization layer PLN1 is laminated so as to cover the wirings S2NT and S1NT.

[0117] Contact holes CH1 and CH2 penetrate the insulating layers PL1N, GI3, GI2, ILD2, ILD1, and GI1, and are in contact with the low-temperature polysilicon layer (specifically, its low-resistance region).

[0118] The contact hole CH3 penetrates the insulating layers PL1N and GI3 and contacts the upper surface of the oxide semiconductor layer OX. The contact hole CH3 further penetrates the oxide semiconductor layer OX and contacts the end face of the hole. The contact hole CH3 further penetrates the insulating layers GI2, ILD2, ILD1, and GI1 and contacts the low-temperature polysilicon layer (the low-resistance region of it).

[0119] Contact holes CH4 and CH5 penetrate the marginal layers PL1N and GI3 and are in contact with the upper surface of the oxide semiconductor layer OX. A passivation layer PV is laminated to cover contact holes CH1 to CH5, and a planarization layer PNL2 is further laminated on top of the passivation layer PV.

[0120] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0121] 105, 107 Low resistance region 108 Low-temperature polysilicon layer 111, 115, 119, 121, 129, 133, 135 Insulating layer 123, 125 Low resistance region 124 oxide semiconductor layer 140, 150, 160, 250, 440, 450, 460, 540, 550, 560 Contact Holes 141, 151, 161, 251, 441, 451, 461, 541, 551, 561 Contact section

Claims

1. a first thin film transistor including a first semiconductor layer on a substrate; a second thin film transistor on the substrate, the second thin film transistor including a second semiconductor layer; one or more upper insulating layers on the substrate; one or more lower insulating layers on the substrate; a metal contact portion in contact with the first semiconductor layer and the second semiconductor layer; Including, the first semiconductor layer and the second semiconductor layer are formed of different materials; the first semiconductor layer, the one or more lower insulating layers, the second semiconductor layer, and the one or more upper insulating layers are stacked in this order when viewed from the substrate; the first semiconductor layer includes a first channel region and first source / drain regions sandwiching the first channel region; the second semiconductor layer includes a second channel region and second source / drain regions sandwiching the second channel region; the metal contact is in a hole penetrating the one or more upper insulating layers and the one or more lower insulating layers and contacts one of the first source / drain regions and one of the second source / drain regions; a diameter of the hole in the lowermost layer of the one or more upper insulating layers is larger than a diameter of the hole in the uppermost layer of the one or more lower insulating layers; the metal contact portion is formed of the same metal material as the source / drain lines of the first thin film transistor and the second thin film transistor; Thin film transistor device.

2. 2. The thin film transistor device according to claim 1, one of the first semiconductor layer and the second semiconductor layer is a low-temperature polysilicon semiconductor layer; the other of the first semiconductor layer and the second semiconductor layer is an oxide semiconductor layer; Thin film transistor device.

3. 2. The thin film transistor device according to claim 1, the one of the second source / drain regions and the one of the first source / drain regions at least partially overlap each other when viewed in a stacking direction; the hole passes through the one of the second source / drain regions; the metal contact portion is in contact with an upper surface of the one of the second source / drain regions and an end surface of the hole, and is in contact with an upper surface of the one of the first source / drain regions; Thin film transistor device.

4. 4. The thin film transistor device according to claim 3, When viewed in the stacking direction, the hole in the one or more upper insulating layers is present within the outline of one of the second source / drain regions; When viewed in the stacking direction, the hole in the one or more lower insulating layers is present within the outline of one of the first source / drain regions. Thin film transistor device.

5. 4. The thin film transistor device according to claim 3, an end surface of the one hole of the second source / drain region is recessed from an end surface of a lower insulating layer immediately below the second semiconductor layer; Thin film transistor device.

6. 2. The thin film transistor device according to claim 1, a thickness of the one of the second source / drain regions within the hole is thinner than a thickness of the one of the second source / drain regions outside the hole; Thin film transistor device.

7. 2. The thin film transistor device according to claim 1, The metal contact portion has a tapered shape. Thin film transistor device.

8. 2. The thin film transistor device according to claim 1, the metal contact portion fills at least a region of the hole below an upper surface of the second semiconductor layer; Thin film transistor device.

9. A method for manufacturing a thin film transistor device, comprising: forming a first semiconductor layer; forming one or more lower insulating layers on the first semiconductor layer; forming a second semiconductor layer of a different material from the first semiconductor layer on an uppermost layer of the one or more lower insulating layers; forming one or more upper insulating layers on the second semiconductor layer; forming holes through the one or more upper insulating layers and the one or more lower insulating layers, exposing a portion of a source / drain region of the first semiconductor layer and a portion of a source / drain region of the second semiconductor layer in the holes; forming a metal pattern in the hole, the metal pattern including a metal contact portion in contact with a part of the first semiconductor layer and a part of the second semiconductor layer, and a source / drain wiring; A method for manufacturing a thin film transistor device.

10. 10. A method for manufacturing a thin film transistor device according to claim 9, comprising: forming the second semiconductor layer by forming holes in source / drain regions of the second semiconductor layer; forming holes through the one or more upper insulating layers and the one or more lower insulating layers; exposing the hole and a peripheral portion of the second semiconductor layer, and over-etching the peripheral portion; A method for manufacturing a thin film transistor device.

11. 10. A method for manufacturing a thin film transistor device according to claim 9, comprising: forming the second semiconductor layer by forming holes in source / drain regions of the second semiconductor layer; forming holes through the one or more upper insulating layers and the one or more lower insulating layers; forming holes penetrating the one or more upper insulating layers by etching using a first photoresist pattern as a mask, thereby exposing the holes and a peripheral edge portion of the second semiconductor layer; removing the first photoresist pattern and forming a second photoresist pattern covering the peripheral portion; forming holes penetrating the one or more lower insulating layers by etching using the second photoresist pattern as a mask; removing the oxide of the first semiconductor layer exposed in the holes through the one or more lower insulating layers; A method for manufacturing a thin film transistor device.

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