Low-resistivity composite silicon-based electrodes

Abstract

A silicon-based electrode forms an interface between a pair of layers: 1. a thin semi-dielectric layer of a lithium (Li) compound, such as lithium fluoride (LiF), disposed on and attached to the electrode surface of the silicon-based electrode; and 2. a molten, ion-concentrated conductive layer of a lithium-containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to create devices such as energy storage devices like batteries. The low resistance of the interface can reduce energy loss and heat generation in the device.

Description

[Technical Field]

[0001] The present invention relates to an interface with a silicon-based layer that reduces interfacial resistance / impedance. More specifically, the present invention relates to a lithium composite that includes a conductive layer and a structural enhancing layer interfacing with a silicon-based layer to reduce interfacial resistance and charge transfer resistance in an energy storage device. [Background technology]

[0002] Integrating energy storage devices such as batteries with microprocessors and memory chips is a key requirement for IoT (Internet of Things) devices. In addition to IoT applications, emerging applications integrating on-board next-generation energy storage devices include mobile devices, communication equipment, remote power such as drones, vehicles, robots, and sensory organs, autonomous functioning machines for the environment, biology, and society, smart dust, or biosensory / drug delivery devices, or a combination thereof.

[0003] Furthermore, electrochemically active materials and processes need to be scaled while being integrated with traditional applications such as electric vehicles, mobile computing and communications devices, and grid storage.

[0004] As human-controlled and autonomous devices become increasingly miniaturized, the total energy consumption requirements from the energy sources powering the electronic devices will decrease. However, while these integrated devices are expected to consume less than 1 watt of power, miniaturization also reduces device volume, meaning that energy and power densities per unit volume will continue to increase in miniaturized devices.

[0005] To increase energy and power density per unit volume, lithium (Li) metal's extremely high theoretical specific capacity (~3860 mAh / g) allows lithium electrode materials to be integrated into the overall cell structure of semi-solid or all-solid-state energy storage devices. In many applications, lithium-based energy storage devices are integrated into and / or interfaced with complementary metal-oxide-semiconductor (CMOS) circuits, resulting in one or more lithium-based components interfacing with silicon (Si) layers. It is also hypothesized that high-energy / power-density storage devices that can be fabricated on a miniaturized scale and mass-produced could be directly applicable to scalable applications such as mobile electronics, electric vehicles, and renewable grid storage.

[0006] In particular, in high-energy and high-power density storage devices, a low-resistivity interface between the silicon-based layer and the lithium-based component is needed to reduce power loss, improve efficiency, and / or prevent degradation of silicon active electrode-containing devices due to volume expansion, overheating, or Li dendrite formation within the device. Summary of the Invention

[0007] According to one embodiment of the present invention, a composite electrode is disclosed that includes a silicon-based electrode that combines two layers (layer pair). The layer pair includes: 1. a thin semi-dielectric lithium conductive layer made of a lithium (Li) compound, such as lithium fluoride, LiF, disposed on and attached to the electrode surface of the silicon-based electrode; and 2. a molten lithium ion-enriched conductive layer (lithium salt layer) of a lithium-containing salt disposed on the semi-dielectric layer. The lithium salt layer is a layer that can condense lithium ions (Li + ) has high conductivity.

[0008] One or more device layers may be disposed on the layer pair, non-limiting examples of which include one or more cathode electrodes, one or more solid polymer electrolyte (SPE) or liquid electrolyte layers, one or more anode layers, or one or more other internal battery component layers, or combinations thereof.

[0009] The layer pair effectively reduces the charge transfer resistance across the silicon interface and the electrolyte / layer pair interface, resulting in a surprisingly low impedance / resistance interface between the device layer and the silicon-based electrode. This layer pair has been used in devices with silicon-based electrodes, including microresistors, next-generation ion-based analog memory devices, and energy storage devices such as lithium-ion batteries.

[0010] Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings, which are briefly described herein, and which illustrate various devices, structures and process steps associated with embodiments of the present invention. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view of one embodiment of a symmetric cell including two layer pairs symmetrically positioned between two silicon-based electrodes and around a separator layer. [Figure 2] FIG. 1C is a cross-sectional view of an alternative embodiment of a cell including a layer pair disposed on a silicon-based electrode with a separator layer between the solid polymer electrolyte (SPE) layer and a portion of the device layer disposed on the layer pair. [Figure 3] 1 is a photomicrograph showing a thin semi-dielectric layer of a lithium (Li) compound, such as lithium fluoride, LiF, disposed on and adhering to the electrode surface of a silicon-based electrode. [Figure 4] 1 is a photomicrograph showing a layer pair disposed on a silicon-based electrode with one or more device layers disposed on the layer pair. [Figure 5]An RC (resistor / capacitor) model of an energy storage device (e.g., a symmetric cell energy storage device) used to fit electrochemical impedance spectroscopy (EIS) spectra. [Figure 6] 6 is a Nyquist plot fitted using the RC model of FIG. 5 to determine the component values ​​of the symmetric cell. [Figure 6A] FIG. 7 is a magnified view of the high- to mid-frequency data points from the Nyquist plot of FIG. 6. [Figure 7] FIG. 1 is a block diagram showing the layer pair disposed on a silicon-based electrode for use in a lithium battery. [Figure 8] 1 is a flow chart of a process for forming a lithium battery using layer pairs to substantially reduce the resistance at the interface with a silicon-based electrode. DETAILED DESCRIPTION OF THE INVENTION

[0012] It will be understood that embodiments of the present invention are not limited to the exemplary methods, apparatus, structures, systems and devices disclosed herein, but instead are more broadly applicable to other alternative and broader methods, apparatus, structures, systems and devices that will become apparent to those skilled in the art given this disclosure.

[0013] Furthermore, it should be understood that the various layers, structures, or regions, or combinations thereof, shown in the accompanying figures are not drawn to scale, and that one or more layers, structures, or regions, or combinations thereof, of a commonly used type may not be explicitly shown in a given figure, and this does not mean that the not-explicitly shown layer, structure, or region, or combinations thereof, are omitted from the actual device.

[0014] Additionally, certain elements may be omitted from the figures for clarity or simplicity, or both, unless the description is necessarily focused on the omitted elements. Furthermore, the same or similar reference numbers used throughout the figures are used to indicate the same or similar features, elements, or structures, and thus, a detailed description of the same or similar features, elements, or structures will not be repeated for each of the figures.

[0015] The semiconductor devices, structures, and methods disclosed according to embodiments of the present invention can be employed in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing embodiments of the present invention can include, but are not limited to, semiconductors, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, neural networks, etc. Systems and hardware incorporating the present invention in semiconductor devices and structures are contemplated as embodiments of the present invention.

[0016] As used herein, "height" refers to the vertical size of an element (e.g., layer, groove, hole, opening, etc.) in cross section or elevation as measured from the bottom to the top of the element, or as measured relative to the surface on which the element is placed, or both.

[0017] Conversely, "depth" refers to the vertical extent of an element (e.g., a layer, trench, hole, opening, etc.) in a cross section or elevation, measured from the top to the bottom of the element. Terms such as "thick," "thickness," "thin," or derivatives thereof, are sometimes used instead of "height."

[0018] As used herein, "lateral," "lateral side," "side," and "lateral surface" refer to the side of an element (e.g., a layer, opening, etc.), such as the left or right side in a drawing.

[0019] As used herein, "width" or "length" refers to the size of an element (e.g., a layer, groove, hole, opening, etc.) in a drawing as measured from the side of the element to the opposite surface. Terms such as "thick," "thickness," "thin," or derivatives thereof may be used in place of "width" or "length."

[0020] As used herein, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods oriented in the drawings depicted. For example, as used herein, "vertical" refers to a direction perpendicular to the top surface of a substrate in an elevational view, and "horizontal" refers to a direction parallel to the top surface of a substrate in an elevational view.

[0021] As used herein, unless otherwise specified, terms such as "on," "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element is present on a second element and that intervening elements may be present between the first and second elements. As used herein, unless otherwise specified, the terms "on," "overlying," "atop," "on top," "positioned on," or "positioned atop," "disposed on," or the term "directly" used in connection with the terms "in contact" or "direct contact," mean that a first element and a second element are connected without an intervening element, such as an intermediate conductive, insulating, or semiconducting layer, present between the first and second elements.

[0022] It is understood that these terms may be affected by the orientation of the device being described: for example, if the device is rotated upside down, the meaning of these descriptions may change, but the descriptions remain valid because they describe the relative relationships between features of the invention.

[0023] Now, referring to the figure.

[0024] 1 shows a cross-sectional view of one embodiment of a symmetric cell 100 including two layer pairs (150 / 150U) symmetrically positioned between two silicon-based electrodes 105 / 105U and around a separator layer 115. This symmetric cell 100 is used for electrochemical impedance spectroscopy (EIS) analysis, as described below.

[0025] Each layer pair 150 / 150U comprises a semi-dielectric layer 111 / 111U and a fused ion conductive layer 112 / 112U. Each fused ion conductive layer 112 / 112U has a respective interface 140 / 140U with the semi-dielectric layer 111 / 111U. Each semi-dielectric layer 111 / 111U has a semi-dielectric layer thickness 121, and each fused ion conductive layer 112 / 112U has a fused ion conductive layer thickness 122.

[0026] Each silicon-based electrode 105 / 105U is combined with a respective layer pair 150 / 150U to form a composite electrode 105 / 150.

[0027] Separator layer 115 electrically insulates layer pair 150 and silicon-based electrode 110 on one side of separator layer 115 from layer pair 150U and silicon-based electrode 110U on the other side of separator layer 115. That is, separator layer 115 substantially prevents electrons from flowing between layer pair 150 / 150U and silicon-based electrode 110 / 110U on opposite sides of separator layer 115. This prevents electrical shorting of cell 100. However, separator layer 115 allows the passage of ions, such as lithium ions (Li+). Thus, separator layer 115 allows ionic current to flow while blocking most electronic current.

[0028] Included is a solid polymer electrolyte (SPE) layer 114. In this embodiment 100, a separator layer 115 divides the solid polymer electrolyte (SPE) layer 114 into an upper SPE layer 114B above the separator layer 115 and a lower SPE layer 114A below the separator layer 115. The SPE layers 114A / 114B are also saturated through the separator layer 115.

[0029] In some embodiments, the electrolyte layer 114 (e.g., 114A / 114B) is a garnet / polymer electrolyte composite (e.g., Li 6.5 La3Zr 1.5 Ta 0.5 O 12 / PEO composite), which functions together as a solid polymer electrolyte 114 and separator 115. In other embodiments, if the electrolyte is harder than Li metal (e.g., sputtered LiPON), the electrolyte functions as both the separator and the electrolyte, and therefore no separator is required.

[0030] 1, the reference numeral "U" indicates that the layer is located above (or opposite to) the separator layer 115 relative to the layer without the reference numeral "U" and is symmetrical about the separator layer 115. In the following discussion, without loss of generality, when describing common symmetrical layers, the "U" in the general numerical notation may be omitted for clarity.

[0031] The layer pair 150 has a facing top surface 151 (the separator 115 side) and a facing bottom surface 152 (electrode side 152 / 152U). The layer pair 150 is disposed directly on the silicon-based electrode 110 such that the facing bottom surface 152 is in direct physical and electrical contact with the facing electrode 131 (the semi-dielectric layer 111 side) of the silicon-based electrode 110. The electrode interfaces 131 / 152 (131U / 152U, respectively) are where the facing bottom surface 152 (electrode side 152 / 152U) and the facing electrode 131 / 131U are in direct contact, respectively.

[0032] In some embodiments, silicon-based electrodes 110 / 110U are disposed on electrode contacts 105 / 105U, respectively. Silicon-based electrode 110 has silicon-based electrode surfaces 132 / 132U that are in electrical contact with electrode contacts 105 / 105U, and electrode facing surfaces 131 / 131U are in electrical contact with semi-dielectric layer 111 to bottom surface 152 (or semi-dielectric layer bottom surface 152, i.e., the electrode contact 105 side) at electrode interfaces 131 / 152 (131U / 151U, respectively). In some embodiments, silicon-based electrode 110 has a diameter of about 15.5 millimeters (mm), and electrode facing surface 131 has an area of ​​about 1.88 cm 2 This is a disc.

[0033] Optional electrode contacts 105 / 105U are made of a conductive material, such as a metal, such as copper (Cu), titanium (Ti), platinum (Pt), nickel (Ni), aluminum (Al), gold (Au), tungsten (W), or titanium nitride (TiN). Electrode contacts 105 / 105U may include a single layer of conductive metal, such as a conductive metal nitride, or a material stack including at least two different conductive metals or conductive metal nitrides, or both. In one example, electrode contact 105 may include, from bottom to top, a stack (not shown) of titanium (Ti), platinum (Pt), and titanium (Ti). Electrode contacts 105 can be formed using deposition techniques well known to those skilled in the art.

[0034] If present, the electrode contact 105 may be mechanically or chemically attached, glued, or bonded to the silicon electrode surface 132 of the silicon-based electrode 110 .

[0035] The silicon-based electrode 110 / 110U may include silicon as well as a semiconductor material and / or any other material with semiconductor properties. In one embodiment, the silicon-based electrode 110 / 110U is a bulk semiconductor substrate. By "bulk," we mean that the base substrate is composed entirely of at least one semiconductor material, such as crystalline silicon. In one example, the silicon-based electrode 110 / 110U may be composed entirely of silicon, which may be monocrystalline. In some embodiments, the bulk semiconductor may include a multilayer semiconductor material stack including at least two different semiconductor materials, one of which is silicon. In one example, the multilayer semiconductor material stack may include a stack of Si and a silicon-germanium alloy, in any order. In another embodiment, the multilayer semiconductor material may include a stack of Si and one or more silicon-based alloys, such as silicon-germanium or a carbon-doped silicon-based alloy, in any order.

[0036] According to the present application, the silicon electrode 110 is made of a material containing silicon, i.e., the silicon electrode 110 is silicon-based. The term "silicon-based" is used throughout the present application to refer to a material that contains at least silicon and has semiconductor properties. Examples of silicon-based materials that can be used for the silicon-based electrode 110 include silicon (Si), silicon-germanium alloys, or carbon-doped silicon-based alloys. Typically, the silicon-based electrode 110 is made of only silicon (Si).

[0037] The silicon-based material included in the silicon-based electrode 110 may be an amorphous or crystalline semiconductor material. The silicon-based electrode 110 may be entirely non-porous, entirely porous, or may include some regions that are non-porous and other regions that are porous. The silicon-containing material may be undoped, doped, or may include some regions that are doped and other regions that are undoped. The dopant may be a p-type dopant or an n-type dopant.

[0038] "P-type" refers to the addition of impurities to an intrinsic semiconductor that create a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of p-type dopants in the silicon-containing material that provides the silicon-based electrode 110 is 1E16 atoms / cm 3 ~3E20atoms / cm 3 The range can be up to.

[0039] "N-type" refers to the addition of an impurity that contributes free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The concentration of n-type dopants in the silicon-containing material of silicon-based electrode 110 / 110U is 1E16 atoms / cm3 ~1E21atoms / cm 3 It can be up to.

[0040] Illustrative examples of silicon-containing materials that can be used for the silicon-based electrode 110 / 110U include non-porous silicon, partially porous crystalline silicon, single-crystalline non-porous silicon, crystalline silicon, low-resistivity doped crystalline silicon, boron-doped crystalline silicon, or boron-doped crystalline porous silicon. In one embodiment, the silicon-based electrode 110 is made of a 1×10 19 atoms / cm 3 ~3×10 20 atoms / cm 3 Boron-doped crystalline silicon having a boron dopant concentration of 0.15 to 0.5% is used.

[0041] The term "low-resistivity doped crystalline silicon" refers to a silicon-based electrode 110 that is a unitary structure (i.e., a monolithic structure) and includes a non-porous region and a porous region, as defined in U.S. Serial No. 16 / 026,461, filed July 3, 2018, entitled "Battery Structure with Anode Structure Containing a Porous Region and Method of Operation," the contents and disclosure of which are incorporated herein by reference in their entirety.

[0042] Low resistivity doped crystalline silicon that can be used as the silicon-based electrode 110 / 110U can be produced by anodizing a substrate containing at least a top region of p-type silicon material, cleaned using standard organic cleaning processes, in a solution of concentrated HF (49%) and applying a current of 0.05 mA / cm , with platinum as the anode and the substrate as the cathode. 2 ~150mA / cm 2 The current density is typically 1 mA / cm. 2 , 2mA / cm 2 , 5mA / cm 2 , 50mA / cm2 , or 100mA / cm 2 In a preferred embodiment, the current density is 1 mA / cm 2 ~10mA / cm 2 The current density can be applied for 1 second to 5 hours. In some examples, the current density may be applied for 5 seconds, 30 seconds, 20 minutes, 1 hour, or up to 3 hours. In one embodiment, the current density is applied for 10 seconds to 4800 seconds, specifically 10 19 atoms / cm 3 Doping levels in the range of 0.1 to 0.5°C may be applied. Anodization is typically performed at nominal room temperature of 20°C to 30°C, or at temperatures slightly elevated above room temperature. After anodization, the structure is typically rinsed with deionized water and then dried.

[0043] The semi-dielectric layer 111 (111U) is a thin layer 121 that adheres well to the silicon-based electrode 110 (110U, respectively) at the electrode facing surface 131 and electrode interface 131 / 151 (131U / 151, respectively). The thickness 121 of the semi-dielectric layer 111 involves a trade-off. Because the semi-dielectric layer 111 is an electrical insulator, using a dielectric material in contact with the electrode facing surface 131 typically increases the resistance / impedance at the electrode interface 131 / 152 (131U / 152U) and between the silicon-based electrode 110 and the fused ion conductive layer 112. However, keeping the semi-dielectric layer 111 very thin 121 reduces the resistance at this electrode interface 131 / 152. The thickness 121 of the semi-dielectric layer 111 must still be large enough to allow strong adhesion to the silicon-based electrode 110 and maintain uniform contact across the entire electrode facing surface 131. In some embodiments, the thickness 121 of the semi-dielectric layer 111 is between 15 nanometers (nm) and 30 nm, in other embodiments, the thickness 121 is between 15 nm and 23 nm, and in other embodiments, the thickness 121 is between 18 nm and 23 nm.

[0044] In some embodiments, the semi-dielectric layer 111 is comprised of a lithium-containing dielectric. In some embodiments, the semi-dielectric layer 111 is comprised of lithium fluoride (LiF). The lithium fluoride semi-dielectric layer 111 can be deposited on the silicon-based electrode 110 by evaporation to form an amorphous lithium fluoride layer 111 disposed directly on the electrode facing 131 of the silicon-based electrode 110, forming the electrode interface 131 / 152.

[0045] The semi-dielectric layer 111 can be made of other materials including, but not limited to, titanium dioxide, niobium oxide, rubidium oxide, tungsten oxide, aluminum oxide, zinc oxide, zirconium oxide, and lithium versions of any of the foregoing.

[0046] Evaporation involves providing a lithium fluoride material. The source material is then evaporated in a vacuum. The vacuum allows lithium fluoride, LiF, vapor particles to travel to the silicon-based electrode 110, where the vapor particles condense and return to a solid state. Evaporation involves an evaporation apparatus, including at least a vacuum pump and an energy source, that evaporates the source material to be deposited, e.g., LiF. Evaporation processes include, but are not limited to, electron beam evaporation, thermal evaporation using Ni, Ta, Mo, or W boats, or radio frequency (RF) sputtering. The pressure during deposition is typically controlled between 10E-8 and 10E-4 Torr, and the temperature is typically controlled between 875°C and 1180°C. The thickness 121 of the semi-dielectric layer 111 can be controlled by pre-measuring the mass of the evaporated material or via a quartz crystal microbalance rate monitor.

[0047] In some embodiments, 5 / 8-inch diameter crystalline boron-doped (at the concentrations defined above) silicon disks 110 were etched in 4% to 10% hydrofluoric acid for 25 to 60 seconds to remove the native oxide layer. These silicon disks were then immediately attached to steel plates 105 and vacuum-sealed as target objects in an evaporation system located in a nitrogen-environment glove box. A layer of lithium fluoride, LiF, was thermally evaporated using a pre-measured amount of LiF between 3.5 and 6.5 milligrams (mg) and deposited onto a conductive powder sample holder attached to the evaporation system's user-controlled power supply. The LiF powder was resistively heated in a tungsten boat, and a 2×10 -5 The boat was completely evaporated by applying a current of 20 to 50 amps, which heated the boat to above 1100°C under a vacuum of less than 1 bar.

[0048] Thereafter, fused ion conductive layer 112 is deposited on semi-dielectric layer 111 to complete the formation of layer pair 150. By depositing fused ion conductive layer 112, mating interface 140 is formed between semi-dielectric layer 111 and fused ion conductive layer 112. Mating upper surface 151 is the surface of fused ion conductive layer 112 opposite mating interface 140.

[0049] The fused ion conductive layer 112 is made of a material that has a high conductivity for ions, particularly for lithium ions (Li+). In some embodiments, the fused ion conductive layer 112 is made of a lithium-containing salt. In some embodiments, the fused ion conductive layer 112 is made of one or more of the following lithium-containing salts: lithium hexafluorophosphate, lithium perchlorate, lithium trifluoromethanesulfonate, lithium fluoride, LiBF4, LiBF6, lithium chloride, lithium phosphate compounds, lithium bromide compounds, lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), lithium difluoro(oxalato)borate (LiDFOB), or lithium bis(oxalato)borate (LiBOB).

[0050] In some embodiments, the fused ion conductive layer 112 is comprised of bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0051] The molten ion conductive layer 112 can be formed by depositing a layer of lithium-containing salt, as defined above, on the semi-dielectric layer 111. Deposition of the lithium-containing salt layer can include any conventional deposition technique, such as drop coating followed by a doctor blade to provide a homogeneous and uniform layer of lithium-containing salt on the surface of the semi-dielectric layer 111. The lithium-containing salt layer is then heated to a temperature that provides molten lithium-containing salt. In some embodiments of the present application, the heating can be performed at a temperature greater than 350 degrees Celsius (°C) to provide molten lithium ions. The heating can be performed in an inert atmosphere, such as helium (He), neon (Ne), argon (Ar), or nitrogen (N), or a combination thereof. In one example, heating is performed at 415°C in a nitrogen glove box. The molten salt increased the adhesion (wetting) of the highly mobile lithium on the semi-dielectric layer 111, providing a uniform layer thickness 122. The molten lithium-containing salt is then cooled to form the molten ion conductive layer 112 comprised of the molten lithium-containing salt. Cooling occurs from the heating temperature to nominal room temperature, which can be in the range of 15° C. to 25° C. or lower. Upon cooling, molten ion conductive layer 112 is a solid continuous layer formed on semi-dielectric layer 111 at mating interface 140.

[0052] In some embodiments, the fused ion conductive layer 112 can have a thickness 122 between 1 nm and 500 nm. In other embodiments, the fused ion conductive layer 112 can have a thickness 122 between 1 nm and 50 nm. Other thicknesses are contemplated.

[0053] On the other side of separator layer 115, the order of deposition of the layers may be reversed.

[0054] FIG. 2 is a cross-sectional view of an alternative embodiment 200 of a single layer pair 150 disposed on a silicon-based electrode 110 with one or more device layers 175 disposed on the layer pair 150 .

[0055] Included is a solid polymer electrolyte (SPE) layer 114. In this alternative embodiment 200, a separator layer 115 divides the solid polymer electrolyte (SPE) layer 114 into an upper SPE layer 114B above the separator layer 115 and a lower SPE layer 114A below the separator layer 115.

[0056] In some embodiments, the electrolyte layer 114 is a garnet / polymer electrolyte composite (e.g., Li 6.5 La3Zr 1.5 Ta 0.5 O 12 / PEO composite), which functions together as a solid polymer electrolyte 114 and separator 115. In other embodiments, when the electrolyte is harder than Li metal (e.g., sputtered LiPON), the electrolyte functions as both the separator and the electrolyte, and therefore no separator is required.

[0057] In FIG. 2 , the layers 175 (e.g., 114 (114A and 114B), 115, 116, 118, 120) formed on the opposing top surface 151 are referred to as device layers, typically 175. The device layer 175 can take multiple forms and combinations depending on the structure of the device / embodiment 100. As will be described below, the combination of the silicon-based electrode 110, layer pair 150, and one or more device layers 175 results in reduced resistance / impedance throughout the structure due to reduced resistance / impedance at the electrode interface 131 / 152 between the paired layer 150 and the silicon-based electrode 110.

[0058] In one embodiment of the battery, electrolyte layer 114 is disposed on opposing upper surface 151 as device layer 175. Electrolyte layer 114 can be any known electrolyte used in prior art batteries. In one embodiment, electrolyte layer 114 is comprised of a solid electrolyte or a solid polymer electrolyte (SPE).

[0059] Non-limiting embodiments of the solid polymer electrolyte layer (SPE) 114 include any solid polymer material capable of conducting Li ions. In one embodiment, the solid polymer electrolyte layer 114 is comprised of a mixture of a polymeric structural host material, a Li-conducting / plasticizing material, and a lithium-containing salt.

[0060] In such embodiments, the mixture comprises 35 to 50 weight percent polymeric structural host material, 15 to 25 weight percent conductive / plasticizing material, and 30 to 45 weight percent lithium-containing salt. In some embodiments, the polymeric host material and conductive / plasticizing material are dissolved in anhydrous acetonitrile having a solids:solvent ratio of between 1:2 and 1:10, with one preferred ratio being 1:3. This mixture can be made using techniques well known to those skilled in the art.

[0061] Examples of polymeric structural host materials include at least one of poly(ethylene oxide) (PEO), poly(propylene oxide) (PPO), poly(dimethylsiloxane), poly(vinyl chloride), or polycaprolactone.

[0062] Examples of Li conductive / plasticizing materials include at least one of succinonitrile (SN), poly(ethylene glycol) (PEG), an aprotic organic solvent, or dimethyl sulfoxide (DMSO), or a combination thereof.

[0063] Exemplary lithium-containing salts that can be used to form the polymer solid electrolyte layer include, but are not limited to, lithium hexafluorophosphate, lithium perchlorate, lithium trifluoromethanesulfonate, lithium fluoride, LiBF, lithium chloride, lithium phosphate compounds, lithium bromide compounds, lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), lithium difluoro(oxalato)borate (LiDFOB), or lithium bis(oxalato)borate (LiBOB).

[0064] The lithium-containing salt present in solid polymer electrolyte (SPE) layer 114 may be the same as or different from the lithium-containing salt used in providing fused ion conducting layer 112. Typically, the lithium-containing salt used in solid polymer electrolyte layer 114 is the same as the lithium-containing salt used in fused ion conducting layer 112. In one embodiment, the lithium-containing salt used in both solid polymer electrolyte layer 114 and fused ion conducting layer 112 comprises lithium bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0065] In one exemplary embodiment, the silicon-based electrode 110 is made of boron-doped crystalline silicon, the semi-dielectric layer 111 is made of LiF, the fused ion conducting layer 112 is made of bis(trifluoromethanesulfonyl)imide (LiTFSI), and the polymer solid electrolyte layer 114 is made of a mixture of polycaprolactone, succinonitrile (SN), and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0066] The solid polymer electrolyte layer 114 can be formed using a deposition process such as drop casting, spin coating, doctor blading, or the like.

[0067] In some embodiments, an optional interface layer 116 may be formed on the solid polymer electrolyte layer 114. The optional interface layer 116 may have a thickness of 1 nm to 50 nm. In some embodiments, the interface layer 116 is omitted. When present, the interface layer 116 forms an interface 116 between the solid polymer electrolyte layer 114 and the counter electrode 118.

[0068] In some embodiments, the interfacial layer 116 is a solid electrolyte interphase (SEI) layer that develops at the cathode / electrolyte interface with electrochemical cycling. The interfacial layer 116 is conductive to Li ions but not to electrons.

[0069] In some embodiments (typically used when the counter electrode 118 is made of a silicon-containing material similar to or the same as the material making up the silicon-based electrode 110), the interfacial layer 116 is made of a lithium-containing salt. The lithium-containing salt making up the interfacial layer 116 can be one or more of the lithium-containing salts used in the fused ion conductive layer 112 described above. In one embodiment, the interfacial layer 116 and the fused ion conductive layer 112 are made of the same lithium-containing salt. In an alternative embodiment, the lithium-containing salt making up the fused ion conductive layer 112 and the interfacial layer 116 are different materials. In one embodiment, the fused ion conductive layer 112 and the interfacial layer 116 are both made of lithium bis(trifluoromethanesulfonyl)imide (LiTFSI).

[0070] In some embodiments (typically used when the counter electrode 118 is made of a silicon-containing material similar to or the same as the material from which the silicon-based electrode 110 is made), the interfacial layer 116 is made of a lithium-containing salt mixed within a polymer. In one embodiment, the interfacial layer is made of polyaniline mixed with the lithium salt LiTFSI.

[0071] In some embodiments (typically used when the counter electrode 118 is made of a cathode or electrode material), the interface layer 116 is made of an interface additive material such as, for example, a carbon (C)-based material, gold (Au), or a dielectric oxide material such as aluminum oxide. The material making up the interface layer 116 may be a mixture of any combination of electrically insulating as well as Li-ion conducting components, such as, but not limited to, LiNbO3, LiZrO2, Li4SiO4, or Li3PO4.

[0072] Depending on the interfacial layer 116 material selected, the interfacial layer 116 can be formed using a deposition process including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), evaporation, electrochemical plating, drop casting, spin coating, or atomic layer deposition (ALD).

[0073] In embodiments in which the silicon-based electrode 110 has an electrode polarity, the counter electrode 118 has a counter electrode polarity that is opposite to the electrode polarity. In some embodiments herein, the silicon-based electrode 110 may be an anode electrode, and the counter electrode 118 may be a cathode electrode. In other embodiments herein, the silicon-based electrode 110 may be a cathode electrode, while the counter electrode 118 may be an anode electrode.

[0074] A counter electrode 118 can be formed on the solid polymer electrolyte (SPE) layer 114 or, optionally, on the interfacial layer 116. The counter electrode 118 can function as an anode or a cathode electrode, but typically the counter electrode 118 is a lithium-hosting electrode, e.g., a cathode.

[0075] In embodiments in which the silicon-based electrode 110 is an anode electrode, the counter electrode 118 is a cathode electrode. In such embodiments, the cathode electrode (i.e., the counter electrode 118) may also be made of a silicon-based material. When the counter electrode 118 is made of a silicon-based material, the material of the counter electrode 118 may be compositionally the same as or different from the material from which the silicon-based electrode 110 is made, and one of the materials for the silicon-based electrode 110 described above may be used.

[0076] In some embodiments, when the counter electrode 118 functions as the cathode electrode 118, the material making up the cathode electrode 118 is a lithium-containing cathode material. The lithium-containing cathode material may include, for example, a lithium-based mixed oxide. Examples of lithium-based mixed oxides that can be employed as lithium-containing cathode materials include, but are not limited to, lithium cobalt oxide (LiCoO), lithium nickel oxide (LiNiO), lithium manganese oxide (LiMnO), lithium manganese oxyfluoride (LiMnOF), lithium vanadium pentoxide (LiVO), nickel manganese cobalt lithium (NMC), nickel cobalt aluminum oxide (NCA), any combination of a sulfur-based material with a structural supporting element such as lithium and iron, or lithium iron phosphate (LiFePO).

[0077] In some embodiments, for example, when a polymer or liquid electrolyte 114 is used, the layer of lithium-containing cathode (counter electrode 118) material may be formed using a deposition process such as slurry casting, lamination and calendaring, or electroplating. In one embodiment, the layer of lithium-containing cathode material is formed by sputtering when using a non-liquid-based electrolyte using any conventional precursor feedstock or combination of precursor feedstocks. In one example, a lithium precursor feedstock and a cobalt precursor feedstock are employed in forming a lithium cobalt mixed oxide.

[0078] Sputtering can be performed in a mixture of an inert gas and oxygen. In such embodiments, the oxygen content of the inert gas / oxygen mixture can be between 0.1 atomic percent and 70 atomic percent, with the remainder of the mixture comprising an inert gas. Examples of inert gases that can be used include argon, helium, neon, nitrogen, or any combination thereof, in combination with oxygen.

[0079] In some embodiments, layers of lithium-containing cathode 118 material may be formed by slurry casting, which may include a mixture of electrochemically active (cathode material, electronically conductive material (e.g., carbon-based material)) and inactive (binder material) components. The thickness of such layers may range from 5 micrometers to 500 micrometers. These slurries may also have electrolyte components in the mixture, along with a lithium-based salt.

[0080] In embodiments in which silicon-based electrode 110 is a cathode electrode, counter electrode 118 is an anode electrode. In such embodiments, the anode electrode (i.e., counter electrode 118) may be a second silicon-based electrode. This second silicon-based electrode 118 may be compositionally the same as or different from silicon-based electrode 110.

[0081] In some embodiments, the anode electrode (i.e., counter electrode 118) comprises a lithium ion source material or a lithium intercalation active material. Examples of materials that can be used as the anode electrode 118 include lithium metal, e.g., Li x Examples of suitable anode electrodes include, but are not limited to, lithium-based alloys such as Si, pre-lithiated carbon-based materials, pre-lithiated silicon-based materials, or lithium-based mixed oxides such as, for example, lithium titanium oxide (LiTiO). The anode electrode can be formed using deposition techniques well known to those skilled in the art. In some embodiments, the anode electrode can be formed by sputtering.

[0082] A current collector 120 or counter electrode 118 contact 120 may be formed on the counter electrode 118. The current collector 120 / counter electrode contact 120 is made of one or more conductive materials similar to or the same as the materials making up the electrode contact 105. In some embodiments, the counter electrode contact 120 can be formed using techniques well known to those skilled in the art.

[0083] 2, the polymer solid electrolyte layer has a lower region 14A and an upper region 14B, with a separator (or dielectric region) 115 between the lower region 114A and the upper region 114B. The separator (or dielectric region) 115 may be comprised of at least one of polyacrylonitrile (PAN), polyethylene oxide (PEO)-based copolymer matrix or structure membrane, quaternized polysulfone membrane, electrospun polynidene fluoride, or methyl methacrylate (MMA) / polyethylene (PE) composite.

[0084] The separator layer 115 electrically insulates the silicon-based electrode 110 from the counter electrode 118. That is, the separator layer 115 substantially prevents electrons from flowing between the silicon-based electrode 110 and the counter electrode 118. However, the separator layer 115 does allow ions, such as lithium ions (Li+), to pass through. Thus, the separator layer 115 allows ionic current to flow while substantially preventing any electronic current. In some embodiments in which a liquid electrolyte 116 is employed, the separator material may comprise a liquid-permeable membrane, such as Nafion.

[0085] In some embodiments, the cell 200 can be used as a microresistor. For example, when lithium is intercalated into the electrode, the resistance of the cell changes. By controlling the amount of lithium transferred to the electrode 110 and keeping that amount constant, the cell 200 has a specific resistance or resistance state. By creating or changing the resistance state of the cell, the device can be used as a resistance-based computing device, where memory is stored as a resistance state held within the cell. In some embodiments, the variable resistance state cell has a cathode 118, an electrolyte 114, and a host anode (e.g., silicon, carbon) 110.

[0086] 3 is a photomicrograph 300 showing a thin semi-dielectric layer 111 of a lithium (Li) compound, e.g., lithium fluoride, LiF, disposed on and adhered to the opposing electrode surface 131 of the silicon-based electrode 110. The thickness 121 of the semi-dielectric layer 111 is 23.29 nm. Note that the fused ion conductive layer 112 is not shown in this photomicrograph 300, and the layer pair 150 has not been formed.

[0087] In the micrograph 300, it can be seen that the adhesion between the semi-dielectric layer 111 and the silicon-based electrode 110 is excellent.

[0088] Semi-dielectric layer 111 was fabricated by evaporating 5.7 mg of LiF powder at 30 amperes to 33 amperes in an evaporation system, as described above, and condensing the LiF on surface 152 of opposing electrode 131 .

[0089] 4 is a micrograph 400 showing a layer pair 150 disposed on a silicon-based electrode 110 having one or more device layers 175 disposed on the layer pair 150. The micrograph represents the structure 400 after disassembly of the symmetric cell, i.e., the structure 100 after EIS testing. The top half (designated "U's") of the symmetric cell 100 was separated during cutting of the symmetric cell 100, thereby displaying only one half of the symmetric cell 100.

[0090] Semi-dielectric layer 111 is fabricated by evaporating and condensing LiF powder as described in FIG. 3. Furthermore, fused ion-conducting layer 112 is fabricated by depositing LiTFSI salt and heating it until the molten phase forms a well-adhered fused ion-conducting layer 112 on semi-dielectric layer 111, forming layer pair 150. Layer pair 150 is formed on silicon-based electrode 110 as described above. Semi-dielectric layer 111 has a thickness 121 of 26.04 nm, and fused ion-conducting layer 112 has a thickness 122 of 39.75 nm. Electrode interface 131 / 152 is shown.

[0091] The interphase layer 425, which is the device layer 175, is formed by the transfer of material, ions, and electrons throughout the structure 400 upon cell completion, resulting in an inherent voltage difference between the two electrodes of the device structure 400. Furthermore, the small applied potential amplitude used in EIS measurements can promote the mobilization of Li ions within the system, thus promoting the formation of the interphase layer 425. Typically, the interphase layer 425 occurs due to a reaction between the electrolyte material 114 and the electrode surfaces 110 / 110U, forming the interphase layer 425. The solid electrolyte interphase (SEI) layer 425 electrically insulates the electrodes while promoting ionic charge mobility. In this example, the interphase layer 425 is 42.49 nm thick.

[0092] FIG. 5 is an RC model 500 of a symmetric cell energy storage device, for example, silicon / layer pair / SPE-PAN / layer pair / silicon, used to fit electrochemical impedance spectroscopy (EIS) generated spectra.

[0093] Generally, in EIS analysis, R is calculated as the real part of the impedance at the high or highest frequency (leftmost data point) on the Nyquist plot, as shown in Figure 6. s is measured / estimated. R s is the pure resistance component, called ohmic resistance or series resistance, between electrodes such as the anode and cathode of a battery, and is often associated with the contact resistance of the cell, or the electrolyte resistance in the cell due to the electrical conductivity of the electrolyte, or both.

[0094] Generally, the resistive component in model 500 refers to a resistor-like element in the cell's electrochemical model configuration, and the capacitor element refers to the cell's impedance component that has a voltage / current phase shift (towards -90 degrees) relative to the current through the resistive element in the component AC current response at a given frequency. For example, EIS elements with high capacitance characteristics (e.g., "C" elements) often correspond to one or more surfaces associated with layers, such as non-intimate contact (exfoliation layers), in cell 100 / 200. A constant phase element (CPE) is an element in the cell impedance that can maintain a constant phase of the AC current response over a given frequency range (often associated with an in-situ grown or established transition layer). These elements are often utilized in optimal RC models when interphase layers are formed in-situ, or interfacial additive layers are deposited in-situ or ex-situ, or both.

[0095] This model uses a series or ohmic related resistance, R s in series with the parallel combination of resistor R1 and capacitor element C1 and its associated impedance, and with the parallel combination of resistor R2 and constant phase element CPE2, and also with a "Warburg" impedance element Ws1 connected in series.

[0096] The coupling elements R1 and C1 in the RC model 500 are assumed to represent the real and imaginary components of the impedance detected as a current at a given applied voltage (e.g., 50 mV) over a high (1 MHz) to medium (~100 Hz) frequency range. These elements are assumed to represent the electrode interface 131 / 152, i.e., the electrode facing 131 in electrical contact with the semi-dielectric layer 111 to bottom surface 152 (or the semi-dielectric layer bottom surface 152). The R1 / C1 time constant present in the RC model is therefore representative of the charge transfer resistance across the layer pair / silicon interface. The combined impedance of the resistance R2 and the capacitance CPE2, a localizing element, is assumed to represent the interface between the interfacial layer 425 and the SPE 114. The R2 / CPE2 time constant is assumed to represent the magnitude of the higher impedance due to in situ interface formation.

[0097] The Warburg impedance, Ws1, models the 100 / 200 impedance effect due to the diffusion of ions, e.g., lithium ions, through the electrode and electrolyte cell components. Typically, in EIS analysis of cells with high ion diffusion, the Warburg impedance component of the cell over the mid-range (~100 Hz) to low-range (200 mHz) frequency range, due to the electrode 110 / 118, or mass transport associated with the electrolyte (electrolyte migration), or both, is observed as a roughly 45-degree "straight, diagonal" section of the Nyquist plot.

[0098] The series resistance Rs represents the purely resistive component of impedance, related to the cell's contact resistance, the electrolyte resistance in the cell due to the electrical conductivity of the electrolyte, or both. Therefore, the value of Rs affects the ease of movement of charge particles within the cell, and therefore has a significant impact on the power loss and heat generated in the battery / cell 100 / 200. The present invention, including the thin semi-dielectric layer 111 included in the layer pair 150, can significantly reduce the resistance value and resistance per area (resistivity) of Rs by approximately 5 to 10 times compared to currently known structures. Therefore, the use of the thin semi-dielectric layer 111 in the layer pair 150 can reduce power loss and heat generated in the battery / cell 100 / 200.

[0099] FIG. 6 is a Nyquist plot 600 with fitted plots 625, 615 from the RC model 500 used in the EIS analysis described in FIG.

[0100] The battery structure used for Nyquist plot 600 was a symmetric cell including a silicon-based electrode 110 with a layer pair 150 and a solid polymer electrolyte (SPE) with a polyacrylonitrile (PAN) separator sandwiched together with a complementary silicon-based electrode 110 with a layer pair 150. The semi-dielectric layer 111 of layer pair 150 was a 23 nm thick LiF layer 121. The molten ion-conducting layer 112 was a LiTFSI salt at or above its melting temperature. The SPE layer 114 was a mixture of polycaprolactone (PCI), succinonitrile (SN), and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI) with a saturated polyacrylonitrile (PAN) separator.

[0101] Nyquist plot 600 is a plot of a series of points, typically 605, measured at a given frequency of excitation voltage across a cell, e.g., 100. At each frequency, the associated point on Nyquist plot 600 represents the real component, Z', of the total impedance of the cell (100, 200), measured in ohms on the X-axis 624, relative to the imaginary component, Z" of the total impedance, measured in ohms on the Y-axis 626 of Nyquist plot 600. Typically, the imaginary component, Z" is a negative value (indicating capacitance), as shown. Points 605 measured at lower frequencies are on the right side of Nyquist plot 600, while points scanned / plotted first toward the left have higher frequencies; i.e., the highest frequency is typically closest to the 0 / 0 vertex. Each point 605 is the impedance measured at one independent frequency.

[0102] Curve 610 is a linear curve that fits the exact impedance measured at each point 605. Curve 615 is a "best fit" curve of points 605 on curve 610, generated from the RC model from FIG. 5. Region 625 on curve 615 is approximately linear, with a slope near 45 degrees. This indicates that the transport / diffusion of ions, e.g., lithium ions, Li+, through cell 100 / 200 is efficient over a wide range of frequencies, thereby warranting the use of the Warburg impedance element displayed in FIG. 5.

[0103] In this exemplary embodiment, when the entire cell was biased at 0 volts, the frequency of the applied voltage was varied from 1 megahertz to 200 millihertz with an excitation potential amplitude of 50 millivolts.

[0104] FIG. 6A is a graph of an expanded portion 650 of FIG. 6, showing points 605 and an RC model line fit 615 at high to mid frequencies of a large Nyquist plot 600. Again, at each frequency, the associated point on the Nyquist plot 650 represents the real component of the total impedance, Z′, of cell (100, 200), measured in ohms on the X-axis 664, versus the imaginary component of the total impedance, Z″, measured in ohms on the Y-axis 665 of the Nyquist plot 650.

[0105] In this plot, the value of R1 675, representing the interface resistance of the silicon-based electrode 110 and the layer pair, is determined to be 17 ohms. This value is extracted from the diameter of a small semicircle in the high frequency region, as indicated by the black arrow pointing from R1. The value of R2 685 is determined to be 1114 ohms. It is proposed that the value of R2, the bulk cell resistance representing mass transport and diffusion resistance through the electrolyte and electrode, can be further reduced by reducing the thickness of the SPE electrolyte and potentially the layer pair 121. Rs is estimated as the real resistance (x-axis value) from the first highest frequency data point.

[0106] A symmetrical prior art cell / battery of the same dimensions that does not include layer pair 150 between the silicon-based electrode 110 and the SPE 114 has an R1 value in the range of around 150 ohms and an R2 value in the range of around 4527 ohms. Thus, by including layer pair 1500, the R1 value is improved by nearly 10 times, and the R2 value is improved by about 4 times.

[0107] TIFF2023538359000002.tif66167

[0108] FIG. 7 is a block diagram illustrating a layer pair 110 disposed on a silicon-based electrode for use in a three-dimensionally patterned full lithium battery cell 700.

[0109] 7 is a block diagram of a novel energy storage device 700 having an active anode material (LiTFSI-PANI & graphite slurry) deposited on an active silicon area 760A / 110 in a silicon-based electrode substrate 110 / 760. The active anode material 777 is present at the base of the grooves 750 and on the groove sidewalls 754 that are partially formed in-situ in the structure 700 during initial current cycling and prior to the formation of the lithium metal anode layer 740.

[0110] In this embodiment, by way of example, structure 700 includes an anode 777 that is entirely contained within a 3D groove 750 in substrate 110 / 760. In this non-limiting example, cathode contact 785 / 118, separator 735 / 115, and electrolyte (732A / 732B) are disposed outside of groove 750, on field 756. Field 756 is the surface of substrate 760 / 110 that is outside of groove 750. Additionally, active anode material 777, polymer 770, and, upon cycling or in situ, lithium metal anode layer 740 are deposited on groove sidewalls 754 and groove bottom 771. Structure 700 is shown after being cycled, e.g., exposed to currents of various amplitudes through battery 700, to form the structures and components within battery 700.

[0111] The cell structure 700 is partially encapsulated in a groove 750 in a substrate 760 / 110. A liner / insulator 754 lines the sidewalls 751 of the groove 750 and may overlap over the field 756. The liner 754 is made of a dielectric, electrically insulating material such as silicon dioxide (SiO) or silicon nitride (SiN), or a combination of multiple insulating layers, and is deposited by known methods.

[0112] Liner 754 does not cover the active surfaces 760A / 110 of the groove bottom 771, which are the surfaces of the groove bottom region 770 between the layers of liner 754 on the sidewalls 751 of the groove 750. The electrically active surfaces 760A / 110 of the groove bottom 771 are where the groove 750 first interfaces with the substrate 760 / 110 before the galvanic cycle causes transformation on these surfaces, initially forming the lithiated substrate region 760A and the lithium metal layer 740 on the groove bottom 771.

[0113] In some embodiments, the pair layer 150 is partially or entirely deposited on the active surface 725 and on the insulating layer 754 on the sidewalls 751. In yet other embodiments, the pair layer 150 is entirely deposited on the insulating layer 754 and on the field 756 of the substrate 760 / 110. The different stacking of the pair layer 150 is performed by known mask deposition techniques.

[0114] In some embodiments, adhesive region 770 is a layer that covers groove bottom 771 and sidewalls 751 of groove 750 .

[0115] In some embodiments, an anode composition (eg, a graphite mixture and lithium / electronically conductive adhesive) 777 also coats the sidewalls 751 of the grooves 750 .

[0116] In some embodiments, the battery structure 700 includes electrolyte layers 732A / 114A and 732B / 114B with separator layers 735 / 115. In some embodiments, the electrolyte layers 732A / 732B are solid polymer electrolytes (SPEs), for example, as described above. However, any electrolyte material would work in the structure 700.

[0117] The cathode 755 / 118 is electrically connected to a cathode contact 785 / 120, which is a conductive material, for example, a metal such as aluminum (Al) and / or other conductive materials as described above. In some embodiments, the cathode contact 785 / 120 is connected to another top outer contact 705, such as the coin cell conductive spacer and / or casing.

[0118] In some embodiments, a bottom outer contact 710, such as a coin cell casing, is attached to the substrate 760 / 110.

[0119] Figure 8 shows that the battery is 40 ohm cm 2 Electrode interface resistivity R1 of less than 2.25E-6 seconds (corresponding to a charge transfer time constant of 2 × 10 3 ohm cm 2 8 is a flowchart of a method of manufacturing or fabricating 800 a lithium battery using layer pair 150 to have a bulk cell resistivity R2 of less than 1.26E-2 seconds (corresponding to a charge transfer time constant of 1.26E-2 seconds).

[0120] The process 800 begins with step 810, as described above, of forming a thin semi-dielectric layer 111 on a silicon-based electrode 110. The thin semi-dielectric layer 111 has a thin semi-dielectric layer thickness 121 of 15 nanometers (nm) and 30 nm.

[0121] In step 820, fused ion conducting layer 112 is deposited on thin semi-dielectric layer 111 to form layer pair 150, as described above.

[0122] In step 830, one or more device layers are deposited on top of layer pair 150 to form device 100 / 200 / 700.

[0123] The descriptions of various embodiments of the present invention are presented for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. For example, the semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, and the like. Systems and hardware incorporating semiconductor devices are contemplated as embodiments of the present invention.

[0124] The terminology used herein has been selected to explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments described herein. Devices, components, elements, features, apparatuses, systems, structures, techniques, and methods described with different terms that perform substantially the same function, work in substantially the same way, have substantially the same application, or perform similar steps, or combinations thereof, are contemplated as embodiments of the present invention.

Claims

1. A composite electrode, comprising: a silicon-based electrode; a dielectric layer disposed directly on the silicon-based electrode, the dielectric layer having a dielectric layer thickness between 15 nanometers (nm) and 30 (nm); a conductive layer disposed on the dielectric layer, the conductive layer and the dielectric layer forming a layer pair, the conductive layer being composed of a lithium-containing salt having high conductivity for lithium ions, and the layer pair being at the bottom of the groove of the silicon-based electrode; a composite electrode comprising the above; an anode disposed on the composite electrode and in the groove; an electrolyte layer disposed on the anode; a cathode disposed on the electrolyte layer; a separator layer for preventing the flow of current between the anode and the cathode; comprising: The composite electrode has a resistivity of less than 40 ohm-cm ２ and the dielectric layer is composed of lithium fluoride (LiF); the lithium-containing salt is one or more of the materials of lithium hexafluorophosphate, lithium perchlorate, lithium trifluoromethanesulfonate, LiBF4, LiBF6, lithium chloride, lithium phosphate compound, lithium bromide compound, lithium bis(trifluoromethanesulfonyl)imide (LiTFSI), lithium difluoro(oxalato)borate (LiDFOB), and lithium bis(oxalato)borate (LiBOB); an energy storage device.

2. The energy storage device according to claim 1, wherein the charge transfer time constant is less than 2.25E-6 seconds.

3. The energy storage device according to claim 1, wherein the dielectric layer thickness is between 18 nm and 23 nm.

4. The energy storage device according to claim 1, wherein the conductive layer has a conductive layer thickness between 1 nm and 50 nm.

5. The energy storage device according to claim 1, wherein the silicon-based electrode is composed of one or more of the materials of bulk silicon, crystalline silicon, amorphous silicon, doped silicon, boron-doped silicon, porous silicon, non-porous silicon, silicon-germanium alloy, and carbon-doped silicon-based alloy.

6. The energy storage device according to claim 1, further comprising an electrode contact composed of one or more of a conductive material, a metal, a metal nitride, tungsten (W), copper (Cu), titanium (Ti), platinum (Pt), nickel (Ni), aluminum (Al), gold (Au), and titanium nitride (TiN).

7. The energy storage device according to claim 1, wherein the layer pair is disposed directly on the silicon-based electrode such that the opposing bottom surfaces of the layer pair are in direct physical and electrical contact with the electrode opposing surfaces of the silicon-based electrode, and the electrode interface is where the opposing bottom surface and the electrode opposing surface are in contact.

8. The energy storage device according to claim 1, wherein the electrolyte layer is one of a polymer solid electrolyte (SPE), a solid electrolyte, a hybrid polymer / solid electrolyte, and a liquid electrolyte.

9. The energy storage device according to claim 1, which is composed of a composite and has a charge transfer time constant of less than 2.25E-6 seconds.

10. The silicon-based electrode is made of boron-doped crystalline silicon, the dielectric layer is made of LiF, the conductive layer is made of bis(trifluoromethanesulfonyl)imide (LiTFSI), and the electrolyte layer is made of a polymer solid electrolyte (SPE) further mixed with polycaprolactone, succinonitrile (SN), and lithium bis(trifluoromethanesulfonyl)imide (LiTFSI). The energy storage device according to claim 1.

Images