Imaging device, control method thereof, and electronic apparatus

Abstract

To add a plurality of pixel signals in an image pickup device while preventing the influence of noise and reducing power consumption.SOLUTION: An image pickup device has: a plurality of holding means that hold a plurality of signals input from a plurality of different pixels; a plurality of conversion means that convert the signals held by the plurality of holding means into currents according to potentials corresponding to the signals; switching means that switches between connection and non-connection of the plurality of conversion means; and a plurality of output means that combine the currents obtained through the conversion performed by the plurality of conversion means and output a resulting current from any one of the plurality of output means during the connection period switched by the switching means, and output the currents obtained through the conversion performed by the plurality of conversion means from the plurality of output means in a non-connection period switched by the switching means.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to an image sensor, a control method thereof, and electronic equipment, and in particular to a technique for adding pixel signals within an image sensor. [Background technology]

[0002] Conventionally, a configuration for reading out signals from each pixel of an image sensor includes a sample-and-hold unit that sequentially outputs signals to a vertical output line shared by multiple pixels in the same column, and stores in a capacitor a signal corresponding to a change in the voltage of the vertical output line due to the output signal. This sample-and-hold unit samples and holds the reset signal and the optical signal, and outputs the differential potential as a signal directly from the image sensor, or outputs it after performing analog-to-digital (A / D) conversion internally.

[0003] Patent Document 1 discloses a circuit that charges and holds the voltage of an output signal from a pixel using a sample-and-hold circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4807440 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned Patent Document 1, the sampled and held signal of each pixel is output as is, and there is no description of a method for adding the signals of multiple pixels in the horizontal and vertical directions. Also, although it is possible to convert the signal of each pixel into a digital signal and then add them, in that case, it is not possible to reduce the power consumed in the image sensor.

[0006] The present invention has been made in consideration of the above problems, and has an object to make it possible to add signals from a plurality of pixels in an image sensor while suppressing the effects of noise and reducing power consumption. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, the imaging element of the present invention comprises a plurality of holding means each holding a plurality of signals input from a plurality of different pixels, a plurality of conversion means each converting the signals held in the plurality of holding means into currents according to potentials corresponding to the signals, a switching means switching between connection and disconnection between the plurality of conversion means, and a plurality of output means which, when connected by the switching means, combines the currents converted by the plurality of conversion means and outputs them from one of the plurality of output means, and when not connected by the switching means, outputs the currents converted by the plurality of conversion means from each of the plurality of output means. Effect of the Invention

[0008] It is possible to add signals from a plurality of pixels in an image sensor while suppressing the effects of noise and reducing power consumption. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of an image pickup apparatus according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic diagram of an image sensor according to an embodiment. [Diagram 3] FIG. 4 is an equivalent circuit diagram of a unit pixel in the embodiment. [Figure 4] FIG. 2 is a schematic diagram showing a layered structure of an image sensor in an embodiment. [Diagram 5] FIG. 3 is a circuit diagram showing a configuration of a part of a column circuit unit in the first embodiment. [Figure 6] 5 is a timing chart showing control during addition reading in the first embodiment. [Figure 7] FIG. 11 is a circuit diagram showing a configuration of a part of a column circuit unit according to a second embodiment. [Figure 8] 10 is a timing chart showing control during addition reading in the second embodiment. [Figure 9] FIG. 11 is a circuit diagram showing a configuration of a part of a column circuit unit according to a third embodiment. [Figure 10] 13 is a timing chart showing control during addition reading in the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted. EXAMPLES

[0011] [Device configuration] FIG. 1 is a block diagram showing a schematic configuration of an image pickup apparatus 100 according to an embodiment of the present invention. The lens unit 101 is composed of, for example, a plurality of lenses, an aperture, etc., and collects light from a subject and makes it incident on the image sensor 102. The image sensor 102 performs photoelectric conversion on the incident light and outputs image data.

[0012] The image processing circuit 109 performs development processes such as color matrix processing and gamma processing on the image data output from the image sensor 102. In these processes, the image processing circuit 109 stores the image data in a memory circuit 111 as necessary. Then, the image processing circuit 109 outputs the processed image data to a display unit 113 and / or a recording unit 110.

[0013] The display unit 113 displays image data processed by the image processing circuit 109, other information such as shooting parameters, etc. Also, an operation unit 116 may be configured together with a touch panel, in which case an image according to the operation state is displayed. The recording unit 110 records the image data processed by the image processing circuit 109, information associated with the image data, etc. in a storage medium (not shown).

[0014] The operation unit 116 is configured with one or a combination of a switch, a dial, a touch panel, a pointing device using line-of-sight detection, a voice recognition device, etc., and is used by the user to input various operational instructions to the imaging device 100. The operation unit 116 generates an operation signal in accordance with the user's operation, and outputs it to the control circuit 112.

[0015] The control circuit 112 controls image processing by the image processing circuit 109 and part of the driving of the image sensor 102. It also controls operations corresponding to operation signals input from an operation unit 116, and transfers data to the memory circuit 111, the display unit 113, and the recording unit 110. Note that at least part of the functions of the control circuit 112 may be provided in the image sensor 102 or the image processing circuit 109.

[0016] The bus 120 is a common path for the control circuit 112, the image sensor 102, the image processing circuit 109, the display unit 113, the operation unit 116, the recording unit 110, and the memory circuit 111 to exchange data with one another.

[0017] In addition, in FIG. 1, the imaging device 100 is shown as including the lens unit 101, but the lens unit 101 may be configured to be detachable from the imaging device 100.

[0018] FIG. 2 is a schematic diagram of the image sensor 102. As shown in FIG. The image sensor 102 has a pixel section 208 in which a plurality of pixels 205 are arranged two-dimensionally. In this embodiment, the pixels 205 are arranged in a plurality of rows in the vertical direction and a plurality of columns in the horizontal direction in the pixel section 208. That is, the pixels 205 are arranged in a matrix. The vertical scanning circuit 204 is configured to output various control signals required for reading out signals to the pixels 205, and selects a pixel row from which signals are to be read out.

[0019] Signals read from pixels 205 in a row selected by the vertical scanning circuit 204 are output to vertical output lines 210 of each column and input to a column circuit section 211. The column circuit section 211 performs processes such as amplification and A / D conversion of the pixel signals to generate image data. The output section 212 sequentially outputs the image data generated by the column circuit section 211 to outside the image sensor 102.

[0020] FIG. 3 shows an equivalent circuit diagram of the pixel 205. The photodiode (PD) 305 accumulates electric charges generated by photoelectric conversion according to the amount of incident light. The electric charges accumulated in the PD 305 are transferred to the floating diffusion (FD) 307 by the vertical scanning circuit 204 controlling the transfer control signal φTX to turn on the transfer switch 306. The output transistor 309, together with a constant current source 311 connected to the vertical output line 210, forms a source follower circuit, amplifies a voltage signal corresponding to the charge accumulated in the FD 307, and outputs it as a pixel signal. Here, under the control of a row selection control signal φSEL by the vertical scanning circuit 204, the output amplifier 309 of a row whose row selection switch 310 is turned ON is connected to the vertical output line 210, and a pixel signal is output to the vertical output line 210.

[0021] Moreover, the vertical scanning circuit 204 controls the reset control signal φRES to turn on the reset switch 308, thereby resetting the FD 307 to a predetermined voltage VDD. Furthermore, the vertical scanning circuit 204 controls the reset control signal φRES and the transfer control signal φTX to simultaneously turn on the reset switch 308 and the transfer switch 306, thereby resetting the PD 305 to a predetermined voltage VDD.

[0022] The transfer control signal φTX, the reset control signal φRES, and the row selection control signal φSEL are output by the control circuit 112 controlling the vertical scanning circuit 204.

[0023] FIG. 4 is a schematic diagram showing the layered structure of the image sensor 102, where FIG. 4(a) is an oblique projection view and FIG. 4(b) is a top view of each semiconductor substrate. The image sensor 102 is formed by stacking a first semiconductor substrate 400 and a second semiconductor substrate 401 at the chip level. An area including a pixel section 208 is formed on the first semiconductor substrate 400, and high-speed logic circuits such as a vertical scanning circuit 204, a column circuit section 211, and an output section 212 are formed on the second semiconductor substrate 401.

[0024] 5 is an equivalent circuit diagram showing the configuration of two columns of column circuit units 211 in Example 1, and a column circuit unit 211(n) is provided for every two columns of pixel units 208. Here, the components corresponding to the nth column of pixel units 208 have (n) added after the reference number indicating the components, and the components corresponding to the n+1th column of pixel units 208 have (n+1) added after the reference number (n is a natural number). The column circuit unit 211(n) has a circuit 213(n) that performs sample hold and current output, and ADCs 542(n) and 542(n+1) that perform A / D conversion. The vertical output line 210(n) and the vertical output line 210(n+1) are connected to the circuit 213(n) of the column circuit unit 211(n).

[0025] In the above configuration, the pixel signal of pixel 205(n) in a row selected by the vertical scanning circuit 204 is output to vertical output line 210(n), and the pixel signal of pixel 205(n+1) is output to vertical output line 210(n+1).

[0026] [Detailed configuration and operation of column circuit unit 211(n)] ●Independent read mode First, the independent readout mode will be described. In the independent readout mode, the pixel signals of pixel 205(n) and pixel 205(n+1) are read out separately. First, the configuration and operation of a circuit portion of the column circuit unit 211(n) that samples and holds a reset signal of the pixel 205(n) (a pixel signal output from the pixel 205(n) after resetting) will be described.

[0027] An input terminal of the switch 501 is connected to the vertical output line 210(n), and is controlled to be turned ON when a reset signal is read out from the pixel 205(n). An output terminal of the switch 501 is connected to an input terminal of a capacitor 554. An output terminal of the capacitor 554 is connected to an input terminal of the switch 550 and a non-inverting input terminal of the non-inverting amplifier 503.

[0028] The output terminal of switch 550 and the output terminal of non-inverting amplifier 503 are connected to one terminal of capacitor 505 and an input terminal of switch 507. The other terminal of capacitor 505 is grounded. The output terminal of switch 507 is connected to the gate of P-type source follower 513, and the source of source follower 513 is connected to the input terminal of resistor 510. When switch 507 is turned ON, the potential becomes equal to the reset signal.

[0029] Next, the configuration and operation of a circuit portion of the column circuit unit 211(n) that samples and holds the optical signal of the pixel 205(n) (a pixel signal corresponding to the photocharge accumulated in the PD 305 of the pixel 205(n)) will be described.

[0030] An input terminal of the switch 502 is connected to the vertical output line 210(n), and is controlled to be turned ON when an optical signal is read out from the pixel 205(n). An output terminal of the switch 502 is connected to an input terminal of a capacitor 555. An output terminal of the capacitor 555 is connected to an input terminal of the switch 551 and a non-inverting input terminal of the non-inverting amplifier 504.

[0031] The output terminal of switch 551 and the output terminal of non-inverting amplifier 504 are connected to one terminal of capacitor 506 and an input terminal of switch 508. The other terminal of capacitor 506 is grounded. The output terminal of switch 508 is connected to the gate of P-type source follower 511, and the source of source follower 511 is connected to the output terminal of resistor 510. When switch 508 is turned ON, a potential corresponding to the optical signal is obtained.

[0032] That is, the input terminal (current source 540 side) of the resistor 510 has a potential corresponding to the reset signal of the pixel 205(n), and the output terminal (opposite the current source 540) of the resistor 510 has a potential corresponding to the optical signal of the pixel 205(n).

[0033] An input terminal of the current source 540 is connected to a high potential power supply, and an output terminal is connected to an input terminal of a switch 509. An output terminal of the switch 509 is connected to an input terminal of a resistor 510, one terminal of a switch 516, and a source of a source follower 513. An output terminal of the resistor 510 is connected to a source of a source follower 511. A drain of the source follower 511 is connected to an input terminal of a switch 512 and one terminal of a switch 517. An output terminal of the switch 512 is connected to an ADC 542(n).

[0034] In this configuration, by turning the switches 509 and 512 ON and turning the switches 516 and 517 OFF, a current according to the potential difference between the optical signal and reset signal of the pixel 205(n) and the impedance of the resistor 510 flows through the current signal transfer line 570 via the switch 512 and is input to the ADC 542(n). The ADC 542(n) performs A / D conversion of the input current signal into a digital signal. The ADC 542(n) may be of any type, such as a successive approximation type, a slope type, or a ΔΣ modulation type. The current of the current source 540 minus the current flowing through the resistor 510 flows to the ground via the source follower 513 and the MOS diode 514 in the excess current line 572.

[0035] Next, the configuration and operation of a circuit portion of the column circuit unit 211(n) that samples and holds the reset signal of the pixel 205(n+1) (the pixel signal output from the pixel 205(n+1) after resetting) will be described.

[0036] An input terminal of the switch 518 is connected to the vertical output line 210(n+1), and is controlled to be turned ON when a reset signal is read out from the pixel 205(n+1). An output terminal of the switch 518 is connected to an input terminal of a capacitor 520. An output terminal of the capacitor 520 is connected to an input terminal of a switch 552 and a non-inverting input terminal of a non-inverting amplifier 522.

[0037] The output terminal of switch 552 and the output terminal of non-inverting amplifier 522 are connected to one terminal of capacitor 524 and an input terminal of switch 526. The other terminal of capacitor 524 is grounded. The output terminal of switch 526 is connected to the gate of P-type source follower 532, and the source of source follower 532 is connected to the input terminal of resistor 529. When switch 526 is turned ON, the potential becomes equal to the reset signal.

[0038] Next, the configuration and operation of a partial circuit in the column circuit unit 211(n) that samples and holds the optical signal of the pixel 205(n+1) (a pixel signal corresponding to the photocharge accumulated in the PD 305 of the pixel 205(n+1)) will be described.

[0039] An input terminal of the switch 519 is connected to the vertical output line 210(n+1), and is controlled to be turned ON when reading out an optical signal from the pixel 205(n+1). An output terminal of the switch 519 is connected to an input terminal of a capacitor 521. An output terminal of the capacitor 521 is connected to an input terminal of a switch 553 and a non-inverting input terminal of a non-inverting amplifier 523.

[0040] The output terminal of switch 553 and the output terminal of non-inverting amplifier 523 are connected to one terminal of capacitor 525 and an input terminal of switch 527. The other terminal of capacitor 525 is grounded. The output terminal of switch 527 is connected to the gate of P-type source follower 530, and the source of source follower 530 is connected to the output terminal of resistor 529. When switch 527 is turned ON, a potential corresponding to the optical signal is obtained.

[0041] That is, the input terminal (current source 541 side) of resistor 529 has a potential corresponding to the reset signal of pixel 205(n+1), and the output terminal (opposite current source 541) of resistor 529 has a potential corresponding to the optical signal of pixel 205(n+1).

[0042] An input terminal of the current source 541 is connected to a high potential power supply, and an output terminal is connected to an input terminal of a switch 528. An output terminal of the switch 528 is connected to an input terminal of a resistor 529, one terminal of a switch 516, and a source of a source follower 532. An output terminal of the resistor 529 is connected to a source of a source follower 530. A drain of the source follower 530 is connected to an input terminal of a switch 531 and one terminal of a switch 517. An output terminal of the switch 531 is connected to an ADC 542(n+1).

[0043] In this configuration, by turning the switches 528 and 531 ON and turning the switches 516 and 517 OFF (disconnected), a current according to the potential difference between the optical signal and reset signal of the pixel 205(n+1) and the impedance of the resistor 529 flows through the current signal transfer line 571 via the switch 531 and is input to the ADC 542(n+1). The ADC 542(n+1) performs A / D conversion on the input current signal to a digital signal. Also, the current of the current source 541 minus the current flowing through the resistor 529 flows to the ground via the source follower 532 and the MOS diode 533 in the excess current line 573.

[0044] By the above-mentioned operation, the signals of the pixel 205(n) and the pixel 205(n+1) can be read out independently by turning off the switch 516 and the switch 517 (disconnected).

[0045] Additive readout mode Next, the additive readout mode will be described. In the additive readout mode, the pixel signals of the pixel 205(n) and the pixel 205(n+1) are added together and read out. The column circuit section 211(n) includes a switch 516 and a switch 517 as a portion for connecting circuits that sample and hold the reset signal and the optical signal of the pixel 205(n) and the pixel 205(n+1), respectively.

[0046] In order to average the sampling signal of the reset signal, the switch 515 connects the node between the capacitor 505 and the non-inverting amplifier 503 and the node between the capacitor 524 and the non-inverting amplifier 522. This makes it possible to equalize the level of the reset signal and reduce reset noise.

[0047] The switch 516 connects the source of the source follower 513 to the source of the source follower 532, and the switch 517 connects the source of the source follower 511 to the source of the source follower 530. By turning on the switches 516 and 517, it becomes possible to add the currents of the pixel 205(n) and the pixel 205(n+1).

[0048] As in the independent readout mode described above, in a state in which the reset signal and optical signal of pixel 205(n) and pixel 205(n+1) are sampled and held, switches 516 and 517 are turned ON. As a result, the input end (current source 540 side) of resistor 510 has a potential corresponding to the sum signal of the reset signal of pixel 205(n) and the reset signal of pixel 205(n+1), and the output end (opposite side to current source 540) of resistor 510 has a potential corresponding to the sum signal of the optical signal of pixel 205(n) and the optical signal of pixel 205(n+1).

[0049] In this state, by turning the switches 509, 512, and 528 ON and turning the switch 531 OFF, a current according to the potential difference between the sum signal of the optical signals of the pixels 205(n) and 205(n+1) and the sum signal of the reset signals and the impedance of the resistor 510 flows through the current signal transfer line 570 via the switch 512 and is input to the ADC 542(n). The ADC 542(n) performs A / D conversion of the input current signal into a digital signal. In addition, the current of the current source 540 minus the current flowing through the resistor 510 flows to ground via the source follower 513 and MOS diode 514 of the excess current line 572.

[0050] By the above-mentioned operation, when the switches 516 and 517 are turned on (when connected), the signals of the pixel 205(n) and the pixel 205(n+1) can be added and read out.

[0051] ●Timing control during addition Fig. 6 is a timing chart showing the control timing of the circuit 213(n) shown in Fig. 5 in the first embodiment, and shows the operation timing of the switches when adding and reading out the signals of the pixels 205(n) and 205(n+1). Note that the ON / OFF control of each switch shown in Fig. 6 is performed by the control circuit 112.

[0052] First, at time t601, the switches 509, 528, and 512 are turned ON to prepare for flow of a current through the current signal transfer line 570.

[0053] At time t602, the switches 550, 551, 552, and 553 are turned ON to reset the non-inverting amplifiers 503, 504, 522, and 523, and at time t603, the switches 550, 551, 552, and 553 are turned OFF.

[0054] Between time t603 and time t604, the vertical scanning circuit 204 resets the pixels 205 in the selected row. Then, when the row selection control signal φSEL is set to HIGH to turn on the row selection switch 310, the reset signals of the FDs 307 of the pixels 205(n) and 205(n+1) are output to the vertical output lines 210(n) and 210(n+1), respectively.

[0055] At time t604, the switches 501 and 518 are turned ON, and the reset signals of the pixel 205(n) and the pixel 205(n+1) are respectively held in the capacitors 554 and 520. At time t605, the switches 501 and 518 are turned OFF.

[0056] At time t606, the switch 515 is turned ON to average the reset signal, and at time t607, the switch 515 is turned OFF.

[0057] Between time t606 and time t608, the vertical scanning circuit 204 sets the transfer control signal φTX for the selected row to HIGH to turn on the transfer switch 306, thereby transferring the charges accumulated in the PD 305 of the pixels 205(n) and 205(n+1) to the FD 307. At this time, since the row selection switch 310 is already ON, a voltage signal corresponding to the charges transferred to the FD 307 of the pixels 205(n) and 205(n+1) in the selected row is output as an optical signal to the vertical output lines 210(n) and 210(n+1).

[0058] At time t608, the switches 502 and 519 are turned ON to hold the optical signals of the pixels 205(n) and 205(n+1) in the capacitors 555 and 521, respectively. At time t609, the switches 502 and 519 are turned OFF.

[0059] At time t610, the switches 507, 508, 526, and 527 are turned ON, and both ends of the resistors 510 and 529 are set to potentials according to the reset signals and pixel signals of the pixels 205(n) and 205(n+1), respectively, via the source followers 513, 511, 532, and 530.

[0060] At time t611, the switches 516 and 517 are further turned ON, so that a signal obtained by adding the current signals of the pixels 205(n) and 205(n+1) is output to the ADC 542(n). The ADC 542(n) performs A / D conversion on the input current signal to a digital signal.

[0061] At time t612, the switches 516, 517, and 512 are turned OFF, and further at time t613, the switches 507, 508, 526, and 527 are turned OFF, thereby terminating the control.

[0062] As described above, according to the first embodiment, the above circuit configuration can convert signals output from unit pixels in multiple columns into current signals and add them up, thereby suppressing the effects of noise and enabling addition of signals from multiple pixels.

[0063] In the above example, the configuration in which the pixels 205 are added in groups of two columns has been described, but the present invention is not limited to this. By adding a configuration for the (n+1)th column and connecting it with a switch similar to the switch 516 and the switch 517, signals output from the pixels 205 in any number of columns can be converted into current signals and added. EXAMPLES

[0064] Next, a second embodiment of the present invention will be described with reference to Fig. 7 and Fig. 8. In the second embodiment, an example is shown in which the total amount of current is suppressed by decreasing the current value of the current source and increasing the resistance value. Note that the configurations of the imaging device 100 and the imaging element 102 are similar to those described with reference to Figs. 1 to 4 in the first embodiment, except for the configuration of the column circuit section 211, and therefore a description thereof will be omitted here.

[0065] Fig. 7 is an equivalent circuit diagram showing a configuration of two columns of the column circuit unit 211 in Example 2. The configuration shown in Fig. 7 is a configuration in which a resistor 702, a resistor 705, a switch 700, and a switch 701 are added to the configuration shown in Fig. 5. More specifically, a resistor 702 is connected in parallel with the resistor 510 , a switch 700 is connected between the resistor 510 and the switch 509 , and a switch 701 is connected between the resistor 702 and the switch 509 . Furthermore, a resistor 705 is connected in parallel to the resistor 529, a switch 703 is connected between the resistor 529 and the switch 528, and a switch 704 is connected between the resistor 705 and the switch 528. The rest of the configuration is the same as that described with reference to Fig. 5, and therefore description thereof will be omitted.

[0066] Here, resistors 702 and 705 having resistance values ​​larger than those of resistors 510 and 529 are used, and further, the number of current sources used is reduced from two to one, so that it is possible to suppress the current while achieving the same signal level as when a smaller resistance value is used. For example, when resistors 510 and 529 are 100Ω, resistors 702 and 705 having a resistance of 200Ω can be used.

[0067] 7, multiple resistors are connected in parallel and one of them is selected, but the present invention is not limited to this and may be configured to change the resistance value. For example, multiple resistors are connected in series and connected to any node including both ends of the connected resistors, thereby changing the resistance value. A variable resistor may also be used.

[0068] ●Timing control during addition Fig. 8 is a timing chart showing the control timing of the circuit 213(n) shown in Fig. 7 in the second embodiment, and shows the operation timing of the switches when adding and reading out the signals of the pixel 205(n) and the pixel 205(n+1). Note that the ON / OFF control of each switch shown in Fig. 8 is performed by the control circuit 112. The difference from the control shown in Fig. 6 described in the first embodiment is that the control at time t801 is different from the control at time t601, that control at time t800 before time t801 is added, and that control at time t802 is added after time t613.

[0069] First, at time t800, the switches 701 and 704 are turned ON to select the resistors 702 and 705 for use.

[0070] Next, at time t801, the switches 509 and 512 are turned ON to prepare for current flow through the current signal transfer line 570. Note that while the switch 528 is turned ON in the first embodiment, it remains OFF in the second embodiment.

[0071] The control from time t602 to time t802 is similar to the control shown in FIG. At time t802, the switch 701 and the switch 704 are turned OFF.

[0072] It is also possible to change the addition ratio of the two signals by changing the addition ratio. For example, by setting resistor 702 to 200 Ω and resistor 705 to 400 Ω, it is possible to add pixel 205(n) and pixel 205(n+1) at a ratio of 2:1 with the same operation.

[0073] As described above, according to the second embodiment, it is possible to reduce power consumption compared to the circuit configuration and control shown in Fig. 5 and Fig. 6. In addition, the addition ratio can be changed by changing the resistance value. This makes it possible to correct the center of gravity position of the addition output even when reading out a compressed number of pixels, making it possible to output a high-quality image. EXAMPLES

[0074] Next, a third embodiment of the present invention will be described with reference to Fig. 9 and Fig. 10. In the third embodiment, an example of current addition of signals output from a plurality of pixels 205 arranged in the vertical direction is shown. Note that the configurations of the imaging device 100 and the imaging element 102 are similar to those described with reference to Figs. 1 to 4 in the first embodiment, except for the configuration of the column circuit section 211, and therefore description thereof will be omitted here.

[0075] 9 is an equivalent circuit diagram showing the configuration of one column of the column circuit section 211 in the third embodiment. The column circuit section 211(n) shown in FIG. 5 is configured to input signals of pixels in the n-th and (n+1)-th columns in parallel, whereas the column circuit section 211(n) (n is a natural number) shown in FIG. 9 has a configuration in which signals of pixels 205 in the m-th and (m+1)-th rows of the same column (n) are input in time series (m is a natural number). Also, it is different from FIG. 5 in that a switch 900 and a switch 901 are added between the vertical output line 210(n) and the circuit 213. Other configurations are the same as those described with reference to FIG. 5, and therefore description thereof will be omitted. ●Timing control during addition Fig. 10 is a timing chart showing the control timing of the circuit 213(n) shown in Fig. 9 in Example 3, and shows the operation timing of the switches when adding and reading out the signals of the pixel 205(m) and the pixel 205(m+1) in the nth column and the mth row. Note that the ON / OFF control of each switch shown in Fig. 10 is performed by the control circuit 112.

[0076] First, at time t1000, the switches 509, 528, and 512 are turned on to prepare for flow of a current through the current signal transfer line 570.

[0077] Next, at time t1001, the switches 550 and 551 are turned ON to reset the non-inverting amplifiers 503 and 504, and at time t1002, the switches 550 and 551 are turned OFF.

[0078] At time t1003, the switch 901 is turned ON. Note that, until time t1003, the vertical scanning circuit 204 resets the pixel 205(m) in the selected row and outputs a reset signal of the FD 307 to the vertical output line 210(n) by turning ON the row selection switch 310 of the pixel 205(m). Also, while the switch 901 is ON (between time t1003 and time t1008), the row selection switch 310 connecting the pixel 205(m) and the vertical output line 210(n) is kept ON, so that the signal of the pixel 205(m) is transferred.

[0079] At time t1004, the switch 501 is turned ON to hold the reset signal of the pixel 205(m) in the capacitor 554, and at time t1005, the switch 501 is turned OFF.

[0080] Between time t1005 and time t1006, the vertical scanning circuit 204 sets the transfer control signal φTX for the selected row (row m) to HIGH to turn on the transfer switch 306, thereby transferring the charge accumulated in the PD 305 of the pixel 205(m) to the FD 307. Because the row selection switch 310 of the pixel 205(m) is ON, an optical signal is output from the FD 307 of the pixel 205(m) to the vertical output line 210(n).

[0081] At time t1006, the switch 502 is turned ON to hold the optical signal of pixel 205(m) in the capacitor 555, and at time t1007, the switch 502 is turned OFF. Furthermore, at time t1008, the switch 901 is turned OFF. This ends the holding of the reset signal and optical signal of pixel 205(m).

[0082] Next, at time t1009, the switches 518 and 519 are turned ON to reset the non-inverting amplifiers 522 and 523, and at time t1010, the switches 518 and 519 are turned OFF.

[0083] At time t1011, the switch 900 is turned ON. Note that, until time t1003, the vertical scanning circuit 204 resets the pixel 205(m+1) in the selected row and outputs the reset signal of the FD 307 to the vertical output line 210(n) by turning ON the row selection switch 310 of the pixel 205(m+1). Also, while the switch 900 is ON (between time t1011 and time t1018), the row selection switch 310 connecting the pixel 205(m+1) and the vertical output line 210(n) is kept ON, so that the signal of the pixel 205(m+1) is transferred.

[0084] At time t1012, the switch 518 is turned ON to hold the reset signal of the pixel 205(m+1) in the capacitor 520, and at time t1013, the switch 518 is turned OFF.

[0085] At time t1014, the switch 515 is turned ON to average the reset signals of the pixel 205(m) and the pixel 205(m+1), and at time t1015, the switch 515 is turned OFF.

[0086] Between time t1015 and time t1016, the vertical scanning circuit 204 sets the transfer control signal φTX for the selected row (row m+1) to HIGH to turn on the transfer switch 306, thereby transferring the charge accumulated in the PD 305 of the pixel 205(m+1) to the FD 307. Because the row selection switch 310 of the pixel 205(m+1) is ON, an optical signal is output from the FD 307 of the pixel 205(m+1) to the vertical output line 210(n).

[0087] At time t1016, the switch 519 is turned ON to hold the optical signal of the pixel 205(m+1) in the capacitor 521, and at time t1017, the switch 519 is turned OFF. Furthermore, at time t1018, the switch 900 is turned OFF. This ends the holding of the reset signal and optical signal of the pixel 205(m+1).

[0088] Next, at time t1019, switches 507, 508, 526, and 527 are turned ON, and both ends of resistors 510 and 529 are set to potentials according to the reset signals and pixel signals of pixel 205(m) and pixel 205(m+1) via source followers 513, 311, 532, and 530, respectively.

[0089] At time t1020, the switches 516 and 517 are further turned ON, so that a signal obtained by adding the current signals of the pixels 205(m) and 205(m+1) is output to the ADC 542(n). The ADC 542(m) performs A / D conversion on the input current signal to a digital signal.

[0090] At time t1021, the switches 516, 517, and 512 are turned OFF, and further at time t1022, the switches 507, 508, 526, and 527 are turned OFF, thereby terminating the control.

[0091] 10, a case has been described in which signals from unit pixels in two rows in the same column connected to the vertical output line 210 are added and read out, but the same configuration may be used to read out the signals independently. In that case, the signals from each of the pixels 205(m) and 205(m+1) may be output to the ADCs 542(m) and 542(m+1), respectively, without turning on the switches 516 and 517 (disconnected state).

[0092] In the above example, the configuration in which the pixels 205 are added two rows at a time has been described, but the present invention is not limited to this. By adding a configuration for the (m+1)th column and connecting it with a switch similar to the switch 516 and the switch 517, signals output from the pixels 205 of any number of rows can be converted into current signals and added.

[0093] In addition, in the third embodiment, an example of adding pixel 205(m) and pixel 205(m+1) is shown, but it is also possible to realize a multi-sampling function that reduces noise by sampling and adding the signal of pixel 205(m) to capacitors 505, 506, 524, and 525, respectively.

[0094] As described above, according to the third embodiment, the above circuit configuration makes it possible to convert signals output from pixels in multiple rows into current signals and add them up, thereby making it possible to add up signals for each of multiple pixels while maintaining the noise reduction effect.

[0095] In the above embodiment, the imaging element 102 of the present invention is mounted on the imaging device 100, but the present invention is not limited to this and may be mounted on various electronic devices. For example, the imaging element of the present invention can be used in mobile communication terminals with a camera function such as mobile phones and smartphones, mobile computers with a camera function, and mobile game consoles with a camera function.

[0096] <Summary> The disclosure of this embodiment includes the following configuration.

[0097] (Configuration 1) a plurality of holding means for holding a plurality of signals input from a plurality of different pixels; a plurality of conversion means for converting the signals held in the plurality of holding means into currents according to potentials corresponding to the signals; A switching means for switching between connection and non-connection between the plurality of conversion means; a plurality of output means, which, when connected by the switching means, outputs the currents converted by the plurality of conversion means together from any one of the plurality of output means, and when not connected by the switching means, outputs the currents converted by the plurality of conversion means from each of the plurality of output means; An imaging element comprising:

[0098] (Configuration 2) the plurality of signals include a first signal and a second signal output from each pixel of the plurality of pixels; Each of the plurality of conversion means converts the first signal and the second signal into a current corresponding to a potential difference between the first signal and the second signal. 2. The imaging device according to configuration 1,

[0099] (Configuration 3) Each of the plurality of pixels includes a photoelectric conversion unit that converts incident light into an electric charge, The imaging element described in configuration 2, characterized in that the first signal is a signal output when each of the pixels is reset, and the second signal is a signal corresponding to an electric charge obtained by photoelectric conversion by the photoelectric conversion means.

[0100] (Configuration 4) Each of the plurality of conversion means includes a current source and a resistor connected in series, Among the plurality of holding means, the holding means for holding the first signal is connected between the current source and the resistor, and the holding means for holding the second signal is connected on the opposite side of the resistor to the current source. 4. The imaging element according to configuration 2 or 3.

[0101] (Configuration 5) Each of the plurality of conversion means includes a current source and a resistor whose resistance value is variable, 5. The imaging element according to any one of configurations 1 to 4, wherein a resistance value of the resistor is increased when the switching means connects the resistor.

[0102] (Configuration 6) Each of the plurality of conversion means includes a current source and a resistor whose resistance value is variable, 5. The imaging element according to any one of configurations 1 to 4, wherein, when the switching means connects the resistors, the resistance values ​​of the resistors are made different among the plurality of conversion means.

[0103] (Configuration 7) 7. The image sensor according to configuration 5 or 6, wherein when the switching means makes a connection, only a current source of any one of the plurality of conversion means is used.

[0104] (Configuration 8) Further comprising a pixel section in which a plurality of pixels are arranged in a matrix, 8. The image sensor according to any one of configurations 1 to 7, wherein the different pixels are pixels in different columns.

[0105] (Configuration 9) 9. The imaging element according to configuration 8, wherein the holding means, the conversion means, the switching means, and the output means are provided for each of a number of predetermined columns.

[0106] (Configuration 10) Further comprising a pixel section in which a plurality of pixels are arranged in a matrix, 8. The image sensor according to any one of configurations 1 to 7, wherein the different pixels are pixels in different rows of the same column.

[0107] (Configuration 11) 11. The imaging element according to configuration 10, further comprising the plurality of holding means, the plurality of conversion means, the switching means, and the plurality of output means for each column.

[0108] (Configuration 12) 12. The image sensor according to any one of configurations 1 to 11, further comprising analog-to-digital conversion means for converting the currents output from the plurality of output means into digital signals.

[0109] (Configuration 13) An imaging element according to any one of configurations 1 to 12, A processing means for processing a signal output from the imaging element; 1. An electronic device comprising:

[0110] (Configuration 14) A step of causing a plurality of holding means to hold a plurality of signals input from a plurality of different pixels, respectively; a step of causing a plurality of conversion means to convert the signals held in the plurality of holding means into currents according to potentials corresponding to the signals; causing a switching means to switch between connection and non-connection between the plurality of conversion means; a step of outputting the currents converted by the plurality of conversion means together when the switching means is in a connected state, and outputting the currents converted by the plurality of conversion means individually when the switching means is in a disconnected state; 13. A method for controlling an imaging element comprising the steps of:

[0111] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0112] 100: imaging device, 102: imaging element, 109: image processing circuit, 112: control circuit, 204: vertical scanning circuit, 205: pixel, 208: pixel section, 210: vertical output line, 211: column circuit section, 212: output section, 305: photodiode, 510, 529, 702, 705: resistor, 516, 517, 900, 901: switch, 540, 541: current source

Claims

1. a plurality of holding means for respectively holding a plurality of signals input from a plurality of different pixels; a plurality of conversion means for converting the signals held in the plurality of holding means into currents according to potentials corresponding to the signals; a switching means for switching between connection and disconnection between the plurality of conversion means; a plurality of output means, which, when connected by the switching means, combines the currents converted by the plurality of conversion means and outputs them from any of the plurality of output means, and, when not connected by the switching means, outputs the currents converted by the plurality of conversion means from each of the plurality of output means; An imaging device comprising:

2. the plurality of signals include a first signal and a second signal output from each pixel of the plurality of pixels; The plurality of conversion means each converts the first signal and the second signal into a current corresponding to a potential difference between the first signal and the second signal.

2. The imaging device according to claim 1, wherein the first and second lenses are arranged in a plane parallel to each other.

3. Each pixel of the plurality of pixels includes a photoelectric conversion unit that converts incident light into an electric charge, and 3. The imaging element according to claim 2, wherein the first signal is a signal output when each of the pixels is reset, and the second signal is a signal corresponding to an electric charge obtained by photoelectric conversion by the photoelectric conversion means.

4. each of the plurality of conversion means includes a current source and a resistor connected in series; Of the plurality of holding means, the holding means for holding the first signal is connected between the current source and the resistor, and the holding means for holding the second signal is connected on the opposite side of the resistor to the current source.

3. The imaging device according to claim 2, wherein the first and second lenses are arranged in a plane parallel to each other.

5. each of the plurality of conversion means includes a current source and a resistor whose resistance value is variable; 2. The image pickup device according to claim 1, wherein the resistance value of the resistor is increased when the switching means makes a connection.

6. each of the plurality of conversion means includes a current source and a resistor whose resistance value is variable; 2. The image sensor according to claim 1, wherein the resistance values ​​of the resistors are made different among the plurality of conversion means when the conversion means is connected by the switching means.

7. 6. The image pickup device according to claim 5, wherein when the switching means connects the plurality of conversion means, only one of the conversion means uses a current source.

8. further comprising a pixel section in which a plurality of pixels are arranged in a matrix; 2. The image sensor according to claim 1, wherein the different pixels are pixels in different columns.

9. 9. The imaging device according to claim 8, wherein the plurality of holding means, the plurality of conversion means, the switching means, and the plurality of output means are provided for each of a predetermined number of columns.

10. further comprising a pixel section in which a plurality of pixels are arranged in a matrix; 2. The image sensor according to claim 1, wherein the different pixels are pixels in different rows of the same column.

11. 11. The image sensor according to claim 10, wherein the plurality of holding means, the plurality of conversion means, the switching means, and the plurality of output means are provided for each column.

12. 2. The image pickup device according to claim 1, further comprising analog-to-digital conversion means for converting the currents output from the plurality of output means into digital signals.

13. The imaging device according to any one of claims 1 to 12; a processing means for processing a signal output from the imaging device; An electronic device comprising:

14. a step of causing a plurality of holding means to respectively hold a plurality of signals input from a plurality of different pixels; a step of causing a plurality of conversion means to convert the signals held in the plurality of holding means into currents according to potentials corresponding to the signals; causing a switching means to switch between connection and disconnection between the plurality of conversion means; a step of outputting the currents converted by the plurality of conversion means together when the switching means is connected, and outputting the currents converted by the plurality of conversion means individually when the switching means is not connected; 1. A method for controlling an imaging element, comprising:

Images