Thermal management structure and method of manufacturing thermal management structure

Abstract

To provide a packaging structure and a method of forming a packaging structure.SOLUTION: A packaging structure includes a first substrate 101 having a front surface 101F and a rear surface 101B on a side opposite to the front surface, and a thermal management structure 1 above the rear surface 101B. The thermal management structure 1 includes a first copper-phosphorus alloy layer 1c thermally coupled to the rear surface 101B of the first substrate 101. The packaging structure further includes a first adhesive layer 1a between the first copper-phosphorus alloy layer 1c and the rear surface 101B of the first substrate 101, and a first diffusion barrier layer 1b between the first adhesive layer 1a and the first copper-phosphorus alloy layer 1c. In the packaging structure, the first copper-phosphorus alloy layer 1c comprises Cu3P.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] (PRIORITY CLAIM AND CROSS REFERENCE) This application claims priority to U.S. Non-provisional Application No. 17 / 815,613, filed July 28, 2022, and U.S. Non-provisional Application No. 18 / 333,130, filed June 12, 2023, the disclosures of which are incorporated by reference in their entireties herein.

[0002] The specification and drawings set forth in U.S. Non-provisional Application No. 17 / 697,937, filed March 18, 2022, are hereby incorporated by reference in their entirety.

[0003] The present invention relates to a thermal management structure and a method for manufacturing a thermal management structure. [Background technology]

[0004] The integrated circuit (IC) industry is experiencing exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, feature density (i.e., the number of interconnected devices per die area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such miniaturization processes generally bring the benefit of increased production efficiency.

[0005] Semiconductor devices and integrated circuits are widely used in various electronic applications, such as mobile phones and other electronic devices. The dies of a wafer may be processed and packaged together with other semiconductor devices and dies at the wafer level, and various techniques have been developed for wafer-level packaging. For example, wafer-level packaging faces many challenges that must be addressed.

[0006] Poor heat dissipation and inability to achieve thermal management is a major problem in semiconductor structures and microelectronic packages, where localized overheating can occur that is undesirable for the yield, performance, and reliability of electronic devices. [Brief description of the drawings]

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard practice in the industry, various features have not been drawn to scale, and in fact, dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] [Figure 1] 1A-1D are cross-sectional views of semiconductor structures at intermediate stages of manufacturing operations according to some embodiments of the present disclosure. [Diagram 2] 1 is a cross-sectional view of a semiconductor structure according to some embodiments of the present disclosure. [Diagram 3] 1A-1D are cross-sectional views of semiconductor structures at intermediate stages of manufacturing operations according to some embodiments of the present disclosure. [Figure 4] 1A-1D are cross-sectional views of semiconductor structures at intermediate stages of manufacturing operations according to some embodiments of the present disclosure. [Figure 5A] 1A-1D are cross-sectional views of a package structure at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. [Figure 5B] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 5C] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 5D] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 6] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 7A]1A-1D are cross-sectional views of semiconductor structures at intermediate stages of manufacturing operations according to some embodiments of the present disclosure. [Figure 7B] 1A-1D are cross-sectional views of semiconductor structures at intermediate stages of manufacturing operations according to some embodiments of the present disclosure. [Figure 7C] 7C is a top view of the semiconductor structure of FIG. 7B at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. [Figure 7D] 7C is a top view of the semiconductor structure of FIG. 7B at an intermediate stage of a manufacturing operation, according to some embodiments of the present disclosure. [Figure 7E] 1A-1D are cross-sectional views of semiconductor structures at intermediate stages of manufacturing operations according to some embodiments of the present disclosure. [Figure 7F] 1A-1D are cross-sectional views of a package structure at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. [Figure 8] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 9A] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 9B] FIG. 9B is a perspective view of the package structure shown in FIG. 9A according to some embodiments of the present disclosure. [Figure 10] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 11] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 12] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 13] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 14] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. [Figure 15] 1A-1D are cross-sectional views of a package structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and organizations are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, spatially relative terms such as "below," "under," "lower," "upper," "top," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings for ease of description. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0011] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the present disclosure are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, these terms can refer to the exact occurrence of the event or circumstance, or to the approximate occurrence of the event or circumstance. For example, when used in conjunction with a numerical value, these terms can refer to a range of variation of the numerical value of ±10% or less, such as ±5% or less, ±4% or less, ±3% or less, ±2% or less, ±1% or less, ±0.5% or less, ±0.1% or less, or ±0.05% or less. For example, two numerical values ​​can be considered to be "substantially" the same or equal if the difference between the two numerical values ​​is within ±10% of the average of the numerical values, e.g., ±5% or less, ±4% or less, ±3% or less, ±2% or less, ±1% or less, ±0.5% or less, ±0.1% or less, or ±0.05% or less. For example, "substantially" parallel can refer to a range of angular variation of ±10° or less from 0°, e.g., ±5° or less, ±4° or less, ±3° or less, ±2° or less, ±1° or less, ±0.5° or less, ±0.1° or less, or ±0.05° or less. For example, "substantially" perpendicular can refer to a range of angular variation of ±10° or less from 90°, e.g., ±5° or less, ±4° or less, ±3° or less, ±2° or less, ±1° or less, ±0.5° or less, ±0.1° or less, or ±0.05° or less. Thus, unless otherwise indicated, the numerical parameters set forth in the present disclosure and the appended claims are approximations that may vary as desired. At the very least, each numerical parameter should be construed by taking into account the number of significant digits reported and applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to another endpoint, i.e., between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified.

[0012] The problem of poor heat dissipation is common in electronic devices. In particular, conventional heat dissipation sheets are large, heavy, and very thick, making them difficult to apply to electronic devices such as advanced package structures, which may go against the trend of miniaturization of electronic devices. Furthermore, conventional heat dissipation sheets are too heavy, causing reliability issues with adjacent microelectronic devices that may contain advanced technological features with low strain / stress resistance. In another comparative embodiment, conventional thermal interface materials (TIMs such as heat dissipation pastes) are prone to reliability issues. In particular, TIMs may burst under dry conditions, and TIMs may generate bubbles (which may further cause cracks) under wet conditions. Such issues have hindered the application of TIMs, particularly in automotive electronics, avionics, or other industries that have very high requirements for reliability. In another comparative embodiment, the use of substantially pure copper as a heat dissipation sheet may face the problem of copper oxidation, which tends to face reliability issues.

[0013] Thus, the present disclosure provides a thermal management structure that is highly compatible with various types of devices and can be smaller, thinner, and lighter. In particular, copper-phosphorous alloys (such as Cu3P) can be incorporated into heat dissipation structures in various types of applications, such as semiconductor devices, packages, wafers, wafer substrates, integrated circuits (ICs), printed circuit boards (PCBs), interposers, redistribution layers, core substrates, coreless substrates, ceramic substrates, bonding structures, bump structures, and the like. In some embodiments, the copper-phosphorous alloy layer may be formed by performing an electroless plating or electroplating operation. U.S. Non-Provisional Application No. 17 / 697,937, entitled Conductive structure including copper-phosphorous alloy and a method of manufacturing conductive structure, is incorporated herein by reference in its entirety. Details of plating techniques can be found by referring to the aforementioned incorporated references. For example, a copper-phosphorus alloy may be formed by providing a phosphorus-based chemical and a copper-based chemical in a plating solution, where the phosphorus-based chemical can be one of the following chemicals: phosphine (PH3), phosphoryl chloride (POCl3), or phosphorus trichloride (PCl3). In contrast, the copper-based chemical can be one of the following chemicals: copper(II) sulfate (CuSO4) or copper(II) pyrophosphate (Cu2P2O7). In some embodiments, the formed copper-phosphorus alloy exhibits improved quality and wettability, which can further improve device performance.

[0014] In the present disclosure, means for thermal management are provided for various types of package structures or semiconductor structures, as discussed with reference to Figures 1-14, respectively. Some embodiments provide a package structure in which thermal management structures are electroplated on the backside of the die in the better known top-side cooling (TSC) manner instead of the bottom-side cooling (BSC) method. Thus, the thermal management of the structure can be improved (since the thermal resistance of the leads is much higher compared to the exposed package top side), and the means for thermal management can help to improve heat dissipation as well as to bleed heat away to alleviate localized overheating problems (e.g., high voltage power devices can prevent the temperature at a certain location of the device from exceeding a threshold, slowing down the rate of temperature rise and increasing reliability).

[0015] Additionally, in the present disclosure, copper-phosphorus alloys (such as Cu3P) have a denser structure and can improve corrosion resistance, wear resistance, wettability, strength, toughness, compatibility, processability, etc. Additionally, heat dissipation structures including copper-phosphorus alloys (such as Cu3P) have higher thermal and electrical conductivity compared to conventional heat sinks and conventional thermal interface materials (such as thermal pastes).

[0016] Copper(I) phosphide (Cu3P) in this disclosure is a non-stoichiometric compound Cu 3-x P may be included, and in some embodiments, x may be less than 0.1, resulting in copper-deficient Cu3P. In other words, the phosphorus content (e.g., calculated by weight percent) in copper(I) phosphide may range from about 13.98% to about 14.39%.

[0017] The aforementioned advantages of copper-phosphorus alloys (especially Cu3P) provide better overall device performance, and their high compatibility with semiconductor structure manufacturing operations allows for increased potential for modifying the configuration of package structures that can further enhance device performance. In some cases, the lack of compatibility and processability of conventional heat dissipation devices can limit their potential application in packaging technology.

[0018] The present disclosure utilizes plating operations to form copper-phosphorus alloys (particularly Cu3P), which can be adapted to various types of processes to form semiconductor devices, packages, wafers, wafer substrates, PCBs, ICs, interposers, redistribution layers, core substrates, coreless substrates, ceramic substrates, bonding structures, bump structures, and the like.

[0019] In some embodiments, copper-phosphorus (which may include Cu3P) may be formed by electroless plating or electroplating techniques. Electroless plating (which may also be referred to as chemical plating or autocatalytic plating) is a type of technique that produces metal or metal-containing alloy coatings on various materials by autocatalytic chemical reduction of metal cations in a liquid bath, where the workpiece to be plated is immersed in a reducing agent, which, when catalyzed by a particular material, transforms the metal ions into metals that form a coating on the workpiece. In general, the advantages of electroless plating techniques include compatibility and product quality. In some cases, electroless plating techniques can be applied to both conductive and non-conductive workpieces, and are also applicable to small workpieces or workpieces with small surface areas. Furthermore, the coating layer formed by electroless plating techniques may exhibit higher corrosion resistance and / or higher wear resistance compared to electroplating techniques.

[0020] In contrast, electroplating is a technique for forming metallic coatings on various materials by applying an externally generated electric current. Advantages of electroplating techniques include higher efficiency and higher throughput.

[0021] In general, it is easy to control the thickness of copper-phosphorus using electroless or electroplating operations, and even if the thickness of thermal management structures including copper-phosphorus is small, such films still exhibit excellent thermal management properties.

[0022] An embodiment of a semiconductor structure including a thermal management structure 1 including an adhesion layer 1a, a diffusion barrier layer 1b above the adhesion layer 1a, and a copper-phosphorus alloy layer 1c (which may include CuP) above the diffusion barrier layer 1b is described below with reference to FIG.

[0023] Referring to Figure 1, Figure 1 is a cross-sectional view of a semiconductor structure at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure: A substrate 101 is provided, the substrate 101 including a front surface 101F and a back surface 101B facing away from the front surface 101F.

[0024] In some embodiments, the substrate 101 is thinned to a predetermined thickness, for example, the substrate 101 is thinned until the thickness T101 of the substrate 101 is about 20 μm to about 50 μm. In some embodiments, a predetermined dicing area 101D is defined in the substrate 101, and the substrate 101 can then be divided to match the dicing area 101D. In some embodiments, a half-cut dicing operation is performed, creating a groove that extends to a central location of the substrate 101, and the portions of the substrate 101 are temporarily not yet separated. In some alternative embodiments, scribe lines can be formed in the substrate to define the areas that will be diced later.

[0025] In some embodiments, the substrate 101 is flipped upside down for the photolithography process. That is, the back surface 101B of the substrate 101 faces upward. A lift-off method is applied to deposit the thermal management structure 1 on the back surface 101B and around the die on the substrate 101. A photoresist layer 191, which may be a dry film acting as a protective layer, is formed above the back surface 101B of the substrate 101, and the photoresist layer 191 may include a negative photoresist of an epoxy-based photoresist material (e.g., SU-8 photoresist, etc.) or a positive photoresist of a polymer material (e.g., polymethylmethacrylate (PMMA), etc.). It is noted that the resolution of the positive photoresist is better than that of the negative photoresist, but electron beam lithography is required to change the positive photoresist into a negative photoresist.

[0026] The photoresist layer 191 may be partially removed to expose at least a portion of the backside 101B of the substrate 101. In some embodiments, remaining portions of the photoresist layer 191 may overlap the dicing area 101D (or scribe line). A thermal management structure 1 is then formed over the exposed portion of the backside 101B of the substrate 101. In some embodiments, the thermal management structure 1 comprises a copper-phosphorus alloy (such as Cu3P).

[0027] In some embodiments, forming the thermal management structure 1 includes forming an adhesion layer 1a over an exposed portion of the backside 101B of the substrate 101, forming a diffusion barrier layer 1b over the adhesion layer 1a, and forming a copper-phosphorus alloy layer 1c (which may include Cu3P) over the diffusion barrier layer 1b. In some embodiments, during the formation of the thermal management structure 1, a composite metal layer 192, including portions of the adhesion layer 1a, the diffusion barrier layer 1b, and the copper-phosphorus alloy layer 1c, is also simultaneously formed or deposited on the top portion of the photoresist layer 191.

[0028] In some embodiments, the adhesion layer 1a is configured to mitigate lattice mismatch issues caused by the underlying silicon surface (i.e., the exposed portion of the backside 101B of the substrate 101), such as by eutectic bonding. Thus, the adhesion layer 1a can enhance adhesion between the thermal management structure 1 and the substrate 101. The adhesion layer 1a may include at least one of: (a) a conductive layer, e.g., a metal layer (e.g., Ag, Al, Au, etc.) having a lattice constant relatively close to that of silicon; (b) a metal silicide layer (e.g., nickel silicide, cobalt silicide, palladium silicide, etc.) that may have a thickness in the range of 0.1 μm to about 0.6 μm; or (c) a wetting layer (e.g., nickel seed layer, etc.) that may reduce the lattice mismatch between nickel and silicon to about 0.4% and provide suitable adhesion between nickel and silicon. In some embodiments, the use of the adhesion layer 1a may help overcome reliability issues (e.g., peeling) when the copper-phosphorus alloy is incorporated into a semiconductor device.

[0029] In some embodiments, for adhesion layer 1a including a nickel seed layer, the thickness of adhesion layer 1a may range from about 0.5 μm to about 2 μm. Additionally, the nickel seed layer may be formed by forming a nickel layer over an underlying silicon surface (i.e., the exposed portion of the backside 101B of substrate 101) and annealing the nickel layer and substrate 101 to change the properties of the interface between the nickel layer and substrate 101. In some embodiments, the annealing operation may include using an excimer laser annealing operation (which may use laser gases such as XeF, XeCl, KrF, KrCl, ArF, fluorine gas, etc.). The annealing operation converts Ni2Si (higher nickel concentration) near the interface between the nickel layer and substrate 101 to NiSi, and further converts a portion of NiSi to NiSi2, which provides improved adhesive bonding over Ni2Si.

[0030] The diffusion barrier layer 1b can be utilized to mitigate diffusion and reduce internal stress. In some embodiments, the diffusion barrier layer 1b can include at least one of: (a) a cobalt-phosphorus (CoP) layer that can be formed by electroless plating techniques and can have a thickness ranging from about 0.1 μm to about 0.6 μm; (b) a nickel layer that can be formed by electroless plating operations and can have a thickness ranging from about 0.5 μm to about 2 μm; or (c) a refractory metal layer, metal nitride derivative, or metal alloy (Ti, W, Mo, Ta, V, titanium-tungsten, TiW nitride, W2N, TiN, TaN, etc.) that can be formed by physical vapor deposition (PVD) and can have a thickness ranging from about 0.1 μm to about 0.5 μm. Specifically, the cobalt-phosphorus (CoP) layer exhibits greater step coverage and greater ability to impede diffusion compared to materials formed by PVD operations. On the other hand, refractory metal layers, metal nitride derivatives or metal alloys (e.g., Ti, W, Mo, Ta, V, titanium-tungsten, TiW nitride, W2N, TiN, TaN, etc.) exhibit higher thermal conductivity while hindering diffusion at high temperatures.

[0031] The copper-phosphorus alloy layer 1c has a higher thermal conductivity and a denser structure than conventional heat sinks and thermal interface materials, and can improve corrosion resistance, wear resistance, wettability, strength, toughness, conformability, processability, etc.

[0032] Further, a lift-off method is applied to remove the photoresist layer 191. Not only the photoresist layer 191 but also the deposited three-layer composite metal layer 192 (1a, 1b, and 1c) can be removed, and only these three layers 1a, 1b, and 1c remain on each die. Then, the substrate 101 is separated into a plurality of dies by a dicing operation. For example, the dicing operation is a full-cut dicing operation, which can be performed according to the dicing area 101D or the scribe line. In some embodiments, the dicing operation is performed by using a diamond cutter or a laser. After performing the dicing operation, a separated portion of the substrate 101 (which may be a die) is obtained with the thermal management structure 1 disposed above the back surface 101B. As mentioned above, the thermal management structure 1 can facilitate thermal management with respect to heat dissipation. The thermal management structure 1 exhibits excellent thermal conductivity, ability to hinder diffusion, great adhesion to silicon surfaces, light weight, and small size (such as thinner thickness). Also, the operation for forming the thermal management structure 1 is highly compatible with other conventional operations for forming other electronic devices.

[0033] Next, an embodiment of a semiconductor structure including a thermal management structure 1 will be described with reference to Fig. 2. Specifically, the thermal management structure 1 discussed with reference to Fig. 2 further includes a corrugated profile on a top surface facing away from the substrate 101. That is, the thermal management structure 1 includes a plurality of protrusions 1d. In some embodiments, the corrugated profile of the thermal management structure 1 includes a planar portion 1c and a corrugated portion 1d above the planar portion 1c.

[0034] A photoresist layer is patterned over the copper-phosphorus alloy layer 1c of the thermal management structure 1, and the photoresist layer may include an epoxy-based photoresist material (such as SU-8 photoresist) or a polymer material (such as polymethylmethacrylate (PMMA)). In some embodiments, the photoresist layer is patterned into several protruding sections 1d (resembling a corrugated crest profile), and at least a portion of the copper-phosphorus alloy layer 1c is exposed from the photoresist layer.

[0035] In some embodiments, the copper-phosphorus alloy material layer 1d is formed above the thermal management structure 1 and the photoresist layer by using an electroless plating operation with a thickness of less than 1 μm. Furthermore, the copper-phosphorus alloy layer 1d can also be formed by an electroplating operation with a thickness of less than 200 μm, resulting in a denser structure, a thicker layer, and improved efficiency. In some embodiments, the profile of the copper-phosphorus alloy material layer 1d matches the surface profile of the thermal management structure 1 and the photoresist layer. In some embodiments, the copper-phosphorus alloy material layer 1d includes a portion above the exposed portion of the copper-phosphorus alloy layer 1c and another portion above the photoresist layer.

[0036] A photoresist removal operation is carried out. It should be noted that the photoresist removal operation carried out here utilizes a negative photoresist such as polyisoprene rubber or a positive resist such as novolac resin, or their equivalents, as the photoresist, which can form a thinner layer compared to conventional epoxy-based photoresist materials (SU-8, PMMA, etc.), and can complete a lift-off operation to remove the photoresist layer and a portion of the copper-phosphorus alloy material layer immediately above the photoresist layer. After removing the photoresist, a portion of the copper-phosphorus alloy material layer remains, and this remaining portion is hereinafter referred to as protrusion 1d. Protrusion 1d includes a copper-phosphorus alloy (Cu3P, etc.).

[0037] Furthermore, a portion of the copper-phosphorus alloy layer 1c may be exposed from the protrusion 1d. The copper-phosphorus alloy layer 1c and the protrusion 1d may be collectively referred to as a thermally conductive layer 1X having a corrugated profile. Furthermore, the thermal management structure 1 (which may include, for example, an adhesive layer 1a, a diffusion barrier layer 1b, and a copper-phosphorus alloy layer 1c) and the protrusion 1d may be collectively referred to as a thermal management module 1Y, and a description of the adhesive layer 1a, the diffusion barrier layer 1b, and the copper-phosphorus alloy layer 1c may be found by referring to the description of FIG. 1. In some embodiments, a further etching operation may be performed to form a recess or hollow structure in the thermal management structure 1, thereby increasing the surface area and facilitating the heat dissipation capability. In some embodiments, the height of the protrusion 1d may be increased by repeating the operation described with reference to FIG. 2.

[0038] Next, an embodiment of a method for forming a die will be described with reference to Figures 3 and 4. Specifically, a thermal management structure 1, a copper-phosphorus alloy material layer 2 (see Figure 4), and a heat spreader 3 are incorporated into the semiconductor structure discussed with reference to Figures 3 and 4 to facilitate heat dissipation capabilities. The overall bottom area of ​​the heat spreader 3 can be larger than the die area 101D.

[0039] Referring to FIG. 3, FIG. 3 is a cross-sectional view of a semiconductor structure at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A carrier 381 having a first surface 381A and a second surface 381B opposite the first surface 381A is received. In some embodiments, the carrier 381 is made of a material with suitable hardness or mechanical strength. For example, the carrier 381 may be made of glass. A tape 382 is attached to the first surface 381A of the carrier 381. In some embodiments, the tape 382 is made of a silicone tape, a thermal release tape, an ultraviolet (UV) epoxy tape, or other suitable material. In some embodiments, the first surface 382A and the second surface 382B of the tape 382 are adhesive, and the second surface 382B of the tape 382 is attached to the first surface 381A of the carrier 381, and the first surface 382A of the tape 382 faces away from the carrier 381.

[0040] A plurality of dies 301 are attached to a first surface 382A of the tape 382. In some embodiments, each of the dies 301 has a front surface 301F attached to the first surface 382A of the tape 382 and a back surface 301B facing away from the tape 382. In some embodiments, some of the dies 301 are organized in an array or along one or more lines when viewed from above. In some embodiments, the dies are thinned before being attached to the tape 382. In some embodiments, some of the dies 301 are separated. In some embodiments, devices, active areas, or conductive features may be formed at locations proximate to the front surface 301F of the die 301.

[0041] In some alternative embodiments, a substrate is attached to the first surface 382A of the tape 382, ​​and the substrate is pre-processed with half-cut dicing to define the location of each die (i.e., how each die will be separated later), which facilitates the subsequent dicing operation. In other words, such a substrate includes multiple dies 301, some of which may be temporarily connected.

[0042] The thermal management structure 1 is formed over the die 301. Details of the thermal management structure 1 can be found by referring to the discussion regarding FIG. 1, where the thermal management structure 1 includes an adhesive layer 1a, a diffusion barrier layer 1b above the adhesive layer 1a, and a copper-phosphorus alloy layer 1c (which may include Cu3P) above the diffusion barrier layer 1b. In some embodiments, the adhesive layer 1a is attached to the die 301, and the copper-phosphorus alloy layer 1c is spaced from the die 301. The copper-phosphorus alloy layer 1c may be thermally coupled to the side of the die 301. In some embodiments, the thickness of the copper-phosphorus alloy layer 1c may be less than 200 μm. In some embodiments, the thermal management structure 1 may also be formed in the gap between the dies 301, and the adhesive layer 1a may be in direct contact with the sidewall of the die 301. In some embodiments, the copper-phosphorus alloy layer 1c is formed by electroless plating and electroplating operations, which may improve the quality of coverage of the copper-phosphorus alloy layer 1c over the die 301. Furthermore, problems caused by the connection of the thermal management structure 1 between the dies 301 can also be avoided.

[0043] In some embodiments, a first photoresist layer (not shown separately) is deposited and patterned to form a mask layer over the dicing areas (not shown separately) between the dies 301. When the thermal management structures 1 are deposited on the top and sidewalls of the die 301, portions of the first surface 382A of the tape 382 are covered by the first photoresist layer and therefore are not covered by the thermal management structures 1. The first photoresist layer may be removed or stripped after formation of the thermal management structures 1 is completed.

[0044] A plurality of heat spreaders 3 are disposed above the thermal management structure 1. In some embodiments, the back surface 301B of each die 301 is provided with one or more heat spreaders 3. In some embodiments, one die 301 corresponds to one heat spreader 3, and the width W3 of the heat spreader 3 is smaller than the width W301 of the die 301. In some embodiments, the heat spreader 3 may include materials such as copper, foamed copper, aluminum, thermally conductive metal, ceramic, Al2O3, AlN, etc. In some embodiments, to improve the efficiency of heat dissipation, the surface area of ​​each heat spreader 3 may be designed to be larger than the surface area of ​​a cube-shaped heat spreader with a similar volume. In some embodiments, the heat spreader 3 may have one or more surfaces with a corrugated profile. For example, each heat spreader 3 may have multiple fin-type protrusions on one or both sides (such as in the Z direction). In some embodiments, the heat spreader 3 is referred to as a fin-type heat spreader 3 over the entire outer surface. In some embodiments, the heat spreader 3 has multiple exposed gaps or holes to reduce weight and increase heat dissipation area. In some embodiments, the heat spreader 3 may have a bottom that is in direct contact with the copper-phosphorus alloy layer 1c of the thermal management structure 1. Considering the thermal capacity aspect, the heat spreader 3 can provide a path for heat dissipation and alleviate localized overheating problems.

[0045] The copper-phosphorus alloy material layer 2M is formed to cover the exposed surface of the heat spreader 3. In some embodiments, the copper-phosphorus alloy material layer 2M is made of Cu3P. In some embodiments, the copper-phosphorus alloy material layer 2M further covers the portion of the first surface 1A of the thermal management structure 1 exposed by the heat spreader 3. In some embodiments, the copper-phosphorus alloy material layer 2M covers the top, four sides, and bottom of the heat spreader 3. The thickness T2 of the copper-phosphorus alloy material layer 2M may range from about 20 μm to about 200 μm. In some embodiments, the copper-phosphorus alloy material layer 2M is formed by applying both electroless plating and electroplating operations, and the die 301, the carrier 381, the tape 382, ​​the thermal management structure 1, and the heat spreader 3 are placed in a plating solution of the system. The copper-phosphorus alloy material layer 2M provides good heat dissipation and further improves adhesion between the heat spreader 3 and the copper-phosphorus alloy layer 1c (not shown in FIG. 3 but visible in FIG. 1) of the thermal management structure 1. That is, the heat spreader 3 may be in close contact with the die 301, improving reliability.

[0046] In some embodiments, a second photoresist layer (not shown separately) is deposited and patterned to form a mask layer above the dicing area between the dies 301. When the copper-phosphorus alloy material layer 2M is deposited on the top surface and sidewalls of the heat spreader 3, a portion of the top surface 382A of the tape 382 is covered by the second photoresist layer and is therefore not covered by the copper-phosphorus alloy material layer 2M. The second photoresist layer may be removed or peeled off after completion of the formation of the copper-phosphorus alloy material layer 2M of the thermal management structure 1. The narrow space in the dicing area between the dies 301 that is not occupied by the thermal management structure 1 or the copper-phosphorus alloy material layer 2M can reduce the material thickness in the dicing area, and thus the dicing operation can be performed more smoothly.

[0047] 3 and 4, FIG. 4 is a cross-sectional view of a semiconductor structure at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A dicing operation is performed to separate each die 301 in a predetermined manner. In some embodiments, the dicing operation is performed by using a diamond cutter or a laser. It is noted that the thickness T2 (shown in FIG. 3) of the copper-phosphorus alloy material layer 2M (or 2) (shown in FIG. 3) may range from about 20 μm to about 200 μm. In some embodiments, the depth of the dicing operation can reach the front surface 381F (shown in FIG. 3) of the die.

[0048] 3 and 4, after the dicing operation, the die 301 can be separated from the tape 382, ​​thereby obtaining the die 301, the thermal management structure 1, the copper-phosphorus alloy material layer 2 (the portion remaining in the copper-phosphorus alloy material layer 2M after dicing), and one or more heat spreaders 3 attached to the die 301. Hereinafter, the thermal management structure 1, the copper-phosphorus alloy material layer 2, and the one or more heat spreaders 3 are collectively referred to as a thermal management auxiliary unit 4.

[0049] In the present specification, the copper-phosphorus alloy material layer 2 exhibits great capabilities in corrosion resistance, wear resistance, strength and / or toughness. Therefore, the copper-phosphorus alloy material layer 2 can also function as an anti-corrosion (anti-rust) protective layer. This allows additional anti-rust treatment for the heat spreader 3 to be omitted, reducing costs and improving throughput. In addition, some of the conventional anti-rust treatments may even reduce the heat dissipation capability of the heat spreader 3. In addition, as described above, the formation of the copper-phosphorus alloy material layer 2 is highly compatible with various materials of the heat spreader 3 (e.g., including but not limited to copper, foamed copper, aluminum, thermally conductive metals, ceramics, Al2O3, and AlN).

[0050] In some alternative embodiments, the thermal management auxiliary unit 4 may further include a conductive layer 2a, a first copper-phosphorus alloy material layer 2b, and a second copper-phosphorus alloy material layer 2c. The conductive layer 2a may be a silver layer or gold coated in a conformal manner above the heat spreader 3. That is, the conductive layer 2a is between the first copper-phosphorus alloy material layer 2b and the heat spreader 3. In some embodiments, the conductive layer 2a covers the top, four sides, and bottom of the heat spreader 3, and the first copper-phosphorus alloy material layer 2b covers the top and four sides of the conductive layer 2a. The silver (or gold) layer 2a can further enhance the heat dissipation capability. Furthermore, the first copper-phosphorus alloy material layer 2b can mitigate the oxidation of the underlying conductive layer 2a and further enhance the corrosion resistance capability of the thermal management auxiliary unit 4. The second copper-phosphorus alloy material layer 2c may be formed on the surfaces of the gaps and holes at the bottom of the heat spreader 3X. In some embodiments, the surfaces of the gaps and holes at the bottom of the heat spreader 3X are coated in a conformal manner with a conductive layer 2a, which is then coated with a second copper-phosphorus alloy material layer 2c.

[0051] In some alternative embodiments, the copper-phosphorus alloy layer 1c of the thermal management structure 1 can be replaced with an aluminum layer, which can be formed by a plating operation. The aluminum layer has excellent heat dissipation capability and low cost. In some embodiments, an anodizing operation may be performed to enhance the corrosion and rust resistance of the aluminum layer.

[0052] The thermal management structure 1 may further be incorporated into a packaging structure, as discussed with reference to FIG. 5A.

[0053] Referring to FIG. 5A, FIG. 5A is a cross-sectional view of a package structure by using copper pillars at an intermediate stage of manufacturing operations according to some embodiments of the present disclosure. Compared to traditional solder bumps, copper pillar technology allows for better control of joint diameter and standoff height, allowing for the creation of finer pitch joints (20-40 μm), while solder bump technology reaches its pitch limit of less than about 125 μm. Copper pillars can provide a cylindrical joint between the bottom of the die and the top of the package substrate. Other benefits include improved electromigration resistance, thermal conductivity, thermal cycling reliability, simplified under-bump metallization (UBM), and higher I / O density. Copper pillar joints are less subject to these limitations and are a must-have feature that allows for the latest silicon process nodes of 28 nm and below, as well as smaller devices and reduced number of package substrate layers, thereby reducing costs, as required by mobile device manufacturers.

[0054] In FIG. 5A, a semiconductor substrate 501 (which may be a semiconductor wafer or a silicon interposer in some embodiments) is provided, the substrate 501 including a front surface 501F and a back surface 501B facing away from the front surface 501F. One or more conductive pads 502, which may function as input / output (I / O) pads for the substrate 501, may be formed above the front surface 501F of the semiconductor substrate 501. In some embodiments, the semiconductor substrate 501 may be a silicon substrate. An insulating layer 503 is formed above the semiconductor substrate 501 and then selectively removed to expose at least a portion of the conductive pads 502. In some embodiments, the insulating layer 503 comprises SiO2. In embodiments where the semiconductor substrate 501 is a silicon interposer, the thickness of the semiconductor substrate 501 may range from about 20 μm to about 50 μm.

[0055] The thermal management structure 1 above the backside 501B of the substrate 501 and an under bump metallization (UBM) material layer (not shown, but patterned to become the UBM layer 1U) above the insulating layer 503 and the conductive pads 502 may be formed in a single operation. In some embodiments, the composition of the UBM material layer is similar to the composition of the thermal management structure 1. Specifically, the UBM material layer and the thermal management structure 1 may each include an adhesion layer 1a, a diffusion barrier layer 1b above the adhesion layer 1a, and a copper-phosphorus alloy layer 1c (which may include Cu3P) above the diffusion barrier layer 1b. The adhesion layer 1a of the thermal management structure 1 is adjacent to the backside 501B of the substrate 501, and the adhesion layer 1a of the UBM material layer is adjacent to the insulating layer 503 and the conductive pads 502. The copper-phosphorus alloy layer 1c of the thermal management structure 1 is spaced from the backside 501B of the substrate 501, and the copper-phosphorus alloy layer 1c of the UBM material layer is spaced from the insulating layer 503 and the conductive pad 502. In some embodiments, the thickness of the adhesion layer 1a is in the range of about 0.5 μm to about 2.0 μm. In some embodiments, the thickness of the diffusion barrier layer 1b is in the range of about 0.1 μm to about 0.5 μm. In some embodiments, the thickness of the copper-phosphorus alloy layer 1c is in the range of about 1 μm to about 3 μm.

[0056] Specifically, the adhesive layer 1a is formed over the back surface 501B of the substrate 501 and over the insulating layer 503 and the conductive pad 502 (which are over the front surface 501F of the substrate 501), respectively. The copper-phosphorus alloy layer 1c of the thermal management structure 1 and the copper-phosphorus alloy layer 1c of the UBM material layer can be formed in a single operation. In some embodiments, the adhesive layer 1a on the back surface 501B and the front surface 501F of the substrate 501 can be formed in a single operation. As described above with reference to FIG. 2, the adhesive layer 1a is configured to mitigate lattice mismatch problems caused by the underlying silicon surface, such as by eutectic bonding. Thus, the adhesive layer 1a can enhance adhesion between the thermal management structure 1 and the back surface 501B of the substrate 501. Furthermore, the adhesive layer 1a of the UBM material layer can improve the reliability of subsequent bonding operations due to its high adhesive strength.

[0057] The adhesion layer 1a may include at least one of: (a) a conductive layer, e.g., a metal layer (Ag, Al, Au, etc.) having a lattice constant relatively close to that of silicon; (b) a metal silicide layer (nickel silicide, cobalt silicide, palladium silicide, etc.); or (c) a wetting layer (such as a nickel seed layer), which can reduce the lattice mismatch between nickel and silicon to about 0.4% and provide sufficient adhesion between nickel and silicon.

[0058] In some embodiments, when the adhesion layer 1a includes a nickel seed layer, the nickel seed layer may be formed by an electroless plating operation followed by an annealing operation. In some embodiments, the annealing operation may include using an excimer laser annealing operation (which may use laser gas such as XeF, XeCl, KrF, KrCl, ArF, fluorine gas, etc.). Furthermore, by using an electroless plating method, the adhesion layer 1a on the back surface 501B and the front surface 501F of the substrate 501 can be formed at once.

[0059] The diffusion barrier layer 1b can be utilized to mitigate copper diffusion to the pads in the conductive pillars 506 (the diameter and pitch vary for different applications, such as 5 μm and 10 μm, respectively, for DRAM), potentially reducing internal stress. In some embodiments, the diffusion barrier layer 1b can include at least one of: (a) a cobalt-phosphorous (CoP) layer, which can be formed by electroless plating techniques; (b) a nickel layer, which can be formed by electroless plating operations; or (c) a refractory metal layer, a metal nitride derivative, or a metal alloy (Ti, W, Mo, Ta, V, titanium-tungsten, TiW nitride, W2N, TiN, TaN, etc.). In particular, the cobalt-phosphorous (CoP) layer has a greater step coverage and greater ability to impede diffusion compared to materials formed by PVD operations. On the other hand, refractory metal layers, metal nitride derivatives or metal alloys (e.g., Ti, W, Mo, Ta, V, titanium-tungsten, TiW nitride, W2N, TiN, TaN, etc.) exhibit higher thermal conductivity while hindering diffusion at high temperatures. In some embodiments, when a cobalt-phosphorus (CoP) layer or a nickel layer is used as the material of the diffusion barrier layer 1b of the thermal management structure 1 and as the material of the UBM material layer, both the diffusion barrier layer 1b of the thermal management structure 1 and the diffusion barrier layer 1b of the UBM material layer can be formed in a single operation by an electroless plating operation.

[0060] The copper-phosphorus alloy layer 1c has a higher thermal conductivity and a denser structure than conventional heat sinks and thermal interface materials, and can improve corrosion resistance, wear resistance, wettability, strength, toughness, conformability, processability, etc.

[0061] In some embodiments, the copper-phosphorus alloy layer 1c can be formed by performing an electroless plating operation. In particular, by using an electroless plating operation, the copper-phosphorus alloy layer 1c of the thermal management structure 1 (above the back surface 501B of the substrate 501) and the copper-phosphorus alloy layer 1c of the UBM material layer (above the front surface 501F of the substrate 501) can be formed in a single operation, since the entire substrate 501 can be immersed in a plating solution.

[0062] Further, the conductive pillars 506 are formed above the UBM material layer, and then the alloy layer 507 is formed above the conductive pillars 506. For example, a photoresist layer (or dry film, not shown) can be formed above the UBM material layer, and a photolithography operation can be performed using a patterned mask (not shown). The conductive pillars 506 can be formed from a conductive material, for example, copper, and the alloy layer 507 can be referred to as a soldering material for bonding. A plurality of recesses corresponding to the conductive pads 502 are defined by the photoresist layer, whereby at least a portion of the UBM material layer is exposed through the photoresist layer. In some embodiments, a protective layer (such as a photoresist layer or dry film) can be formed above the copper-phosphorus alloy layer 1c of the thermal management structure 1. Also, the conductive pillars 506 can be formed in the recesses, and the conductive pillars 506 can be in direct contact with the copper-phosphorus alloy layer 1c of the UBM material layer. In some embodiments, the conductive pillars 506 may be formed by an electroplating operation, which may be more efficient as discussed above. Additionally, the protective layer may protect the thermal management structure 1 during the electroplating operation. In some embodiments, the thickness of the conductive pillars 506 may range from about 8 μm to about 10 μm.

[0063] In some embodiments, the solder alloy layer 507 may include Sn-Ag alloy such as Sn, Ag, Cu, and Sb (e.g., 96.3% Sn, 3% Ag, 0.5% Cu, and 0.2% Sb). In some alternative embodiments, the solder alloy layer 507 may include Sn, Ag, Bi, and Cu (e.g., 93.3% Sn, 3.1% Ag, 3.1% Bi, and 0.5% Cu). In some embodiments, the thickness of the solder alloy layer 507 may range from about 10 μm to about 15 μm. In some embodiments, the solder alloy layer 507 may be utilized as a conductive bump for a subsequent bonding operation. After forming the solder alloy layer 507, the photoresist protective layer may be removed by performing a lift-off operation to expose the sidewalls of the conductive pillars 506 and the sidewalls of the solder alloy layer 507.

[0064] Further, by removing the portion of the UBM material layer that is not under the coverage of the conductive pillars 506, the underlying portion of the insulating layer 503 is exposed to form the UBM layer 1U (which is a patterned version of the UBM material layer). In some embodiments, the removal operation may include a reactive ion etching (RIE) operation or other suitable removal operation. Thereby, the remaining UBM layer 1U and the conductive pads 502 can be collectively referred to as conductive pads, contact pads, or input / output (I / O) pads 509. In other words, the conductive pads 509 include a copper-phosphorus alloy (such as Cu3P). During the formation of the UBM layer 1U, there is no need to create a vacuum environment, which may be expensive and face challenges of low throughput. The patterned mask layer may be removed from the front side of the substrate 501 after the formation of the UBM layer 1U and the thermal management structure 1. The patterning of the UBM material layer to form the UBM layer can be performed before the formation of the conductive pads 502 and the conductive pads 509, or after the patterning operation of the conductive pads 502 and the conductive pads 509.

[0065] A reflow operation can also be performed to form pillars including copper-based alloys and Sn-Ag alloys. The semiconductor substrate 501 can be bonded to a carrier 599 (such as an IC substrate or substrate) to form a package. In some embodiments, the conductive pads 509 including copper-phosphorus alloys as described with reference to the present disclosure can be applied to other multi-layer wiring structures such as wafer substrates, PCBs, interposers, IC carriers, redistribution layers, core substrates, coreless substrates, ceramic substrates, etc. Such configurations may improve the reliability and performance of the electrical connections.

[0066] FIG. 5B is a cross-sectional view of a package structure 530 according to some embodiments of the present disclosure. The package structure 530 may be similar to the package structure shown in FIG. 5A, and details of these similar features will not be repeated for brevity. With reference to FIG. 5B, a substrate 501 is provided. One or more conductive pads 502 are then deposited and patterned over a front surface 501F of the substrate 501. An insulating layer 522 is formed over the front surface 501F and the conductive pads 502. The insulating layer 522 may be formed of a dielectric material, for example, silicon oxide. The insulating layer 522 is patterned to remove portions of the insulating layer 522 from the top surfaces of the conductive pads 502 such that central portions of each of the conductive pads 502 are exposed.

[0067] The adhesion layer 1a of the UBM layer 1U is formed and patterned above the conductive pad 502. The sidewalls of the patterned adhesion layer 1a may be flush with the sidewalls of the insulating layer 522. The patterning of the adhesion layer 1a may include lithography and etching operations associated with a lift-off process using a lift-off photoresist layer. A first layer 524, a second layer 526, and a third layer 528 of a dielectric layer are then deposited above the adhesion layer 1a and the insulating layer 522 to form a tri-layer anti-reflective structure 529. The tri-layer anti-reflective structure 529 may be formed from several dielectric layers to form a dielectric layer stack. According to some embodiments, the first layer 524 and the third layer 528 of the tri-layer anti-reflective structure 529 include silicon nitride, silicon oxynitride, etc., and are deposited using a low-temperature deposition method or a spin-on coating method. According to some embodiments, the second layer 526 of the triple layer anti-reflective structure 529 comprises silicon oxide or the like and is deposited using a low temperature deposition or spin-on coating method. The first layer 524 may be conformally deposited over the top surface of the insulating layer 522 and the adhesion layer 1a, and the second layer 526 and the third layer 528 may be blanket deposited over the first layer 524.

[0068] One or more vias (not separately shown) are formed through the tri-layer anti-reflective structure 529 to expose the adhesion layer 1a. According to some embodiments, a photoresist layer (not separately shown) is blanket deposited above the tri-layer anti-reflective structure 529. Photolithography and etching operations are performed to etch vias through layers 528, 526, and 524 until the top surface of adhesion layer 1a is exposed. The sidewalls of layers 524, 526, and 528 may define the sidewalls of the vias above adhesion layer 1a.

[0069] Subsequently, the diffusion barrier layer 1b and the copper-phosphorus alloy layer 1c of the UBM layer 1U are deposited above the adhesion layer 1a and the upper surface of the photoresist layer above the three-layer anti-reflection structure 529. Furthermore, a conductive material for forming a conductive pillar 506 is deposited in the via above the UBM layer 1U. A conductive material for forming a solder alloy layer 507 is deposited above the conductive material of the conductive pillar 506. According to some embodiments, the deposition operation of the conductive pillar 506 can be repeated several times to increase the deposition height of the conductive pillar 506 according to different requirements.

[0070] A lift-off operation is performed on the photoresist layer to remove it from the tri-layer anti-reflective structure 529. Excess material of the conductive material for forming the conductive pillars 506 and the solder alloy layer 507 above the tri-layer anti-reflective structure 529 is also removed together with the removal of the photoresist layer. As a result, the top surface of the third layer 528 is exposed. A reflow operation is performed on the material of the solder alloy layer 507 to form a spherical or hemispherical solder alloy layer 507.

[0071] According to some embodiments, the conductive pillars 506 may be formed through the substrate 501 via a through substrate via (TSV) structure where the substrate 501 is generally formed in bulk silicon. In that case, the substrate 501 may be thinned and through vias formed through the substrate 501, after which the tri-layer anti-reflective structure 529 is deposited and the through vias are electroplated with copper. The remaining operations for forming the UBM layer 1U and the conductive pillars 506 are similar to the embodiment previously described with respect to the package structure 530.

[0072] The package structure 530 provides an advantage: since the space between the adjacent conductive pillars 506 and the solder alloy layer 507 is filled with the three-layer anti-reflective structure 529, external particles, moisture, water or dust will not enter the gaps between the conductive pillars 506. As a result, the electrical insulation performance and reliability of the conductive pillars 506 can be maintained.

[0073] FIG. 5C is a cross-sectional view of a package structure 540 according to some embodiments of the present disclosure. The package structure 540 is similar to the package structure 530 in many aspects, and these similar features will not be repeated for brevity. With reference to FIG. 5B and FIG. 5C, the difference between the package structure 540 and the package structure 530 is that most of the triple-layer anti-reflective structure 529 between adjacent conductive pillars 506 has been removed. Only a thin portion of the triple-layer anti-reflective structure 529 remains on the sidewall of the diffusion barrier layer 1b. According to some embodiments, the horizontal portion of the first layer 524 is retained above the insulating layer 522 to protect and encapsulate the underlying insulating layer 522.

[0074] FIG. 5D is a cross-sectional view of a package structure 550 according to some embodiments of the present disclosure. The package structure 550 is similar to the package structure 530 or 540 in many aspects, and these similar features will not be repeated for brevity. With reference to FIG. 5C and FIG. 5D, the difference between the package structure 550 and the package structure 540 is that the second layer 526 and the third layer 528 of the three-layer anti-reflective structure 529 between adjacent conductive pillars 506 are entirely removed. The first layer 524 of the three-layer anti-reflective structure 529 remains on the sidewalls of the diffusion barrier layer 1b, the adhesive layer 1a, and the insulating layer 522, and above the horizontal portion of the insulating layer 522. The spaces between adjacent conductive pillars 506 are filled with only air, so that the diffusion barrier layers 1b of adjacent conductive pillars 506 face each other.

[0075] 5A, the adhesion layer 1a, the diffusion barrier layer 1b, and the copper-phosphorus alloy layer 1c of the thermal management structure 1 can be deposited simultaneously with the formation of the adhesion layer 1a, the diffusion barrier layer 1b, and the copper-phosphorus alloy layer 1c of the UBM layer 1U, respectively. According to some embodiments, the adhesion layer 1a and the UBM layer of the thermal management structure 1 can be formed using a single deposition process, the diffusion barrier layer 1b and the UBM layer of the thermal management structure 1 can be formed using a single deposition process, and the copper-phosphorus alloy layer 1c and the UBM layer of the thermal management structure 1 can be formed using a single deposition process. With reference to FIGS. 5B-5D, although not separately illustrated, the thermal management structure 1 can also be formed on the backside 501B of the substrate 501 of the package structure 530, 540, or 550. Similarly, the adhesion layer 1a, the diffusion barrier layer 1b, and the copper-phosphorus alloy layer 1c of the thermal management structure 1 of the package structures 530, 540, 550 may be deposited simultaneously with the formation of the adhesion layer 1a, the diffusion barrier layer 1b, and the copper-phosphorus alloy layer 1c of the UBM layer 1U of the package structures 530, 540, 550, respectively. According to some embodiments, the adhesion layer 1a of the thermal management structure 1 and the UBM layer of the package structures 530, 540, or 550 may be formed using a single deposition process, the diffusion barrier layer 1b of the thermal management structure 1 and the UBM layer of the package structures 530, 540, or 550 may be formed using a single deposition process, and the copper-phosphorus alloy layer 1c of the thermal management structure 1 and the UBM layer of the package structures 530, 540, 550 may be formed using a single deposition process.

[0076] Next, an embodiment of a package structure with a thermal management structure including an interface layer 6 and a copper-phosphorus alloy layer 7 will be described with reference to FIG.

[0077] Referring to FIG. 6, FIG. 6 is a cross-sectional view of a package structure (such as Fan-Out Wafer Level Package (FOWLP)) according to some embodiments of the present disclosure. There are two fan-out structures / processes, the first of which is chip-first, where the chip is first embedded in a temporary (carrier or panel) or permanent material structure, followed by a RDL (redistribution layer) formation process. The second of which is chip-last (also known as RDL-first), where the chip is not incorporated into the packaging process until the RDL on the carrier or panel is pre-formed. In the following embodiments, either the first structure / process (with some intervening layers of ABF or BT) is modified or a second structure / process (such as a ceramic interposer) is applied. In some embodiments, each of the dies 803 has a front surface 803F with a conductive pattern and a back surface 803B opposite the front surface 803F. In some embodiments, the die 803 is thinned before being attached to the tape. In some embodiments, the die 803 is a known good die (KGD). In some embodiments, the die 803 is a fan-out type semiconductor die. Referring to FIG. 5A and FIG. 6, the UBM layer 1U of the bump structure 510 disposed above the front surface 803F of the die 803 contacts the input / output (I / O) pads (or contact pads) 502 on the front surface of the die 803. Referring to FIG. 6, the substrate 501 may be diced to produce a plurality of dies 803. The plurality of dies 803 are arranged with their back surfaces 803B attached on a tape or panel (e.g., silicon tape, thermal release tape, ultraviolet (UV) epoxy tape, or other suitable material) and / or a carrier (not shown), each of the dies 803 being spaced apart from each other at a pitch, thus forming a fan-out interposer having a fan-out region RO between the two dies 803 to comply with the specifications of the fan-out device. The encapsulant or molding compound 804 is formed only in the fan-out region RO to encapsulate, e.g., laterally surround, the die 803.The molding compound 804 may further be formed in the gap between the dies 803. The molding compound 804 may encapsulate at least one side of the die 803. In some embodiments, the thickness T804 of the molding compound 804 in the fan-out region RO is similar to the thickness T803 of the die 803. In some embodiments, the difference between the thickness T804 and the thickness T803 is in the range of about 2 μm to about 5 μm. In some embodiments, the molding compound 804 is made of epoxy molding compound (EMC), polyimide (PI), or other suitable material such as a plastic or polymer material. In some embodiments, the molding compound 804 may be formed by molding techniques (such as injection molding), 3D printing, additive manufacturing, etc. In some embodiments, multiple recesses are formed in molding compound 804 in fan-out region RO of redistribution layer (RDL) 811, which allow for the subsequent formation of conductive vias 805 (with diameter and pitch varying for various applications, such as 5 μm and 10 μm, respectively, for DRAM), which may be formed as through vias in molding compound 804. Stated another way, conductive vias 805 are laterally surrounded by molding compound 804.

[0078] 5 and 6, following the FOWLP fabrication process, several vias are formed either on the input / output (I / O) pads 502 (or contact pads) or in the molding compound 804, and then copper is electroplated to fill both vias and also form the intervening conductive features 812. Finally, conductive pillars 8a and alloy (tin-silver (Sn-Ag)) layer 8b are formed on the interposer 811. In some embodiments, a protective layer (not shown, which can be photoresist, dry film, tape, mask, or sacrificial layer) is formed above the RDL 811 during the formation of 8a and 8b.

[0079] In some embodiments, the conductive vias 805 are made of copper and may be formed by an electroplating operation.

[0080] A redistribution layer (RDL) 811 of the fan-out interposer FO is formed on the front surface 803F of the die 803 with a bump structure (not shown) on the pads 502 (part A shown in FIG. 6), and the pads 502 of the die are fanned out by the interposer 811. The bump structure on the pads 502 in FIG. 6 may correspond to the bump structure 510 in FIG. 5, which includes a conductive pad 509, a conductive pillar 506, and an alloy layer 507. In some embodiments, the bonding operation is discussed with reference to FIG. 5 of this disclosure or FIGS. 5A-5D of U.S. Non-Provisional Application No. 17 / 697,937, which is incorporated herein by reference. The RDL 811 includes a plurality of conductive features 12 facing away from the die 803. The module M1 formed by the die 803, molding compound 804, conductive vias 805 formed in molding compound 804, and redistribution layer (RDL) 811 can then be separated from the tape. Module M1 is then flipped and placed on another tape for the next manufacturing steps, such as:

[0081] An interface layer 6 and a copper-phosphorus alloy layer 7 are formed above the back surface 803B of each die 803. In some embodiments, the interface layer 6 includes an adhesion layer and a diffusion barrier layer, which may correspond to the adhesion layer 1a and the diffusion barrier layer 1b described with reference to FIG. 1 or FIG. 5A. In some embodiments, a copper-phosphorus alloy layer 7 (which may be made of Cu3P) is formed above each interface layer 6 by an electroless plating operation with a thickness of less than 1 μm. Furthermore, the copper-phosphorus alloy layer 7 can also be formed by an electroplating operation with a thickness of less than 200 μm, resulting in a denser structure, a thicker layer, and improved efficiency. In this disclosure (including other applicable embodiments), the interface layer 6 and the copper-phosphorus alloy layer 7 are collectively referred to as a thermal management structure TM that is thermally coupled to the back surface 803B of the die 803. In some embodiments, both the interface layer 6 and the copper-phosphorus alloy layer 7 may extend further to locations above a portion of the molding compound 804 and some of the conductive vias 805 formed in the molding compound 804. In some embodiments, a protective layer (not shown, which can be a photoresist, dry film, tape, mask or sacrificial layer) is formed above the RDL 811 during the formation of the interface layer 6 and the copper-phosphorus alloy layer 7 to avoid contamination.

[0082] In some embodiments, the subset of conductive vias 805 covered by interface layer 6 and copper-phosphorus alloy layer 7 may be referred to as ball grid array ground vias or ground through vias 805' in some applications below. The ground through vias 805' may be arranged adjacent to the remaining through vias 805 not covered by interface layer 6. The ground through vias 805' are electrically connected to a thermal management structure of a bump structure 510 on a pad 502 above the front surface 803F of the die 803 via a conductive feature 812. In some embodiments, the bump structure 510 on the pad 502 is connected to a system ground point G and configured to ground the die 803. Sometimes, the combination of the conductive ground feature 812, the ground through vias 805', and the bump structure on the pad 502 can increase the heat dissipation efficiency by 30-40% over the application of the thermal management structure TM alone. These new ideals are the focus of the present invention.

[0083] The pillar 8 is formed above the plurality of conductive vias 805 exposed by the interface layer 6 and the copper-phosphorus alloy layer 7. Furthermore, the pillar 8 is formed above the plurality of conductive features 812 facing away from the die 803. In some embodiments, the pillar 8 is a multi-layer structure, for example, the pillar 8 includes a conductive pillar 8a and an alloy (tin-silver (Sn-Ag)) layer 8b above the conductive pillar 8a. In some embodiments, the conductive pillar 8a is formed of a conductive material, for example, copper, and the alloy layer 8b serves as a soldering material of the pillar 8 for bonding. In some embodiments, the conductive pillar 8a and the alloy layer 8b can be formed by an electroplating operation. In some embodiments, a photoresist layer (not shown) can be formed above a predetermined area before performing an electroplating operation to form the pillar 8, and the photoresist layer (or dry film) can be removed thereafter. In some embodiments, the pillar 8 is adapted to be bonded to another die (not shown) or other suitable device to form a stacked connection. By using this type of FOWLP, the cost is much lower than using a TSV interposer.

[0084] In some embodiments, the outer end 8E of the conductive via 805 is leveled with the end of the through via 805' that is connected to the thermal management structure of the bump structure. The outer end 8E of the conductive via 805 is connected to the alloy layer 8b of the pillar 8 through the conductive pillar 8a. In some embodiments, the inner end 8I of the conductive via 805 is connected to the RDL 811 above the front side 803F of the die 803. The first module of the FOWLP of FIG. 6 is then fully completed and ready to be combined with other packages.

[0085] Next, an embodiment of a package structure with a heat dissipation layer will be described with reference to Figures 7A-7F. Specifically, Figures 7A, 7B, and 7C illustrate a method of forming a first die with a thermal management structure, Figure 7E illustrates a method of forming a second die with a thermal management structure, and Figure 7F illustrates a method of bonding the first die to the second die.

[0086] 7A and 7B are cross-sectional views of a semiconductor structure at intermediate stages of a manufacturing operation according to some embodiments of the present disclosure. Referring to FIG. 7A, following the first manufacturing process of the FOWLP, multiple layers of ABF (or BT) (with redistribution line (RDL) 911) of the fan-out interposer FO are formed above the front surface 803F of the first die 901, and several vias are formed on the input / output (I / O) pads (or contact pads) 502, and then the UBM layer 1U of the bump structure 510 disposed above the surface 901F of the die 901 contacts the input / output (I / O) pads (or contact pads) 502 on the front surface of the die 901. The fan-out region RO (e.g., made by layers of ABF (preferred) or BT) and encapsulant or molding compound 912 are formed to at least partially surround the first die 901 laterally, the first die 901 having a front surface 901F and a back surface 901B opposite the front surface 901F. In some embodiments, the molding compound 912 is made of epoxy molding compound (EMC), polyimide (PI), or other suitable material such as a plastic or polymer material. The molding compound 912 may encapsulate at least one side of the die 901. In some embodiments, the molding compound 912 may be formed by molding techniques (such as injection molding), 3D printing, additive manufacturing, etc. A plurality of conductive vias 913 are configured in the molding compound 912 and are laterally surrounded by the molding compound 912. In some embodiments, a plurality of ground or through vias 913' are formed in proximity to the first die 901 to reduce ground loop area and parasitic effects. In some embodiments, the through vias 913' are configured to ground the first die 901. The ground vias 913' may be configured to electrically connect the front side 901F of the first die 901 to a thermal management structure TM above the back side 901B of the first die 901. The conductive features 914 on the RDL 911 may be electrically connected to some of the conductive vias 913 and / or ground vias 913'.Thus, the RDL 911 of the fan-out interposer RO is fully formed, and the front surface 901F of the first die 901 having the UBM layer 1U in a bump structure on the pads 502 (not shown) is fanned out by the fan-out interposer FO.

[0087] A plurality of pillars 8 are formed above the plurality of conductive vias 913 and the plurality of conductive features 914 of the RDL 911, respectively. In some embodiments, the pillars 8 are multi-layered structures, for example, the pillars 8 include a conductive pillar 8a (copper) and an alloy layer 8b (tin-silver (Sn-Ag)) above the conductive pillars 8a. In some embodiments, the conductive pillars 8a and the alloy layer 8b can be formed by an electroless plating operation.

[0088] It should be noted that during the fabrication of the device, the following operations may be applied: A first photoresist layer 916 (or dry film) is patterned above the molding compound 912 to cover the pillars 8 above the molding compound 912. In some embodiments, a plurality of ground vias 913′ and the backside 901B of the first die 901 are exposed from the first photoresist layer 916. A second photoresist layer 916′ is formed above the RDL 911 to cover the pillars 8 above the RDL 911. In some embodiments, the sidewalls of each pillar 8 are covered by the first photoresist layer 916 or the second photoresist layer 916′. In some alternative embodiments, the second photoresist layer 916′ can be replaced by another sacrificial layer or an adhesive tape.

[0089] 7B and 7C, FIG. 7B is a cross-sectional view of a semiconductor structure at an intermediate stage of a manufacturing operation, and FIG. 7C is a top view of the semiconductor structure of FIG. 7B at an intermediate stage of a manufacturing operation, according to some embodiments of the present disclosure. An interface layer 6 is formed above the back surface 901B of the first die 901 and the ground via 913′. In some embodiments, the interface layer 6 includes an adhesion layer and a diffusion barrier layer, which may correspond to the adhesion layer 1a and the diffusion barrier layer 1b described with reference to FIG. 1 or FIG. 5A. In some embodiments, a copper-phosphorus alloy layer 7 (which may be made of Cu3P) is formed above each interface layer 6, thereby forming a thermal management structure TM that is thermally coupled to the back surface 901B of the die 901. In some embodiments, the interface layer 6 and the copper-phosphorus alloy layer 7 may be formed by an electroless plating operation, and the pillars 8 are protected by a first photoresist layer 916 (or a dry film) or a second photoresist layer 916′ (shown in FIG. 7A) during the electroless plating operation. After forming the interface layer 6 and the copper-phosphorus alloy layer 7, the first photoresist layer 916 and the second photoresist layer 916' are removed to form the first structure 900A.

[0090] Referring to FIG. 7D, FIG. 7D is a top view of a semiconductor structure at an intermediate stage of a manufacturing operation. The top view shown in FIG. 7D is similar to the top view shown in FIG. 7C, except that FIG. 7C shows that the ground vias 913' are arranged to surround two opposing sides of the first die 901 or the copper-phosphorus alloy layer 7 (or the interface layer 6) in a top view, and FIG. 7D shows that the ground vias 913' are arranged to surround four sides of the first die 901 or the copper-phosphorus alloy layer 7 (or the interface layer 6) in a top view. The ground vias 913' may be arranged between the through vias 913 and the first die 901. In some embodiments, the ground vias 913' are also configured to provide electromagnetic interference (EMI) shielding for the first die 901 from its four sides. By organizing the ground vias 913' on the four sides of the first die 901, the heat dissipation area of ​​the ground vias 913' can be significantly increased, so that the heat dissipation performance shown in FIG. 7D can be greatly improved. Sometimes, the combination of both the conductive ground circuit and the ground through vias 913' can increase the heat dissipation efficiency by 30-40% by applying only the thermal management structure TM. Therefore, these are the two key points of the present invention.

[0091] Referring to FIG. 7E, FIG. 7E is a cross-sectional view of a semiconductor structure at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. A second die 902 is provided, the second die 902 having a front surface 902F and a back surface 902B opposite the front surface 902F. In some embodiments, the second die 902 is a memory die including one or more memory devices. In some embodiments, the second die 902 may be a dynamic random access memory (DRAM) die or a flash memory die. A plurality of interface layers 6′ are formed above a portion of the second die 902 (where the area of ​​the interface layers 6′ may be defined by a sacrificial photoresist or dry film). A pillar 8 may be formed above each interface layer 6′. The composition of the interface layer 6′ may be similar to that of the interface layer 6 described above. In some embodiments, the pillar 8 is a multi-layer structure, for example, the pillar 8 includes a conductive pillar 8a and an alloy layer 8b on the conductive pillar 8a. The conductive pillars 8 a , the alloy layer 8 b , and the interface layer 6 ′ are sometimes referred to herein collectively as a bump structure 906 of the second die 902 , which is configured to be electrically connected to the first die 901 .

[0092] An interface layer 6 is formed over the backside 902B of the second die 902, and a copper-phosphorus alloy layer 7 (which may be made of Cu3P) is formed over the interface layer 6 to form a second structure 900B. The composition of the interface layer 6 is described with reference to FIG. 6. In some embodiments, the interface layer 6 may be formed by an electroless plating operation with a thickness of less than 1 μm, and the copper-phosphorus alloy layer 7 may be formed by an electroless plating and electroplating operation with a thickness of less than 200 μm, while the interface layer 6′ and the pillars 8 may be protected by a photoresist layer or tape (not shown) during the electroless plating operation. The interface layer 6 and the copper-phosphorus alloy layer 7 are collectively referred to herein as a thermal management structure TM that is thermally coupled to the backside 902B of the die 902.

[0093] Referring to FIG. 7F, FIG. 7F is a cross-sectional view of a package structure at an intermediate stage of a manufacturing operation according to some embodiments of the present disclosure. The first structure 900A shown in FIG. 7B is bonded to the second structure 900B shown in FIG. 7E, resulting in a vertical stacking of the first die 901 and the second die 902. In some embodiments, the first die 901 overlaps the second die 902 in the vertical direction. In some embodiments, the back surface 901B of the first die 901 faces the front surface 902F of the second die 902 after bonding the first structure 900A to the second structure 900B. The pillars 8 on the fan-out region RO above the back surface 901B of the first die 901 are connected to corresponding pillars 8 on the front surface 902F of the second die 902. In some embodiments, some of the pillars 8 above the front surface 902F of the second die 902 are connected to the copper-phosphorus alloy layer 7 above the front surface 901F of the first die 901. In some embodiments, the alloy layer 8b of the pillar 8 in the first structure 900A (shown in FIG. 7B ) merges with the alloy layer 8b of the pillar 8 in the second structure 900B (shown in FIG. 7E ), and performs reflow or thermocompression bonding to convert the alloy layer 8b into a plurality of solder balls 8b″ to strengthen the bonding between the first structure 900A and the second structure 900B. Therefore, the difference between the thickness T804 and the thickness T803 in FIG. 6 is not so important. Thus, the package structure 900C is formed. The two conductive pillars 8a, the two solder balls 8b″, and the interface layer 6′ between the first structure 900A and the second die 902 may be collectively referred to herein as the bump structure 910 of the second structure 900B, which can electrically connect the first die 901 to the second die 902. In some embodiments, the multiple bump structures 910 arranged between the first structure 900A and the second die 902 include a first (type) bump 915 and a second (type) bump 915′. The first (type) bump 915 is arranged to electrically couple the conductive vias 913 of the first structure 900A to the second die 902, and the second (type) bump 915′ is arranged proximal to the first die 901 and thermally couples the interface layer 6 and the copper-phosphorus alloy layer 7 to the second die 902.In some embodiments, due to the effect of gravity, the shape of the solder balls 8b" may resemble an oval, a rugby ball, or an American football shape. Each solder ball 8b" is isolated from each other to avoid electrical shorting issues. In some embodiments, pillars 8 formed of copper plugs encapsulated by insulating material are preferred over pillars formed of through-silicon vias because copper plugs are inexpensive.

[0094] An embodiment of the package structure of Figure 7E with a heat spreader will now be described with reference to Figure 8. Specifically, Figure 8 illustrates an approach to forming a first die with a thermal management structure and a heat spreader, forming a second die with a thermal management structure and a heat spreader, and bonding the first die to the second die.

[0095] Referring to FIG. 8, FIG. 8 is a cross-sectional view of a package structure according to some embodiments of the present disclosure. The package structure 1000C includes a first structure 1000A and a second structure 1000B stacked on the first structure 1000A. The first structure 1000A is similar to the first structure 900A described with reference to FIG. 7B, except that the thickness of the alloy layer 8b (or the overall thickness of the pillar 8) of the first structure 1000A is further increased (e.g., by repeating some of the solder alloy depositing operations described with reference to FIG. 7A several times). Furthermore, one or more heat spreaders 3X ​​are disposed on the copper-phosphorus alloy layer 7 above the back surface 901B of the first die 901. In some embodiments, the heat spreader 3X may include materials such as copper, foamed copper, aluminum, thermally conductive metal, ceramic, Al2O3, AlN, etc. In some embodiments, to improve the efficiency of heat dissipation, the surface area of ​​each heat spreader 3X can be designed to be larger than that of a cube-shaped heat spreader having a similar volume. In some embodiments, the heat spreader 3X may have one or more surfaces with a corrugated profile. For example, each heat spreader 3X may have multiple protrusions on the upper and / or lower sides, such as multiple first fin-type protrusions 3X' facing toward the first die 901 and multiple second fin-type protrusions 3X" facing away from the first die 901. In some embodiments, the heat spreader 3X may have multiple recesses or holes. Furthermore, a copper-phosphorus alloy material layer 2 (which may be made of Cu3P) is formed above the surface area of ​​the heat spreader 3X, for example, the copper-phosphorus alloy material layer 2 covers the multiple first fin-type protrusions 3X' and the multiple second fin-type protrusions 3X". The copper-phosphorus alloy material layer 2 may also be referred to as a coating layer coated on the heat spreader 3X. In some embodiments, since the heat spreader 3X comprises a plurality of first protrusions 3X′, the copper-phosphorus alloy material layer 2 can be formed in the gap between the heat spreader 3X and the copper-phosphorus alloy layer 7 by using an electroplating operation. In some embodiments, the wettability of the copper-phosphorus alloy 2 improves the accessibility of the formation of the copper-phosphorus alloy in the gap.The combination of the copper-phosphorus alloy material layer 2 and the copper-phosphorus alloy layer 7 improves the mechanical strength, adhesion, and reliability of the heat spreader 3X. Furthermore, the copper-phosphorus alloy material layer 2 and the copper-phosphorus alloy layer 7 have high thermal conductivity, providing a better means of heat dissipation and temperature management.

[0096] Furthermore, the copper-phosphorus alloy layer 7 can be formed by an electroless plating operation to obtain a denser structure, and the copper-phosphorus alloy material layer 2 can be formed by an electroplating operation to obtain a thicker layer, which improves efficiency. Furthermore, the use of an electroplating operation can help improve the coverage and accessibility of the copper-phosphorus alloy material layer 2 above the heat spreader 3X to gaps or holes.

[0097] The second structure 1000B is similar to the second structure 900B described with reference to FIG. 7E. However, it differs in that one or more heat spreaders 3Y are further disposed on the copper-phosphorus alloy layer 7 above the back surface 902B of the second die 902. In some embodiments, the heat spreaders 3Y may include materials such as copper, foamed copper, aluminum, thermally conductive metals, ceramics, Al2O3, AlN, etc. In some embodiments, the surface area of ​​each heat spreader 3Y may be designed to be larger than that of a cube-shaped heat spreader to improve the efficiency of heat dissipation. In some embodiments, the heat spreader 3Y may have one or more surfaces with a corrugated profile. For example, each heat spreader 3Y may have multiple protrusions on one or both sides, such as multiple first protrusions 3Y' facing towards the second die 902 and multiple second protrusions 3Y" facing away from the second die 902. In some embodiments, the heat spreader 3Y may have multiple recesses or holes. In some embodiments, the width W3Y of the heat spreader 3Y is greater than the width W3X of the heat spreader 3X. Furthermore, a copper-phosphorus alloy material layer 2 (which may be made of Cu3P) is formed above a surface region of the heat spreader 3Y, for example, the copper-phosphorus alloy material layer 2 covers the multiple first protrusions 3Y' and the multiple second protrusions 3Y". In some embodiments, since the heat spreader 3Y comprises multiple first protrusions 3Y', the copper-phosphorus alloy material layer 2 can be formed in the gap between the heat spreader 3Y and the copper-phosphorus alloy layer 7 by using an electroplating operation.

[0098] Additionally, the use of an electroplating operation can help improve the coverage and accessibility of gaps or holes in the copper-phosphorous alloy material layer 2 above the heat spreader 3Y. In some embodiments, the second die 902 is logic having some higher power dissipation and is connected to either one or more memory devices 901 having lower power dissipation. In some embodiments, the second die 902 may be a DRAM die or a flash memory die.

[0099] In some embodiments, the thickness of the alloy layer 8b of the second structure 1000B (or the overall thickness of the pillar 8) can be further increased by repeating the solder alloy deposition process described with respect to Figures 7B and 7E several times.

[0100] The first structure 1000A is bonded to the second structure 1000B, and the back surface 901B of the first die 901 faces the front surface 902F of the second die 902. The pillars 8 of the first structure 1000A (shown in FIG. 8) are connected to the corresponding pillars 8 of the second structure 1000B (shown in FIG. 8). A reflow operation can be performed, and the pillars 8 of the first structure 1000A merge with the pillars 8 of the second structure 1000B, thereby forming a plurality of bump structures 8P. The bump structures 8P after bonding the first structure 900A to the second structure 900B include the pillars 8 of the first structure 900A shown in FIG. 7B and the bump structures 910 shown in FIG. 7E. It should be noted that both bump structure 8P configurations should have a higher height, respectively, and there exists a gap between the heat spreader 3X and the die 902 for air convection. Thus, the first die 901 can be stacked vertically with the second die 902 without causing interference (i.e., the two elements undesirably physically contact at certain locations, but the surface tension generated by both sides of the solder can cover this alignment problem in the reflow operation). In some embodiments, the first die 901 overlaps the second die 902 vertically. Furthermore, an underfill layer 1001 is formed to cover the sidewalls of the bump structure 8P, thus forming a package structure 1000C. In some embodiments, the underfill layer 1001 encapsulates the bump structure 8P. The underfill layer 1001 may be between the molding compound 912 of the first structure 1000A and the second die 902 of the second structure 1000B. In some embodiments, the underfill layer 1001 may be a no-flow underfill, and the underfill layer 1001 may not substantially have direct contact with the first die 901. This improves the heat dissipation capability of the package structure 1000C since the underfill layer 1001 can be prevented from significantly impeding heat dissipation.

[0101] Next, an embodiment of a package structure with a thermal management structure and a heat spreader will be described with reference to FIG. 9A and FIG. 9B. Such a configuration allows to accommodate several push-pull drivers. For example, the first die 901 is a MIMO solution of driver amplifier set #1 for 5G wireless system, and its copper pillars are attached to an interposer substrate (not shown). The second die 902 is another set of driver amplifier #2. Therefore, thermal management should be added. To trade off space and reduce interference with both electromagnetic interference (EMI) and heat convection problems caused by large driver currents, both dies can be placed crosswise (e.g., vertically) from a top view perspective and partially stacked instead of both being set on a plane with the same level, as shown in FIG. 9A and FIG. 9B. In some alternative embodiments, a heat spreader 3X (shown in FIG. 9A) can be placed between the second die 902 and the copper-phosphorus alloy layer 7 above the first die 901. 9B, the underside of the heat spreader 3X is substantially level with the top surface of the copper-phosphorus alloy layer 7 below the heat spreader 3X, and the top sides of the heat spreader 3X at both ends may extend above the second die 902, but the middle region of 3X cannot contact the second die 902 due to air convection. In some embodiments, at least a portion of the heat spreader 3X is substantially level with the second die 902.

[0102] 9A and 9B, FIG. 9A is a cross-sectional view of a package structure according to some embodiments of the present disclosure, and FIG. 9B is a perspective view of the package structure shown in FIG. 9A. The cross-sectional view of FIG. 9A is taken along the cutting line BB shown in FIG. 9B. The package structure 1100 shown in FIG. 9A and 9B is similar to the package structure 1000C shown in FIG. 8, except that instead of increasing the height of the bump structure 8P, the configuration of the heat spreader 3X and the copper-phosphorus alloy material layer 2 formed above the heat spreader 3X is changed. In some embodiments, referring to FIG. 9B, the side of the heat spreader 3X is substantially flush with the side of the first die 901.

[0103] Referring to FIG. 9B, an additional thermal management structure TM formed between the first die 901 and the second die 902 is thermally coupled to the first die 901. A space (5-10 μm) can be reserved between the first die 901 and the second die 902. Such space may be filled by an underfill layer 1001. In particular, a plurality of heat spreaders 3X ​​are disposed above the copper-phosphorus alloy layer 7 of the first die 901 (the copper-phosphorus alloy material layer 2 covering the heat spreaders 3Y is only shown in FIG. 9A but is omitted in FIG. 9B for clarity). A part or all of the heat spreaders 3X ​​may not overlap the first die 901 or the second die 902 along the vertical direction. Thus, the heat dissipation paths of the dies do not interfere with each other. In some embodiments, there is no heat spreader 3X disposed between the second die 902 and the copper-phosphorus alloy layer 7 above the first die 901. In some alternative embodiments, a smaller heat spreader 3X can be disposed between the second die 902 and the copper-phosphorus alloy layer 7 above the first die 901. In some embodiments, referring to FIG. 9B, the underside of the heat spreader 3X can be substantially flush with the top surface of the copper-phosphorus alloy layer 7 below the heat spreader 3X, and the top side of the heat spreader 3X can extend above the second die 902. In some embodiments, at least a portion of the heat spreader 3X is substantially flush with the second die 902. In some embodiments, the first die 901 has a die width W901 from a cross-sectional or top-view perspective. In some embodiments, the second die 902 has a die width W902 from a cross-sectional or top-view perspective. The die width W902 can be greater than the die width W901. In some embodiments, the first die 901 has a first die length measured from a direction perpendicular to the section line BB, and the second die 902 has a second die length measured from a direction perpendicular to the section line BB. As shown in FIG. 9B, the first die length is greater than the second die length, but in other embodiments, the first die length may be substantially equal to the second die length.

[0104] Next, an embodiment of a package structure with a thermal management structure and a heat spreader will be described with reference to Fig. 10. Specifically, Fig. 10 shows a package structure for a tablet computer having a first module stacked with several (e.g., two) DRAM dies and a second die (logic die) connected horizontally.

[0105] Referring to FIG. 10, FIG. 10 is a cross-sectional view of a package structure according to some embodiments of the present disclosure. The package structure 1200C includes a first structure 1200A and a second structure 1200B disposed along the first structure 1200A. The first structure 1200A shown in FIG. 10 is similar to the first structure 1000A described with reference to FIG. 8, except that the first structure 1200A has a wider redistribution layer, herein denoted as RDL 911X, and the RDL 911X has a first region RA and a second region RB adjacent to the first region RA. The first die 901 is disposed above the first region RA. Furthermore, the pillar is disposed above the molding compound 912 in the fan-out region RO on which the second DRAM is stacked. The same method as described above can be used to stack the second DRAM (with thermal management structure and heat spreader) on the first DRAM. In some embodiments, the copper-phosphorus alloy material layer 2 on the second DRAM further extends above the molding compound 912 and covers the conductive vias 913. However, the ground conductive vias 913' may not contact the copper-phosphorus alloy layer 7 on the backside of the first die 901 for thermal conduction. Then, an interface layer 6 and a copper-phosphorus alloy layer 7 are electrolessly plated on the backside 901B of the second die. In addition to covering the heat spreader on the backside of the second die, a layer of copper-phosphorus alloy material 2 is also electroplated over the fan-out region RO to cover the ground conductive vias 913' to increase the heat dissipation area. Instead of stacking a set of DRAMs using TSV interposers, the FOWLP technique can achieve not only cost reduction but also yield improvement. In some embodiments, a gap 909 exists between the two layers of copper-phosphorus alloy 2 for air convection.

[0106] Further, the RDL 911X of the second region RB has a front surface 911F and a back surface 911B opposite the front surface 911F. A plurality of conductive features 914 are disposed on the front surface 911F and the back surface 911B, and a plurality of pillars 8 are disposed on some of the conductive features 914 disposed on the front surface 911F and the back surface 911B. In some embodiments, the pillars 8 are multi-layered structures, for example, referring to FIG. 7A or FIG. 7B, the pillars 8 include a conductive pillar 8a and an alloy layer 8b above the conductive pillars 8a.

[0107] The second structure 1200B shown in FIG. 10 is similar to the second structure 1000B shown in FIG. 8. In some embodiments, as shown in the second structure 1200B shown in FIG. 10, the copper-phosphorus alloy material layer 2 may be in direct contact with the peripheral area of ​​the second die 902. It is noted that if it is necessary to relieve the stress on the second die 902, the heat spreader 3Y may be made of foamed copper to reduce the overall weight of the tablet computer. Furthermore, the power dissipation of the second die (logic die) is somewhat larger, so its thermal management should be given special consideration.

[0108] The second structure 1200B is bonded above the second region RB above the front surface 911F of the RDL 911X to form the package structure 1200C. In some embodiments, the power dissipation of the second die 902 (logic die) is greater than that of the first die 901 (DRAM). A reflow operation can be performed to fuse and connect the pillar 8 of the second structure 1200B with the pillar 8 above the front surface 911F of the RDL 911X, and the extended joint can release the mechanical stress generated by the logic driver. By the way, several logic dies can also be stacked on the first logic die to create a multi-core computer by using the FOWLP technology.

[0109] Next, an embodiment of a package structure with a thermal management structure for a dual-path RF transmitter will be described with reference to Fig. 11. Specifically, Fig. 11 shows an approach to vertically connect a first die (e.g., mixer) and a second die (e.g., power amplifier) ​​to form a thermal management structure. Therefore, a shielding (and TM) plate should be applied to solve the EMI and heat dissipation problems caused by the power amplifier.

[0110] 11, which is a cross-sectional view of a package structure according to some embodiments of the present disclosure. The package structure 1300C includes a first structure 1300A and a second structure 1300B stacked above the first structure 1300A. The first structure 1300A described with reference to FIG. 11 is similar to the first structure 900A described with reference to FIGS. 7B, 7C, and 7F, except that the configuration of the conductive vias 913 and the ground vias 913' is different. In some embodiments, as shown in FIG. 11, the conductive vias 913 may be disposed proximal to the first die 901, and the ground vias 913' may be organized in a peripheral area, and the conductive vias 913 may be between the ground vias 913' and the first die 901.

[0111] The second structure 1300B (such as a dual path RF transmitter) described with reference to Fig. 11 is similar to the second structure 900B described with reference to Fig. 7E and Fig. 7F, except that the interface layer 6 and the copper-phosphorus alloy layer 7 of the second structure 1300B described with reference to Fig. 11 further extend above the fan-out region RO of the first structure 1300A and are applied as a shielding plate for EMI / EMC consideration. The first structure 1300A is bonded to the second structure 1300B, and the back surface 901B of the first die 901 faces the front surface 902F of the second die 902.

[0112] The pillars 8 of the first structure 1300A are connected to corresponding pillars 8 of the second structure 1300B. A reflow operation can be performed, and the pillars 8 of the first structure 1300A may merge with the pillars 8 of the second structure 1300B, thereby forming a plurality of bump structures 8P to reduce mechanical stress generated by the second die of the dual path RF transmitter.

[0113] In some embodiments, the first die 901 vertically overlaps the second die 902. Further, an underfill layer 1001 is formed to cover the sidewalls of the bump structure 8P. At least a portion of a front surface 902F of the second die 902 and at least a portion of a back surface 901B of the first die 901 are exposed through the underfill layer 1001. In some embodiments, the underfill layer 1001 may be a no-flow underfill.

[0114] The interface layer 6 is formed over the back surface 902B of the second die 902, over the front surface 902F of the second die 902 exposed through the underfill layer 1001, and over the back surface 901B of the first die 901 exposed from the underfill layer 1001. The interface layer 6 over the back surface 902B of the second die 902 may further extend over the side surface 902S of the second die 902, over the sidewall of the underfill layer 1001, over the first surface 912S of the molding compound 912 in the fan-out region RO (facing away from the RDL 911), and over the ground vias 913'. In some embodiments, the first surface 912S of the molding compound 912 is flush with the back surface 901B of the first die 901. A copper-phosphorus alloy layer 7 (which may be made of Cu3P) is formed over each interface layer 6 to form the package structure 1300C. The interface layer 6 and the copper-phosphorus alloy layer 7 formed thereon are collectively referred to as a thermal management structure TM or shielding plate for EMI / EMC considerations. In some embodiments, a gap 909 exists between both layers of copper-phosphorus alloy 2 for air convection.

[0115] In some embodiments, the interface layer 6 may be formed by an electroless plating operation, the copper-phosphorus alloy layer 7 may be formed by an electroplating operation, and each of the interface layers 6 (the interface layer over the back surface 902B of the second die 902, the interface layer on the front surface 902F of the second die 902, the interface layer over the back surface 901B of the first die 901) may be formed in a single operation, and the copper-phosphorus alloy layer 7 over each of the aforementioned interface layers 6 may also be formed in a single operation. Optionally, a sacrificial layer may be formed to protect certain portions of the first structure 1300A or the second structure 1300B during the plating operations to form the interface layer 6 and the copper-phosphorus alloy layer 7.

[0116] Furthermore, the ground vias 913′ are connected to the interface layer 6 and the copper-phosphorus alloy layer 7 that extends from the back surface 902B of the second die 902 to an area above the first surface 912S of the molding compound 912. Such a configuration can address not only issues related to electromagnetic compatibility (EMC), but also issues related to electromagnetic interference (EMI) of the package structure 1300C.

[0117] Next, an embodiment of a package structure and a shielding plate that takes EMI / EMC into consideration and are provided simultaneously with a thermal management structure will be described with reference to FIG.

[0118] 12, which is a cross-sectional view of a package structure according to some embodiments of the present disclosure. The package structure 1400 shown in FIG. 12 is similar to the package structure 1300C shown in FIG. 11, except that one or more heat spreaders 3Y are further disposed on the copper-phosphorus alloy layer 7 above the back surface 902B of the second die 902, and a copper-phosphorus alloy material layer 2 (which may be made of Cu3P) is formed above the surface area of ​​the heat spreader 3Y, for example, the copper-phosphorus alloy material layer 2 covers the first protrusions 3Y′ and the second protrusions 3Y″. Details of the heat spreader 3Y can be found by returning to the description of FIG. 8. In some embodiments, the heat spreader 3Y is made of copper, foamed copper, aluminum, a thermally conductive metal, ceramic, Al2O3 , AlN, and other materials. Furthermore, the copper-phosphorus alloy layer 7 can be formed by an electroless plating operation to obtain a denser structure, and the copper-phosphorus alloy material layer 2 can be formed by an electroplating operation to obtain a thicker layer, which improves efficiency. In some embodiments, the copper-phosphorus alloy material layer 2 conforms to the profile of the top and sidewalls of the copper-phosphorus alloy layer 7 above the back surface 902B of the second die 902. In some embodiments, the copper-phosphorus alloy material layer 2 can be formed above the other copper-phosphorus alloy layer 7. Note that due to air convection, a gap 909 exists between both layers of copper-phosphorus alloy 2 above 901B and 902F.

[0119] Next, an embodiment of a package structure containing multiple dies will be described with reference to FIG.

[0120] 13, which is a cross-sectional view of a package structure according to some embodiments of the present disclosure. The first structure 1500A includes a primary die 1501 and a secondary die 1502 attached to the primary die 1501. In some embodiments, the primary die 1501 may be a processor die, such as a central processing unit (CPU) die comprising one or more processing units. The secondary die 1502 may be a logic die comprising one or more logic devices. The tertiary die 1503 comprises one or more memory devices. The first structure 1500A further includes two types of fan-out interposers FO as follows:

[0121] The first fan-out interposer FO is made of a layer of ceramic thin film, and the second FOWLP method of chip-last (also called RDL-first) should be applied, i.e., the chip is not incorporated into the packaging process until the RDL (including the conductive vias 1513 and ground vias 1513' formed in the fan-out area (FO)) and the bump structure 8P of copper pillars on both sides of the RDL are pre-formed. The primary die 1501 has a first (front) surface 1501F and a second (back) surface 1501S opposite to the first surface 1501F. Then, the die 1501 and the ceramic RDL are both bonded by depositing silver paste on the die pad and curing the silver paste. The thermal performance of such ceramic RDL is suitable for high-performance power devices. Other processes and considerations are similar to the first method described above. It should be noted that the method of packaging the die can be changed according to the overall performance. The interposer applied in FIG. 13 is merely exemplary. Conductive vias 1513 may be between ground vias 1513 ′ and the primary die 1501 . Further, a plurality of conductive pillars 8a and solder balls 8b″ (which may be made of a tin-silver alloy) may be disposed above each conductive feature 1514 (not shown) exposed through the RDL 1511. The die 1501 is then flip-chip bonded onto the ceramic RDL. The thermal performance of such a ceramic RDL is suitable for high-performance power devices. Other processes and considerations are similar to those of the first method described above. It should be noted that the method of packaging the die can be changed depending on the overall electrical performance, thermal management, and cost performance. The interposer applied in FIG. 13 is merely exemplary. Further, the secondary die 1502 is flip-chip bonded to the primary die 1501 via a bump structure 8P, with a first (front) surface 1502F of the secondary die 1502 facing towards the primary die 1501 and a second surface 1502S of the secondary die 1502 facing away from the primary die 1501.Each bump structure 8P includes an interface layer 6' (whose composition is similar to the aforementioned interface layer 6) above the second surface 1502S of the secondary die 1502, an interface layer 6' disposed above each of the conductive vias 1513, a conductive pillar 8a above the interface layer 6', and a solder ball 8b" connecting between the aforementioned two conductive pillars 8a. Further, an underfill layer 1001 is formed to cover the sidewall of the bump structure 8P. In some embodiments, the underfill layer 1001 may be a non-flowing underfill, and the underfill layer 1001 may not substantially have direct contact with the primary die 1501. Furthermore, a portion of the secondary die 1502 may be exposed through the underfill layer 1001. It is noted that due to air convection, a gap 1509 exists between both copper-phosphorus alloy layers 7 above 1501S and 1502F.

[0122] The second structure 1500B includes a tertiary die 1503, which comprises one or more memory devices. In some embodiments, the tertiary die 1503 may be a DRAM die or a flash memory die. The second structure 1500B further includes a fan-out interposer FO (made by a layer of ABF (preferred) or bismaleimide-triazine (BT)) having an encapsulant or molding compound 1522 laterally at least partially surrounding the tertiary die 1503, the tertiary die 1503 having a first (front) surface 1503F and a second (back) surface 1503S opposite the front surface 1503F. The molding compound 1522 may encapsulate at least one side of the tertiary die 1503. In some embodiments, the molding compound 1522 is made of epoxy molding compound (EMC), polyimide (PI), or other suitable material such as a plastic or polymer material. In some embodiments, molding compound 1522 may be formed by molding techniques (such as injection molding), 3D printing, additive manufacturing, etc. A plurality of conductive vias 1523 and a plurality of ground vias (or through vias) 1523' are organized within and laterally surrounded by molding compound 1522. In some embodiments, ground vias 1523' are formed in a peripheral area of ​​molding compound 1522, and conductive vias 1523 may be between ground vias 1523' and tertiary die 1503.

[0123] The second structure 1500B further includes a first RDL 1521a and a second RDL 1521b arranged on two opposite sides of the molding compound 1522, the first RDL 1521a being adjacent to the second surface 1503S of the tertiary die 1503. In some embodiments, the second surface 1503S of the tertiary die 1503 is exposed through the first RDL 1521a. Furthermore, a plurality of conductive pillars 8a and alloy layers 8b may be disposed on the first RDL 1521a and the second RDL 1521b.

[0124] The first structure 1500a is bonded to the second structure 1500b via the bump structure 8P'. An underfill layer 1001 is formed covering the sidewall of the bump structure 8P', and the underfill layer 1001 is between the second RDL 1521b of the second structure 1500B and the RDL 1511 of the first structure 1500A. A plurality of thermal management structures TM, including an interface layer 6 and a copper-phosphorus alloy layer 7 (which may be made of Cu3P) above the interface layer 6, are formed above the exposed surfaces of the primary, secondary or tertiary die 1501, 1502, 1503 to obtain the package structure 1500C. For example, the thermal management structures TM are formed over and thermally coupled to the first side 1503F of the tertiary die 1503, the second side 1501S of the primary die 1501, the first side 1502F of the secondary die 1502, and the second side 1502S of the secondary die 1502, respectively, thereby helping to improve heat dissipation of each of the aforementioned dies 1501, 1502, 1503. In some embodiments, the thermal management structures TM are further thermally coupled to the first side 1502F of the secondary die 1502, the second side 1502S of the secondary die 1502, a side of the underfill layer 1001 that encapsulates the bump structure 8P, and a side of the underfill layer 1001 that encapsulates the bump structure 8P'.

[0125] In some embodiments, the thermal management structures TM on the second side 1502S of the secondary die 1502 further extend above the sidewalls of the underfill layer 1001 of the first structure 1500a, the sidewalls of the underfill layer 1001 of the second structure 1500b, the sidewalls of the RDL 1511, and the sidewalls of the molding compound 1512. The thermal management structures TM above the second side 1501S of the primary die 1501 can further extend above the peripheral area of ​​the second RDL 1521b and the molding compound 1512, thereby electrically connecting to the ground vias 1513' of the first structure 1500A and the ground vias 1523' of the second structure 1500B. The ground vias 1523' and the ground vias 1513' may have the same electrical potential, thereby providing a reference voltage level. Such a configuration of the thermal management structures TM can both improve heat dissipation capability and provide a reference voltage level. Furthermore, by using an electroless plating operation, the interface layer 6 of the thermal management structure TM disposed on each of the die can be formed in a single operation, and the copper-phosphorous alloy layer 7 of the thermal management structure TM disposed on each of the die can also be formed in a single operation. An embodiment of a package structure including multiple die will now be described with reference to Figure 14, which is similar to that described with reference to Figure 13, except that the thermal management structure is formed before connecting the first structure to the second structure.

[0126] Referring to FIG. 14, FIG. 14 is a cross-sectional view of a package structure according to some embodiments of the present disclosure. The first structure 1600A shown in FIG. 14 is similar to the first structure 1500A shown in FIG. 13, except that the thermal management structure TM is formed above and thermally coupled to the second side 1501S of the primary die 1501, the first side 1502F of the secondary die 1502, and the second side 1502S of the secondary die 1502. The aforementioned configuration helps to improve the heat dissipation of each of the aforementioned dies 1501, 1502, 1503. Furthermore, the thermal management structure TM on the second side 1502S of the secondary die 1502 further extends above the sidewalls of the underfill layer 1001 of the first structure 1500A and above the peripheral area of ​​the molding compound 1512, thereby covering the ground vias 1513′.

[0127] The second structure 1600B is bonded to the first structure 1600A to obtain the package structure 1600C. The package structure 1600C shown in Fig. 14 is similar to the package structure 1500C shown in Fig. 13, except that in some cases, the thermal management structure TM on the second side 1502S of the secondary die 1502 may not extend further above the peripheral area of ​​the second RDL 1521b. Note that a gap 1509 exists between both copper-phosphorous alloy layers 7 above 1501S and 1502F for air convection.

[0128] 15 is a cross-sectional view of a package structure 1700 according to some embodiments of the present disclosure. The package structure 1700 includes a first die 1710, a second die 1720, a third die 1730, and a substrate 1740. In some embodiments, the first die 1710 is a package die and includes a first semiconductor device 1712 and a plurality of second semiconductor devices 1714 arranged in a stack. In some embodiments, the first semiconductor device 1712 is a logic die and the second semiconductor device 1714 is a memory die. The first die 1710 may further include a first RDL 1716 arranged between the first semiconductor device 1712 and the bottom second semiconductor device 1714. Furthermore, the first die 1710 includes one or more second RDLs 1718 between two adjacent second semiconductor devices 1714. The second semiconductor devices 1714 are arranged in an alternating fashion with the second RDLs 1718. The aforementioned components of the first die 1710, for example, the first semiconductor device 1712, the first RDL 1716, a first one of the second semiconductor devices 1714, a first one of the second RDL 1718, a second one of the second semiconductor devices 1714, a second one of the second RDL 1718, and up to the Nth one of the second semiconductor devices 1714 (N is the number of second semiconductor devices 1714) are stacked and bonded to construct the first die 1710.

[0129] In some embodiments, the second die 1720 is a wireless transceiver die and includes at least one of a transceiver, a memory chip, an antenna, and an RF device, In some embodiments, the third die 1730 is a sensor die and includes at least one of a sensor device, a memory chip, and an analog circuit.

[0130] The substrate 1740 may include a first layer 1742 and a second layer 1744 above the first layer 1740. In some embodiments, the first layer 1742 serves as a ground layer for the package structure 1700 and is formed of ceramic, silicon, glass, or any other suitable material. In some embodiments, the second layer 1744 is an RDL or interconnect layer configured to electrically interconnect the first die 1710, the second die 1720, and the third die 1730.

[0131] In some embodiments, the package structure 1700 further includes conductive bumps 1746 arranged on an upper side of the second layer 1742 of the substrate 1740. The package structure 1700 may further include conductive bumps 1748 arranged on an underside of each of the first die 1710, the second die 1720, and the third die 1730. Each of the conductive bumps 1746 may be aligned with a corresponding conductive bump 1748. The conductive bumps 1746 and 1748 may be microbumps, C4 bumps, etc. The package structure 1700 further includes conductive pillars 1752 electrically connecting the bumps 1746 and the corresponding bumps 1748 to electrically couple the substrate 1740 to the first die 1710, the second die 1720, and the third die 1730. In some embodiments, the conductive pillars 1752 are omitted and the conductive bumps 1746 are directly bonded to the corresponding conductive bumps 1748.

[0132] In some embodiments, the package structure 1700 further includes a UBM layer 1760 over the top and sidewalls of the first die 1710, the second die 1720, and the third die 1730. In some embodiments, the material, configuration, and method of formation of the UBM layer 1760 are similar to those of the UBM layer 1U described with reference to Figures 5A-5D. In some other embodiments, the UBM layer 1760 is formed of a first sub-layer and a second sub-layer above the first sub-layer, where the first sub-layer is similar to the adhesion layer 1a described with reference to Figures 1, 2, and 5A-5D, and the second sub-layer is similar to the diffusion barrier layer 1b described with reference to Figures 1, 2, and 5A-5D. In some embodiments, the package structure 1700 further includes a copper-phosphorus alloy layer 1770 formed over the UBM layer 1760. A copper-phosphorus alloy layer 1770 may be deposited over the top surface and sidewalls of the first die 1710, the second die 1720, and the third die 1730. The material, function, configuration, and formation method of the copper-phosphorus alloy layer 1770 are similar to those of the copper-phosphorus alloy layer 1c described with reference to Figures 1, 2, and 5A-5D. In some embodiments, antennas, RF devices, or other components of the second die 1720 or the third die 1730 for transmitting or receiving electromagnetic waves are exposed through the UBM layer 1760, the copper-phosphorus alloy layer 1770, and the thermal management structure 1750 to ensure proper function of the antennas, RF devices, and the like.

[0133] In some embodiments, each of the first die 1710, the second die 1720, and the third die 1730 includes a thermal management structure 1750, which includes a heat spreader 3X above the top (back) surface of each of the first die 1710, the second die 1720, and the third die 1730. The heat spreader 3X may be formed above the top surface of the copper-phosphorus alloy layer 1770. In some embodiments, the thermal management structure 1750 further includes a copper-phosphorus alloy material layer 2 deposited on the surface and gaps of each of the heat spreaders 3X. The heat spreader 3X and the copper-phosphorus alloy material layer 2 may be similar to the heat spreader 3X and the copper-phosphorus alloy material layer 2 described with reference to Figures 3, 4, 8, 9A, 9B, and 10.

[0134] In some embodiments, the first die 1710 further includes a plurality of through package vias 1810 and a second through package via 1820 extending through the package of the first die 1710 (FIG. 15 illustrates only two exemplary through package vias 1810 and 1820). The through package vias 1810 may be used as a signal path configured to electrically connect the first semiconductor device 1712 and the second semiconductor device 1714 to the second layer 1744 of the substrate 1740. The first semiconductor device 1712, the second semiconductor device 1714, the first RDL 1716, and the second RDL 1718 may include conductive lines electrically coupled to the through package vias 1810 to transmit signals. The through package vias 1820 may be used as a ground path configured to electrically connect the first semiconductor device 1712 and the second semiconductor device 1714 to the first layer 1742 of the substrate 1740 for grounding. The first semiconductor device 1712, the second semiconductor device 1714, the first RDL 1716, and the second RDL 1718 may include conductive lines for connecting to the through package via 1820 for grounding.

[0135] In some embodiments, each of the through package vias 1810 and 1820 includes a core layer 1812, a wetting layer 1814, and a diffusion barrier layer 1816. In some embodiments, the core layer 1812 is formed of a conductive material, such as copper, tungsten, aluminum, etc., and is configured to conduct an electrical or ground path of the through package vias 1810, 1820. In some embodiments, the wetting layer 1814 is formed of a copper-phosphorus alloy layer and laterally surrounds the core layer 1812. The copper-phosphorus alloy layer 1814 can improve the wettability of the material of the core layer 1812. In some embodiments, the diffusion barrier layer 1816 is formed of a transition metal or its nitride, for example, titanium and titanium nitride, and laterally surrounds the wetting layer 1814 and the core layer 1812. In some embodiments, the through package vias 1810, 1820 are defined by sidewalls 1810S or 1820S formed on the first die 1710. In some embodiments, the liner layer 1818 lines the sidewalls 1810S or 1820S between the diffusion barrier layer 1816 and the first die 1710 or through package via 1810, 1820, and laterally surrounds the diffusion barrier layer 1816, the copper-phosphorus alloy layer 1814, and the core layer 1812. The liner layer 1818 may be formed of a dielectric material, such as an oxide or nitride, and is configured to electrically insulate the diffusion barrier layer 1816 from the semiconductor substrate of the first die 1710. Although the depicted example shows only a copper-phosphorus alloy layer functioning as a wetting layer 1814 for the through package via 1810 or through package via 1820, the wetting layer 1814 formed of a copper-phosphorus alloy layer can also be applied to other types of through vias, such as through molded vias, through silicon vias, through substrate vias, etc.

[0136] In some embodiments, the top of the through package via 1820 extends through the top second semiconductor device 1714 and is coupled to the bottom surface of the UBM layer 1760. In some embodiments, the top of the through package via 1810 extends to the bottom surface of the top second semiconductor device 1714 and is separated from the UBM layer 1760 by the top second semiconductor device 1714 to avoid abnormal shorting of the signal path.

[0137] In some embodiments, an exemplary method of forming the package structure 1700 is provided below. The substrate 1740 comprises multiple insulating layers and conductive trace layers to form one or more conductive paths, in which a signal path is provided on the second layer 1744 while a ground path is provided on the first layer 1742. A conductive bump 1746 is then formed on the top side of the substrate 1740. In some embodiments, a conductive through via (e.g., a lower portion of the through package via 1820) is formed through the second layer 1744 of the substrate 1740 and electrically connected to the first layer 1742.

[0138] A first die 1710 is provided. For example, a first semiconductor device 1712 and a second semiconductor device 1714 are formed on one or more wafer substrates and cut into individual dies. Additionally, a first RDL 1716 and a second RDL 1718 are also formed on one or more wafer substrates and cut into individual dies. In some embodiments, a portion of the through package vias 1810 and 1820 are formed in each of the first semiconductor device 1712, the second semiconductor device 1714, the first RDL 1716, and the second RDL 1718. Each of the aforementioned components of the first die 1710 may be aligned and bonded to one another through a suitable bonding process, such as thermo-compression bonding (TCB), hybrid bonding, fusion bonding, etc. Different portions of the through package vias 1810, 1820 in the first semiconductor device 1712, the second semiconductor device 1714, the first RDL 1716, and the second RDL 1718 are electrically coupled to form vertically extending through vias 1810, 1820.

[0139] A second die 1720 and a third die 1730 may be provided. Further, conductive bumps 1748 may be formed on the undersides of the first die 1710, the second die 1720 and the third die 1730, and are bonded to the substrate 1740 through bonding of the conductive bumps 1746 and 1748. A UBM layer 1760 and a copper-phosphorus alloy layer 1770 are successively deposited on the top surfaces and sidewalls of the first die 1710, the second die 1720 and the third die 1730. A heat spreader 3X is arranged above the first die 1710, the second die 1720 and the third die 1730 and on the copper-phosphorus alloy layer 1770. A copper-phosphorus alloy material layer 2 is deposited on the surface and gaps of the heat spreader 3X to form a thermal management structure 1750. In this manner, the package structure 1700 is completed.

[0140] In the present disclosure, the means for thermal management (such as improving heat dissipation) are provided for various types of package structures or semiconductor structures, as described with reference to Figs. 1-14, respectively. Due to the compatibility of the operations for improving heat dissipation, it can be incorporated into various types of operations for forming package structures or semiconductor structures. The means for thermal management in the present disclosure include, but are not limited to, a thermal management structure TM including a thermal management structure 1, a heat spreader (such as heat spreader 3, 3X, or 3Y), a copper-phosphorus alloy material layer 2, an interface layer 6, and a copper-phosphorus alloy layer 7 (which may be made of Cu3P), a thermal management auxiliary unit 4, or a combination thereof. As described with reference to Figs. 1 and 2, the thermal management structure 1 (including an adhesive layer 1a, a diffusion barrier layer 1b above the adhesive layer 1a, and a copper-phosphorus alloy layer 1c (which may include Cu3P) above the diffusion barrier layer 1b) is utilized for thermal management, which can improve heat dissipation. The adhesive layer 1a can enhance adhesion between the thermal management structure 1 and a substrate. The diffusion barrier layer 1b may be utilized to mitigate diffusion and may also reduce internal stress. The copper-phosphorus alloy layer 1c exhibits greater thermal conductivity and has a denser structure than conventional heat sinks and conventional thermal interface materials, and may improve corrosion resistance, wear resistance, wettability, strength, toughness, conformability, processability, and the like. In addition, the embodiment of FIG. 2 further includes forming a plurality of protrusions 1d to further improve the ability to dissipate heat. The thermal management structure 1 may be further incorporated into the package structure as described with reference to FIG. 5A, and in particular, a common material between the thermal management structure 1 formed on the back surface of the substrate and the UBM layer 1U of the pillar may be formed in a single operation.

[0141] 3 and 4, a thermal management auxiliary unit 4 is provided, which includes a thermal management structure 1, a copper-phosphorus alloy material layer, and one or more heat spreaders 3. The heat spreader 3 configuration provides a large surface area for dissipating heat, and the incorporation of a copper-phosphorus alloy material layer 2 formed on the heat spreader 3 helps improve thermal management and adhesion of the heat spreader 3.

[0142] The thermal management structure TM including the interface layer 6 and the copper-phosphorus alloy layer 7 can be used in package structures to improve heat dissipation (or thermal management), such as those described with reference to Figure 6 (thermal management structure TM formed above one or more die disposed in a molding compound) and Figures 7A-7F (multiple dies stacked vertically).

[0143] Multiple heat spreaders (such as heat spreaders 3, 3X, or 3Y) and copper-phosphorus alloy material layers 2 formed thereon, and thermal management structures TM under the heat spreaders can be further incorporated in the process to form a package structure to improve heat dissipation (or thermal management). Further examples can be seen in Figure 8 (increasing the overall pillar thickness to avoid interference), Figure 9A, Figure 9B, and Figure 10 (connecting the first die and the second die horizontally).

[0144] An efficient method of incorporating thermal management structures TM into a package structure including multiple vertically stacked dies is described with reference to Figs. 11, 13, and 14. For example, Fig. 11 shows a two-die configuration and further uses thermal management structures TM covering ground vias for a specific application. Figs. 13 and 14 show a package structure with three or more dies stacked, and the time at which the thermal management structures TM are formed may be adjusted based on the application. Furthermore, one of the thermal management structures TM may further connect ground vias away from the die, thereby providing a reference voltage level. Fig. 12 further shows the incorporation of one or more heat spreaders (such as heat spreader 3, 3X, or 3Y) and a copper-phosphorus alloy material layer 2 formed on the heat spreader to further improve heat dissipation or thermal management capabilities.

[0145] Although not separately illustrated, in some embodiments, the thermal management structures TM discussed in this disclosure are shown, for example, in Figures 7B, 7E, 7F, 11, 13, and 14 and may be organized to include protrusions 1d in a similar configuration to the protrusions 1d shown in Figure 2. The protrusions 1d may include a copper-phosphorus alloy material similar to the copper-phosphorus alloy layer 7. In some embodiments, the corrugated profile of the thermal management structures TM includes a planar portion 7 and a corrugated portion 1d above the planar portion 7.

[0146] Furthermore, the techniques described above can be applied to various technology nodes and various types of technology generations. For example, the techniques described above can be further applied to 2.5D and 3D package structures.

[0147] Some embodiments of the present disclosure provide a package structure that includes a first die having a front surface and a back surface opposite the front surface, and a thermal management structure above the back surface, the thermal management structure including a first copper-phosphorus alloy layer thermally coupled to the back surface of the first die.

[0148] Some embodiments of the present disclosure provide a package structure, which includes a first die having a front surface and a back surface opposite the front surface of the first die and having a first width, a second die having a front surface and a back surface opposite the front surface of the second die, the second die having a second width greater than the first width, the back surface of the first die facing the front surface of the second die, a bump structure electrically connecting the first die and the second die, and a thermal management structure between the back surface of the first die and the back surface of the second die. The thermal management structure comprises a first copper-phosphorus alloy layer thermally coupled to the back surface of the first die and the back surface of the second die.

[0149] Some embodiments of the present disclosure provide a package structure, which includes a first die having a front surface and a back surface opposite the front surface of the first die, a second die having a front surface and a back surface opposite the second die, the front surface of the first die facing the front surface of the second die, a first bump structure electrically connecting the first die and the second die, and a thermal management structure (TM, 6 / 7) above the back surface of the first die and the back surface of the second die. The thermal management structure includes a first copper-phosphorus alloy layer thermally coupled to the back surface of the first die and the back surface of the second die.

[0150] The above outlines some features of the embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use this disclosure as a basis for designing or modifying other works and structures to carry out the same purposes and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the present disclosure.

[0151] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described herein. As one skilled in the art can readily appreciate from the present disclosure, any currently existing or hereafter developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein may be utilized in accordance with the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.

Claims

1. a first die having a front surface and a back surface opposite to the front surface; a first heat management structure above the back surface, the first heat management structure comprising: a first copper-phosphorus alloy layer thermally coupled to the back surface of the first die and covering the entire back surface of the first die; a first heat management structure; a package structure.

2. a first adhesive layer between the first copper-phosphorus alloy layer and the back surface of the first die; a first diffusion barrier layer between the first adhesive layer and the first copper-phosphorus alloy layer; The package structure according to claim 1, further comprising.

3. The first copper-phosphorus alloy layer is composed of Cu ３ P, and the package structure according to claim 1.

4. The package structure according to claim 1, wherein the first copper-phosphorus alloy layer comprises a planar portion and a corrugated portion above the planar portion.

5. The package structure according to claim 1, further comprising a heat spreader disposed above the first heat management structure.

6. The package structure according to claim 1, further comprising a first conductive pillar on the front surface of the first die and a second heat management structure laterally surrounding the first conductive pillar.

7. The package structure according to claim 6, further comprising a dielectric layer stack laterally surrounding the second heat management structure.

8. The package structure according to claim 1, further comprising a third heat management structure disposed above the front surface of the first die, the third heat management structure comprising a third copper-phosphorus alloy layer woven into a stack, a second adhesive layer, and a second diffusion barrier layer, the third heat management structure being in contact with input / output (I / O) pads on the front surface of the first die.

9. a second conductive pillar above the third heat management structure; a soldering material connected to the second conductive pillar; The package structure according to claim 8, further comprising.

10. The package structure according to claim 9, further comprising a fourth heat management structure laterally surrounding the second conductive pillar.

11. a sealant for sealing at least one side surface of the first die; a first through via in the sealant and in contact with the first heat management structure above the back surface of the first die; The package structure according to claim 1, further comprising.

12. The first die comprises a through via extending through the first die, the through via comprising: a core layer made of a conductive material; A wetting layer including a fourth copper-phosphorus alloy layer that laterally surrounds the core layer, The package structure according to claim 1, comprising:

13. A second die adjacent to the first die, On the front surface of the first die, a first under bump metallization (UBM) connected to a first conductive pad of the first die, On the front surface of the second die, a second UBM connected to a second conductive pad of the second die, Further comprising: Each of the first UBM and the second UBM includes a second copper-phosphorus alloy layer. The package structure according to claim 1.

14. A second die adjacent to the first die, A third die having a front surface and a back surface opposite to the front surface of the third die, and the front surface of the third die faces the back surface of the first die. A third die, A first bump structure for electrically connecting the first die and the second die, A second bump structure for electrically connecting the first die and the third die, Further comprising: The thermal management structure is further thermally coupled to the front surface of the third die, the back surface of the third die, the side surfaces of the first underfill that seals the first bump structure, and the side surfaces of the second underfill that seals the second bump structure. The package structure according to claim 1.

15. A first die having a front surface and a back surface opposite to the front surface of the first die, and the first die has a first width. A first die, A second die having a front surface and a back surface opposite to the front surface of the second die, and the second die has a second width greater than the first width, and the back surface of the first die faces the front surface of the second die. A second die, A bump structure for electrically connecting the first die and the second die, A thermal management structure above the back surface of the first die and the back surface of the second die, A package structure comprising: The thermal management structure is thermally coupled to the back surface of the first die and the back surface of the second die, and includes a first copper-phosphorus alloy layer that covers the entire back surface of the first die. A package structure.

16. A sealing agent for sealing the first die, Among the sealing agents, a first through-via that electrically connects the front surface of the first die to the heat management structure above the back surface of the first die; The package structure according to claim 15, further comprising the above.

17. The package structure according to claim 16, wherein the bump structure includes a first bump that electrically connects the front surface of the second die to the heat management structure above the back surface of the first die.

18. The package structure according to claim 17, wherein the first bump and the first through-via are each configured to ground the second die and the first die.

19. The package structure according to claim 18, further comprising a plurality of through-vias including the first through-via so as to surround four side surfaces of the first die as viewed from the top view.

20. A heat spreader thermally coupled to the heat management structure above the back surface of the first die; A coating layer covering the heat spreader, the coating layer comprising a second copper-phosphorus alloy layer; The package structure according to claim 15, further comprising the above.

21. A first heat spreader thermally coupled to the heat management structure above the back surface of the first die, the first heat spreader being a fin-type heat spreader and substantially on the same plane as the second die; The package structure according to claim 15, further comprising the above.

22. The package structure according to claim 15, wherein the first die and the second die are arranged to intersect in a top view.

23. The package structure according to claim 15, wherein the heat management structure further comprises a third copper-phosphorus alloy layer thermally coupled to the front surface of the second die.

24. A first die having a front surface and a back surface opposite to the front surface of the first die; A second die having a front surface and a back surface opposite to the front surface of the second die; A first connection structure that electrically connects the first die and the second die; A copper-phosphorus alloy layer thermally coupled to the back surface of the first die and the back surface of the second die and covering the entire back surface of the second die; A package structure comprising the above. **Claim 25**: A package structure according to claim 24, further comprising an under bump metallization (UBM) layer between the second die and the copper-phosphorus alloy layer, wherein the connection structure electrically connects through the first die and the second die and is a through via electrically coupled to the UBM layer.

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