Time-to-digital conversion device, distance measurement device, and mobile

Abstract

To implement high-accuracy time-to-digital conversion.SOLUTION: A time-to-digital conversion device for outputting time-to-digital data corresponding to a time from first timing to second timing comprises: a first circuit 20A including a high-order counter 26 which starts counting a clock signal in accordance with the first timing, and generating high-order bits in the time-to-digital data; a second circuit 20B including a delay element 23 which starts operating in accordance with the second timing, and generating low-order bits in the time-to-digital data; and a control circuit 50 controlling a phase of an output signal from the delay element 23 based on the clock signal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a time-to-digital conversion device, a distance measuring device, and a moving object. [Background technology]

[0002] In recent years, time-to-digital converters (TDCs) that convert time into digital signals have been used in various fields. The time-to-digital converter described in Patent Document 1 is applied to a sensor capable of capturing a three-dimensional (3D) distance image, and measures the time-of-flight of photons detected by a SPAD (Single Photon Avalanche Diode) pixel. The time-to-digital converter in Patent Document 1 also includes a coarse TDC and a fine TDC. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2013 / 034770 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the time-to-digital conversion device described in Patent Document 1, a code error at the connection between the higher-order TDC data and the lower-order TDC data causes a decrease in conversion accuracy. [Means for solving the problem]

[0005] According to one disclosure of the present specification, there is provided a time-to-digital conversion device that outputs time digital data corresponding to a time from a first timing to a second timing, the time-to-digital conversion device comprising: a first circuit including an upper counter that starts counting a clock signal in response to the first timing and generates upper bits of the time digital data; a second circuit including a delay element that starts operating in response to the second timing and generates lower bits of the time digital data; and a control circuit that controls the phase of an output signal of the delay element based on the clock signal. Effect of the Invention

[0006] According to the present invention, it is possible to realize highly accurate time-to-digital conversion. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of a range image sensor system according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram of a range image sensor in the first embodiment. [Diagram 3] FIG. 2 is a circuit diagram of a pixel according to the first embodiment. [Figure 4] 1 is a circuit diagram of a time-to-digital conversion device according to a first embodiment. [Diagram 5] 1 is a circuit diagram of a time-to-digital conversion device according to a first embodiment. [Figure 6] 1 is a circuit diagram of a time-to-digital conversion device according to a first embodiment. [Figure 7] 1 is a circuit diagram of a time-to-digital conversion device according to a first embodiment. [Figure 8] 1 is a circuit diagram of a time-to-digital conversion device according to a first embodiment. [Figure 9] 4 is a timing chart of the range image sensor in the first embodiment. [Figure 10] 4 is a timing chart of the range image sensor in the first embodiment. [Figure 11]10 is a timing chart of the range image sensor in the second embodiment. [Figure 12] FIG. 11 is a circuit diagram of a time-to-digital conversion device according to a third embodiment. [Figure 13] FIG. 11 is a circuit diagram of a time-to-digital conversion device according to a third embodiment. [Figure 14] FIG. 13 is a block diagram of an optical time-of-flight range image sensor in a fourth embodiment. [Figure 15] FIG. 13 is a block diagram of an optical time-of-flight range image sensor in a fifth embodiment. [Figure 16] FIG. 13 is a schematic diagram of a time-to-digital conversion device according to a sixth embodiment. [Figure 17] FIG. 23 is a diagram illustrating an example of the configuration of an apparatus according to the seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] An embodiment of the present invention will be described below with reference to the drawings. The embodiments shown below are intended to embody the technical ideas of the present invention, and are not intended to limit the present invention. The sizes and positional relationships of the components shown in each drawing may be exaggerated to clarify the description. In the following description, the same components may be assigned the same numbers and descriptions thereof may be omitted.

[0009] [First embodiment] 1 is a schematic diagram of a range image sensor system according to this embodiment. The range image sensor system is a distance measuring device that measures the distance to an object based on the time of flight (TOF) of light, and includes a light emitting unit 110, an optical system 105, a range image sensor 100, an image processing circuit 101, a memory 102, and a monitor 103.

[0010] The light emitting unit 110 can irradiate a pulsed light such as a laser toward an object. The optical system 105 includes one or more lenses, and forms an image of the image light (incident light) reflected by the object on the light receiving surface (light receiving unit) of the range image sensor 100. The range image sensor 100 includes a SPAD (Single Photon Avalanche Diode) that receives a single photon, and a time-to-digital converter that converts the time from light emission to light reception into a digital signal. The image processing circuit 101 generates a distance image according to the distance to the object based on the signal output from the time-to-digital converter and the known speed of light. The generated distance image is output to the memory 102 and the monitor 103. The memory 102 can store the distance image, and the monitor 103 can display the distance image.

[0011] Fig. 2 is a block diagram of the range image sensor 100 in this embodiment. The range image sensor 100 includes a plurality of pixels 10 arranged across a plurality of rows and a plurality of columns, and a time-to-digital conversion device that converts the time from light emission to light reception into a digital signal based on signals from the plurality of pixels 10. The digital conversion device further includes a TDC 20, a frequency divider 30, a signal generating circuit 40, a PLL (Phase Locked Loop) circuit 50, and a correction circuit 60. The configuration of each part of the range image sensor 100 will be described in detail below with reference to Figs. 2 to 8.

[0012] 3 is a circuit diagram of a pixel 10 in this embodiment. The pixel 10 includes a SPAD 11, a quenching element 12, and a waveform shaping unit 13, and functions as a light receiving unit of pulsed light. The SPAD 11 generates a pair of charges according to the incident light by photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the SPAD 11, and a voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the SPAD 11. A reverse bias voltage is applied to the anode and cathode, and the SPAD 11 is in a state where avalanche multiplication is possible. When a photon is incident on the SPAD 11 in a state where the reverse bias voltage is supplied, the charge generated by the photon undergoes avalanche multiplication, generating an avalanche current.

[0013] The quench element 12 is provided between a power supply line that supplies the voltage VH and the cathode of the SPAD 11. The quench element 12 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the SPAD 11 and suppressing avalanche multiplication (quench operation). The quench element 12 also functions to return the voltage supplied to the SPAD 11 to the voltage VH by passing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0014] The waveform shaping unit 13 functions as a signal generating unit that generates a detection pulse based on the output generated by the incidence of a photon. That is, the waveform shaping unit 13 shapes the potential change of the cathode of the SPAD 11 obtained at the time of photon detection, and outputs a square wave STOP signal (detection pulse). The waveform shaping unit 13 may be configured, for example, with an inverter circuit. Although one inverter circuit is shown in FIG. 3, a circuit in which a plurality of inverter circuits are connected in series may also be used. Also, other circuits having a waveform shaping effect may also be used.

[0015] 4 is a circuit diagram of the TDC 20 in this embodiment. The TDC 20 is provided for each row of pixels 10, and the pixels 10 in each column can be sequentially connected to the TDC 20 by an operation circuit (not shown). The TDC 20 includes a sequencer 21, a multiplexer 22, a polyphase VCO (Voltage Controlled Oscillator) 23, a lower encoder 24, a lower counter 25, and an upper counter 26. In the following description, the upper counter 26 may be referred to as an upper TDC 20A (first circuit), and the polyphase VCO 23, the lower encoder 24, and the lower counter 25 may be referred to as a lower TDC 20B (second circuit).

[0016] The sequencer 21 receives a START signal, a STOP signal, and a clock signal TDCLK. The START signal is a signal synchronized with the light emission timing (first timing) of the light emitting unit 110 in FIG. 1. The TDC 20 starts measuring time in response to the START signal. The STOP signal is a signal output from the pixel 10. That is, the STOP signal represents the timing (second timing) at which the pulsed light emitted from the light emitting unit 110 and reflected by the object is received by the pixel 10. The TDC 20 can convert the time from the START signal to the STOP signal into a digital signal. The clock signal TDCLK is a reference clock common to the multiple TDCs 20. The clock signal TDCLK is a so-called global clock that is used not only by the TDC 20 but also by the entire range image sensor system in FIG. 1. The sequencer 21 generates a clock signal CoarseCLK of the upper counter 26 and a sequencer signal ENS that controls the multi-phase VCO 23 based on the input START signal, STOP signal, and clock signal TDCLK.

[0017] Multiplexer 22 is a switching circuit that selects either sequencer signal ENS or signal PERIOD from signal generating circuit 40 depending on the operation mode, and outputs the selected signal as enable signal EN to polyphase VCO 23. The time-to-digital conversion device in this embodiment has a distance image measurement mode in which a distance image of an object is measured, and a period measurement mode in which periods of lower encoder 24, lower counter 25, and upper counter 26 are measured. In the distance image measurement mode (first operation mode), multiplexer 22 outputs sequencer signal ENS as enable signal EN, and in the period measurement mode (second operation mode), outputs signal PERIOD for correction processing as enable signal EN.

[0018] The multi-phase VCO 23 is a delay element and can be a multi-phase output voltage controlled oscillator such as a ring oscillator circuit. When the ring oscillator circuit is composed of M (M is a multiple integer) inverting circuits, the multi-phase VCO 23 can output an M-bit signal. The multi-phase VCO 23 will be described in detail later.

[0019] The lower encoder 24 encodes the M-bit signal of the multi-phase VCO 23 and outputs binary code data Dfine_phase. The lower counter 25 counts one phase (1 bit) of the M-bit signal of the multi-phase VCO 23 and outputs binary code data Dfine_cycle. That is, the data Dfine_cycle represents the oscillation period of the multi-phase VCO 23. The upper counter 26 starts counting the clock signal CoarseCLK (clock signal TDCLK) at the rising edge of the START signal and stops counting after a predetermined period has elapsed since the rising edge of the STOP signal. The upper counter 26 outputs the count result as binary code data Dcoarse. In the following description, the data Dcoarse of the upper counter 26 may be referred to as upper TDC data (upper bits), and the data Dfine_cycle of the lower counter 25 and the data Dfine_phase of the lower encoder 24 may be referred to as lower TDC data (lower bits).

[0020] 5 is a circuit diagram showing the details of the sequencer 21. The sequencer 21 includes flip-flops 211 and 212 and gates 213, 214, and 215, and controls the operation of the TDC 20. Although not shown, a circuit for latching the START signal and the STOP signal is provided in the front stage of the sequencer 21. The flip-flops 211 and 212 are D-type and cascade-connected. That is, the STOP signal is input to the input node D of the flip-flop 211, and the output node of the flip-flop 211 is connected to the input node D of the flip-flop 212. The clock signal TDCLK is input to the clock nodes of the flip-flops 211 and 212. The output node of the flip-flop 212 is connected to the inverting input nodes of the gates 213 and 214. The clock signal TDCLK is input to the non-inverting input node of the gate 213, and the STOP signal is input to the non-inverting input node of the gate 214. The sequencer signal ENS maintains a high level from the rising edge of the STOP signal to the timing of two rising edges of the clock signal TDCLK. The sequencer signal ENS is output as an enable signal EN from the multiplexer 22 to the multi-phase VCO 23. The START signal is input to one input node of the gate 215, and the other input node is connected to the output node of the gate 213. Therefore, the clock signal TDCLK is output from the output node of the gate 215 from the rising edge of the START signal to the timing of two rising edges of the clock signal TDCLK after the rising edge of the STOP signal. The clock signal TDCLK at the output node of the gate 215 is output to the upper counter 26 as the clock signal CoarseCLK.

[0021] FIG. 6 is a circuit diagram showing the details of the multi-phase VCO 23. As described above, the multi-phase VCO 23 is composed of a ring oscillator circuit including M inverter circuits 231 to 23M. The non-inverting output node of the inverter circuit 231 is connected to the inverting input node of the inverter circuit 232, and the inverting output node of the inverter circuit 231 is connected to the non-inverting input node of the inverter circuit 232. Similarly, the inverter circuits 232 to 23M are connected in cascade, and the output node of the inverter circuit 23M is connected to the input node of the inverter circuit 231. An enable signal EN is input to the inverter circuits 231 to 23M. When the enable signal EN becomes high level, the output signals of the output nodes of the inverter circuits 231 to 23M are sequentially inverted with a predetermined delay time. This allows the multi-phase VCO 23 to operate as an M-bit multi-phase oscillator. When the enable signal EN becomes low level, the inversion operation of the inverter circuits 231 to 23M is stopped, and the M-bit output signal is reset to an initial value (initial phase). In addition, a control voltage VCTRL is applied to the multi-phase VCO 23, and the oscillation frequency and phase of the inverter circuits 231-23M can be controlled by the control voltage VCTRL. For example, the control voltage VCTRL is applied to the gate nodes of the current source transistors or load transistors that configure the inverter circuits 231-23M. This causes the delay time (phase) of the inverter circuits 231-23M to change according to the control voltage VCTRL, making it possible to control the oscillation frequency and phase of the ring oscillator circuit.

[0022] The frequency divider 30 and the signal generating circuit 40 generate a signal PERIOD for the period measurement mode. FIG. 7 is a circuit diagram of the signal generating circuit 40. The signal generating circuit 40 includes flip-flops 41 and 42 and a gate 43. The flip-flops 41 and 42 are D-type and cascade-connected. An input node D of the flip-flop 41 is set to a high level (power supply voltage), and a node N1 of the flip-flop 41 is connected to an input node D of the flip-flop 42. A clock signal TDCLK is input to the clock nodes of the flip-flops 41 and 42. A non-inverting input node of the gate 43 is connected to the node N1, and an inverting input node of the gate 43 is connected to a node N2. After the signal RESET at the reset nodes of the flip-flops 41 and 42 goes to a low level, the node N1 goes to a high level at the rising edge of the clock signal TDCLK. One period later, the node N2 goes to a high level at the rising edge of the clock signal TDCLK. As a result, a signal PERIOD that goes high during one cycle of the clock signal TDCLK is output from the output node of the gate 43. Also, in the preceding stage of the signal generating circuit 40, the frequency divider 30 divides the frequency of the clock signal TDCLK, making it possible to generate a signal PERIOD that goes high every two or four cycles of the clock signal TDCLK.

[0023] 8 is a circuit diagram of a PLL circuit (control circuit) 50 in this embodiment. The PLL circuit 50 is a phase-locked loop circuit, and includes a phase comparator 51, a loop filter 52, a multi-phase VCO 53, and a frequency divider 54. The phase comparator 51, the loop filter 52, and the frequency divider 54 configure a feedback circuit that feeds back a control voltage (control signal) VCTRL to the multi-phase VCO 53.

[0024] The multi-phase VCO 53 is composed of a ring oscillator circuit, and preferably has the same characteristics as the multi-phase VCO 23. For example, the multi-phase VCO 53 may be configured as a replica circuit having the same circuit configuration and size as the multi-phase VCO 23 on a semiconductor substrate. The frequency divider 54 divides the frequency of a 1-bit clock signal of the M bits of the multi-phase VCO 53 by 1 / N (N is an integer equal to or greater than 2) and outputs a feedback clock signal FBCLK. That is, the feedback clock signal FBCLK is a frequency-divided signal of the oscillation period of the multi-phase VCO 53. The phase comparator 51 includes a phase comparison circuit and a charge pump circuit, and outputs a charge pump voltage obtained by integrating the phase difference between the clock signal TDCLK and the feedback clock signal FBCLK. The loop filter 52 smoothes the charge pump voltage and outputs a control voltage VCTRL. The control voltage VCTRL is input to the multi-phase VCO 53, and the phase of the multi-phase VCO 53 is controlled by the control voltage VCTRL. As a result, the clock signal TDCLK and the feedback clock signal FBCLK obtained by dividing the output signal of the multi-phase VCO 53 are in phase. The control voltage VCTRL is also supplied to the multi-phase VCO 23 of each TDC 20 in the same manner. The multi-phase VCO 23 of the TDC 20 oscillates at a frequency N times (N is an integer equal to or greater than 2) the frequency of the clock signal TDCLK, and the phases of the multi-phase VCOs 23 are synchronized. In this way, the frequency and phase of the multi-phase VCO 23 of the multiple TDCs 20 are controlled by the common PLL circuit 50, and are therefore robust against manufacturing processes, voltages, and temperatures. Therefore, even if the element sizes of the multi-phase VCOs 23 and 53 are reduced, it is possible to suppress characteristic variations in the multiple TDCs 20, and to realize highly accurate time-to-digital conversion while reducing power consumption.

[0025] Next, the operation of the distance image sensor in this embodiment will be described. Fig. 9 is a timing chart of the distance image sensor, and shows the operation in the distance image measurement mode. Note that an operational delay may occur in the actual circuit, but the timing chart in Fig. 10 shows the circuit as having no operational delay. In the distance image measurement mode, the multiplexer 22 outputs the sequencer signal ENS from the sequencer 21 to the polyphase VCO 23 as an enable signal EN.

[0026] At time t10, the START signal transitions from low to high in synchronization with the rising edge of the clock signal TDCLK, and the light emitting unit 110 emits a pulse of light toward the target (first timing). The sequencer 21 outputs the clock signal TDCLK as the clock signal CoarseCLK to the upper counter 26, and the upper counter 26 starts counting. At the rising edge of the clock signal CoarseCLK, the data Dcoarse changes from "0" to "1".

[0027] At time t11, at the rising edge of the clock signal CoarseCLK, the data Dcorse of the upper counter 26 changes from "1" to "2".

[0028] At time t12, the pixel 10 detects the pulsed light reflected by the object and outputs a STOP signal (second timing). The sequencer signal ENS transitions from low to high, and the enable signal EN of the multiplexer 22 also transitions from low to high. When the enable signal EN becomes high, the multi-phase VCO 23 starts oscillating.

[0029] At time t13, the clock signal CoarseCLK rises, and the data Dcoarse of the upper counter 26 changes from "3" to "4". Also, in FIG. 5, the output node of the flip-flop 211 of the sequencer 21 goes from low level to high level. The output node of the flip-flop 212 maintains the low level, and the sequencer signal ENS maintains the high level. Therefore, the enable signal EN from the multiplexer 22 also maintains the high level, and the multi-phase VCO 23 continues to oscillate. Also, the sequencer 21 continues to output the clock signal TDCLK as the clock signal CoarseCLK.

[0030] At time t14, the clock signal TDCLK rises, and the output node of the flip-flop 212 of the sequencer 21 in FIG. 5 becomes high level. The sequencer signal ENS at the output node of the gate 214 transitions from high level to low level. That is, the sequencer 21 sets the sequencer signal ENS to low level from the rising timing of the STOP signal to the timing of two rising timings of the clock signal. The low level sequencer signal ENS is supplied as an enable signal EN from the multiplexer 22 to the multi-phase VCO 23, and the multi-phase VCO 23 stops oscillating. In addition, the sequencer 21 stops outputting the clock signal CoarseCLK, and the upper counter 26 stops counting.

[0031] After that, the TDC 20 outputs the upper TDC data (Dcoarse) and the lower TDC data (Dfine_cycle, Dfine_phase). The range image sensor 100 calculates these data and outputs them as time digital data (measured distance information). The time digital data corresponding to the time from the START signal to the STOP signal is expressed by the bit string of the following formula.

number

[0032] Here, b2 represents the bit length (resolution) of the data Dfine_cycle, and b3 represents the bit length (resolution) of the data Dfine_phase. For example, when the bit length b1 of the data Dcoarse is 6 bits "101010", the bit length b2 of the data Dfine_cycle is 5 bits "01010", and the bit length b3 of the data Dfine_phase is 3 bits "010", the time digital data before correction is "10101001010010". That is, the 6-bit upper TDC data (upper bits) and the 8-bit lower TDC data (lower bits) are concatenated to obtain time digital data with a resolution of 14 bits (=b1+b2+b3). If the upper TDC 20A and the lower TDC 20B were to operate asynchronously, the ratio of bit change with respect to time in the connection code between the lower TDC data and the upper TDC data, i.e., the carry from the 8th bit to the 9th bit, would not be linear, and a step would occur. In this embodiment, as described later, it is possible to reduce code errors in the connection between the upper TDC data and the lower TDC data by the PLL circuit 50 and the correction circuit 60.

[0033] In addition, the TDC 20 in this embodiment performs time-to-digital conversion in two stages, the upper TDC 20A and the lower TDC 20B. Since the lower TDC 20B operates at high speed, the power consumption of the multi-phase VCO 23 in particular may be large. However, in this embodiment, the operation time of the lower TDC 20B is limited to a predetermined period from the light reception timing (time t12). That is, the operation time of the lower TDC 20B (times t12 to t14) is shorter than the conversion time from the light emission timing to the light reception timing (times t10 to t12). Therefore, it is possible to realize high-precision time-to-digital conversion using the lower TDC 20B while suppressing power consumption.

[0034] FIG. 10 is a timing chart of the range image sensor in this embodiment, showing the operation in the period measurement mode. In the period measurement mode, the lower TDC data (Dfine_cycle_tdclk, data Dfine_phase_tdclk) in one or more periods of the clock signal TDCLK is measured. The correction circuit 60 can correct the time digital data of the above-mentioned formula 1 based on the measured lower TDC data. Note that in FIG. 10, an operation delay may occur in the actual circuit, but it is shown as if there is no operation delay. In the period measurement mode, the multiplexer 22 outputs the period signal PERIOD from the signal generation circuit 40 to the multi-phase VCO 23 as an enable signal EN.

[0035] 7 are at a high level, and the flip-flops 41 and 42 are in a reset state. Therefore, the nodes N1 and N2, the signal PERIOD, and the enable signal EN are at a low level, and the multi-phase VCO 23 stops oscillating.

[0036] At time t21, the reset nodes of the flip-flops 41 and 42 of the signal generating circuit 40 transition from high level to low level.

[0037] At time t22, when the clock signal TDCLK rises, the node N1 of the flip-flop 41 of the signal generating circuit 40 transitions from low to high, and the signal PERIOD at the output node of the gate 43 transitions from low to high. The multiplexer 22 in FIG. 4 outputs the signal PERIOD as the enable signal EN, which also transitions from low to high. The multi-phase VCO 23 receives the high-level enable signal EN and starts oscillating. The lower encoder 24 and the lower counter 25 in the TDC 20 start counting based on the clock signal of the multi-phase VCO 23.

[0038] At time t23, when the clock signal TDCLK rises, the node N2 of the flip-flop 42 of the signal generating circuit 40 transitions from low to high, and the signal PERIOD at the output node of the gate 43 transitions from high to low. The enable signal EN also transitions to low, and the multi-phase VCO 23 stops oscillating. The lower counter 25 outputs data Dfine_cycle_tdclk, and the lower encoder 24 outputs data Dfine_phase_tdclk. The data Dfine_cycle_tdclk and the data Dfine_phase_tdclk correspond to one cycle of the clock signal TDCLK.

[0039] The measured data Dfine_cycle_tdclk and data Dfine_phase_tdclk are recorded in a memory in the correction circuit 60 and used to correct the distance information in the distance image measurement mode. Note that the data Dfine_cycle_tdclk and data Dfine_phase_tdclk may be measured for each TDC 20, or may be measured for any one of the TDCs 20.

[0040] The correction circuit 60 can correct the time digital data measured in the distance image measurement mode using the data Dfine_cycle_tdclk and the data Dfine_phase_tdclk measured in the period measurement mode. The correction circuit 60 can include a memory that stores a program for the correction process and an arithmetic circuit that executes the program. The period measurement mode and the correction process are described in detail below.

[0041] The correction circuit 60 performs correction (calibration) on the uncorrected distance information (Equation 1) in the distance image measurement mode using the data Dfine_cycle_tdclk and data Dfine_phase_tdclk in the period measurement mode. The corrected time digital data is calculated according to the following equation.

number

[0042] In Equation 2, b2 represents the bit length (resolution) of the lower counter 25, and b3 represents the bit length (resolution) of the lower encoder 24. In Equation 2, (Dfine_cycle_tdclk×2 b3 +Dfine_phase_tdclk) represents the lower TDC data corresponding to one cycle of the clock signal TDCLK. The correction circuit 60 corrects the lower TDC data in the distance image measurement mode using the lower TDC data in one cycle of the clock signal TDCLK as a reference. This makes it possible to reduce code errors at the connection between the upper TDC data and the lower TDC data, and to realize a highly accurate TDC.

[0043] Here, as an alternative to this embodiment, it is also possible to adjust the frequency of the clock signal TDCLK in order to reduce errors in the connecting code between the upper TDC data and the lower TDC data. However, the clock signal TDCLK is often used in common in a system, and changing the frequency of the clock signal TDCLK may cause problems in the operation of the system. According to this embodiment, it is possible to reduce code errors in the connecting code between the upper TDC data and the lower TDC data without changing the clock signal TDCLK.

[0044] In this embodiment, the frequency of the multi-phase VCO 23 of the lower TDC 20B is controlled by the PLL circuit 50. That is, the frequency of the multi-phase VCO 53 of the PLL circuit 50 is controlled by the control voltage VCTRL so as to be an integer multiple of the frequency of the clock signal TDCLK, and the control voltage VCTRL of the multi-phase VCO 53 is also supplied to the multi-phase VCO 23 of the lower TDC 20B. The multi-phase VCO 53 of the PLL circuit 50 is configured as a replica circuit of the multi-phase VCO 23 of the lower TDC 20B. Although the multi-phase VCO 23 of the lower TDC 20B does not constitute a feedback loop of the PLL circuit 50, the multi-phase VCO 23 operates in the same manner as the multi-phase VCO 53 of the PLL circuit 50, and the multi-phase VCO 23 can oscillate at a frequency that is an integer multiple of the clock signal TDCLK. This makes it possible to reduce code errors in the connection between the upper TDC data and the lower TDC data.

[0045] Moreover, the PLL circuit 50 can reduce the frequency fluctuation of the multi-phase VCO 23 of the lower TDC 20B and the variation in the oscillation frequency of the multiple lower TDCs 20B. The delay time of the inverting circuit constituting the ring oscillator is likely to vary, and the oscillation frequency of each of the multi-phase VCOs 23 may vary. In order to reduce power consumption, it is preferable to configure the element size of the ring oscillator small, but in this case, the deviation of the oscillation frequency of the ring oscillator is likely to become large. Furthermore, the oscillation frequency of the ring oscillator may vary due to factors such as the manufacturing process, the driving voltage, and the temperature. Therefore, the least significant bit LSB (Least Significant Bit) of the lower TDC data may vary. According to this embodiment, the PLL circuit 50 is shared by multiple multi-phase VCOs 23, and the multiple multi-phase VCOs 23 are controlled by a common PLL circuit 50. Moreover, the PLL circuit 50 operates by a multi-phase VCO 53 which is a replica circuit of the multi-phase VCO 23. Therefore, it is possible to reduce the frequency fluctuation of the multi-phase VCO 23 of the lower TDC 20B and the variation in the oscillation frequencies of the multiple lower TDCs 20B.

[0046] Furthermore, according to this embodiment, the lower TDC data in the distance image measurement mode is corrected by the correction circuit 60, using the lower TDC data in the period measurement mode as a reference. This makes it possible to further reduce code errors at the connection between the upper TDC data and the lower TDC data, and to realize a highly accurate TDC.

[0047] [Second embodiment] Next, the distance image sensor system in this embodiment will be described. In the period measurement mode described above, the lower TDC data corresponding to one period of the clock signal TDCLK is measured, but the number of periods is not limited. Hereinafter, the present embodiment will be described with a focus on the configuration different from the first embodiment.

[0048] 11(A) and 11(B) are timing charts of the distance image sensor, showing the operation in the period measurement mode. As shown in FIG. 11(A), the lower TDC data corresponding to two periods of the clock signal TDCLK may be measured. Also, as shown in FIG. 11(B), the lower TDC data corresponding to four periods of the clock signal TDCLK may be measured. When the lower TDC data is measured in N periods (N is an integer equal to or greater than 2) of the clock signal TDCLK, the data Dfine_cycle_tdclk and the data Dfine_phase_tdclk corresponding to one period of the clock signal TDCLK are 1 / N of the data Dfine_cycle and Dfine_phase of the N periods. In this way, the correction circuit 60 can correct the time data in the distance image measurement mode by using the lower TDC data for multiple periods of the clock signal TDCLK.

[0049] This embodiment can also achieve the same effect as the above embodiment. That is, it is possible to further reduce the code error of the connection between the upper TDC data and the lower TDC data. In addition, since the oscillation frequency may not be stable immediately after the multi-phase VCO 23 starts oscillating, it is possible to realize a more accurate TDC by increasing the number of periods in the period measurement mode.

[0050] [Third embodiment] Next, the range image sensor system in this embodiment will be described. The delay element of the low-order TDC 20B is not limited to the multi-phase VCO 23, and may be replaced with another configuration. Hereinafter, the present embodiment will be described, focusing on the differences from the above-mentioned embodiment.

[0051] FIG. 12 is a circuit diagram of the TDC 20 in this embodiment. The TDC 20 in this embodiment includes a voltage controlled delay line (VCDL) 27 instead of the multi-phase VCO 23 described above. The voltage controlled delay line 27 includes a plurality of delay elements connected in series to configure a multi-phase output type VCDL. Each delay element includes, for example, an inverting circuit such as a differential amplifier circuit, and a load circuit of the inverting circuit. The control voltage VCTRL is applied to a transistor gate or the like that configures the load circuit, and the delay time is controlled by the control voltage VCTRL. Similarly to the first embodiment, the voltage controlled delay line 27 can start operating in response to a high-level enable signal EN. The lower encoder 24 encodes the data of the output phase of the voltage controlled delay line 27, and outputs binary code data Dfine_phase. The voltage controlled delay line 27 does not have a ring oscillator configuration like the multi-phase VCO 23. For this reason, the TDC 20 in this embodiment does not include a lower counter 25, and the data Dfine_phase is output as the lower TDC data Dfine.

[0052] FIG. 13 is a circuit diagram of the PLL circuit 50 in this embodiment. In the PLL circuit 50 in this embodiment, a voltage-controlled delay line 58 is provided instead of the multi-phase VCO 53. The PLL circuit 50 using the voltage-controlled delay line 58 is sometimes called a DLL (Delay Locked Loop). It is desirable that the voltage-controlled delay line 58 of the PLL circuit 50 has the same characteristics as the voltage-controlled delay line 27 of the TDC 20, and the voltage-controlled delay line 58 can be configured as a replica circuit having the same circuit and size as the voltage-controlled delay line 27 on a semiconductor substrate. The phase (delay time) of the voltage-controlled delay line 58 is controlled so that the clock signal TDCLK and the feedback clock signal FBCLK are in phase. The control voltage VCTRL is supplied to the voltage-controlled delay lines 27 of each TDC 20 in the same manner. As a result, the phase of the voltage-controlled delay line 27 is synchronized with the phase of a signal having a frequency that is an integer multiple of the clock signal TDCLK. In addition, the frequency and phase of the voltage-controlled delay lines 27 of each TDC 20 are controlled by the common PLL circuit 50, so that the TDC 20 is robust against variations in the manufacturing process, voltage, and temperature. Therefore, even if the element sizes of the voltage-controlled delay lines 27 and 58 are small, the variation in characteristics is reduced, enabling low power consumption.

[0053] In this embodiment, the range image sensor 100 can also perform calculations on the data output from the TDC 20 and output the data as time digital data (measured distance information). When the upper TDC data is represented by data Dcoarse with a bit length of b1 and the lower TDC data is represented by data Dfine with a bit length of b2, the above-mentioned formula 1 can be rewritten as the following formula. Dcoarse x 2 b2 -Dfine (Formula 3) Here, the lower TDC data Dfine is (Dfine_phase) in this embodiment, or (Dfine_clock×2) in the first embodiment. b3 +Dfine_phase) is a generalized representation.

[0054] Furthermore, the correction circuit 60 can correct the time digital data using the data Dfine_tdclk of the lower TDC 20B during one cycle of the clock signal TDCLK. The above-mentioned Equation 2 can be simplified to the following equation. Dcoarse x 2 b2 -(Dfine / Dfine_tdclk) × 2 b2 ...(Formula 4)

[0055] In this embodiment as well, it is possible to further reduce code errors at the connection between the higher order TDC data and the lower order TDC data, and to achieve highly accurate time-to-digital conversion.

[0056] [Fourth embodiment] 14 is a block diagram of a range image sensor 100 in this embodiment. The following describes this embodiment, focusing on the configuration different from the first to third embodiments.

[0057] In the above-described embodiment, a TDC 20 is provided for each row of pixels 10, but in the present embodiment, a TDC 20 is provided for each pixel 10 (for each light receiving section). In each pixel 10, a STOP signal is output to the TDC 20, and time-to-digital conversion can be performed by the TDC 20 for each pixel 10. In the present embodiment as well, multiple TDCs 20 are controlled by a common PLL circuit 50, so that it is possible to reduce the variation and fluctuation of the oscillation frequency in each TDC 20. Furthermore, the data Dfine_cycle and data Dfine_phase of each TDC 20 are output to a correction circuit 60, and the lower TDC data is corrected in the correction circuit 60. Therefore, in the present embodiment as well, it is possible to reduce code errors in the connection between the upper TDC data and the lower TDC data, and to realize highly accurate time-to-digital conversion.

[0058] [Fifth embodiment] 15 is a block diagram of a range image sensor 100 in this embodiment. The following describes this embodiment, focusing on the configuration different from the first to fourth embodiments.

[0059] A TDC 20 is provided for each subarray including a plurality of pixels 10. In FIG. 15, the subarray includes two rows and two columns of pixels 10, and a TDC 20 is provided for every four pixels 10. In this embodiment as well, all the TDCs 20 are controlled by the common PLL circuit 50, so that it is possible to reduce the variation and fluctuation of the oscillation frequency of each TDC 20. Furthermore, because the lower TDC data is corrected in the correction circuit 60, it is possible to reduce code errors at the connection between the upper TDC data and the lower TDC data, and to realize a highly accurate TDC.

[0060] [Sixth embodiment] FIG. 16 is a schematic diagram of the range image sensor 100 in this embodiment, showing the configuration of the stacked range image sensor 100. The range image sensor 100 includes a sensor substrate (first substrate) 1 and a circuit substrate (second substrate) 2 stacked on each other, and the sensor substrate 1 and the circuit substrate 2 are electrically connected to each other. The range image sensor 100 is a back-illuminated type, in which light is incident from a first surface of the sensor substrate 1, and the circuit substrate 2 is disposed on a second surface of the sensor substrate 1. The sensor substrate 1 has a first semiconductor layer and a first wiring structure. The circuit substrate 2 has a second semiconductor layer and a second wiring structure. The second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer are stacked in this order to form the range image sensor 100.

[0061] The sensor substrate 1 and the circuit substrate 2 may be diced chips, but are not limited to chips. For example, each substrate may be a wafer. Also, each substrate may be stacked in a wafer state and then diced, or may be chipped and then stacked and bonded. The sensor substrate 1 is provided with a pixel region 1a including an array of pixels 10, and the circuit substrate 2 is provided with a circuit region 2a for processing signals detected by the pixel region 1a. In the circuit region 2a, a TDC 20, a frequency divider 30, a signal generating circuit 40, a PLL circuit 50, a correction circuit 60, etc. are formed.

[0062] This embodiment can also achieve the same effects as the above-described embodiment. Moreover, by stacking the sensor substrate 1 and the circuit substrate 2, it is possible to realize a range image sensor 100 with high sensitivity and high integration. The range image sensor 100 may be formed on the same substrate.

[0063] [Seventh embodiment] A moving body according to the seventh embodiment of the present invention will be described with reference to Fig. 17. Fig. 17 is a diagram showing an example of the configuration of a moving body according to this embodiment.

[0064] 17(a) shows an example of the configuration of a device mounted on a vehicle as an on-board camera. The device 300 has a distance measurement unit 303 and a collision determination unit 304. The distance measurement unit 303 is configured from the distance image sensor 100 in the first to sixth embodiments, and measures the distance to an object. The distance information is information related to the distance to the object, etc. The collision determination unit 304 determines whether or not there is a possibility of a collision based on the distance measured by the distance measurement unit 303.

[0065] The device 300 is connected to a vehicle information acquisition device 310 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. In addition, the device 300 is connected to a control ECU 320, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 304. In addition, the device 300 is also connected to an alarm device 330 that issues an alarm to the driver based on the judgment result of the collision judgment unit 304. For example, when the judgment result of the collision judgment unit 304 indicates that there is a high possibility of a collision, the control ECU 320 instructs the vehicle to apply the brakes, stop the accelerator, suppress the engine output, etc., to avoid the collision and reduce damage. The alarm device 330 warns the user through alarm output such as sound, display of alarm information on the screen of a car navigation system, etc., and vibration of the seat belt and steering wheel. These devices of the device 300 function as a mobile object control unit that controls the operation of controlling the vehicle as described above.

[0066] In this embodiment, the device 300 measures distances around the vehicle, for example, in front or behind. Fig. 17(b) shows the device when measuring distances in front of the vehicle (distance measurement range 350). A vehicle information acquisition device 310, which serves as a distance measurement control means, sends an instruction to the device 300 or the distance measurement unit 303 to perform a distance measurement operation. This configuration can further improve the accuracy of distance measurement.

[0067] Although the above describes the control of avoiding collision with other vehicles, the present embodiment can also be applied to control of automatic driving by following other vehicles, control of automatic driving so as not to deviate from lanes, etc. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present embodiment can be applied to devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, in addition to moving bodies.

[0068] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present invention.

[0069] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0070] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

[0071] The disclosure of the above-described embodiment includes the following configurations. (Configuration 1) A time-to-digital conversion device that outputs time digital data corresponding to a time from a first timing to a second timing, a first circuit including a high-order counter that starts counting a clock signal in response to the first timing and that generates high-order bits of the time digital data; a second circuit including a delay element that starts operating in response to the second timing and that generates lower bits of the time digital data; a control circuit for controlling the phase of the output signal of the delay element based on the clock signal. (Configuration 2) The control circuit includes: a replica circuit of the delay element of the second circuit; a phase locked loop circuit that feeds back to the replica circuit a control voltage based on a comparison between a phase of a frequency-divided signal of an output signal of the replica circuit and a phase of the clock signal; 2. The time-to-digital conversion device according to configuration 1, wherein the control circuit further supplies the control voltage to the delay element of the second circuit. (Configuration 3) Further comprising a plurality of the first circuits and a plurality of the second circuits; 3. The time-to-digital conversion device according to configuration 1 or 2, wherein the control circuit supplies the control voltage to a plurality of the delay elements of a plurality of the second circuits. (Configuration 4) 4. The time-to-digital conversion device according to any one of configurations 1 to 3, wherein the upper counter and the delay element stop operating after a predetermined period has elapsed from the second timing. (Configuration 5) 5. The time-to-digital conversion device according to configuration 4, wherein the predetermined period is a timing synchronized with the clock signal. (Configuration 6) 6. The time-to-digital conversion device according to any one of configurations 1 to 5, wherein the delay element is a voltage-controlled oscillator. (Configuration 7) 6. The time-to-digital conversion device according to any one of configurations 1 to 5, wherein the delay element is a multiphase output type voltage controlled oscillator. (Configuration 8) 6. A time-to-digital conversion device according to any one of configurations 1 to 5, wherein the delay element is a voltage-controlled delay line. (Configuration 9) The time-to-digital conversion device according to configuration 7, wherein the second circuit further includes a lower counter that counts an oscillation period of the delay element, and a lower encoder that encodes the multi-phase output of the delay element. (Configuration 10) When the upper bits are represented by data Dcoarse of bit length b1, the data of the lower counter are represented by data Dfine_cycle of bit length b2, and the data of the lower encoder are represented by data Dfine_phase of bit length b3, The time digital data has a bit length (b1+b2+b3) and

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[0072] 10 pixels 20 TDC 20A Upper TDC 20B Lower TDC 23 Polyphase VCO 24 Lower Encoder 25 Lower Counter 26 Upper Counter 30 divider 40 Signal Generator Circuit 50 PLL circuit 53 Polyphase VCO 60 Correction circuit

Claims

1. A time-to-digital conversion device that outputs time digital data corresponding to a time from a first timing to a second timing, a first circuit including a high-order counter that starts counting clock signals in response to the first timing and that generates high-order bits of the time digital data; a second circuit including an oscillator circuit that starts operating in response to the second timing and that generates lower bits of the time digital data based on an output of the oscillator circuit; a control circuit that controls the phase of the output signal of the oscillation circuit based on the clock signal.

2. The control circuit a replica circuit of the oscillator circuit of the second circuit; a phase locked loop circuit that feeds back to the replica circuit a control voltage based on a comparison between the phase of the frequency-divided signal of the output signal of the replica circuit and the phase of the clock signal; 2. The time-to-digital conversion device according to claim 1, wherein the control circuit further supplies the control voltage to the oscillator circuit of the second circuit.

3. further comprising a plurality of the first circuits and a plurality of the second circuits; 3. The time-to-digital conversion device according to claim 2, wherein the control circuit supplies the control voltage to a plurality of the oscillator circuits of a plurality of the second circuits.

4. 2. The time-to-digital conversion device according to claim 1, wherein the upper counter and the oscillator circuit stop operating after a predetermined period has elapsed from the second timing.

5. 5. The time-to-digital conversion device according to claim 4, wherein the predetermined period is a timing synchronized with the clock signal.

6. 2. The time-to-digital conversion device according to claim 1, wherein the oscillator circuit is a voltage-controlled oscillator.

7. 2. The time-to-digital conversion device according to claim 1, wherein the oscillator circuit is a multiphase output voltage-controlled oscillator.

8. 8. The time-to-digital conversion device according to claim 7, wherein the second circuit further comprises a lower-order counter that counts the oscillation period of the oscillation circuit, and a lower-order encoder that encodes the multiphase output of the oscillation circuit.

9. When the upper bits are represented by data Dcoarse of bit length b1, the data of the lower counter are represented by data Dfine_cycle of bit length b2, and the data of the lower encoder are represented by data Dfine_phase of bit length b3, The time digital data has a bit length (b1+b2+b3), and [Equation 1] The time-to-digital conversion device according to claim 8, wherein the time-to-digital conversion device is represented by the following formula:

10. a correction circuit for correcting the time digital data; The correction circuit calculates, using data Dfine_cycle_tdclk of the lower counter and data Dfine_phase_tdclk of the lower encoder during one cycle of the clock signal, [Equation 2] 10. The time-to-digital converting device according to claim 9, wherein the time digital data is corrected according to the following formula:

11. The time-to-digital conversion device of claim 10, wherein the correction circuit calculates the data Dfine_cycle_tdclk of the lower counter and the data Dfine_phase_tdclk of the lower encoder by dividing the data Dfine_cycle of the lower counter and the data Dfine_phase of the lower encoder by N, respectively, for N periods (N is a positive integer) of the clock signal.

12. a switching circuit for switching an operation mode of the second circuit; The switching circuit In the first operation mode, the oscillation circuit is operated until a predetermined period has elapsed from the second timing; 11. The time-to-digital conversion device according to claim 10, wherein in the second operation mode, the oscillator circuit operates for N periods of the clock signal (N is a positive integer).

13. When the upper bits are represented by data Dcoarse of bit length b1 and the lower bits are represented by data Dfine of bit length b2, The time digital data has a bit length (b1+b2), and Dcoarse×2 ｂ２ - Dfine ・・・(Formula 3) 2. The time-to-digital conversion device according to claim 1, wherein the time-to-digital conversion device is represented by the following formula:

14. a correction circuit for correcting the time digital data; The correction circuit uses the lower-order bit data Dfine_tdclk during one cycle of the clock signal to Dcoarse x 2 ｂ２ -(Dfine / Dfine_tdclk)×2 ｂ２ ...(Formula 4) 14. The time-to-digital converting device according to claim 13, wherein the time digital data is corrected according to the following formula:

15. a light receiving unit that receives pulsed light that is emitted toward an object and reflected by the object; and a time-to-digital conversion device according to any one of claims 1 to 14, The time-to-digital conversion device defines the timing of emitting the pulsed light as the first timing and the timing of receiving the pulsed light as the second timing, and acquires distance information to the target object based on the time digital data corresponding to the time from the first timing to the second timing.

16. The plurality of light receiving units are arranged in a plurality of rows and a plurality of columns, the first circuit and the second circuit are provided for each row, 16. The distance measuring device according to claim 15, wherein the control circuit is shared by a plurality of the second circuits.

17. The plurality of light receiving units are arranged in a plurality of rows and a plurality of columns, the first circuit and the second circuit are provided for each of the light receiving units, 16. The distance measuring device according to claim 15, wherein the control circuit is shared by a plurality of the second circuits.

18. The plurality of light receiving units are arranged in a plurality of rows and a plurality of columns, the first circuit and the second circuit are provided for each sub-array including a plurality of the light receiving units, 16. The distance measuring device according to claim 15, wherein the control circuit is shared by a plurality of the second circuits.

19. A mobile object, a distance measuring device according to claim 15; a control means for controlling the moving object based on the distance information acquired by the distance measuring device; A moving object characterized by having:

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