Display device

Abstract

To provide a display device using an oxide semiconductor as a wiring material.SOLUTION: A display device includes: a display panel including a display section having a plurality of pixels; and a sensor element disposed on the back side of the display section. The display section has: a first region overlapping the sensor element in a planar view; and a second region other than the first region. Each of the plurality of pixels has a semiconductor device including a channel part and a conduction part consisting of an oxide semiconductor having a polycrystal structure. Each of the plurality of pixels in the first region is connected by a first signal line consisting of the same layer as the conduction part, and each of the plurality of pixels in the second region is connected by a second signal line consisting of a metal layer connected to the conduction part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices have become known that have an imaging element disposed on the rear side of a display panel and capture an image of a subject facing the display device. For example, a display device described in Patent Document 1 displays an image on the entire display area during normal operation, and performs imaging processing using a camera disposed on the rear side during imaging. When capturing an image, the camera captures light transmitted through the display panel to capture an image of the subject. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-89428 Summary of the Invention [Problem to be solved by the invention]

[0004] As described above, in conventional display devices, the transmittance of the display panel greatly affects the quality of the captured image because external light incident on the camera passes through the display panel. Therefore, in a display device that captures an image through a display panel, it is desirable to maximize the transmittance of the display panel. However, the display area of ​​the display panel is provided with a plurality of pixels for image display, and many elements and wirings that constitute each pixel are provided. In the above-mentioned conventional display devices, the transmittance is increased by devising the layer structure of the display panel, but there is a problem that the degree of freedom in circuit design is reduced.

[0005] An embodiment of the present invention has been made in view of the above problems, and has an object to provide a display device having an improved transmittance of a display panel with a simple structure. [Means for solving the problem]

[0006] A display device in one embodiment of the present invention includes a display panel including a display unit having a plurality of pixels, and a sensor element arranged on the rear side of the display unit, the display unit having a first region overlapping with the sensor element in a planar view and a second region other than the first region, each of the plurality of pixels having a semiconductor device including a channel portion and a conductive portion made of an oxide semiconductor having a polycrystalline structure, each of the plurality of pixels in the first region being connected by a first signal line made of the same layer as the conductive portion, and each of the plurality of pixels in the second region being connected by a second signal line made of a metal layer connected to the conductive portion. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view showing the appearance of a display device according to an embodiment of the present invention; [Diagram 2] 1 is a plan view showing a configuration of an organic EL panel in a display device according to one embodiment of the present invention. [Diagram 3] 1 is a diagram showing a configuration of a pixel circuit in a display device according to an embodiment of the present invention; [Figure 4] 1 is a diagram showing an outline of a system configuration of a display device according to an embodiment of the present invention; [Diagram 5] 1 is a plan view showing a pixel structure of pixels in an imaging region in a display device according to an embodiment of the present invention; [Figure 6] 2 is a cross-sectional view showing a pixel structure of a pixel in an imaging region in a display device according to one embodiment of the present invention. [Figure 7] 1 is a plan view showing a pixel structure of pixels in a non-imaging region in a display device according to an embodiment of the present invention. [Figure 8] 2 is a cross-sectional view showing a pixel structure of a pixel in a non-imaging region in a display device according to one embodiment of the present invention. [Figure 9] 1 is a plan view showing a pixel structure near the boundary between an imaging region and a non-imaging region in a display device according to an embodiment of the present invention. [Figure 10]1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 11] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 12A] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 12B] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 12C] 1A and 1B are schematic diagrams illustrating a bonding state of Poly-OS included in a conductive portion of an oxide semiconductor layer. [Figure 13] 1 is a band diagram illustrating a band structure of a conductive portion of an oxide semiconductor layer. [Figure 14] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 15] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Diagram 25] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 26] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 30] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Diagram 31] 1 is a plan view showing a pixel structure of pixels in an imaging region in a display device according to an embodiment of the present invention; [Diagram 32] 1 is a plan view showing the vicinity of an imaging area in a display device according to an embodiment of the present invention; [Diagram 33] 1 is a cross-sectional view showing the vicinity of an imaging area in a display device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In each embodiment described later, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". Thus, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the order of stacking in a structure in which multiple layers are stacked, and when it is expressed as "a pixel electrode above a transistor", it may be a positional relationship in which the transistor and the pixel electrode do not overlap in a planar view. On the other hand, when it is expressed as "a pixel electrode vertically above a transistor", it means a positional relationship in which the transistor and the pixel electrode overlap in a planar view.

[0010] In each embodiment described below, the "front side" refers to the side that constitutes the display screen of the display device, and the "rear side" refers to the side opposite to the front side.

[0011] In each embodiment described later, a plurality of elements formed by processing a certain film such as etching may be described as elements having different functions or roles. These elements are composed of the same layer structure and the same material, and are described as elements composed of the same layer.

[0012] In each embodiment described later, the term "display device" refers to a device that displays an image using an electro-optical layer. For example, the term display device refers to a device in which other optical members (e.g., a sensor element, a polarizing member, a backlight, or a touch panel) are attached to a display panel including an electro-optical layer. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. In each embodiment described later, an organic EL display device including an organic EL layer will be described as an example, but the present invention can also be applied to display devices including the other electro-optical layers described above.

[0013] In each embodiment described below, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] (First embodiment) [Display device configuration] A display device 100 according to an embodiment of the present invention will be described. In this embodiment, the display device 100 is a mobile terminal (e.g., a smartphone) equipped with an organic EL panel as a display panel. However, the display panel is not limited to this example, and may be a display panel including a liquid crystal layer, an inorganic EL layer, an electrochromic layer, or an electrophoretic layer.

[0015] FIG. 1 is a plan view showing the appearance of a display device 100 according to an embodiment of the present invention. As shown in FIG. 1, the display device 100 according to the present embodiment includes a housing 110, a display screen 120, and an imaging unit 130. The housing 110 houses a circuit group for driving an organic EL panel 200 described later and for controlling a mobile terminal. The display screen 120 is an interface for displaying images. The display screen 120 is the surface of the organic EL panel 200 housed in the housing 110. The surface of the organic EL panel 200 functions as the display screen 120 when viewed through a cover glass or the like. The imaging unit 130 includes an imaging element 132 described later and a control unit (not shown) for forming an image from incident light detected by the imaging element 132.

[0016] The imaging unit 130 is housed inside the housing 110 and disposed on the rear side of the organic EL panel 200. That is, when the user's viewpoint is used as a reference, the imaging unit 130 is disposed on the rear side of the display screen 120 and cannot be seen by the user. In this specification, an area of ​​the organic EL panel 200 in a plan view that overlaps with a portion where the imaging element 132 of the imaging unit 130 is disposed is referred to as an "imaging area 130A." In the display device 100 of this embodiment, the imaging area 130A has a different pixel structure from areas other than the imaging area 130A (i.e., the non-imaging area 130B). This point will be described later.

[0017] In this embodiment, during normal image display, an image is displayed on the entire display screen 120 including both the imaging region 130A and the non-imaging region 130B. On the other hand, when an image is captured, image display is stopped only in the imaging region 130A. Specifically, when an image is captured, light emission from pixels located in the imaging region 130A is stopped, and the imaging region 130A is made to be in a state where external light is transmitted through the imaging region 130A. For example, by stopping image display in the imaging region 130A over one or more frames during image display, external light can reach the imaging element 132 and image capture processing can be performed.

[0018] In this embodiment, an example in which the image sensor 132 (i.e., a camera) is disposed on the rear surface side of the organic EL panel 200 is shown, but the device disposed on the rear surface side is not limited to the image sensor, and may be a sensor element. For example, the sensor element may be a light sensor that detects external light.

[0019] Fig. 2 is a plan view showing a configuration of an organic EL panel 200 in a display device 100 according to one embodiment of the present invention. However, for ease of explanation, Fig. 2 shows only a circuit board 200A of the organic EL panel 200, and omits other elements (for example, optical members such as a polarizing plate).

[0020] 2, a display circuit 210, a scanning signal line driving circuit 220, and a terminal section 230 are provided on the front side of a circuit board 200A of the organic EL panel 200. Note that the imaging area 130A shown in FIG. 1 has a pixel structure different from that of the non-imaging area 130B, but the basic circuit arrangement is as shown in FIG.

[0021] The circuit board 200A is a substrate in which a plurality of semiconductor devices formed using oxide semiconductors are arranged on a light-transmitting support substrate. In this embodiment, an example in which thin film transistors are arranged as the semiconductor devices is shown, but the present invention is not limited to this example, and other semiconductor devices may be arranged as long as they function as switching elements. The circuit board 200A may also be called an active matrix substrate. A light-transmitting substrate may be used as the support substrate constituting the circuit board 200A. For example, it is preferable to use a glass substrate or a flexible resin substrate as the support substrate.

[0022] The display circuit 210 is a circuit for controlling a plurality of pixels 212 that display an image. Specifically, the display circuit 210 includes a plurality of scanning signal lines 214 extending in a first direction (D1 direction) and a plurality of video signal lines 216 extending in a second direction (D2 direction), and has pixels 212 including semiconductor devices such as thin film transistors corresponding to each of the intersections of the plurality of scanning signal lines 214 and the plurality of video signal lines 216. In this embodiment, each pixel 212 is a sub-pixel corresponding to any one of the colors R (red), G (green), and B (blue). Therefore, in reality, the display circuit 210 is configured to perform color display with one pixel (main pixel) including three pixels 212 corresponding to each of the colors RGB as a unit.

[0023] Here, a pixel circuit 300 for controlling the emission of each pixel 212 will be described with reference to Fig. 3. For convenience of explanation, a basic configuration using two semiconductor devices (thin film transistors) will be described as an example, but the configuration of the pixel circuit 300 is not limited to this example.

[0024] Fig. 3 is a diagram showing the configuration of a pixel circuit 300 in a display device 100 according to one embodiment of the present invention. As shown in Fig. 3, the pixel circuit 300 includes elements such as a drive transistor 301, a selection transistor 302, a storage capacitor 303, and a light-emitting element 304. The drive transistor 301 and the selection transistor 302 are formed of semiconductor devices such as thin film transistors.

[0025] The source of the driving transistor 301 is connected to an anode power line 305, and the drain of the driving transistor 301 is connected to one end (anode) of the light-emitting element 304. The other end (cathode) of the light-emitting element 304 is connected to a cathode power line 306. In this embodiment, a power supply voltage higher than that applied to the cathode power line 306 is applied to the anode power line 305.

[0026] The gate of the selection transistor 302 is connected to the scanning signal line 214, and the source of the selection transistor 302 is connected to the video signal line 216. The drain of the selection transistor 302 is connected to the gate of the drive transistor 301. Note that the source and drain of the selection transistor 302 may be switched depending on the relationship between the voltage applied to the video signal line 216 and the voltage stored in the storage capacitor 303.

[0027] The storage capacitor 303 is connected to the gate and drain of the drive transistor 301 and the drain of the selection transistor 302. A gradation signal that determines the light emission intensity of the light emitting element 304 is supplied to the video signal line 216. A scanning signal for selecting a pixel to which the gradation signal is to be written is supplied to the scanning signal line 214.

[0028] The pixel circuit 300 described above is disposed in each pixel 212 of the display device 100. In other words, it can be said that the display circuit 210 shown in FIG.

[0029] Returning to FIG. 2, the explanation is given. The scanning signal line driving circuit 220 is connected to the scanning signal line 214 and transmits a scanning signal to the scanning signal line 214. Specifically, the scanning signal is provided to the gate of a selection transistor included in the pixel 212 and is used for switching control of the selection transistor. The selection transistor is a semiconductor device for selecting whether or not a signal is input to the pixel 212. In this embodiment, like the multiple pixels 212, the scanning signal line driving circuit 220 is also formed using a thin film transistor, but it is also possible to substitute an IC chip or the like. In this embodiment, the circuit board 200A includes two scanning signal line driving circuits 220, but only one of them may be used.

[0030] Although not shown, the terminal unit 230 is an assembly of multiple terminals connected to the scanning signal line driving circuit 220 and the multiple video signal lines 216. The terminal unit 230 is disposed outside the display circuit 210. Video signals and control signals supplied from the outside are supplied to the display circuit 210 or the scanning signal line driving circuit 220 via the terminal unit 230.

[0031] The organic EL panel 200 is connected to a flexible printed circuit board 240 via a terminal portion 230. The flexible printed circuit board 240 is an interface board for connecting a circuit board 200A of the organic EL panel 200 to an external control circuit (not shown). In this embodiment, a display control circuit 250 is mounted on the flexible printed circuit board 240. The display control circuit 250 is a signal processing circuit that processes various control signals to be transmitted to the scanning signal line driving circuit 220 and video signals to be transmitted to the video signal lines 216. In this embodiment, the display control circuit 250 is mounted on the flexible printed circuit board 240 in the form of an IC chip.

[0032] The flexible printed circuit board 240 is a circuit board in which wiring is printed on a flexible substrate made of a resin material, and therefore can be bent. In this embodiment, the flexible printed circuit board 240 can be bent along the dashed dotted line 242 so that the flexible printed circuit board 240 and the back side of the circuit board 200A (the side on which the display circuit 210 and the like are not formed) overlap. This allows the organic EL panel 200 and the flexible printed circuit board 240 to be stored compactly inside the housing 110.

[0033] 4 is a diagram showing an outline of a system configuration of the display device 100 according to one embodiment of the present invention. As described above, various control signals transmitted to the scanning signal line driving circuit 220 are processed by the display control circuit 250. The display control circuit 250 may generate control signals such as a start pulse, or may perform predetermined signal processing on control signals acquired from an external system control circuit 270. The display control circuit 250 may also perform predetermined signal processing on video signals acquired from the system control circuit 270.

[0034] The system control circuit 270 controls the display control circuit 250 and the imaging unit 130 in an integrated manner. In this embodiment, the system control circuit 270 synchronizes the operation of the imaging unit 130 with the operation of the display circuit 210. As a result, for example, when the imaging unit 130 is not used, an image can be displayed on the entire display screen including the imaging region 130A and the non-imaging region 130B, and when the imaging unit 130 is used, image display can be stopped only in the imaging region 130A. Specifically, when the imaging unit 130 is used, the display circuit 210 can be controlled so that the pixel 212 located in the imaging region 130A stops emitting light and external light passes through the imaging region 130A.

[0035] Next, a description will be given of the difference in pixel structure between the imaging region 130A and the non-imaging region 130B in the display device 100. First, the pixel structure of the imaging region 130A will be described.

[0036] Fig. 5 is a plan view showing the pixel structure of the pixel 212A in the imaging region 130A in the display device 100 according to one embodiment of the present invention. Fig. 6 is a cross-sectional view showing the pixel structure of the pixel 212A in the imaging region 130A in the display device 100 according to one embodiment of the present invention. Specifically, Fig. 6 corresponds to a cross-sectional view showing a cross section of the pixel structure of the pixel 212A shown in Fig. 5 taken along line segment A1-A2. However, in Figs. 5 and 6, the description will be focused on the structure of the selection transistor 302 described in Fig. 3, and therefore the driving transistor 301, the storage capacitor 303, and the anode power line 305 are omitted.

[0037] 5, the pixel 212A includes a light emitting element 304 arranged in an area surrounded by a scanning signal line 214 extending in a first direction (direction D1) and a video signal line 216A extending in a second direction (direction D2). A video signal transmitted by the video signal line 216A is input to the pixel 212A via a selection transistor 302. Although not shown, a terminal electrode 407 of the selection transistor 302 is connected to the gate of the drive transistor 301 (see FIG. 3).

[0038] In the imaging region 130A, the conductive portion 403b that functions as the source region of the selection transistor 302 is formed in the same layer as the video signal line 216A. That is, as shown in Fig. 5, in the selection transistor 302 that constitutes the pixel 212A, the conductive portion 403b and the video signal line 216A are integrated together. In other words, each of the multiple pixels 212A in the imaging region 130A is connected by the video signal line 216A that is formed in the same layer as the conductive portion 403b of the selection transistor 302.

[0039] As shown in Fig. 5, in the imaging region 130A, the scanning signal line 214 includes a plurality of wirings 214a and a connection wiring 214b that connects the wirings 214a. In Fig. 5, each wiring 214a is provided corresponding to each pixel and is arranged so as not to straddle the video signal line 216A. The connection wiring 214b is electrically connected to each wiring 214a via a contact portion 214c, and connects each wiring 214a to each other across the video signal line 216A. In other words, the connection wiring 214b functions as a bridge wiring that connects the wirings 214a that are separated from each other with the video signal line 216 between them.

[0040] 5, in the region surrounded by the frame line CP, the connection wiring 214b is omitted in order to show the positional relationship between the wiring 214a and the video signal line 216A. As shown in the region surrounded by the frame line CP, the wirings 214a are spaced apart from each other so as to face each other with the video signal line 216A therebetween. The connection wiring 214b electrically connects the wirings 214a spaced apart in this manner.

[0041] As described later, the conductive portion 403b is a portion of the oxide semiconductor layer that is made conductive in the process of adding impurities. Therefore, the oxide semiconductor layer used as the video signal line 216A needs to be doped with impurities as a whole. However, if the wiring 214a overlaps with the portion of the oxide semiconductor layer used as the video signal line 216A, the portion overlapping with the wiring 214a is not doped with impurities and has a higher resistance than the portion doped with impurities. Therefore, the oxide semiconductor layer cannot function as the video signal line 216A.

[0042] For the above reasons, in this embodiment, the wirings 214a are arranged so as not to overlap the video signal lines 216A, and impurities are added to the oxide semiconductor layer in a state where the oxide semiconductor layer functioning as the video signal lines 216A is exposed. This makes it possible to impart conductivity to the entire oxide semiconductor layer functioning as the video signal lines 216A. In this embodiment, after forming the oxide semiconductor layer functioning as the video signal lines 216A (conductive portions 403b), the separated wirings 214a are electrically connected to each other by the connection wirings 214b to form the scanning signal lines 214.

[0043] 6, the selection transistor 302 is provided on a substrate 401. The substrate 401 is a light-transmitting substrate, and may be, for example, a glass substrate or a resin substrate. The base layer 402 is composed of a silicon oxide layer, a silicon nitride layer, or a stacked film of a silicon oxide layer and a silicon nitride layer. The base layer 402 serves to prevent the intrusion of impurities and the like from the substrate 401.

[0044] The selection transistor 302 of this embodiment includes an oxide semiconductor layer 403 made of an oxide semiconductor having a polycrystalline structure. As the oxide semiconductor, for example, a metal oxide containing two or more metals including indium (In) is used. In general, an oxide semiconductor has a light-transmitting property and is transparent to visible light.

[0045] The oxide semiconductor layer 403 includes a channel portion 403a and a conductive portion 403b. The channel portion 403a and the conductive portion 403b function as a source region or a drain region of the selection transistor 302. As shown in FIGS. 5 and 6, in the imaging region 130A, one of the conductive portions 403b is extended to function as a video signal line 216A. For convenience of explanation, in FIGS. 5 and 6, the conductive portion 403b connected to the video signal line 216A may be referred to as a source region, and the conductive portion 403b connected to the terminal electrode 407 may be referred to as a drain region.

[0046] The oxide semiconductor layer 403 is covered with a gate insulating layer 404 made of a silicon oxide layer. A gate electrode 405 made of a metal layer is provided directly above a channel portion 403a of the oxide semiconductor layer 403 via the gate insulating layer 404. The gate electrode 405 corresponds to a portion of the scanning signal line 214 that overlaps with the channel portion 403a. Therefore, the scanning signal line 214 is also made of a metal layer.

[0047] An interlayer insulating layer 406 made of a silicon oxide layer, a silicon nitride layer, or a laminated film thereof is provided on the gate electrode 405 and the gate insulating layer 404. A contact hole 406a is provided in the interlayer insulating layer 406, and a terminal electrode 407 and a conductive portion 403b (drain region) are connected via the contact hole 406a.

[0048] A planarization layer 410 made of a resin material is provided on the selection transistor 302. A light-emitting element 304 is provided on the planarization layer 410. Although not shown in Fig. 6, the light-emitting element 304 is connected to the driving transistor 301 described in Fig. 3. Specifically, a pixel electrode 411 functioning as an anode electrode of the light-emitting element 304 is connected to the drain of the driving transistor 301.

[0049] The light emitting element 304 includes a pixel electrode 411 having a structure in which a transparent conductive film such as ITO and a metal layer such as silver are laminated. The end of the pixel electrode 411 is covered with a resin layer 412 called a bank or rib. An opening 412a provided in the resin layer 412 exposes a part of the surface of the pixel electrode 411. The outline of the pixel electrode 411 exposed by the opening 412a defines the light emitting region of the light emitting element 304. A light emitting layer 413 and a common electrode 414 are provided inside the opening 412a. The common electrode 414 functions as a cathode electrode of the light emitting element 304 and is disposed across a plurality of pixels 212A. As described in FIG. 3, the common electrode 414 is connected to the cathode power line 306 (not shown). On the other hand, the pixel electrode 411 and the light emitting layer 413 are provided individually for each pixel 212A. The light emitting layer 413 is made of a different material depending on the display color of the pixel.

[0050] As described above, in this embodiment, for the pixel 212A arranged in the imaging region 130A, the source region (conductive portion 403b) of the selection transistor 302 and the video signal line 216A are integrally formed. That is, the conductive portion 403b and the video signal line 216 are formed in the same layer, specifically, made of an oxide semiconductor that is given conductivity. The selection transistor 302 of this embodiment can be used as wiring because the resistance of the conductive portion 403b is significantly lower than that of the conventional one. Specifically, the sheet resistance of the conductive portion 403b is 1000 Ω / sq. or less (preferably 500 Ω / sq. or less), so that it can be used as the video signal line 216.

[0051] The display device 100 of this embodiment uses the video signal line 216A made of an oxide semiconductor in the imaging region 130A, so that the video signal line does not block visible light. In addition, the video signal line 216A is formed simultaneously with the formation of the source region and the drain region of the selection transistor 302, so that the video signal line 216A can be made translucent with a simple structure. Thus, according to this embodiment, the transmittance of the display panel (organic EL panel 200) can be improved with a simple structure.

[0052] The pixel structure of the imaging region 130A described above is realized by reducing the resistance of the oxide semiconductor to a level where it can be used as wiring. Specifically, it is realized by reducing the resistance of the conductive part 403b of the selection transistor 302, which is a semiconductor device using an oxide semiconductor. The configuration and manufacturing method of the semiconductor device (thin film transistor) used in this embodiment will be described later.

[0053] Note that wiring using the conductive portion 403b made of an oxide semiconductor has a relatively high resistance compared to wiring made of a metal material. However, in this embodiment, in a part of the region of the organic EL panel 200 (specifically, the imaging region 130A), the video signal line 216A and the conductive portion 403b of the selection transistor 302 are configured in the same layer. In this way, when the conductive portion 403b is used as wiring limited to a specific region, it can function sufficiently as wiring even if the sheet resistance is higher than that of a metal layer.

[0054] Next, the pixel structure of the non-imaging region 130B will be described.

[0055] Fig. 7 is a plan view showing the pixel structure of pixel 212B in non-imaging region 130B in display device 100 according to one embodiment of the present invention. Fig. 8 is a cross-sectional view showing the pixel structure of pixel 212B in non-imaging region 130B in display device 100 according to one embodiment of the present invention. Specifically, Fig. 8 corresponds to a cross-sectional view showing a cross section of pixel structure of pixel 212B shown in Fig. 7 taken along line segment B1-B2. However, in Figs. 7 and 8, the description will be focused on the structure of selection transistor 302 described in Fig. 3, and therefore illustration of drive transistor 301, storage capacitor 303, and anode power line 305 will be omitted.

[0056] As shown in Fig. 7, the pixel structure of the non-imaging region 130B is the same as the pixel structure of the imaging region 130A shown in Fig. 5. That is, the pixel 212B includes a light emitting element 304 arranged in an area surrounded by a scanning signal line 214 extending in a first direction (D1 direction) and a video signal line 216B extending in a second direction (D2 direction). A video signal transmitted by the video signal line 216B is input to the pixel 212B via a selection transistor 302. A terminal electrode 407 of the selection transistor 302 is connected to the gate of the drive transistor 301, although not shown.

[0057] 5 is that in the non-imaging region 130B, the conductive portion 403b functioning as the source region of the selection transistor 302 is connected to the video signal line 216B made of a metal material. That is, as shown in FIG. 7, each of the multiple pixels 212B in the non-imaging region 130B is connected by the video signal line 216B made of a metal layer connected to the conductive portion 403b of the selection transistor 302.

[0058] 8, a video signal line 216B is connected to a conductive portion 403b functioning as a source region of the selection transistor 302 through a contact hole 406b provided in an interlayer insulating layer 406. The video signal line 216B is formed in the same layer as a terminal electrode 407 connected to the drain region of the selection transistor 302. For example, the video signal line 216B can be formed in a laminated structure of a titanium layer / aluminum layer / titanium layer.

[0059] 1, the non-imaging region 130B has a larger area than the imaging region 130A. Therefore, the video signal lines 216B in the non-imaging region 130B are relatively longer than the video signal lines 216A in the imaging region 130A. Therefore, in order to prevent signal delay, it is desirable to form the video signal lines 216B in the non-imaging region 130B using a metal material.

[0060] FIG. 9 is a plan view showing a pixel structure near the boundary between the imaging region 130A and the non-imaging region 130B in the display device 100 according to an embodiment of the present invention. As shown in FIG. 9, near the boundary between the imaging region 130A and the non-imaging region 130B, the video signal line 216A and the video signal line 216B are electrically connected. The connection structure between the video signal line 216A and the video signal line 216B is the same as the connection structure between the conductive portion 403b functioning as the source region and the video signal line 216B described in FIG. 8. The configuration of the scanning signal line 214 is the same as the structure shown in FIG. 5. Specifically, the multiple wirings 214a are connected to each other by the connection wiring 214b arranged so as to straddle the video signal line 216A, and function as the scanning signal line 214 as a whole. The connection wiring 214b may be formed in the same layer as the video signal line 216B.

[0061] In the display device 100 of this embodiment, the video signal line 216 provided on the circuit board 200A of the organic EL panel 200 includes a video signal line 216A made of an oxide semiconductor material and a video signal line 216B made of a metal material. In other words, the display panel in the display device 100 of this embodiment includes an area (imaging area 130A) including the video signal line 216A made of an oxide semiconductor material and an area (non-imaging area 130B) including the video signal line 216B made of a metal material.

[0062] In this embodiment, in the imaging region 130A, an oxide semiconductor is used as a conductive layer constituting the semiconductor device (the driving transistor 301 and the selection transistor 302), the video signal line 216A, the storage capacitor 303, and the light emitting element 304. Therefore, the transmittance of the organic EL panel 200 can be improved with a simple structure, and external light can be sufficiently taken in when the imaging element 132 performs imaging processing. On the other hand, in the display device 100 of this embodiment, wiring made of a metal material is used as the video signal line 216B in the non-imaging region 130B, so that the effect of signal delay can be suppressed. As a result, the display device 100 of this embodiment realizes improvement in imaging performance without incurring signal delay by locally arranging the video signal line 216A made of an oxide semiconductor in the imaging region 130A that requires a relatively high transmittance.

[0063] In the present embodiment, an example has been shown in which wiring made of a metal material is used as the video signal line 216B in the non-imaging region 130B. However, if the resistance of the conductive portion 403b of the semiconductor layer is low enough to be practical, it is also possible to use wiring made of an oxide semiconductor as the video signal line 216A in the imaging region 130A.

[0064] As described above, in this embodiment, this is achieved by sufficiently reducing the resistance of the conductive portion 403b made of an oxide semiconductor. Therefore, the configuration and manufacturing method of the semiconductor device used in this embodiment will be described below.

[0065] [Configuration of semiconductor device 10] The configuration of the semiconductor device 10 used in the display device 100 of the present embodiment will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a cross-sectional view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. Fig. 11 is a plan view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. The cross section taken along the dashed dotted line shown in Fig. 11 corresponds to the cross-sectional view shown in Fig. 10.

[0066] 10, the semiconductor device 10 is provided above a substrate 500. The semiconductor device 10 includes an undercoat film 520, an oxide semiconductor layer 544, a gate insulating layer 550, a gate electrode 564, an insulating layer 570, an insulating layer 580, a source electrode 601, and a drain electrode 603. However, as described above, the source electrode 601 is omitted from the selection transistor 302 disposed in the imaging region 130A (see FIG. 6).

[0067] The base film 520 is provided over the substrate 500. The oxide semiconductor layer 544 is provided over the base film 520. The oxide semiconductor layer 544 is in contact with the base film 520. Of the main surfaces of the oxide semiconductor layer 544, a surface in contact with the base film 520 is referred to as a lower surface. The base film 520 functions as a barrier film that blocks impurities diffusing from the substrate 500 toward the oxide semiconductor layer 544.

[0068] The oxide semiconductor layer 544 has light transmitting properties. The oxide semiconductor layer 544 is divided into a source region 544S, a drain region 544D, and a channel region 544CH. The channel region 544CH is a region of the oxide semiconductor layer 544 vertically below the gate electrode 564. The source region 544S is a region of the oxide semiconductor layer 544 that does not overlap with the gate electrode 564 and is closer to the source electrode 601 than the channel region 544CH. The drain region 544D is a region of the oxide semiconductor layer 544 that does not overlap with the gate electrode 564 and is closer to the drain electrode 603 than the channel region 544CH. The channel region 544CH corresponds to the channel portion 403a shown in FIG. 6 and FIG. 8, and the source region 544S and the drain region 544D correspond to the conductive portion 403b shown in FIG. 6 and FIG. 8, respectively.

[0069] The gate electrode 564 is made of a metal layer and faces the oxide semiconductor layer 544. The gate insulating layer 550 is provided between the oxide semiconductor layer 544 and the gate electrode 564. The gate insulating layer 550 is in contact with the oxide semiconductor layer 544. Of the main surfaces of the oxide semiconductor layer 544, the surface in contact with the gate insulating layer 550 is referred to as the upper surface. The surface between the upper surface and the lower surface is referred to as the side surface. The insulating layer 570 and the insulating layer 580 are provided on the gate insulating layer 550 and the gate electrode 564, respectively. The insulating layer 570 and the insulating layer 580 are provided with contact holes 571 and 573 that reach the oxide semiconductor layer 544. The source electrode 601 is in contact with the source region 544S through the contact hole 571. The drain electrode 603 is in contact with the drain region 544D through the contact hole 573.

[0070] The oxide semiconductor layer 544 has a polycrystalline structure including a plurality of crystal grains. Although details will be described later, the oxide semiconductor layer 544 having a polycrystalline structure can be formed by using a polycrystalline oxide semiconductor (Poly-OS) technique. In the following description, an oxide semiconductor having a polycrystalline structure itself may be referred to as Poly-OS.

[0071] In this embodiment, the oxide semiconductor layer 544 contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more. Metal elements other than indium include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides. However, the present invention is not limited to this example, and the oxide semiconductor layer 544 may contain metal elements other than the above.

[0072] The source region 544S and the drain region 544D may contain elements other than the above metal elements. As will be described in detail later, the source region 544S and the drain region 544D have a lower resistivity than the channel region 544CH. Such a decrease in resistivity is achieved by adding an element such as argon (Ar), phosphorus (P), or boron (B) (hereinafter referred to as an "impurity element") to the oxide semiconductor layer 544.

[0073] The concentration of impurity elements contained in the source region 544S and the drain region 544D is 1×10 18 cm -3 More than 1×10 21 cm -3 The source region 544S and the drain region 544D are preferably 1×10 18 cm -3 More than 1×10 21 cm -3 When the impurity element is contained in the source region 544S and the drain region 544D, it is presumed that the impurity element is intentionally added by ion implantation or ion doping. 18 cm -3 Impurity elements other than argon (Ar), phosphorus (P), or boron (B) may be contained in the channel region 544CH at a concentration of less than 1×10. Note that if an impurity element is contained in the channel region 544CH, it will affect the characteristics of the semiconductor device 10. Therefore, the concentration of the impurity element contained in the channel region 544CH is set to 1×10 18 cm -3 Less than (more preferably 1 × 10 16 cm -3 It is preferable that

[0074] The gate electrode 564 functions as a top gate of the semiconductor device 10. The gate insulating layer 550 functions as a gate insulating layer for the top gate, and has a function of releasing oxygen by heat treatment in the manufacturing process. The insulating layer 570 and the insulating layer 580 insulate the gate electrode 564 from the source electrode 601 and the gate electrode 564 from the drain electrode 603, respectively. This makes it possible to reduce parasitic capacitances occurring between the gate electrode 564 and the source electrode 601 and between the gate electrode 564 and the drain electrode 603.

[0075] 11, the gate wiring 565 extends in a first direction (D1 direction). A part of the gate wiring 565 branches out toward a second direction (D2 direction) and overlaps with the oxide semiconductor layer 544. The part of the gate wiring 565 that overlaps with the oxide semiconductor layer 544 functions as a gate electrode 564. The length of a region where the oxide semiconductor layer 544 and the gate electrode 564 overlap (i.e., a channel region 544CH) in the first direction (D1 direction) is the channel length (L), and the length in the second direction (D2 direction) is the channel width (W).

[0076] [Crystal structure of oxide semiconductor layer] The oxide semiconductor layer 544 includes Poly-OS. The crystal grains included in the Poly-OS observed from the upper surface of the oxide semiconductor layer 544 (or in the film thickness direction of the oxide semiconductor layer 544) have a crystal grain size of 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grains can be obtained by, for example, cross-sectional SEM observation, cross-sectional TEM observation, or an electron backscattered diffraction (EBSD) method.

[0077] In the Poly-OS, a plurality of crystal grains may have one type of crystal structure or a plurality of types of crystal structures. The crystal structure of the Poly-OS can be identified by electron beam diffraction, XRD, or the like. That is, the crystal structures of the oxide semiconductor layer 544 and the oxide conductive layer 164 can be identified by electron beam diffraction, XRD, or the like.

[0078] The oxide semiconductor layer 544 preferably has a cubic crystal structure. A cubic crystal structure has high symmetry, and even if oxygen defects are generated in the oxide semiconductor layer 544, structural relaxation is unlikely to occur and the crystal structure is stable. As described above, the oxide semiconductor layer 544 contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more. By increasing the ratio of indium element, the crystal structure of each of the multiple crystal grains can be controlled, and the oxide semiconductor layer 544 having a cubic crystal structure can be formed.

[0079] As shown in FIG. 10, the oxide semiconductor layer 544 includes a channel portion 403a (see FIGS. 6 and 8) corresponding to the channel region 544CH, and a conductive portion 403b (see FIGS. 6 and 8) corresponding to the source region 544S and the drain region 544D. In the oxide semiconductor layer 544, the channel portion 403a has a first crystal structure, and the conductive portion 403b has a second crystal structure. The conductive portion 403b has a higher electrical conductivity than the channel portion 403a, but the second crystal structure is the same as the first crystal structure. Here, the two crystal structures being the same means that the crystal systems are the same. For example, when the crystal structure of the oxide semiconductor layer 544 is a cubic crystal, the first crystal structure of the channel portion 403a and the crystal structure of the conductive portion 403b are both cubic crystals and are the same. The first crystal structure and the second crystal structure can be identified using, for example, a microelectron beam diffraction method or the like.

[0080] In addition, in a given crystal orientation, the d-spacing value of the first crystal structure and the d-spacing value of the second crystal structure are substantially the same. Here, "substantially the same" refers to one d-spacing value being 0.95 to 1.05 times the other d-spacing value. Alternatively, this refers to the two diffraction patterns being almost identical in a microelectron beam diffraction method.

[0081] There may be no crystal grain boundary between the channel portion 403a and the conductive portion 403b. Also, the channel portion 403a and the conductive portion 403b may be included in one crystal grain. In other words, the change from the channel portion 403a to the conductive portion 403b may be a continuous change in crystal structure.

[0082] 12A to 12C are schematic diagrams illustrating a bonding state of Poly-OS included in the conductive portion 403b of the oxide semiconductor layer 544. 12A to 12C show Poly-OS including indium atoms (In atoms) and metal atoms (M atoms) different from In atoms.

[0083] In the Poly-OS shown in FIG. 12A, each of the In atom and the metal atom M is bonded to an oxygen atom (O atom). In the crystal structure of the Poly-OS shown in FIG. 12A, in the conductive portion 403b, in order to increase the electrical conductivity compared to the channel portion 403a, the bond between the In atom and the O atom (or the metal atom M and the O atom) is cut, and oxygen defects resulting from the removal of the O atom are generated (see FIG. 12B). Since the Poly-OS contains crystal grains with a large crystal grain size, the long-range order is easily maintained. Therefore, even if oxygen defects are generated, structural relaxation is unlikely to occur, and the positions of the In atom and the metal atom M are hardly changed. In the state shown in FIG. 12B, if hydrogen is present, the dangling bond of the In atom in the oxygen defect and the dangling bond of the metal atom M are bonded to the hydrogen atom (H atom) and stabilized (see FIG. 12C). Since the H atom in the oxygen defect functions as a donor, the carrier concentration of the conductive portion 403b increases.

[0084] 12C, in Poly-OS, even if an H atom is bonded in an oxygen defect, the positions of the In atom and the metal atom M hardly change. Therefore, the second crystal structure of the conductive portion 403b does not change from the crystal structure of Poly-OS without oxygen defects. That is, the second crystal structure of the conductive portion 403b is the same as the first crystal structure of the channel portion 403a.

[0085] FIG. 13 is a band diagram illustrating the band structure of the conductive portion 403b of the oxide semiconductor layer 544. In FIG.

[0086] As shown in FIG. 13, the Poly-OS of the conductive portion 403b has a band gap E g The energy level includes a first energy level 1010 and a second energy level 1020. In addition, the energy level E C The first energy level 1010 includes a tail level 1030 adjacent to each of the first and second energy levels. g The first energy level 1010 is a deep trap level present in the conduction band and is due to oxygen vacancies. The second energy level 1020 is a donor level present near the bottom of the conduction band and is due to hydrogen atoms bonded in the oxygen vacancies. The tail level 1030 is due to a disorder of the long-range order.

[0087] Although the Poly-OS in the conductive portion 403b contains oxygen defects, it has a crystalline structure and maintains long-range order. In addition, in the Poly-OS in the conductive portion 403b, hydrogen atoms can be bonded within the oxygen defects without causing structural disorder. Therefore, the DOS of the second energy level 1020 can be increased while suppressing the DOS of the tail level 1030. Therefore, the DOS of the second energy level 1020 is larger than the DOS of the tail level 1030 near the bottom of the conduction band, and the DOS of the second energy level 1020 is larger than the DOS of the energy level E C That is, the Fermi level E Fis the energy level E at the bottom of the conduction band C , and the Poly-OS in the conductive portion 403b has metallic properties.

[0088] As described above, the Poly-OS in the conductive portion 403b has metallic properties, unlike conventional oxide semiconductors. Therefore, the conductive portion 403b can have a sufficiently low resistance by generating oxygen defects. The sheet resistance of the conductive portion 403b is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq.

[0089] In this manner, in this embodiment, since it is possible to sufficiently reduce the resistance of the source region 544S and the drain region 544D (i.e., the conductive portion 403b) of the oxide semiconductor layer 544, the conductive portion 403b can be used as wiring. The pixel structure of the imaging region 130A described with reference to Figs. 5 and 6 utilizes the features of the oxide semiconductor layer 544.

[0090] In this embodiment, a light-shielding layer may be provided between the substrate 500 and the oxide semiconductor layer 544. By providing the light-shielding layer in a region overlapping with the channel region 544CH, it is possible to suppress a change in characteristics of the semiconductor device 10 caused by irradiation of light to the channel region 544CH.

[0091] In this embodiment, a top-gate transistor in which the gate electrode 564 is provided on the oxide semiconductor layer 544 is exemplified as the semiconductor device 10, but the present invention is not limited to this configuration. For example, the semiconductor device 10 may be a bottom-gate transistor in which the gate electrode 564 is provided below the oxide semiconductor layer 544, or a dual-gate transistor in which the gate electrode 564 is provided both above and below the oxide semiconductor layer 544.

[0092] [Method of Manufacturing Semiconductor Device 10] A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 14 to Fig. 23. Fig. 14 is a sequence diagram showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figs. 15 to 23 are cross-sectional views showing the method for manufacturing the semiconductor device 10 according to one embodiment of the present invention.

[0093] First, as shown in FIGS. 14 and 15, an undercoat film 520 is formed on a substrate 500 (step S1001).

[0094] A rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, is used as the substrate 500. When the substrate 500 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used as the substrate 500. When a substrate containing a resin is used as the substrate 500, an impurity element may be introduced into the resin in order to improve the heat resistance of the substrate 500.

[0095] The base film 520 is formed by a chemical vapor deposition (CVD) method or a sputtering method. A general insulating material is used as the base film 520. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), and aluminum nitride (AlN x ) and other inorganic insulating materials are used.

[0096] The above SiO x N y and AlO x N yis a silicon and aluminum compound that contains a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0097] The base film 520 is formed in a single layer structure or a laminated structure. When the base film 520 has a laminated structure, it is preferable that the insulating material containing nitrogen and the insulating material containing oxygen are formed in this order from the substrate 500. By using the insulating material containing nitrogen, for example, it is possible to block impurities diffusing from the substrate 500 side toward the oxide semiconductor layer 544. In addition, by using the insulating material containing oxygen, it is possible to release oxygen by heat treatment. The temperature of the heat treatment at which the insulating material containing oxygen releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the insulating material containing oxygen releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 500. In this embodiment, for example, silicon nitride is used as the insulating material containing nitrogen. For example, silicon oxide is used as the insulating material containing oxygen.

[0098] 14 and 16, an oxide semiconductor layer 540 is formed on the base film 520 (step S1002). This step may also be referred to as forming the oxide semiconductor layer 540 on the substrate 500.

[0099] The oxide semiconductor layer 540 is formed by sputtering or atomic layer deposition (ALD). The oxide semiconductor layer 540 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm.

[0100] A metal oxide having semiconductor properties can be used as the oxide semiconductor layer 540. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 540. The ratio of indium in the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or lanthanoids is used as the oxide semiconductor layer 540. Elements other than the above may be used as the oxide semiconductor layer 540. In this embodiment, a metal oxide (IGO-based oxide semiconductor) containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 540.

[0101] When the oxide semiconductor layer 540 is crystallized by OS annealing (step S1004) described later, the oxide semiconductor layer 540 after deposition and before OS annealing is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). In other words, the oxide semiconductor layer 540 is preferably formed under conditions that prevent the oxide semiconductor layer 540 immediately after deposition from crystallizing as much as possible. For example, when the oxide semiconductor layer 540 is formed by a sputtering method, the oxide semiconductor layer 540 is formed while controlling the temperature of the object to be deposited (the substrate 500 and a structure formed thereon).

[0102] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object increases with the film formation process. If the temperature of the target object increases during the film formation process, the oxide semiconductor layer 540 contains microcrystals immediately after the film formation, and crystallization by the subsequent OS annealing is inhibited. In order to control the temperature of the target object as described above, for example, the target object can be cooled while the film is formed. For example, the target object can be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by forming the oxide semiconductor layer 540 while cooling the target object, the oxide semiconductor layer 540 having a small amount of crystalline components immediately after the film formation can be formed.

[0103] Next, as shown in FIGS. 14 and 17, a pattern of the oxide semiconductor layer 540 is formed by photolithography (step S1003). Although not shown, a resist mask is formed on the oxide semiconductor layer 540, and the oxide semiconductor layer 540 is etched using the resist mask. Either wet etching or dry etching may be used when etching the oxide semiconductor layer 540. In the case of wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0104] The oxide semiconductor layer 540 is preferably patterned before the OS annealing performed in step S1004. If the oxide semiconductor layer 540 is crystallized by the OS annealing, it tends to be difficult to etch. Even if the oxide semiconductor layer 540 is damaged by etching, the damage can be repaired by the OS annealing.

[0105] After the oxide semiconductor layer 540 is patterned, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 540 (step S1004). In the OS annealing, the oxide semiconductor layer 540 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. By performing the OS annealing, the oxide semiconductor layer 540 is crystallized, and an oxide semiconductor layer 544 having a polycrystalline structure is formed.

[0106] Next, as shown in FIGS. 14 and 18, a gate insulating layer 550 is formed on the oxide semiconductor layer 544 (Step S1005).

[0107] The description of the base film 520 may be referred to for the method for forming and the insulating material of the gate insulating layer 550. In this embodiment, the thickness of the gate insulating layer 550 is, for example, 50 nm or more and 150 nm or less, but is not limited to this example.

[0108] It is preferable to use an insulating material containing oxygen for the gate insulating layer 550. It is also preferable to use an insulating layer with few defects for the gate insulating layer 550. For example, when the oxygen composition ratio in the gate insulating layer 550 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 550 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layer 550 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. For example, when silicon oxide (SiO x ), the composition ratio of oxygen in the silicon oxide used as the gate insulating layer 550 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the insulating layer 580. For example, the gate insulating layer 550 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0109] In order to form an insulating layer with few defects as the gate insulating layer 550, the gate insulating layer 550 may be formed at a film formation temperature of 350° C. or higher. In addition, after forming the gate insulating layer 550, a process of implanting oxygen into a part of the gate insulating layer 550 may be performed. In this embodiment, in order to form an insulating layer with few defects as the gate insulating layer 550, a silicon oxide layer is formed at a film formation temperature of 350° C. or higher.

[0110] Next, as shown in FIGS. 14 and 18, a metal oxide layer 590 containing aluminum as a main component is formed on the gate insulating layer 550 (step S1006).

[0111] The metal oxide layer 590 is formed by a sputtering method. By forming the metal oxide layer 590, oxygen is implanted into the gate insulating layer 550. The metal oxide layer mainly composed of aluminum is, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used. "Aluminum-based metal oxide layer" means that the ratio of aluminum contained in metal oxide layer 590 is 1% or more of the entire metal oxide layer 590. The ratio of aluminum contained in metal oxide layer 590 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 590. The above ratio may be a mass ratio or a weight ratio.

[0112] The thickness of the metal oxide layer 590 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 590. Aluminum oxide has high barrier properties against gas. In this embodiment, aluminum oxide used as the metal oxide layer 590 suppresses outward diffusion of oxygen implanted into the gate insulating layer 550 during deposition of the metal oxide layer 590.

[0113] For example, when the metal oxide layer 590 is formed by a sputtering method, the process gas used in the sputtering remains in the film of the metal oxide layer 590. For example, when Ar is used as the process gas for the sputtering, Ar may remain in the film of the metal oxide layer 590. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 590.

[0114] A gate insulating layer 550 is formed on the oxide semiconductor layer 544, and a metal oxide layer 590 is formed on the gate insulating layer 550. In this state, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 544 (step S1007).

[0115] During the process from when the oxide semiconductor layer 544 is formed until when the gate insulating layer 550 is formed on the oxide semiconductor layer 544, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 544. By the above-mentioned oxidation annealing, oxygen released from the base film 520 is supplied to the upper surface and side surfaces of the oxide semiconductor layer 544, and the oxygen defects inside the oxide semiconductor layer 544 are repaired.

[0116] In the above-mentioned oxidation annealing, oxygen implanted into the gate insulating layer 550 is blocked by the metal oxide layer 590, and thus is prevented from being released into the atmosphere. Therefore, by the oxidation annealing performed in step S1007, oxygen is efficiently supplied to the oxide semiconductor layer 544, and oxygen defects in the oxide semiconductor layer 544 are repaired.

[0117] Next, as shown in FIG. 14 and FIG. 19, after the oxidation annealing, the metal oxide layer 590 is etched (removed) (step S1008). Either wet etching or dry etching may be used for etching the metal oxide layer 590. As an etchant for the wet etching, for example, diluted hydrofluoric acid (DHF) is used. By this etching, the metal oxide layer 590 formed on the entire surface of the gate insulating layer 550 is removed. In other words, the metal oxide layer 590 is removed without using a mask. In further other words, by the etching performed in step S1008, all of the metal oxide layer 590 in the region overlapping with the oxide semiconductor layer 544 formed in a certain pattern is removed at least in a plan view.

[0118] 14 and 20, a gate electrode 564 is formed on the gate insulating layer 550 (step S1009). The gate electrode 564 is formed by patterning a metal layer formed by sputtering or atomic layer deposition. As described above, the gate electrode 564 is formed so as to be in contact with the gate insulating layer 550 exposed by removing the metal oxide layer 590.

[0119] A common metal material is used as the material of the gate electrode 564. Examples of the metal material that can be used include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The gate electrode 564 may be made of the above materials in a single layer structure or a multilayer structure.

[0120] 14 and 21, with the gate electrode 564 formed, a source region 544S and a drain region 544D of the oxide semiconductor layer 544 are formed (step S1010). Specifically, an impurity element is implanted into the oxide semiconductor layer 544 through the gate insulating layer 550 by ion implantation or ion doping using the gate electrode 564 as a mask. In step S1010, an impurity element such as argon (Ar), phosphorus (P), or boron (B) is implanted into a part of the oxide semiconductor layer 544 that is not covered with the gate electrode 564.

[0121] The region of the oxide semiconductor layer 544 into which the impurity element is implanted has a low resistance to such an extent that the region can function as a conductive layer due to the formation of oxygen vacancies. That is, as a result of implanting the impurity element into the oxide semiconductor layer 544 in step S1010, a conductive portion 403b (a source region 544S and a drain region 544D) is formed in the region not covered with the gate electrode 564. On the other hand, a channel portion 403a (a channel region 544CH) is formed in the region of the oxide semiconductor layer 544 covered with the gate electrode 564. Since the gate electrode 564 functions as a mask, the impurity element is not implanted into the channel portion 403a.

[0122] In this embodiment, since the impurity element is implanted into the oxide semiconductor layer 544 through the gate insulating layer 550, the impurity element such as argon (Ar), phosphorus (P), or boron (B) is contained not only in the source region 544S and the drain region 544D but also in the gate insulating layer 550.

[0123] Next, as shown in FIGS. 14 and 22, insulating layers 570 and 580 are formed as interlayer films on the gate insulating layer 550 and the gate electrode 564 (step S1011).

[0124] The description of the base film 520 may be referred to for the film formation method and insulating material of the insulating layers 570 and 580. The insulating layer 570 has a thickness of 50 nm or more and 500 nm or less. The insulating layer 580 has a thickness of 50 nm or more and 500 nm or less. In this embodiment, for example, a silicon nitride layer is formed as the insulating layer 570, and a silicon oxide layer is formed as the insulating layer 580.

[0125] 14 and 23, contact holes 571 and 573 are formed in the gate insulating layer 550 and the insulating layers 570 and 580 (step S1012). The source region 544S is exposed through the contact hole 571, and the drain region 544D is exposed through the contact hole 573. After the source region 544S and the drain region 544D are exposed through the contact holes 571 and 573, the source electrode 601 and the drain electrode 603 shown in FIG. 10 are formed (step S1013). Through the above processes, the semiconductor device 10 shown in FIG. 10 is completed.

[0126] The source electrode 601 and the drain electrode 603 are formed by, for example, a sputtering method. The source electrode 601 and the drain electrode 603 can be formed by using a general metal material. As the metal material, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof can be used. The source electrode 601 and the drain electrode 603 may have a single-layer structure or a multilayer structure.

[0127] In the semiconductor device 10 manufactured by the above manufacturing method, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2In this embodiment, the field effect mobility means the field effect mobility in the saturation region of the semiconductor device 10, and refers to the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the voltage (Vg) supplied to the gate electrode minus the threshold voltage (Vth) of the semiconductor device 10 (Vg-Vth).

[0128] In the semiconductor device 10 of this embodiment, the resistance values ​​of the source region 544S and the drain region 544D are sufficiently low, so that they can be used as wiring. Since an oxide semiconductor has light transmitting properties, if an oxide semiconductor can be used as a wiring material as in this embodiment, it is very advantageous in improving the transmittance of a display panel (in this embodiment, the organic EL panel 200).

[0129] Second Embodiment In this embodiment, a semiconductor device 10a having a different configuration from the semiconductor device 10 shown in the first embodiment will be described.

[0130] [Configuration of semiconductor device 10a] The configuration of the semiconductor device 10a according to this embodiment is similar to that of the semiconductor device 10 of the first embodiment, but differs from the semiconductor device 10 of the first embodiment in that a metal oxide layer 530 is provided between an undercoat film 520 and an oxide semiconductor layer 544. In the following description, the description of the same configuration as in the first embodiment will be omitted, and the differences from the first embodiment will be mainly described.

[0131] 24 is a cross-sectional view showing an outline of a semiconductor device 10a according to one embodiment of the present invention. As shown in FIG. 24, the semiconductor device 10a includes an undercoat film 520, a metal oxide layer 530, an oxide semiconductor layer 544, a gate insulating layer 550, a gate electrode 564, an insulating layer 570, an insulating layer 580, a source electrode 601, and a drain electrode 603.

[0132] The metal oxide layer 530 is provided on the base film 520. The metal oxide layer 530 is in contact with the base film 520. The oxide semiconductor layer 544 is provided on the metal oxide layer 530. The oxide semiconductor layer 544 is in contact with the metal oxide layer 530. Of the main surfaces of the oxide semiconductor layer 544, the surface in contact with the metal oxide layer 530 is referred to as the lower surface. An end of the metal oxide layer 530 and an end of the oxide semiconductor layer 544 approximately coincide with each other.

[0133] The metal oxide layer 530 is a layer containing a metal oxide mainly composed of aluminum, similar to the metal oxide layer 590 (see FIG. 18), and has a function as a gas barrier film that blocks gases such as oxygen and hydrogen. The metal oxide layer 530 can be made of the same material as the metal oxide layer 590, but may also be made of a different material.

[0134] 11, and therefore is not shown. However, in plan view, the planar pattern of the metal oxide layer 530 is substantially the same as the planar pattern of the oxide semiconductor layer 544. With reference to FIG. 24, the lower surface of the oxide semiconductor layer 544 is covered with the metal oxide layer 530. In particular, in this embodiment, the entire lower surface of the oxide semiconductor layer 544 is covered with the metal oxide layer 530.

[0135] A high-mobility semiconductor device 10a can be realized by setting the ratio of indium to 50% or more in the oxide semiconductor layer 544. On the other hand, in such an oxide semiconductor layer 544, oxygen contained in the oxide semiconductor layer 544 is easily reduced, and oxygen defects are easily formed in the oxide semiconductor layer 544.

[0136] In the semiconductor device 10a, during a heat treatment step in the manufacturing process, hydrogen is released from a layer (for example, the base film 520) provided on the substrate 500 side of the oxide semiconductor layer 544, and the hydrogen reaches the oxide semiconductor layer 544, which may cause oxygen defects in the oxide semiconductor layer 544. The occurrence of oxygen defects is more prominent as the pattern size of the oxide semiconductor layer 544 becomes larger. In order to prevent the occurrence of such oxygen defects, it is necessary to prevent hydrogen from reaching the lower surface of the oxide semiconductor layer 544.

[0137] The upper surface of the oxide semiconductor layer 544 is affected by a process (for example, a patterning process or an etching process) performed after the oxide semiconductor layer 544 is formed. On the other hand, the lower surface of the oxide semiconductor layer 544 (the surface of the oxide semiconductor layer 544 facing the substrate 500) is not affected in the above manner.

[0138] Therefore, the number of oxygen defects formed on the upper surface of the oxide semiconductor layer 544 is greater than the number of oxygen defects formed on the lower surface of the oxide semiconductor layer 544. That is, the oxygen defects inside the oxide semiconductor layer 544 are not uniformly distributed in the film thickness direction of the oxide semiconductor layer 544, but are non-uniformly distributed in the film thickness direction of the oxide semiconductor layer 544. Specifically, the number of oxygen defects inside the oxide semiconductor layer 544 is fewer on the lower surface side of the oxide semiconductor layer 544 and more on the upper surface side of the oxide semiconductor layer 544.

[0139] When oxygen supplying treatment is performed uniformly on the oxide semiconductor layer 544 having oxygen defects distributed therein as described above, if an amount of oxygen necessary to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layer 544 is supplied, an excess of oxygen is supplied to the lower surface side of the oxide semiconductor layer 544. As a result, a defect level different from the oxygen defects is formed on the lower surface side due to the excess oxygen, causing phenomena such as characteristic fluctuation in a reliability test or a decrease in field-effect mobility. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layer 544 while suppressing the supply of oxygen to the lower surface side of the oxide semiconductor layer 544.

[0140] In the conventional configuration and manufacturing method, even if the initial characteristics of the semiconductor device are improved by supplying oxygen to the oxide semiconductor layer, there are cases where the characteristics fluctuate due to the reliability test. That is, in the conventional configuration and manufacturing method, there is a trade-off between the initial characteristics and the reliability test. However, the configuration and manufacturing method according to the present embodiment makes it possible to obtain good initial characteristics and reliability tests for the semiconductor device 10a.

[0141] [Manufacturing Method of Semiconductor Device 10a] A method for manufacturing the semiconductor device 10a according to one embodiment of the present invention will be described with reference to Fig. 25 to Fig. 28. Fig. 25 is a sequence diagram showing the method for manufacturing the semiconductor device 10a according to one embodiment of the present invention. Fig. 26 to Fig. 28 are cross-sectional views showing the method for manufacturing the semiconductor device 10a according to one embodiment of the present invention.

[0142] 25, a base film 520 is formed on a substrate 500 (step S2001). For step S2001, refer to the description of step S1001 shown in FIGS. 14 and 15. In this embodiment, silicon nitride and silicon oxide are used as materials for the base film 520. Silicon oxide is preferable in terms of reducing oxygen defects in the oxide semiconductor layer 544 because it releases oxygen by heat treatment.

[0143] 25 and 26, a metal oxide layer 530 and an oxide semiconductor layer 540 are formed on an undercoat film 520 (step S2002). The metal oxide layer 530 and the oxide semiconductor layer 540 are formed by a sputtering method or an atomic layer deposition method (ALD).

[0144] For the material of the metal oxide layer 530, the description of the material of the metal oxide layer 590 shown in FIG. 18 may be referred to. The film thickness of the metal oxide layer 530 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm, or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 530. Aluminum oxide has high barrier properties against gas. In this embodiment, aluminum oxide used as the metal oxide layer 530 blocks hydrogen and oxygen released from the base film 520 and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer 540.

[0145] The oxide semiconductor layer 540 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, an oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer 540. The oxide semiconductor layer 540 is amorphous before OS annealing performed in step S2004 described later.

[0146] When the oxide semiconductor layer 540 is crystallized by OS annealing described later, the oxide semiconductor layer 540 is preferably amorphous (having a small amount of crystalline components in the oxide semiconductor) after deposition and before OS annealing. For a deposition method for making the oxide semiconductor layer 540 amorphous after deposition, the description of step S1002 in FIG. 14 may be referred to.

[0147] Next, as shown in FIG. 25 and FIG. 27, a pattern of the oxide semiconductor layer 540 is formed (step S2003). Although not shown, a resist mask is formed on the oxide semiconductor layer 540, and the oxide semiconductor layer 540 is etched using the resist mask. The oxide semiconductor layer 540 may be etched by either wet etching or dry etching. The wet etching can be performed using an acidic etchant. As the acidic etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0148] 25, after the oxide semiconductor layer 540 is patterned, heat treatment (OS annealing) is performed on the oxide semiconductor layer 540 (step S2004). In this embodiment, the oxide semiconductor layer 540 is crystallized by the OS annealing. The crystallized oxide semiconductor layer is referred to as an oxide semiconductor layer 544.

[0149] Next, as shown in FIG. 25 and FIG. 28, a pattern of the metal oxide layer 530 is formed (step S2005). The metal oxide layer 530 is etched using the crystallized oxide semiconductor layer 544 as a mask. Either wet etching or dry etching may be used for etching the metal oxide layer 530. As an etchant for wet etching, for example, diluted hydrofluoric acid (DHF) is used. The crystallized oxide semiconductor layer 544 has etching resistance to diluted hydrofluoric acid compared to the amorphous oxide semiconductor layer 540. Therefore, the metal oxide layer 530 can be etched in a self-aligned manner using the oxide semiconductor layer 544 as a mask. This makes it possible to omit a photolithography process.

[0150] The process shown in steps S2006 to S2014 in Fig. 25 is similar to steps S1005 to S1013 in Fig. 14, and therefore the following description will be omitted. By going through steps S2006 to S2014, the semiconductor device 10a shown in Fig. 24 can be formed.

[0151] In the semiconductor device 10a manufactured by the above manufacturing method, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 50 cm 2 / Vs or more, 55cm 2 / Vs or more, or 60cm 2 In this embodiment, the field effect mobility is defined in the same manner as in the first embodiment.

[0152] Third embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the second embodiment will be described. The structure of the semiconductor device of this embodiment is identical in appearance to the semiconductor device 10a described in the second embodiment. In this embodiment, the differences from the second embodiment will be described.

[0153] Fig. 29 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in Fig. 29, in this embodiment, two steps, step S2007 and step S2009 shown in Fig. 25, are omitted. That is, in this embodiment, after the gate insulating layer 550 is formed, oxidation annealing (step S2008) is performed in this state. By the oxidation annealing, oxygen released from the gate insulating layer 550 is supplied to the oxide semiconductor layer 540, and oxygen defects contained in the oxide semiconductor layer 540 are repaired. The role of the metal oxide layer 530 in this case is the same as in the second embodiment, and therefore will not be described here.

[0154] In the semiconductor device 10a manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region 544CH is in the range of 2 μm to 4 μm and the channel width of the channel region 544CH is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 In this embodiment, the field effect mobility is defined in the same manner as in the first embodiment.

[0155] Fourth embodiment In this embodiment, a semiconductor device manufactured by a method different from that of the first embodiment will be described. The structure of the semiconductor device of this embodiment is identical in appearance to the semiconductor device 10 described in the first embodiment. In this embodiment, the differences from the first embodiment will be described.

[0156] Fig. 30 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in Fig. 30, in this embodiment, two processes, step S1006 and step S1008 shown in Fig. 14, are omitted. That is, in this embodiment, after the gate insulating layer 550 is formed, oxidation annealing (step S1007) is performed in this state. By the oxidation annealing, oxygen released from the gate insulating layer 550 is supplied to the oxide semiconductor layer 544, and oxygen defects contained in the oxide semiconductor layer 544 are repaired.

[0157] Fifth embodiment In the first embodiment, an example in which the scanning signal lines 214 in the imaging region 130A are configured using a metal layer is shown, but in this embodiment, an example in which a transparent conductive layer is used instead of the metal layer is shown. The structure of the display device of this embodiment is the same in appearance as the display device 100 described in the first embodiment. In this embodiment, the configurations different from those of the first embodiment are described, and the same configurations are illustrated using the same reference numerals, and description thereof is omitted.

[0158] Fig. 31 is a plan view showing the pixel structure of the pixel 212A in the imaging region 130A in the display device 100 according to an embodiment of the present invention. In this embodiment, the scanning signal line 214-1 (including the gate electrode 405a) in Fig. 31 is formed of a transparent conductive layer. Specifically, in this embodiment, ITO (Indium Tin Oxide) is used as a material constituting the transparent conductive layer. Other metal oxides having light transmitting properties may also be used as the transparent conductive layer.

[0159] In the display device 100 of this embodiment, the scanning signal lines 214-1 are formed of a transparent conductive layer in the imaging region 130A, so that the scanning signal lines 214-1 do not block visible light. Therefore, according to this embodiment, the transmittance of the display panel can be further improved compared to the imaging region 130A of the first embodiment. The configuration of the scanning signal lines 214-1 is the same as the structure shown in FIG. 5. Specifically, the multiple wirings 214-1a are connected to each other by the connection wirings 214-1b arranged so as to straddle the video signal lines 216A, and function as the scanning signal lines 214-1 as a whole. The connection wirings 214-1b are electrically connected to each wiring 214-1a via the contact parts 214-1c. The positional relationship between the wirings 214-1a and the video signal lines 216A is as shown in the part surrounded by the frame line CP.

[0160] In this embodiment, the scanning signal lines 214a in the imaging region 130A are formed of a transparent conductive layer, and the scanning signal lines in the non-imaging region 130B are formed of a metal layer. That is, in this embodiment, a transparent conductive layer with a relatively high resistance is used in a limited region (i.e., the imaging region 130A), and a metal layer with a relatively low resistance is used in the non-imaging region 130B that is wider than the imaging region 130A. This makes it possible to suppress display defects due to signal delays and the like even if a transparent conductive layer is used for some of the scanning signal lines. However, this is not limited to this example, and a transparent conductive layer may be used for the scanning signal lines not only in the imaging region 130A but also in the non-imaging region 130B.

[0161] In this embodiment, an example in which a transparent conductive layer is used for the scanning signal line 214a has been shown, but a transparent conductive layer may also be used for the anode power line 305 (see FIG. 3). In this case, the transmittance of the display panel can be further improved.

[0162] Sixth embodiment In this embodiment, an example in which the pixel density is different between the imaging region 130A and the non-imaging region 130B will be described. Specifically, in this embodiment, an example in which the pixel density in the imaging region 130A is smaller than the pixel density in the non-imaging region 130B will be described. In this embodiment, configurations different from those in the first embodiment will be described, and the same configurations will be illustrated with the same reference numerals, and description thereof will be omitted.

[0163] Fig. 32 is a plan view showing the vicinity of the imaging region 130A in the display device 100 according to an embodiment of the present invention. As shown in Fig. 32, in this embodiment, the pixel density of the pixels 212A arranged in the imaging region 130A is made smaller than that of the pixels 212B arranged in the non-imaging region 130B. Here, the pixel density is the number of pixels included per unit area. That is, in the imaging region 130A, the distance between adjacent pixels is greater than the distance between adjacent pixels in the non-imaging region 130B.

[0164] According to this embodiment, since a larger gap can be provided between pixels arranged in the imaging region 130A than in the non-imaging region 130B, the transmittance of the display panel (here, the organic EL panel 200) can be improved.

[0165] Seventh embodiment In this embodiment, an example in which the thickness of the substrate is different between the imaging region 130A and the non-imaging region 130B will be described. Specifically, in this embodiment, an example in which the thickness of the substrate in the imaging region 130A is thinner than the thickness of the substrate in the non-imaging region 130B will be described. In this embodiment, configurations different from those in the first embodiment will be described, and the same configurations will be illustrated with the same reference numerals, and description thereof will be omitted.

[0166] FIG. 33 is a cross-sectional view showing the vicinity of the imaging region 130A in the display device 100 according to an embodiment of the present invention. As shown in FIG. 33, in this embodiment, the thickness of the circuit board 200A (strictly speaking, the thickness of the board 401 shown in FIG. 6 and FIG. 8) is locally thin in the imaging region 130A. For example, in FIG. 33, the thickness of the circuit board 200A in the non-imaging region 130B is T2, whereas the thickness of the circuit board 200A in the imaging region 130A is T1. In order to thin the thickness of the circuit board 200A, for example, a part of the board 401 shown in FIG. 6 and FIG. 8 (a part corresponding to the imaging region 130A) may be thinned by wet etching, dry etching, laser etching, or the like.

[0167] According to this embodiment, the optical path length through which external light passes through the display panel (organic EL panel 200) in the imaging region 130A is shortened, and therefore the transmittance of the display panel can be substantially improved. In addition, in this embodiment, when the imaging element 132 is disposed on the back side of the circuit board 200A, the imaging element 132 is disposed inside a recess formed by the circuit board 200A, so that the display device 100 can be made thinner.

[0168] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions, based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0169] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0170] 10, 10a...semiconductor device, 100...display device, 110...casing, 120...display screen, 130...imaging unit, 130A...imaging area, 130B...non-imaging area, 132...imaging element, 164...oxide conductive layer, 200...organic EL panel, 200A...circuit board, 210...display circuit, 212, 212A, 212B...pixel, 214, 214-1...scanning signal line, 214a, 214-1a...wiring, 241b, 214-1b...connecting wiring , 214c, 214-1c...contact portion, 216, 216A, 216B...video signal line, 220...scanning signal line drive circuit, 230...terminal portion, 240...flexible printed circuit board, 250...display control circuit, 270...system control circuit, 300...pixel circuit, 301...drive transistor, 302...selection transistor, 303...storage capacitance, 304...light emitting element, 305...anode power line, 306...cathode power line, 401 ...substrate, 402...underlying layer, 403...oxide semiconductor layer, 403a...channel portion, 403b...conductive portion, 404...gate insulating layer, 405...gate electrode, 406...interlayer insulating layer, 406a, 406b...contact holes, 407...terminal electrode, 410...planarization layer, 411...pixel electrode, 412...resin layer, 412a...opening, 413...light-emitting layer, 414...common electrode, 500...substrate, 520...underlying film, 530...metal oxide layer, 540, 544... oxide semiconductor layer, 544CH... channel region, 544D... drain region, 544S... source region, 550... gate insulating layer, 564... gate electrode, 565... gate wiring, 570... insulating layer, 571, 573... contact holes, 580... insulating layer, 590... metal oxide layer, 601... source electrode, 603... drain electrode, 1010... first energy level, 1020... second energy level, 1030... tail level

Claims

1. a display panel including a display unit having a plurality of pixels; a sensor element disposed on the rear side of the display unit; Including, the display unit has a first region overlapping with the sensor element in a plan view and a second region other than the first region, each of the plurality of pixels has a semiconductor device including a channel portion and a conductive portion made of an oxide semiconductor having a polycrystalline structure; each of the plurality of pixels in the first region is connected by a first signal line formed in the same layer as the conductive portion; A display device, wherein each of the plurality of pixels in the second region is connected by a second signal line made of a metal layer connected to the conductive portion.

2. The display device according to claim 1 , wherein the first signal line and the conductive portion are integral with each other.

3. The display device according to claim 1 , wherein the pixel density in the first region is smaller than the pixel density in the second region.

4. the plurality of pixels are disposed on a substrate; The display device according to claim 1 , wherein the thickness of the substrate in the first region is thinner than the thickness of the substrate in the second region.

5. 2. The display device according to claim 1, wherein, in a predetermined crystal orientation, the d-spacing of the crystal structure of the conductive portion is substantially the same as the d-spacing of the crystal structure of the channel portion.

6. The display device according to claim 1 , wherein the crystal structure of the channel portion and the crystal structure of the conductive portion are cubic.

7. 2. The display device according to claim 1, wherein the sheet resistance of the conductive portion is 500 Ω / sq. or less.

8. The display device according to claim 1 , wherein the sensor element is an image pickup element.

Images