Analog-to-digital converter, imaging element, and electronic equipment

Abstract

To prevent reduction in bit precision when digital gain is applied to a digital signal obtained by a ΔΣ AD conversion circuit.SOLUTION: An analog-to-digital converter comprises: analog-to-digital conversion means for performing analog-to-digital conversion using ΔΣ modulation on an image signal outputted from a pixel; setting means for setting an operation frequency of the analog-to-digital conversion means; and generation means for generating a clock signal having the operation frequency and supplying the clock signal to the analog-to-digital conversion means. The setting means sets the operation frequency on the basis of at least any one of digital gain to be applied to the signal outputted from the analog-to-digital conversion means and a photographing mode.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an analog-to-digital converter, and an imaging element and electronic device using the same, and in particular to an analog-to-digital conversion technique using ΔΣ modulation. [Background technology]

[0002] In recent years, CMOS image sensors have become more and more pixel-rich and faster to read out. Accordingly, these sensors can be operated by arranging many analog-to-digital converters (ADCs) in parallel to achieve higher pixel counts and faster readout speeds. However, the conventional slope-type ADCs have issues with the increase in circuit size and power consumption that accompanies the parallel arrangement of many ADCs.

[0003] For this reason, a CMOS image sensor using a ΔΣ ADC has been proposed, which has a smaller circuit scale, requires a lower voltage for the ADC, and is capable of high-speed AD conversion compared to a slope-type ADC. For example, Patent Document 1 discloses the configuration of a CMOS image sensor that uses ΔΣ modulation in the AD conversion circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 3904111 Summary of the Invention [Problem to be solved by the invention]

[0005] However, whereas a slope-type ADC can apply gain during AD conversion depending on the slope of the reference voltage used during conversion, a ΔΣ ADC configured as in Patent Document 1 cannot apply gain during conversion. Therefore, in a ΔΣ ADC, a digital gain is applied in the signal processing unit after AD conversion, but the larger the digital gain, the lower the bit precision of the final output becomes.

[0006] The present invention has been made in consideration of the above problems, and has an object to prevent a decrease in bit precision when a digital gain is applied to a digital signal obtained by a ΔΣ AD converter. [Means for solving the problem]

[0007] In order to achieve the above object, an analog-to-digital converter of the present invention comprises an analog-to-digital conversion means that performs analog-to-digital conversion using ΔΣ modulation on an image signal output from a pixel, a setting means that sets an operating frequency of the analog-to-digital conversion means, and a generation means that generates a clock signal of said operating frequency and supplies it to the analog-to-digital conversion means, wherein the setting means sets the operating frequency based on at least one of a digital gain applied to the signal output from the analog-to-digital conversion means and a shooting mode. Effect of the Invention

[0008] According to the present invention, when a digital gain is applied to a digital signal obtained by a ΔΣ AD converter, it is possible to prevent a decrease in bit precision. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of an image capturing apparatus according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing a schematic configuration of an image sensor according to the embodiment. [Diagram 3] FIG. 2 is a block diagram showing a configuration of a read circuit according to the embodiment. [Figure 4] FIG. 1 is a block diagram showing a configuration of a ΔΣ ADC according to an embodiment. [Diagram 5] FIG. 2 is a block diagram showing a configuration of a CLK generating circuit unit according to the embodiment. [Figure 6] 3A and 3B are diagrams showing examples of input voltage waveforms and output voltage waveforms of a comparator according to the first embodiment. [Figure 7]13A and 13B are diagrams illustrating input / output characteristics for non-Log moving images and Log moving images in the second embodiment. [Figure 8] 13A to 13C are diagrams showing an example of a gamma curve in SDR mode and gamma curves in the PQ and HLG formats in HDR mode according to the second embodiment. [Figure 9] 13 is a flowchart showing switching control of the operating frequency of a ΔΣ ADC in the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] <First embodiment> 1 is a block diagram showing the configuration of an imaging device using an imaging element according to a first embodiment of the present invention. Note that the imaging device to which the present invention can be applied may be any electronic device equipped with a camera function, and may be, for example, a camera such as a digital camera or a digital video camera, a camera-equipped mobile phone, a camera-equipped computer, a game machine, etc.

[0012] 1, lens unit 101 includes a plurality of lenses, such as a zoom lens and a focus lens, and an aperture, and zoom control, focus control, aperture control, and the like are performed by a drive device 102. An optical image of a subject incident via lens unit 101 is formed on an image sensor 105.

[0013] The lens unit 101 may be configured as an integral part of the imaging device, or may be configured to be detachable. The mechanical shutter 103 is controlled by a shutter driving device 104. The imaging element 105 photoelectrically converts the optical image of the subject formed by the lens unit 101, and outputs an image signal.

[0014] The signal processing circuit 106 performs digital gain processing for applying digital gain to the image signal output from the image sensor 105, various corrections, data compression, etc., and outputs image data. The memory unit 107 is used to temporarily store image data. The system control unit 108 performs various calculations and controls the entire imaging device. The I / F unit 109 is an interface for recording or reading data to the recording medium 110, which is a semiconductor memory such as a flash memory for holding image data, etc., and is configured to be removable. The display unit 111 displays various information and captured images.

[0015] Next, the operation of the imaging device having the above configuration during shooting will be briefly described. When a main power supply (not shown) is turned on, the power supply of the system control unit 108 is turned on, and further the power supply of the imaging system circuits such as the signal processing circuit 106 is turned on. Then, when an instruction to shoot is given by pressing a release button (not shown), the shooting operation is started. When the shooting operation is completed, the image signal output from the image sensor 105 is subjected to image processing including various corrections and digital gain processing in the signal processing circuit 106, and the obtained image data is written to the memory unit 107 under the instruction of the system control unit 108. The image data held in the memory unit 107 is recorded in a removable recording medium 110 such as a semiconductor memory via the I / F unit 109 under the control of the system control unit 108.

[0016] Furthermore, the ROW image data may be sent to a computer or the like via an external I / F unit (not shown), and image processing may be performed in the computer or the like.

[0017] FIG. 2 is a block diagram showing a schematic configuration of the image sensor 105 in this embodiment. The image sensor 105 includes a pixel section 200, a vertical scanning section 202, a timing generator (TG) 203, a circuit control section 204, a CLK generation circuit section 205, column output lines 206, a signal readout section 207, and an output section 209.

[0018] In the pixel section 200, a plurality of pixels 201 are arranged in a matrix. For ease of explanation, the pixels 201 are shown as a 4×4 pixel array in the pixel section 200, but in practice, a large number of pixels, for example, several million or more, are arranged. The signal readout section 207 has a plurality of readout circuits 208.

[0019] The vertical scanning unit 202 selects the pixels 201 of the pixel unit 200 on a row-by-row basis, and supplies a plurality of driving signals to each pixel 201 of the selected row. As a result, pixel signals of the pixels 201 of the selected row are output to a signal readout unit 207 via column output lines 206. The output pixel signals are converted into digital signals in each readout circuit 208, and output to the outside of the image sensor 105 via an output unit 209.

[0020] The readout circuit 208 converts the input pixel signal into a digital signal value by AD conversion at a predetermined bit rate using a so-called ΔΣ AD conversion method. An output unit 209 converts the digital signal value of each pixel into a predetermined signal format and outputs it from a transmission line to the outside of the image sensor 105 .

[0021] The TG 203 sends a timing signal to the vertical scanning unit 202, and the vertical scanning unit 202 generates a control signal for driving the pixels 201 based on the timing signal, and drives the pixels 201. The circuit control unit 204 controls the CLK generation circuit unit 205 and the signal readout unit 207 based on the timing signal from the TG 203. In addition, the CLK generation circuit unit 205 generates a clock signal to be supplied to the signal readout unit 207 based on the clock signal supplied from the TG 203 and the control by the circuit control unit 204.

[0022] FIG. 3 is a block diagram showing a configuration of each read circuit 208 shown in FIG. The readout circuit 208 includes an analog-to-digital converter (ΔΣADC) 300 that uses ΔΣ modulation, and a digital filter 301. The ΔΣADC 300 converts pixel signals input via the column output lines 206 into digital signals using ΔΣ modulation. The digital filter 301 removes out-of-band quantization noise that has been shifted to higher frequencies by the ΔΣ modulation. It also performs thinning and moving averaging of the high-rate output of the ΔΣADC 300 to reduce the output rate and convert it into a multi-bit signal value.

[0023] FIG. 4 is a block diagram showing a configuration of the ΔΣ ADC 300 shown in FIG. As shown in FIG. 4, the ΔΣ ADC 300 includes a subtraction circuit 400, an integration circuit 401, a comparator 402, and a digital-to-analog converter (DAC) 403.

[0024] The subtraction circuit 400 outputs the difference between the pixel signal input via the column output line 206 and the output signal of the DAC 403 to the integration circuit 401. However, as an embodiment of the present invention, a configuration may be provided in which a sample-and-hold circuit is provided between the column output line 206 and the subtraction circuit 400. In that case, the pixel signal output from the sample-and-hold circuit is input to the subtraction circuit 400.

[0025] The integrating circuit 401 includes an integrator that integrates an input signal from the subtracting circuit 400. As the integrating circuit 401, a gm-C integrating circuit using a transconductor, an RC integrating circuit using an operational amplifier, or the like, which is a general integrating circuit, can be used.

[0026] The comparator 402 compares the reference voltage Vref with the voltage signal output from the integrating circuit 401 in synchronization with the clock signal, and outputs the comparison result as a 1-bit digital signal. For example, if the voltage signal output from the integrating circuit 401 is lower than the reference voltage Vref, the comparator 402 outputs 0, and if the voltage signal is equal to or higher than the reference voltage Vref, the comparator 402 outputs 1. This digital signal is supplied to the digital filter 301 and the DAC 403.

[0027] The DAC 403 converts the digital signal output from the comparator 402 into a predetermined analog signal amount and outputs it to the subtraction circuit 400. For example, when the digital signal output is 1, an analog signal of a predetermined level is output. Note that various circuits can be used as the configuration of the digital-to-analog conversion circuit.

[0028] FIG. 5 is a block diagram showing the configuration of the CLK generating circuit unit 205. As shown in FIG. The CLK generation circuit unit 205 is made up of a frequency divider A 500 , a PLL (Pulse-Locked Loop) 501 , and a frequency divider B 502 .

[0029] The division ratios of the frequency divider A500 and the frequency divider B502 are controlled by the circuit control unit 204. The frequency divider A500 divides the clock f M The frequency divider B 502 divides the output of the PLL 501 by 1 / N and inputs the divided signal to the PLL 501 again.

[0030] The PLL 501 multiplies the input clock so that the phase and frequency of the inputs from the divider A 500 and the divider B 502 match, so the output of the PLL 501 is f OS f M *N / M. OS is the frequency of the clock signal supplied to ΣADC300, and is therefore the operating frequency of ΣADC300, i.e., the oversampling frequency.

[0031] FIG. 6 shows an example of the input voltage waveform and the output voltage waveform of the comparator 402. In FIG. 6 shows an example of a part of a process in which pixel signals of the same level input to the ΔΣADC 300 via the column output line 206 are ΔΣ AD converted at different oversampling frequencies. In reality, such a waveform pattern is repeated for a predetermined period of time.

[0032] Figures 6(a) and (b) show the voltage waveforms on the input terminal side, that is, the output voltage of the integrating circuit 401 and the reference voltage. Also, Figure 6(c) shows the ΔΣ modulated digital signal waveform on the output terminal side corresponding to Figure 6(a), and Figure 6(d) shows the ΔΣ modulated digital signal waveform on the output terminal side corresponding to Figure 6(b).

[0033] 6(a) and (c) show an example in which the oversampling frequency is twice that of FIGs. 6(b) and (d), and the time on the horizontal axis is expressed as one unit per one cycle of the clock in FIGs. 6(a) and (c). As shown in FIGs. 6(a) and (b), the states of the ΔΣ ADCs 300 are the same at the start of the ΔΣ AD conversion process (immediately after each circuit is reset), so at time 0, the voltages input to the comparator 402 via the subtraction circuit 400 and the integration circuit 401 are also at the same level. In FIGs. 6(a) and (b), this voltage is illustrated as 0.3 V.

[0034] In this case, the changes in the voltage signal that occur up to time 10 in the example shown in Fig. 6(d) occur by time 5, which is half the time, in the voltage signal shown in Fig. 6(c) where the oversampling frequency is twice as high. In other words, when ΔΣ AD conversion is performed for the same amount of time, doubling the oversampling frequency can roughly double the number of times the voltage signal changes.

[0035] Tables 1 and 2 below show the relationship between the ISO sensitivity setting of the imaging device, the oversampling rate (hereinafter referred to as "OSR") which is the ratio between the Nyquist frequency and the oversampling frequency, and bit precision.

[0036] TIFF2024047276000002.tif67119

[0037] TIFF2024047276000003.tif67120

[0038] In Table 1, the OSR is n regardless of the ISO sensitivity, and the bit precision of the AD conversion including processing by the decimation filter is 14 bits at ISO100. In this case, it is necessary to apply digital gain (Dgain) to increase the ISO sensitivity to ISO200, ISO400, etc., and as a result, the bit precision of the final output becomes 1 / Dgain, which is 10 bits at ISO1600. In this case, the obtained image is adversely affected by tone jumps and quantization noise multiplied by the gain.

[0039] To eliminate these effects, in this embodiment, the OSR is changed according to the ISO sensitivity, as shown in Table 2. For example, at ISO1600, by setting the OSR to 16n, the bit precision of the AD conversion becomes 18 bits, and even if the signal is multiplied by 16 with Dgain, the bit precision of the final output becomes 14 bits. In addition, by increasing the OSR, the effect of noise shaping is improved, and quantization noise is reduced.

[0040] In the above example, the case where the OSR is determined according to the digital gain based on the ISO sensitivity has been described, but the OSR may be changed according to the digital gain due to various corrections such as peripheral light amount correction. For example, when a lens with large peripheral light amount falloff is attached and digital gain is applied to the peripheral parts of the image according to the image height by peripheral light amount falloff correction, tone jumps and noise in the peripheral parts of the image can be reduced even after correction by changing the OSR according to the digital gain as shown in Table 2.

[0041] As described above, according to the first embodiment, by changing the OSR according to the digital gain, it is possible to eliminate the reduction in bit precision due to the digital gain and obtain a good image with reduced tone jumps and increases in quantization noise.

[0042] In the first embodiment, a first-order ΔΣ modulator constituting a first-order loop filter has been used for explanation, but the present invention can be similarly applied to a circuit configuration using a second-order or higher ΔΣ modulator to stabilize the feedback loop. Also, in an incremental ΔΣ ADC, although the digital signal waveform is different from that in Fig. 6, the effect of changing the OSR can be obtained in the same way.

[0043] <Second embodiment> Next, a second embodiment of the present invention will be described. In the above-described first embodiment, a case where the OSR is changed depending on the digital gain is described, but in the second embodiment, a case where the OSR is changed depending on the shooting mode, etc. Note that the configuration of the imaging device in the second embodiment is similar to that described in the first embodiment with reference to Figs. 1 to 5, and therefore description thereof will be omitted.

[0044] Table 3 shows an example of a shooting mode in the second embodiment, and the relationship between the OSR and bit precision.

[0045] TIFF2024047276000004.tif8392

[0046] In Table 3, the OSR in the still image mode is n and the bit precision is 14 bits, and the OSR in the moving image mode is n / 4 and the bit precision is 12 bits. The difference in bit precision between the still image mode and the moving image mode is due to, for example, restrictions on the data transfer rate from the image sensor 105 to the signal processing circuit 106.

[0047] When implementing a high-quality still image mode that can obtain better images with less noise than the still image mode, the OSR is set to 2n to obtain images with 15-bit precision.

[0048] In the live view (LV) mode, the image is not recorded in the recording medium 110, and an image is acquired to be displayed on the display unit 111, so the requirement for image quality is not high. Therefore, the OSR is set to n / 16 for the purpose of reducing power consumption by reducing the amount of data, that is, a low OSR.

[0049] On the other hand, in Log video mode to obtain a wide dynamic range, the OSR is set high at 4n. Log video has input / output characteristics such as those shown in Fig. 7. The horizontal axis in Fig. 7 shows the number of stops for 18% gray, and the vertical axis shows the signal level in a 10-bit recording file. The dashed line shows the characteristics of non-Log format BT.709, and the solid line shows the characteristics of Log video.

[0050] As shown in Figure 7, the dark area of ​​Log video is steeper than that of BT.709, and by allocating a higher signal level to the dark areas, the dark gradation is enriched. However, this results in a state where a high gain is applied, making noise in the dark areas more noticeable. Therefore, although the final video file is recorded as a 10-bit file, noise and gradation in dark areas can be improved by increasing the OSR and reducing quantization noise through noise shaping.

[0051] Figure 8 shows gamma curves for the PQ (Perceptual Quantization) method and the HLG (Hybrid Log Gamma) method in SDR (Standard Dynamic Range) mode and HDR (High Dynamic Range) mode. The solid line shows an example of the gamma curve for SDR, the dotted line shows an example of the gamma curve for HLG, and the dashed line shows an example of the gamma curve for PQ. Also, unlike Figure 7, the horizontal axis represents luminance.

[0052] As with Log video, the HLG method allocates more signal level to the dark areas compared to SDR, resulting in richer dark gradation, but also more noticeable noise in the dark areas. This tendency is even more pronounced with the PQ method. Therefore, by increasing the OSR and reducing quantization noise through noise shaping, it is possible to improve noise and gradation in the dark areas.

[0053] As described above, according to the second embodiment, by changing the OSR depending on the shooting mode, etc., it is possible to obtain images with image quality suitable for each shooting mode, etc., and to reduce power consumption.

[0054] <Third embodiment> Next, a third embodiment of the present invention will be described. In the third embodiment, a description will be given of OSR switching control that combines the OSR switching control described in the first embodiment and the OSR switching control described in the second embodiment.

[0055] FIG. 9 is a flowchart showing OSR switching control in this embodiment. When the power of the imaging device is turned on, in S901, the set shooting conditions are acquired. In S902, the OSR to be set is calculated based on the combination of ISO sensitivity and shooting mode from the acquired current shooting conditions. For example, in the case of ISO 400 and video mode, the OSR is 4n and n / 4 according to Tables 2 and 3, respectively, so the OSR to be set is n.

[0056] In S903, it is determined whether the OSR found in S902 can be set. Ideally, it is desirable to be able to set the OSR without any restrictions, but in reality, there are circuit-related setting limits for clock division and multiplication. If the OSR is within the settable range, the found OSR is set in S904. If the OSR is below the lower settable limit, the lower limit OSR is set in S905. Also, if the OSR is above the upper settable limit, the upper limit OSR is set in S906.

[0057] In S907, it is determined whether a change in ISO sensitivity and / or shooting mode that requires a change in OSR has been instructed. If a change in OSR is required, the process returns to S902, and the OSR is calculated again based on the changed ISO sensitivity and / or shooting mode.

[0058] If there is no change in ISO sensitivity and / or shooting mode that requires a change in OSR, it is determined in S908 whether or not shooting has been instructed by pressing the release button, etc. If there has been no instruction to shoot, the process returns to S907.

[0059] On the other hand, if a shooting command is issued, moving image recording or still image shooting is performed in S909, and after signal processing in the signal processing circuit 106, the obtained image data is stored in the memory unit 107 and recorded on the recording medium 110 via the I / F unit 109, and the processing ends.

[0060] As described above, according to the third embodiment, by switching the OSR depending on the combination of ISO sensitivity and shooting mode, it is possible to obtain images with image quality suited to each combination and reduce power consumption.

[0061] In the example shown in FIG. 9, the case where the OSR is switched depending on the combination of ISO sensitivity and shooting mode is described; however, the present invention is not limited to this. For example, as described above, the OSR may be changed based on various corrections such as peripheral illumination correction.

[0062] <Summary> The disclosure of this embodiment includes the following configuration.

[0063] (Configuration 1) an analog-to-digital conversion means for performing analog-to-digital conversion using ΔΣ modulation on an image signal output from a pixel; A setting means for setting an operating frequency of the analog-to-digital conversion means; generating means for generating a clock signal having the operating frequency and supplying the clock signal to the analog-to-digital conversion means; The analog-to-digital converter according to claim 1, wherein the setting means sets the operating frequency based on at least one of a digital gain to be applied to a signal output from the analog-to-digital conversion means and a shooting mode.

[0064] (Configuration 2) 2. The analog-to-digital converter according to configuration 1, wherein the generating means generates a clock signal having the operating frequency by dividing and multiplying a frequency of a predetermined clock signal.

[0065] (Configuration 3) 3. The analog-to-digital converter according to configuration 1 or 2, wherein the setting means sets the operating frequency so that the bit precision after the digital gain is applied to the image signal analog-to-digital converted by the analog-to-digital conversion means is equal regardless of the magnitude of the digital gain.

[0066] (Configuration 4) The analog-to-digital converter according to configuration 3, wherein when a predetermined digital gain is M and the digital gain to be applied to the image signal is N, the setting means obtains the operating frequency by multiplying a predetermined frequency by M / N.

[0067] (Configuration 5) 5. The analog-to-digital converter according to configuration 3 or 4, wherein the digital gain is determined based on at least one of an ISO sensitivity and a correction method including peripheral light amount correction.

[0068] (Configuration 6) The analog-to-digital converter according to any one of configurations 1 to 5, wherein the shooting modes include at least one of a high-quality still image mode, a still image mode, a Log video mode, a video mode, a live view mode, and an HLG (Hybrid Log Gamma) method and a PQ (Perceptual Quantization) method in an HDR (High Dynamic Range) mode.

[0069] (Configuration 7) The analog-to-digital converter according to configuration 6, wherein the setting means determines the operating frequency by multiplying a predetermined frequency by a first magnification in the PQ method, a second magnification smaller than the first magnification in the Log video mode or the HLG method, a third magnification smaller than the second magnification in the high-quality still image mode, a fourth magnification lower than the third magnification in the still image mode, a fifth magnification lower than the fourth magnification in the video mode, and a sixth magnification lower than the fifth magnification in the live view mode.

[0070] (Configuration 8) The analog-to-digital converter according to any one of configurations 1 to 7, wherein the setting means determines the operating frequency based on at least one of the digital gain and the shooting mode, and if the determined operating frequency is a frequency that the generating means can generate, sets the determined operating frequency without changing it.

[0071] (Configuration 9) The analog-to-digital converter according to any one of configurations 1 to 8, wherein the setting means determines the operating frequency based on at least one of the digital gain and the shooting mode, and if the determined operating frequency exceeds an upper limit of a frequency that the generating means can generate, changes the operating frequency to the upper limit frequency.

[0072] (Configuration 10) The analog-to-digital converter according to any one of configurations 1 to 9, wherein the setting means determines the operating frequency based on at least one of the digital gain and the shooting mode, and if the determined operating frequency is lower than a lower limit frequency that the generating means can generate, changes the lower limit frequency to be the operating frequency.

[0073] (Configuration 11) A plurality of the analog-to-digital converters according to any one of configurations 1 to 10; A plurality of the pixels; An imaging element comprising:

[0074] (Configuration 12) The imaging element according to configuration 11, a signal processing means for processing the image signal converted by the analog-to-digital converter; 1. An electronic device comprising:

[0075] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0076] 105: imaging element, 106: signal processing circuit, 203: timing generator, 204: circuit control unit, 205: CLK generation circuit unit, 207: readout circuit unit, 208: readout circuit, 300: ΔΣADC, 301: digital filter, 400: subtraction circuit, 401: integration circuit, 402: comparator, 403: DAC, 500: divider A, 501: PLL, 502: divider B

Claims

1. an analog-to-digital conversion unit that performs analog-to-digital conversion using ΔΣ modulation on an image signal output from a pixel; A setting means for setting an operating frequency of the analog-to-digital conversion means; generating means for generating a clock signal having the operating frequency and supplying the clock signal to the analog-to-digital conversion means; 13. An analog-to-digital converter according to claim 12, wherein the setting means sets the operating frequency based on at least one of a digital gain to be applied to a signal output from the analog-to-digital conversion means and a shooting mode.

2. 2. The analog-to-digital converter according to claim 1, wherein said generating means generates a clock signal having said operating frequency by dividing and multiplying the frequency of a predetermined clock signal.

3. 2. The analog-to-digital converter according to claim 1, wherein the setting means sets the operating frequency so that the bit precision after the digital gain is applied to the image signal analog-to-digital converted by the analog-to-digital conversion means is equal regardless of the magnitude of the digital gain.

4. 4. The analog-to-digital converter according to claim 3, wherein when a predetermined digital gain is M and the digital gain applied to the image signal is N, the setting means obtains the operating frequency by multiplying a predetermined frequency by M / N.

5. 4. The analog-to-digital converter according to claim 3, wherein the digital gain is determined based on at least one of an ISO sensitivity and a correction method including peripheral light amount correction.

6. 2. The analog-to-digital converter according to claim 1, wherein the shooting modes include at least one of a high-quality still image mode, a still image mode, a Log video mode, a video mode, a live view mode, and a Hybrid Log Gamma (HLG) method and a Perceptual Quantization (PQ) method in a High Dynamic Range (HDR) mode.

7. 7. The analog-to-digital converter according to claim 6, wherein the setting means determines the operating frequency by multiplying a predetermined frequency by a first magnification in the PQ method, a second magnification smaller than the first magnification in the Log video mode or the HLG method, a third magnification smaller than the second magnification in the high-quality still image mode, a fourth magnification lower than the third magnification in the still image mode, a fifth magnification lower than the fourth magnification in the video mode, and a sixth magnification lower than the fifth magnification in the live view mode.

8. 2. The analog-to-digital converter according to claim 1, wherein the setting means determines the operating frequency based on at least one of the digital gain and the shooting mode, and if the determined operating frequency is a frequency that the generating means can generate, sets the determined operating frequency without changing it.

9. 2. The analog-to-digital converter according to claim 1, wherein the setting means determines the operating frequency based on at least one of the digital gain and the shooting mode, and if the determined operating frequency exceeds an upper limit of a frequency that the generating means can generate, changes the operating frequency to the upper limit frequency.

10. 2. The analog-to-digital converter according to claim 1, wherein the setting means determines the operating frequency based on at least one of the digital gain and the shooting mode, and when the determined operating frequency is lower than a lower limit frequency that the generating means can generate, changes the lower limit frequency to be the operating frequency.

11. A plurality of the analog-to-digital converters according to any one of claims 1 to 10; A plurality of the pixels; An imaging element comprising:

12. The imaging element according to claim 11 ; a signal processing means for processing the image signal converted by the analog-to-digital converter; 1. An electronic device comprising:

Images