Analog-to-digital converter, imaging element, and electronic equipment

Abstract

To reduce noise influences of a ΔΣ AD converter due to parallel operations.SOLUTION: An analog-to-digital converter comprises: a plurality of analog-to-digital conversion means for performing analog-to-digital conversion using ΔΣ modulation by comparing an image signal outputted from a plurality of pixels with a reference voltage; and a plurality of supply means for supplying any one of a plurality of different reference voltages to each of the plurality of analog-to-digital conversion means. The plurality of supply means supply the reference voltages different from each other to adjacent analog-to-digital conversion means among the plurality of analog-to-digital conversion means.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an analog-to-digital converter, and an imaging element and electronic device using the same, and in particular to an analog-to-digital conversion technique using ΔΣ modulation. [Background technology]

[0002] Conventionally, imaging elements used in digital cameras and the like include CMOS image sensors that use a so-called column AD conversion method, in which analog-to-digital (hereinafter referred to as AD) conversion circuits are arranged in each column of pixels arranged in a matrix to convert the analog signals of the pixels into AD signals and read them out sequentially.

[0003] For example, Patent Document 1 discloses the configuration of a CMOS image sensor that uses ΔΣ modulation in an AD conversion circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 163679 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional technology disclosed in the above-mentioned Patent Document 1, if the power supply circuit is unable to supply the instantaneous current required for the parallel operation of the comparators in the ΔΣ AD conversion circuit, noise caused by voltage fluctuations may occur, degrading image quality.

[0006] The present invention has been made in consideration of the above problems, and has an object to reduce the influence of noise in a ΔΣ AD converter caused by parallel operation. [Means for solving the problem]

[0007] In order to achieve the above object, an analog-to-digital converter of the present invention has a plurality of analog-to-digital conversion means that compares image signals output from a plurality of pixels with a reference voltage and performs analog-to-digital conversion using ΔΣ modulation, and a plurality of supply means that supply one of a plurality of different reference voltages to each of the plurality of analog-to-digital conversion means, and the plurality of supply means supply mutually different reference voltages to adjacent analog-to-digital conversion means among the plurality of analog-to-digital conversion means. Effect of the Invention

[0008] According to the present invention, it is possible to reduce the influence of noise in the ΔΣ AD converter caused by parallel operation. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of an image capturing apparatus according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a block diagram showing a schematic configuration of an image sensor according to a first embodiment. [Diagram 3] FIG. 2 is a block diagram showing a configuration of a read circuit according to the embodiment. [Figure 4] FIG. 1 is a block diagram showing a configuration of a ΔΣ ADC according to an embodiment. [Diagram 5] 3A and 3B are diagrams showing examples of input voltage waveforms and output voltage waveforms of a comparator according to the first embodiment. [Figure 6] FIG. 11 is a block diagram showing a schematic configuration of an image sensor according to a second embodiment. [Figure 7] FIG. 11 is a diagram showing a method for controlling switching of a reference voltage in the second embodiment. [Figure 8] FIG. 13 is a block diagram showing the configuration of a ΔΣ ADC in a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] <First embodiment> 1 is a block diagram showing the configuration of an imaging device using an imaging element according to a first embodiment of the present invention. Note that the imaging device to which the present invention can be applied may be any electronic device equipped with a camera function, and may be, for example, a camera such as a digital camera or a digital video camera, a camera-equipped mobile phone, a camera-equipped computer, a game machine, etc.

[0012] 1, lens unit 101 includes a plurality of lenses, such as a zoom lens and a focus lens, and an aperture, and zoom control, focus control, aperture control, and the like are performed by a drive device 102. An optical image of a subject incident via lens unit 101 is formed on an image sensor 105.

[0013] The lens unit 101 may be configured as an integral part of the imaging device, or may be configured to be detachable. The mechanical shutter 103 is controlled by a shutter driving device 104. The imaging element 105 photoelectrically converts the optical image of the subject formed by the lens unit 101, and outputs an image signal.

[0014] The signal processing circuit 106 performs digital gain processing for applying digital gain to the image signal output from the image sensor 105, various corrections, data compression, etc., and outputs image data. The memory unit 107 is used to temporarily store image data. The system control unit 108 performs various calculations and controls the entire imaging device. The I / F unit 109 is an interface for recording or reading data to the recording medium 110, which is a semiconductor memory such as a flash memory for holding image data, etc., and is configured to be removable. The display unit 111 displays various information and captured images.

[0015] Next, the operation of the imaging device having the above configuration during shooting will be briefly described. When a main power supply (not shown) is turned on, the power supply of the system control unit 108 is turned on, and further the power supply of the imaging system circuits such as the signal processing circuit 106 is turned on. Then, when an instruction to shoot is given by pressing a release button (not shown), the shooting operation is started. When the shooting operation is completed, the image signal output from the image sensor 105 is subjected to image processing including various corrections and digital gain processing in the signal processing circuit 106, and the obtained image data is written to the memory unit 107 under the instruction of the system control unit 108. The image data held in the memory unit 107 is recorded in a removable recording medium 110 such as a semiconductor memory via the I / F unit 109 under the control of the system control unit 108.

[0016] Furthermore, the ROW image data may be sent to a computer or the like via an external I / F unit (not shown), and image processing may be performed in the computer or the like.

[0017] FIG. 2 is a block diagram showing a schematic configuration of the image sensor 105 in this embodiment. The image sensor 105 includes a pixel section 200 , a vertical scanning section 202 , a timing generator (TG) 203 , a circuit control section 204 , a CLK generating circuit section 205 , column output lines 206 , a readout section 207 , and an output section 209 .

[0018] In the pixel section 200, a plurality of pixels 201 are arranged in a matrix. For ease of explanation, the pixels 201 are shown as a 4×4 pixel array in the pixel section 200, but in practice, a large number of pixels, for example, several million or more, are arranged. The signal readout section 207 has a plurality of readout circuits 208.

[0019] The vertical scanning unit 202 selects the pixels 201 of the pixel unit 200 on a row-by-row basis, and supplies a plurality of driving signals to each pixel 201 of the selected row. As a result, pixel signals of the pixels 201 of the selected row are output to a signal readout unit 207 via column output lines 206. The output pixel signals are converted into digital signals in each readout circuit 208, and output to the outside of the image sensor 105 via an output unit 209.

[0020] The readout circuit 208 converts the input pixel signal into a digital signal value by AD conversion at a predetermined bit rate using a so-called ΔΣ AD conversion method. An output unit 209 converts the digital signal value of each pixel into a predetermined signal format and outputs it from a transmission line to the outside of the image sensor 105 .

[0021] The TG 203 sends a timing signal to the vertical scanning unit 202, and the vertical scanning unit 202 generates a control signal for driving the pixels 201 based on the timing signal, and drives the pixels 201. The circuit control unit 204 controls the CLK generation circuit unit 205 and the signal readout unit 207 based on the timing signal from the TG 203. In addition, the CLK generation circuit unit 205 generates a clock signal to be supplied to the signal readout unit 207 based on the clock signal supplied from the TG 203 and the control by the circuit control unit 204.

[0022] FIG. 3 is a block diagram showing a configuration of each read circuit 208 shown in FIG. The readout circuit 208 includes an analog-to-digital converter (ΔΣADC) 300 that uses ΔΣ modulation, and a digital filter 301. The ΔΣADC 300 converts pixel signals input via the column output lines 206 into digital signals using ΔΣ modulation. The digital filter 301 removes out-of-band quantization noise that has been shifted to higher frequencies by the ΔΣ modulation. It also performs thinning and moving averaging of the high-rate output of the ΔΣADC 300 to reduce the output rate and convert it into a multi-bit signal value.

[0023] FIG. 4 is a block diagram showing a configuration of the ΔΣ ADC 300 shown in FIG. As shown in FIG. 4, the ΔΣ ADC 300 includes a subtraction circuit 400, an integration circuit 401, a comparator 402, a digital-to-analog converter (DAC) 403, and a reference voltage switching unit 404.

[0024] The subtraction circuit 400 outputs the difference between the pixel signal input via the column output line 206 and the output signal of the DAC 403 to the integration circuit 401. However, a sample-and-hold circuit may be provided between the column output line 206 and the subtraction circuit 400. In that case, the pixel signal output from the sample-and-hold circuit is input to the subtraction circuit 400.

[0025] The integrating circuit 401 includes an integrator that integrates an input signal from the subtracting circuit 400. As the integrating circuit 401, a gm-C integrating circuit using a transconductor, an RC integrating circuit using an operational amplifier, or the like, which is a general integrating circuit, can be used.

[0026] The comparator 402, in synchronization with the clock signal, compares the reference voltage Vref1 or Vref2 output from the reference voltage switching unit 404 with the voltage signal output from the integrating circuit 401, and outputs the comparison result as a 1-bit digital signal. For example, if the voltage signal output from the integrating circuit 401 is lower than the reference voltage Vref1 or Vref2, it outputs 0, and if it is equal to or higher than the reference voltage Vref1 or Vref2, it outputs 1. This digital signal is supplied to the digital filter 301 and the DAC 403.

[0027] The DAC 403 converts the digital signal output from the comparator 402 into a predetermined analog signal amount and outputs it to the subtraction circuit 400. For example, when the digital signal output is 1, an analog signal of a predetermined level is output. Note that various circuits can be used as the configuration of the digital-to-analog conversion circuit. The subtraction circuit 400, the integration circuit 401, the comparator 402, and the DAC 403 form a feedback loop.

[0028] The reference voltage switching unit 404 receives a control signal output from the circuit control unit 204, switches between the reference voltages Vref1 and Vref2, and supplies either one of the voltages to the comparator 402. The circuit control unit 204 controls the reference voltage switching unit 404, whereby the comparators 402 operating in parallel perform AD conversion processing using a plurality of types of reference voltages.

[0029] FIG. 5 shows an example of an input voltage waveform and an output voltage waveform of the comparator 402 in the first embodiment.

[0030] 5 shows an example of a part of a process in which pixel signals of the same level input to the ΔΣADC 300 via the column output line 206 are ΔΣAD converted using different reference voltages Vref. In reality, such a waveform pattern is repeated for a predetermined period of time.

[0031] Figures 5(a) and (b) show the voltage waveform on the input terminal side, that is, the output voltage of the integrating circuit 401, and the reference voltage. Also, Figure 5(c) shows the ΔΣ modulated digital signal waveform on the output terminal side corresponding to Figure 5(a), and Figure 5(d) shows the ΔΣ modulated digital signal waveform on the output terminal side corresponding to Figure 5(b). Also, in Figure 5, the time on the horizontal axis is expressed as one clock cycle.

[0032] 5(a) and (b), the states of the ΔΣADCs 300 are the same at the start of the ΔΣ AD conversion process (immediately after each circuit is reset), so the voltage input to the comparator 402 via the subtraction circuit 400 and the integration circuit 401 is also at the same level at time 0. In FIGS. 5(a) and (b), this voltage is illustrated as 0.3 V.

[0033] 5(a), the reference voltage of the comparator 402 is Vref1=0.4 V, and in the example shown in Fig. 5(b), the reference voltage of the comparator 402 is Vref2=0.6 V. However, in the embodiment of the present invention, Vref1=0.4 V and Vref2=0.6 V are merely examples, and in practice, they are appropriately determined in accordance with the design voltage range of the image sensor 105.

[0034] Since the output digital signal of the comparator 402 is synchronized with the clock signal, when pixel signals of the same level are input to the ΔΣADCs 300 operating in parallel, each comparator 402 will synchronously output the same digital signal. At this time, the power supply circuit may not be able to supply the instantaneous current required for the operation of each comparator 402, and noise may occur due to instantaneous voltage fluctuations. When there are a particularly large number of comparators 402 operating in parallel, such as in the image sensor 105, such kickback noise is superimposed and propagates inside and outside the readout circuit 208, ultimately degrading the image quality of the output image.

[0035] 5, in this embodiment, different reference voltages Vref1 and Vref2 are divided and supplied to multiple comparators 402. As a result, even if pixel signals of the same level are input to the ΔΣADC 300, the output voltage waveforms of the integration circuit 401 operate differently, as shown in FIGS.

[0036] In Figures 5(a) and (b), at time 0, the output voltage of the integrator circuit 401 is the same, but because the reference voltages are different, the timing at which the output of the comparator 402 is next inverted differs, being time 1 in Figure 5(a) and time 2 in Figure 5(b).

[0037] Even when comparing FIGS. 5(c) and (d), the digital signal waveforms change at different timings, so that it is possible to reduce kickback noise in the circuit system and improve the image quality of the image sensor 105.

[0038] In the case of converting an optical image of a subject formed on the image sensor 105 into a pixel signal as in this embodiment, the pixel signals of adjacent pixels 201 tend to be at the same level. For this reason, the circuit control unit 204 performs switching control so that the reference voltages are different from each other in the readout circuit 208 that reads out the signals of adjacent pixels 201, and thereby the kickback noise reduction effect described above can be easily obtained.

[0039] As described above, according to the first embodiment, it is possible to reduce the influence of noise in the ΔΣ ADCs due to parallel operation.

[0040] In addition, the output signal of the comparator 402 is further processed by the downstream digital filter 301. More specifically, the digital signal that has been ΔΣ modulated at the oversampling rate is subjected to multiple moving average processes, thereby converting it into a multi-bit signal value for each pixel. For this reason, in the process of digitally filtering the ΔΣ modulated signal, phase shifts caused by different reference voltages such as those shown in Figures 5(c) and (d) are not an issue.

[0041] <Second embodiment> Next, a second embodiment of the present invention will be described. In the above-described first embodiment, since the signals of adjacent pixels 201 tend to be pixel signals of the same level, a configuration has been described in which the circuit control unit 204 performs switching control to supply different reference voltages to the readout circuit 208 that reads out the signals of the adjacent pixels 201.

[0042] On the other hand, in the second embodiment, a case will be described in which the pixel 201 is provided with a color filter, and the reference voltage switching control is performed so that the reference voltages of pixels provided with color filters having the same spectral characteristics are different. Note that the overall configuration of the imaging device is similar to that described in the first embodiment with reference to FIG. 1, and therefore a description thereof will be omitted.

[0043] Fig. 6 is a block diagram showing a schematic configuration of an image sensor 105 according to the second embodiment. Note that the same components as those in the image sensor 105 shown in Fig. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate. The image sensor 105 in the second embodiment has a configuration including two signal readout units 207a and 207b for a pixel unit 200. Furthermore, the signal readout unit 207a includes readout circuits 208a, 208b, 208c, and 208d, and selection circuits 600a, 600b, 600c, and 600d.

[0044] Moreover, the signal readout unit 207b includes readout circuits 208e, 208f, 208g, and 208h, and selection circuits 600e, 600f, 600g, and 600h. For ease of explanation, 32×4 pixels 201 are shown in the pixel unit 200 in Fig. 6, but in practice, a large number of pixels, for example, more than several million pixels, are arranged.

[0045] Each pixel 201 is provided with a color filter having different spectral characteristics, and three types, red (R), green (G), and blue (B), are indicated. In an image sensor, pixels provided with color filters that transmit R, G, and B light, respectively, are generally arranged in a pattern called a Bayer array, as shown in FIG. 6. In the following description, the pixels 201 provided with color filters that transmit red, green, and blue light are also referred to as "R pixels," "G pixels," and "B pixels," respectively.

[0046] The selection circuits 600a-600h are each connected to four column output lines 206 and one readout circuit 208, and are configured to sequentially select pixel signals of each pixel 201 outputted via the four column output lines 206 and output them to each of the readout circuits 208a-208h. That is, while the vertical scanning section 202 selects a row of the pixel section 200 during one vertical scanning period, the selection circuits 600a-600h sequentially select pixel signals outputted via the four column output lines 206 and perform AD conversion processing in the readout circuits 208a-208h.

[0047] As shown in FIG. 6, the column output lines 206 connected to the selection circuits 600a to 600d are configured to be connected to R pixels and G pixels, and the column output lines 206 connected to the selection circuits 600e to 600h are configured to be connected to B pixels and G pixels.

[0048] FIG. 7 is a reference voltage switching control table in the second embodiment, illustrating patterns of reference voltages used by each of the read circuits 208a to 208h.

[0049] FIG. 7 is a diagram showing a reference voltage switching control method in one vertical scanning period when pixel signals of R pixels are output to readout circuits 208a to 208d and pixel signals of G pixels are output to readout circuits 208e to 208h and read out in parallel.

[0050] In this case, among the readout circuits 208a to 208d that perform AD conversion on signals from R pixels having the same spectral characteristics, Vref1 and Vref2 are supplied alternately so that the reference voltages of adjacent readout circuits are as different as possible. On the other hand, among the readout circuits 208e to 208h that perform AD conversion on signals from G pixels, Vref1 and Vref2 are supplied alternately so that the reference voltages of adjacent readout circuits are as different as possible.

[0051] In this way, even if the color of pixel signals processed by adjacent readout circuits 208 is the same, kickback noise can be reduced by performing switching control so that the reference voltages of adjacent circuit control units 204 to which pixel signals of the same color are input are different.

[0052] The above-described switching control method is merely an example, and various modifications can be made within the scope of the present invention in accordance with the design and characteristics of each image sensor and its image quality.

[0053] For example, in the configuration of the image sensor 105 of the second embodiment, various combination patterns of pixel signals to be AD converted in parallel can be considered depending on the wiring configuration / scanning method from the vertical scanning unit 202 to each pixel 201 and the selection order of the selection circuits 600a to 600h. However, among the pixels 201 equipped with color filters having the same type of spectral characteristics, the signals output from adjacent pixels 201 tend to be pixel signals of the same level. For this reason, the circuit control unit 204 performs switching control so that the reference voltages of the adjacent circuit control units 204 to which the signals output from the adjacent pixels 201 are input are different from each other, thereby achieving a reduction effect of kickback noise.

[0054] In addition, since the image sensor 105 generally adds / thins out pixel signals in the vertical / horizontal directions for each drive mode, the combination pattern of pixel signals to be AD converted in parallel also changes depending on the drive mode. Therefore, the circuit control unit 204 can obtain a kickback noise reduction effect according to the drive mode by controlling the switching of the reference voltage according to the drive mode of the image sensor 105 determined by the system control unit 108. Furthermore, in accordance with the above concept, the present invention is applicable regardless of the spectral characteristics of the color filters and the method of arranging them.

[0055] In the first and second embodiments, two types of voltage values ​​are used as the reference voltage, but the present invention is not limited to this, and three or more types of voltage values ​​may be used as the reference voltage and selectively supplied to each comparator 402. In this case, the phase of the digital output signal of the comparator 402 is further dispersed, and the occurrence of kickback noise can be further reduced.

[0056] Also, instead of the circuit control unit 204 and the reference voltage switching unit 404, whether Vref1 or Vref2 is to be used may be fixed in the circuit so that the reference voltages are different even when pixel signals of the same color are used in adjacent readout circuits 208. In this case, readout circuits 208 in which Vref1 is input to the comparator 402 as shown in Fig. 8(a) and readout circuits 208 in which Vref2 is input to the comparator 402 as shown in Fig. 8(b) are alternately arranged in the signal readout unit 207. In this case, it is not possible to control the switching of the reference voltage according to the drive mode of the image sensor 105, but the circuit configuration of the readout circuits 208 can be simplified.

[0057] <Summary> The disclosure of this embodiment includes the following configuration.

[0058] (Configuration 1) A plurality of analog-to-digital conversion means for comparing image signals output from a plurality of pixels with a reference voltage and performing analog-to-digital conversion using ΔΣ modulation; a plurality of supplying means for supplying one of a plurality of different reference voltages to each of the plurality of analog-to-digital conversion means; The analog-to-digital converter according to claim 1, wherein the plurality of supplying means supply different reference voltages to adjacent analog-to-digital conversion means among the plurality of analog-to-digital conversion means.

[0059] (Configuration 2) The analog-to-digital converter according to configuration 1, wherein each of the plurality of supplying means has a selection means for selecting one of the plurality of different reference voltages, and supplies the reference voltage selected by the selection means to the plurality of analog-to-digital conversion means.

[0060] (Configuration 3) 2. The analog-to-digital converter according to configuration 1, wherein the plurality of supplying means are wirings for supplying different reference voltages to the adjacent analog-to-digital conversion means.

[0061] (Configuration 4) Each of the plurality of pixels is covered with a color filter having one of a plurality of types of spectral characteristics; 4. The analog-to-digital converter according to any one of configurations 1 to 3, wherein among the plurality of analog-to-digital conversion means, adjacent analog-to-digital conversion means are configured to perform analog-to-digital conversion on image signals output from pixels covered by color filters having the same type of spectral characteristics.

[0062] (Configuration 5) The analog-to-digital converter according to any one of configurations 1 to 4; The plurality of pixels. An imaging element comprising:

[0063] (Configuration 6) The imaging element according to configuration 5, a control means for switching a reference voltage to be supplied to the plurality of analog-to-digital conversion means in accordance with a drive mode of the imaging element; 1. An electronic device comprising:

[0064] The invention is not limited to the above-described embodiment, and various modifications and variations are possible without departing from the spirit and scope of the invention. Therefore, the present invention is appended hereto in order to make the scope of the invention public. [Explanation of symbols]

[0065] 105: imaging element, 106: signal processing circuit, 203: timing generator, 204: circuit control unit, 205: CLK generation circuit unit, 207, 207a, 207b: readout circuit unit, 208, 208a to 208h: readout circuits, 300: ΔΣADC, 301: digital filter, 400: subtraction circuit, 401: integration circuit, 402: comparator, 403: DAC, 404: reference voltage switching unit, 600a to 600h: selection circuit

Claims

1. a plurality of analog-to-digital conversion means for comparing image signals output from a plurality of pixels with a reference voltage and performing analog-to-digital conversion using ΔΣ modulation; a plurality of supplying means for supplying one of a plurality of different reference voltages to each of the plurality of analog-to-digital conversion means; 2. An analog-to-digital converter according to claim 1, wherein the plurality of supplying means supply different reference voltages to adjacent analog-to-digital converting means among the plurality of analog-to-digital converting means.

2. 2. The analog-to-digital converter according to claim 1, wherein each of the plurality of supplying means has a selection means for selecting one of the plurality of different reference voltages, and supplies the reference voltage selected by the selection means to the plurality of analog-to-digital conversion means.

3. 2. The analog-to-digital converter according to claim 1, wherein the plurality of supplying means are wirings for supplying different reference voltages to the adjacent analog-to-digital conversion means.

4. Each of the plurality of pixels is covered with a color filter having one of a plurality of types of spectral characteristics; 2. The analog-to-digital converter according to claim 1, wherein among the plurality of analog-to-digital conversion means, adjacent analog-to-digital conversion means are each configured to perform analog-to-digital conversion on image signals output from pixels covered by color filters having the same type of spectral characteristics.

5. An analog-to-digital converter according to claim 1; The plurality of pixels. An imaging element comprising:

6. The imaging element according to claim 5 ; a control means for switching a reference voltage to be supplied to the plurality of analog-to-digital conversion means in accordance with a drive mode of the imaging element; 1. An electronic device comprising:

Images