Self-luminous display device and driving method of self-luminous display device

Abstract

To provide a self-luminous display device allowing narrower frame and size reduction.SOLUTION: The self-luminous display device comprises: a first transistor controlled using a second control signal obtained by shifting a first control signal and connected between an image data signal line and a first node; a second transistor connected between the first node and a second node; a third transistor controlled using the first control signal and connected between the second node and a gate electrode of the second transistor; a fourth transistor controlled using a fourth control signal obtained by shifting a third control signal and connected between a drive power source line and the second node; a fifth transistor controlled using the third control signal and connected to the first node; a light-emitting element connected to a first electrode of the fifth transistor; and a sixth transistor controlled using the third control signal and connected to the light-emitting element and the first electrode.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a self-luminous display device and a method for driving the self-luminous display device.

Background Art

[0002] In recent years, self-luminous display devices have been mounted on televisions, smartphones, digital signage (electronic billboards, electronic advertising boards, etc.) and the like, and have become widespread. A self-luminous display device includes, for example, a plurality of pixels and a driver for driving the plurality of pixels. Each of the plurality of pixels includes, for example, a plurality of transistors, a capacitive element, and a light-emitting element. The light-emitting element is, for example, a light-emitting diode (LED), a micro light-emitting diode (micro LED), or an organic electroluminescence (EL) element. In the self-luminous display device, a driver supplies a voltage to each of the plurality of pixels, and a current corresponding to the supplied voltage value flows through the light-emitting elements included in each of the plurality of pixels. Each of the light-emitting elements emits light with a luminance corresponding to the current flowing through the light-emitting element, and a pixel including the light-emitting element can display an image with a gradation corresponding to the luminance.

[0003] For example, Patent Document 1 discloses a pixel including six transistors, one capacitive element, and one light-emitting element, and a self-luminous display device including the pixel. The self-luminous display device described in Patent Document 1 can control the light emission of pixels using, for example, four drive circuits and display an image in a display area.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a display device having a large number of drive circuits, the ratio of the area for arranging drive circuits (e.g., the frame area) in the display device becomes larger than the ratio of the display area in the display device. That is, in a display device having a large number of drive circuits, the frame area becomes large, and it is difficult to miniaturize the display device.

[0006] In view of such problems, one object of an embodiment of the present invention is to provide a self-emitting display device capable of narrow bezeling and miniaturization, and a driving method of a self-emitting display device using the self-emitting display device capable of narrow bezeling and miniaturization.

Means for Solving the Problems

[0007] A self-emitting display device according to an embodiment of the present invention is controlled using a second control signal obtained by shifting a first control signal, and includes a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a third transistor controlled using the first control signal and electrically connected between the second node and a gate electrode of the second transistor, a fourth transistor controlled using a fourth control signal obtained by shifting a third control signal and electrically connected between a drive power line to which a drive voltage is supplied and the second node, a fifth transistor controlled using the third control signal and electrically connected to the first node, a light-emitting element electrically connected to a first electrode of the fifth transistor, and a sixth transistor controlled to supply an initialization voltage to the light-emitting element and the first electrode using the third control signal and electrically connected to the light-emitting element and the first electrode.

[0008] A driving method for an organic light-emitting display device according to an embodiment of the present invention includes at least a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a third transistor electrically connected between the second node and a gate electrode of the second transistor, a fourth transistor electrically connected to the second node, a fifth transistor electrically connected to the first node, a light-emitting element electrically connected to a first electrode of the fifth transistor, and a sixth transistor electrically connected to the light-emitting element and the first electrode. The driving method sequentially shifts and outputs a first control signal and a second control signal, sequentially shifts and outputs a third control signal and a fourth control signal, controls the third transistor using the first control signal, controls the first transistor using the second control signal, controls the fifth transistor and the sixth transistor using the third control signal, and controls the fourth transistor using the fourth control signal.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in many different modes and is not to be construed as being limited to the description of the embodiments exemplified below. Also, the drawings are schematically represented in terms of the width, thickness, shape, configuration, etc. of each part compared to the actual mode in order to make the explanation clearer, but this is merely an example and does not limit the interpretation of the present invention. Note that the letters “first” and “second” attached to each element are for convenience of distinguishing each element and do not have any further meaning unless otherwise specified.

[0011] Also, in this specification, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0012] The self-emitting display device according to an embodiment of the present invention is, for example, a light-emitting device using an EL element as a light-emitting element.

[0013] <1. First Embodiment> <1-1. Outline of the Self-Emitting Display Device 10> Referring to FIGS. 1 and 2, an outline of the self-emitting display device 10 according to the first embodiment will be described. FIGS. 1 and 2 are schematic diagrams showing the configuration of the self-emitting display device 10 according to the first embodiment. The configuration of the self-emitting display device 10 shown in FIGS. 1 and 2 is an example, and the configuration of the self-emitting display device 10 is not limited to the configuration shown in FIGS. 1 and 2.

[0014] As shown in FIG. 1 or FIG. 2, the self-emitting display device 10 includes an array substrate 100, a flexible printed circuit board 160 (FPC 160), and an IC chip 170. Further, the self-emitting display device 10 includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0015] In the display area 22, a plurality of pixels 180 are arranged in a matrix. The pixel 180 is the minimum unit that constitutes a part of the image to be displayed in the display area 22. Each of the plurality of pixels 180 may correspond to, for example, a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may be formed by three sub-pixels. There is no limitation on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 is, for example, a stripe arrangement. The arrangement of the self-emitting display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0016] The sub-pixel R, the sub-pixel G, and the sub-pixel B are configured to display images of different colors. For example, each of the sub-pixel R, the sub-pixel G, and the sub-pixel B may include a light-emitting element including a light-emitting layer that emits the three primary colors of red, green, and blue. An arbitrary voltage or current is supplied to each of the three sub-pixels, and the self-emitting display device 10 can display an image.

[0017] In the peripheral region 24, a source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130 are provided. Each of the source driver circuit 110, the gate driver circuit 120, and the light emission control circuit 130 is connected to the terminal portion 150 using a connection wiring 341. The peripheral region 24 may be called a frame region. The connection wiring 341 may be called the connection wiring 341 alone, or a bundle of a plurality of connection wirings 341 may be called the connection wiring 341.

[0018] In the terminal region 26, a terminal portion 150 and an FPC 160 electrically connected to the terminal portion 150 are provided. The terminal region 26 is a region on the opposite side to the display region 22 with respect to the peripheral region 24 in the first direction D1.

[0019] The FPC 160 is connected to an external device (not shown) outside the self-emitting display device 10. Therefore, the self-emitting display device 10 is connected to the external device via the FPC 160 and the terminal portion 150 connected to the FPC. A control signal and a voltage are transmitted from the external device to the self-emitting display device 10 via the FPC 160 and the terminal portion 150 connected to the FPC. The self-emitting display device 10 drives each pixel 180 provided in the self-emitting display device 10 using the received control signal and voltage from the external device. As a result, the self-emitting display device 10 can display an image in the display region 22.

[0020] The IC chip 170 is provided, for example, on the FPC 160. The IC chip 170 supplies signals, voltages, etc. for driving each pixel 180 to the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the pixel 180 (pixel circuit 181) via the FPC 160, the terminal portion 150, and the connection wiring 341.

[0021] In the first embodiment, each of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the IC chip 170 may be individually referred to as a control circuit, or a circuit group including some or all of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130, and the IC chip 170 may be referred to as a control circuit.

[0022] <1-2. Configuration of Source Driver Circuit 110> Referring to FIGS. 1 and 2, the outline of the source driver circuit 110 will be described. As shown in FIG. 1 or FIG. 2, the source driver circuit 110 is provided at a position adjacent to the display area 22 in the first direction D1 (column direction). The image data signal lines 321 extend from the source driver circuit 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0023] As shown in FIG. 2, the source driver circuit 110 includes, for example, a plurality of selection circuits 112. Each of the plurality of selection circuits 112 is controlled based on, for example, an on signal and an off signal supplied to the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB. The selection circuit 112 is selected by the on signal supplied to the selection signal (for example, the selection signal MUXR), and supplies the image data signal SL(m + 1) including the data signal VDATA supplied to the input terminal 114 to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. Although details will be described later, the data signal VDATA includes, for example, the voltage RDATA(n), the voltage GDATA(n), or the voltage BDATA(n).

[0024] The selection circuit 112 is, for example, a switch 118 including an input terminal 114 and an output terminal 116. For example, an on signal supplied from the IC chip 170 to the selection signal MUXR conducts (connects) the input terminal 114 and the output terminal 116, and an off signal supplied from the IC chip 170 to the selection signal MUXR disconnects (non-connects) the input terminal 114 and the output terminal 116. The on signal is a signal including a voltage that conducts the input terminal 114 and the output terminal 116, and the off signal is a signal including a voltage that disconnects the input terminal 114 and the output terminal 116.

[0025] In the present invention, the on signal may be high (HI), and the off signal may be low (LO), or the on signal may be low (LO), and the off signal may be high (HI).

[0026] <1-3. Configuration of Gate Driver Circuit 120> Referring to FIGS. 1 and 2, an overview of the gate driver circuit 120 will be described. As shown in FIG. 1 or FIG. 2, the gate driver circuit 120 is provided at a position adjacent to the display area 22 in the second direction D2 (row direction). The scanning signal lines 329, 330, 331, 332, and 333 extend from the gate driver circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0027] As shown in FIG. 2, the gate driver circuit 120 includes a plurality of shift registers (for example, shift registers 121, 122, and 123). The shift registers 121, 122, and 123 sequentially supply scanning signals with different timings (for example, scanning signal G(n), scanning signal G(n + 1), scanning signal G(n + 2), etc.) to each of the scanning signal lines 330, 331, 332, and 333 based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and have a role of driving the pixels 180 (pixel circuits 181) electrically connected to each scanning signal line. The scanning signal G(n) or the operation signal G(n + 2) may be called a first control signal, and the scanning signal G(n + 1) may be called a second control signal.

[0028] For example, the shift register 121 is electrically connected to the shift register 122, and the shift register 122 is electrically connected to the shift register 123. The shift register 121 is electrically connected to the scanning signal line 330 and supplies, for example, the scanning signal G(n) to the scanning signal line 330. Similar to the shift register 121, the shift register 122 is electrically connected to the scanning signal line 331 and supplies, for example, the scanning signal G(n+1) to the scanning signal line 331. The shift register 123 is electrically connected to the scanning signal line 332 and supplies, for example, the scanning signal G(n+2) to the scanning signal line 332. Although not shown, the next-stage shift register electrically connected to the shift register 123 is electrically connected to the scanning signal line 333, and the successive-stage shift registers electrically connected to the next-stage shift register are electrically connected to scanning signal lines different from the aforementioned operation signal lines. The scanning signal G(n+1) includes a pulse width equivalent to that of the scanning signal G(n) and is a signal obtained by shifting the scanning signal G(n). Similar to the scanning signal G(n+1), the scanning signal G(n+2) includes a pulse width equivalent to that of the scanning signal G(n+1) and is a signal obtained by shifting the scanning signal G(n+1).

[0029] <1-4. Configuration of the light emission control circuit 130> Referring to FIGS. 1 and 2, the outline of the light emission control circuit 130 will be described. As shown in FIG. 1 or FIG. 2, the light emission control circuit 130 is adjacent to the display area 22 in the second direction D2 (row direction) and is provided on the side opposite to the position where the gate driver circuit 120 is arranged with respect to the display area 22. The light emission control signal lines 334, 335, 336, and 337 extend from the light emission control circuit 130 in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits 181) arranged in the second direction D2.

[0030] As shown in FIG. 2, the light emission control circuit 130 includes a plurality of shift registers (for example, shift registers 131, 132, and 133). The shift registers 131, 132, and 133 supply, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, light emission control signals with different timings (for example, light emission control signal EM(n), light emission control signal EM(n + 1), light emission control signal EM(n + 2), etc.) to each of the light emission control signal lines 334, 335, 336, and 337 in sequence, and have a role of driving the pixel 180 (pixel circuit 181) electrically connected to each light emission control signal line. The light emission control signal EM(n) or the light emission control signal EM(n + 2) may be called the third control signal, and the light emission control signal EM(n + 1) may be called the fourth control signal.

[0031] For example, the shift register 131 is electrically connected to the shift register 132, and the shift register 132 is electrically connected to the shift register 133. The shift register 131 is electrically connected to the light emission control signal line 334 and supplies, for example, the light emission control signal EM(n) to the light emission control signal line 334. Similarly to the shift register 131, the shift register 132 is electrically connected to the light emission control signal line 335 and supplies, for example, the light emission control signal EM(n + 1) to the light emission control signal line 335, and the shift register 133 is electrically connected to the light emission control signal line 336 and supplies, for example, the light emission control signal EM(n + 2) to the light emission control signal line 336. The pulse width of the light emission control signal EM(n + 1) is the same as that of the light emission control signal EM(n), and the light emission control signal EM(n + 1) is a signal obtained by shifting the light emission control signal EM(n). Similarly, the pulse width of the light emission control signal EM(n + 2) is the same as that of the light emission control signal EM(n + 1), and the light emission control signal EM(n + 2) is a signal obtained by shifting the light emission control signal EM(n + 2).

[0032] <1-5. Configuration of Pixel 180> Referring to FIGS. 3 and 4, the outline of pixel 180 will be described. FIG. 3 is a schematic diagram showing input signals to pixel circuit 181 included in pixel 180. FIG. 4 is a circuit diagram showing the configuration of pixel circuit 181. FIGS. 3 and 4 show, as an example, the configuration of pixel circuit 181 of pixel 180 shown in FIGS. 1 and 2. The configurations of pixel 180 and pixel circuit 181 are not limited to the configurations shown in FIGS. 3 and 4. For configurations that are the same as or similar to those in FIGS. 1 and 2, the description here will be omitted.

[0033] Pixel circuit 181 is a circuit for driving pixel 180. The pixel circuits of sub-pixels R, G, and B included in pixel 180 are the same as pixel circuit 181, except that the colors emitted by light-emitting elements OLED are different. In the following description, as an example, a light-emitting element OLED that emits red light will be mainly described.

[0034] As shown in FIG. 3, scanning signals G(n), G(n + 1), image data signal SL(m + 1), emission control signals EM(n), EM(n + 1), and initialization voltage VINI are supplied to pixel circuit 181. Also, as a power source for driving pixel 180, driving voltage VDDEL and reference voltage VSSEL are supplied to pixel circuit 181.

[0035] The initialization voltage VINI is supplied to the initialization voltage line VM, the drive voltage VDDEL is supplied to the drive power supply line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. Each of the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS may be electrically connected to, for example, different connection wirings 341, or may be different connection wirings 341. The initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL may be supplied from an external circuit to a plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal portion 150, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS. Also, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL may be supplied from the IC chip 170 to a plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal portion 150, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS. The initialization voltage VINI is smaller than the drive voltage VDDEL. The initialization voltage VINI may be the same as the reference voltage VSSEL. The reference voltage VSSEL is smaller than the drive voltage VDDELL.

[0036] As shown in FIG. 4, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitive element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source electrode and drain electrode) composed of a first electrode and a second electrode. Each of the capacitive element CS and the light-emitting element OLED has a pair of electrodes composed of a first electrode and a second electrode.

[0037] The first transistor T1 is, for example, a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m + 1) to the second transistor T2.

[0038] The second transistor T2 is a so-called drive transistor. The second transistor T2 has a function of flowing a current through the light-emitting element OLED using the input image data signal SL(m + 1) to cause the light-emitting element OLED to emit light.

[0039] The third transistor T3 conducts the second node N2 and the gate electrode 622 of the second transistor T2 (and the second electrode 694 of the capacitor element CS) to supply a drive voltage VDDEL to the gate electrode 622 of the second transistor T2 and has a function of resetting the gate electrode 622 of the second transistor T2. The drive voltage VDDEL is a voltage for driving the pixel and also a reset voltage for resetting the pixel. Further, the third transistor T3 has a function of accumulating charges corresponding to the threshold voltage Vth of the second transistor T2 in the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS.

[0040] The fourth transistor T4 controls the connection and disconnection between the drive power supply line PVDD and the second transistor T2. That is, the fourth transistor T4 has a function of supplying the drive voltage VDDEL to the second transistor T2.

[0041] The fifth transistor T5 controls the connection and disconnection between the second transistor T2 and the light-emitting element OLED. That is, the fifth transistor T5 controls the connection and disconnection between the second transistor T2 and the light-emitting element OLED and has a function of supplying current to the light-emitting element OLED and controlling the light emission and non-light emission of the light-emitting element OLED.

[0042] The sixth transistor T6 supplies an initialization voltage VINI to the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitor element CS and has a function of initializing the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitor element CS.

[0043] The capacitive element CS has a function of holding a charge (first charge) corresponding to, for example, the threshold voltage Vth of the second transistor T2. Further, the capacitive element CS has a function of holding a charge (second charge) corresponding to a data voltage (for example, RDATA(n) (see FIG. 6)) included in the image data signal SL(m+1) input to the gate electrode 622 of the second transistor T2.

[0044] The light-emitting element OLED has diode characteristics and has a function of emitting light based on the current flowing through the light-emitting element OLED (that is, the drain current of the second transistor T2).

[0045] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 331. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 624 of the second transistor T2, and the second electrode 656 of the fifth transistor T5. A scan signal G(n+1) is supplied to the scan signal line 331. The first transistor T1 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scan signal G(n+1). When the signal supplied to the scan signal G(n+1) is low (LO), the first transistor T1 becomes non-conductive. When the signal supplied to the scan signal G(n+1) is high (HI), the first transistor T1 becomes conductive.

[0046] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the first electrode 634 of the third transistor T3 and the 2 electrode 694 of the capacitive element CS. The second electrode 626 is electrically connected to the second node N2, the second electrode 636 of the third transistor T3, and the first electrode 644 of the fourth transistor T4.

[0047] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scanning signal line 330. A scanning signal G(n) is supplied to the scanning signal line 330. The third transistor T3 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal G(n). When the signal supplied to the scanning signal G(n) is low (LO), the third transistor T3 becomes non-conductive. When the signal supplied to the scanning signal G(n) is high (HI), the third transistor T3 becomes conductive.

[0048] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the emission control signal line 335. The second electrode 646 is electrically connected to the drive power supply line PVDD. A drive voltage VDDEL is supplied to the drive power supply line PVDD. An emission control signal EM(n + 1) is supplied to the emission control signal line 335. The fourth transistor T4 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the emission control signal EM(n + 1). In the first embodiment, when the signal supplied to the emission control signal EM(n + 1) is low (LO), the fourth transistor T4 becomes non-conductive, and when the signal supplied to the emission control signal EM(n + 1) is high (HI), the fourth transistor T4 becomes conductive.

[0049] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the emission control signal line 334. The first electrode 654 is electrically connected to the second electrode 666 of the sixth transistor T6, the first electrode 692 of the capacitor element CS, and the second electrode 684 of the light-emitting element OLED. An emission control signal EM(n) is supplied to the emission control signal line 334. The fifth transistor T5 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the emission control signal EM(n). In the first embodiment, when the signal supplied to the emission control signal EM(n) is low (LO), the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the emission control signal EM(n) is high (HI), the fifth transistor T5 is in a conductive state.

[0050] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the emission control signal line 334. The first electrode 664 is electrically connected to the initialization voltage line VM. As described above, an emission control signal EM(n) is supplied to the emission control signal line 334, and an initialization voltage VINI is supplied to the initialization voltage line VM. Similar to the fifth transistor T5, the sixth transistor T6 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the emission control signal EM(n). In the first embodiment, when the signal supplied to the emission control signal EM(n) is low (LO), the sixth transistor T6 is in a conductive state, and when the signal supplied to the emission control signal EM(n) is high (HI), the sixth transistor T6 is in a non-conductive state.

[0051] The first electrode 682 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, a reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0052] In the self-emitting display device 10, the conductive state of the transistor means, for example, that the source electrode and the drain electrode of the transistor are conductive and the transistor indicates an on state, and the non-conductive state of the transistor means that the source electrode and the drain electrode of the transistor are non-conductive and the transistor indicates an off state. Note that in each transistor, the source electrode and the drain electrode may be interchanged according to the voltage or potential supplied to each electrode. Also, it is easily understood by those skilled in the art that even when the transistor is in the off state, a slight current may flow, such as a leakage current.

[0053] Each transistor shown in FIG. 4 can have a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor characteristics, in the channel region. For example, the channel region of each transistor has low-temperature polysilicon (LTPS). In the self-emitting display device 10, each transistor is formed using a thin-film transistor (TFT). Each transistor may have either an n-channel type field-effect transistor or a p-channel type field-effect transistor. The self-emitting display device 10 may appropriately adapt the configuration of the transistor, the connection of the holding capacitance, the power supply voltage, etc., according to the application and specifications. In the first embodiment, the first transistor T1 to the fifth transistor T5 are n-channel type field-effect transistors, and the sixth transistor T6 is a p-channel type field-effect transistor.

[0054] <1-6. Driving method of the self-emitting display device 10> Referring to FIGS. 5(A) to 14, a driving method of the self-emission type display device 10 will be described. FIGS. 5(A), 5(B), 6, and 13 are schematic diagrams showing the timing charts of the self-emission type display device 10. FIGS. 7 to 12 are schematic diagrams showing the operating states of the pixel 180 (pixel circuit 181) at the timing shown in FIG. 6. FIG. 14 is a schematic diagram showing the operating state of the pixel 180 (pixel circuit 181) at the timing shown in FIG. 13. The driving method of the self-emission type display device 10 is not limited to the driving methods shown in FIGS. 5(A) to 14. For the configurations identical or similar to those in FIGS. 1 to 4, the descriptions here will be omitted. Note that the horizontal axis of the timing chart is time (TIME).

[0055] FIG. 5(A) is, for example, a timing chart of the driving method of the self-emission type display device 10 when the self-emission type display device 10 is driven at a high frequency. The high frequency is, for example, 60 Hz, which is the frequency at which 1 frame (1 FRAME) is driven at 60 Hz. FIG. 5(A) shows, for example, the current frame (Kth FRAME), a part of the frame immediately before the current frame (K-1st FRAME), and a part of the frame immediately after the current frame (K+1st FRAME). The driving method shown in FIG. 5(A) is called, for example, high-frequency driving.

[0056] As shown in FIG. 5(A), the driving method of the self-emission type display device 10 includes at least a reset period PRS, a sampling period PWR, and a light emission period PEM within 1 frame. In the pixel 180 (pixel circuit 181) included in the self-emission type display device 10, the sampling period PWR is executed after the reset period PRS, and the light emission period PEM is executed after the sampling period PWR. Also, after the light emission period PEM of the frame immediately before the current frame, the reset period PRS of the current frame is executed, and after the light emission period PEM of the current frame, the reset period PRS and the sampling period PWR of the frame immediately after the current frame are executed.

[0057] FIG. 5(B) is a timing chart of a driving method of the self-luminous display device 10 when the self-luminous display device 10 is driven at a low frequency. The low frequency is, for example, 1 Hz, which is the frequency at which 1 frame (1 FRAME) is driven at 1 Hz. The driving method shown in FIG. 5(B) is, for example, called low-frequency driving. Low-frequency driving is a driving method in which, compared with high-frequency driving, during the light-emitting period PEM, a period for displaying black (black period PBWR) is executed multiple times. In low-frequency driving, the driving other than the black period PBWR is the same as that in high-frequency driving.

[0058] FIG. 6 is a diagram for explaining the reset period PRS, the sampling period PWR, and the light-emitting period PEM of the driving method of the pixel 180 (pixel circuit 181) of the self-luminous display device 10. FIG. 6 shows the light-emitting period PEM of the frame (K - 1st FRAME) one frame before the current frame, the reset period PRS, the sampling period PWR, and the light-emitting period PEM of the current frame (Kth FRAME). Further, FIG. 6 shows a plurality of one horizontal periods (horizontal period N - 1st HP, horizontal period Nth HP, horizontal period N + 1st HP, horizontal period N + 2nd HP, horizontal period N + 3rd HP, horizontal period N + 4th HP). One horizontal period is, for example, a period during which an image data signal SL(m + 1) including a data signal VDATA is input to a pixel (pixel circuit) electrically connected to one scanning signal line, and the image data signal SL(m + 1) including the data signal VDATA is input to the pixels (pixel circuits) electrically connected to all the scanning signal lines, and the image of the current frame corresponding to 1 FRAME is displayed.

[0059] With reference to FIGS. 6 to 12, an example of a driving method in which the pixel 180 (pixel circuit 181) displays an image based on a voltage RDATA(n) included in the data signal VDATA input during one horizontal period N + 1st HP will be described.

[0060] First, the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB will be described. In accordance with each horizontal period, an image data signal SL(m + 1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data including, for example, a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. The voltage VDM is a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. In each horizontal period, for example, using the selection signal MUXR, the voltage RDATA is selected and supplied to the image data signal line, using the selection signal MUXG, the voltage GDATA is selected and supplied to the image data signal line, using the selection signal MUXB, the voltage BDATA is selected and supplied to the image data signal line. During a period when data is not selected using the selection signal MUXG, the data signal VDATA is maintained at, for example, the voltage VDM.

[0061] Next, with reference to FIGS. 6 and 7, a driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the frame immediately preceding the current frame (K - 1st FRAME) will be described. The light emission period PEM of the frame immediately preceding the current frame (K - 1st FRAME) is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the voltage RDATA(n - 1).

[0062] The gate electrode 622 of the second transistor T2 is supplied with the voltage RDATA(n - 1). The scan signals G(n) and G(n + 1) are supplied with LOW (LO), and the first transistor T1 and the third transistor T3 are in an off state. Also, the fourth transistor T4 is supplied with HIGH (HI) from the light emission control signal EM(n + 1), the fifth transistor T5 and the sixth transistor T6 are supplied with HIGH (HI) from the light emission control signal EM(n), the fourth transistor T4 and the fifth transistor T5 are in an on state, and the sixth transistor T6 is in an off state.

[0063] The second transistor T2 is in an on state based on the voltage RDATA(n - 1). As a result, the second transistor T2 can conduct a current IEL based on the gate-source voltage Vgs and the source-drain voltage Vds corresponding to the voltage RDATA(n - 1).

[0064] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on state, and a current IEL flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the current IEL flows through the light-emitting element OLED, and the light-emitting element OLED emits light.

[0065] Next, referring to FIGS. 6 and 8, a method of driving the pixel 180 (pixel circuit 181) during the reset period PRS of the frame will be described. The reset period PRS is a period in which a driving voltage VDDEL corresponding to the reset voltage and an initialization voltage VINI are written to the pixel 180 (pixel circuit 181) to reset the pixel 180 (pixel circuit 181). The reset period PRS of the frame is a period that overlaps a part of the (N - 1)st horizontal period N - 1stHP and a part of the Nth horizontal period NthHP.

[0066] During the reset period PRS, the scan signal G(n) is supplied from low (LO) to high (HI), and the third transistor T3 is in an on state. The emission control signal EM(n) is supplied from high (HI) to low (LO), the fifth transistor T5 is turned off, and the sixth transistor T6 is in an on state. Also, the fourth transistor T4 remains in an on state, and the first transistor T1 remains in an off state.

[0067] Based on the fifth transistor T5 and the third transistor T3 being turned on, a driving voltage VDDEL is supplied to the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Also, based on the sixth transistor T6 being turned on, an initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS are reset, and the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are initialized. Also, since the fourth transistor T4 is in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and current flows from the initialization voltage line VM to the reference voltage line PVSS. The current flowing through the light-emitting element OLED is generally a current based on the potential difference between the initialization voltage VINI and the reference voltage line PVSS. The potential difference between the initialization voltage VINI and the reference voltage line PVSS is small, and the light-emitting element OLED hardly emits light.

[0068] Although detailed illustration is omitted, when the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 (the potential difference between the gate electrode 622 and the first node N1) becomes the same as the threshold voltage Vth of the second transistor T2, the second transistor T2 turns off. As a result, the difference between the driving voltage VDDEL and the threshold voltage Vth (VDDEL - Vth) is held at the first node N1 and each electrode electrically connected to the first node N1, and the driving voltage VDDEL is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS.

[0069] Next, referring to FIGS. 6 and 9, a driving method of the pixel 180 (pixel circuit 181) during the period between the reset period PRS and the sampling period PWR of the frame will be described. The period between the reset period PRS and the sampling period PWR of the frame is a period overlapping with a part of one horizontal period NthHP.

[0070] During the period between the reset period PRS and the sampling period PWR of the frame, the emission control signal EM(n + 1) is supplied from high (HI) to low (LO), and the fourth transistor T4 is turned off. Also, the third transistor T3 and the sixth transistor T6 remain in the on state, and the first transistor T1 and the fifth transistor T5 remain in the off state. Note that since the potential difference between the gate electrode 622 of the second transistor T2 and the first electrode 624 (the potential difference between the gate electrode 622 and the first node N1) is the same as the threshold voltage Vth of the second transistor T2, the second transistor T2 is in the off state.

[0071] Also, during the period between the reset period PRS and the sampling period PWR of the frame, for the first node N1 and each electrode electrically connected to the first node N1, for example, the difference between the driving voltage VDDEL corresponding to the reset voltage and the threshold voltage Vth (VDDEL - Vth) is held, and for the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS, the driving voltage VDDEL corresponding to the reset voltage is held. Also, since the sixth transistor T6 remains in the on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Also, since the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Similar to the reset period PRS, current flows from the initialization voltage line VM to the reference voltage line PVSS, and the light emitting element OLED hardly emits light.

[0072] During the period between the reset period PRS and the sampling period PWR of the current frame, based on the supply of an on signal to the selection signal MUXR, the voltage RDATA(n) is selected. Therefore, the image data signal SL(m + 1) includes the voltage RDATA(n). Further, the image data signal SL(m + 1) including the voltage RDATA(n) is supplied to the image data signal line 321. Based on the supply of an off signal to the selection signal MUXR, the image data signal line 321 holds the voltage RDATA(n).

[0073] Next, with reference to FIGS. 6 and 10, a driving method of the pixel 180 (pixel circuit 181) during the sampling period PWR of the current frame will be described. The sampling period PWR is a period in which a voltage corresponding to the image data to be displayed by the pixel 180 (pixel circuit 181) is written into the pixel 180 (pixel circuit 181). The sampling period PWR of the current frame is a period overlapping a part of one horizontal period NthHP.

[0074] During the sampling period PWR of the current frame, the scanning signal G(n + 1) is supplied from low (LO) to high (HI), and the first transistor T1 is in an on state. Also, the third transistor T3 and the sixth transistor T6 remain in an on state, and the fourth transistor T4 and the fifth transistor T5 remain in an off state.

[0075] Based on the first transistor T1 being turned on, the voltage RDATA(n) is supplied to the first node N1 and each electrode electrically connected to the first node N1. Also, when the voltage RDATA(n) is supplied to the first node N1, the voltage (VDDEL - Vth) held at the first node N1 gradually becomes the voltage RDATA(n). Further, as the voltage of the first node N1 changes, the voltage between the gate and source of the second transistor T2 also changes, and the second transistor T2 turns on. As a result, the voltage RDATA(n) is supplied to the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Also, since the sixth transistor T6 remains on, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Also, since the fourth transistor T4 and the fifth transistor T5 remain off, no current flows from the drive power supply line PVDD to the reference voltage line PVSS. Similar to the reset period PRS, current flows from the initialization voltage line VM to the reference voltage line PVSS, and the light-emitting element OLED hardly emits light.

[0076] Although detailed illustration is omitted, when the potential difference between the gate electrode 622 of the second transistor T2 and the first electrode 624 (the potential difference between the gate electrode 622 and the first node N1) becomes the same as the threshold voltage Vth of the second transistor T2, the second transistor T2 turns off. For example, when a voltage RDATA(n) is supplied to the first node N1 and each electrode electrically connected to the first node N1, and writing proceeds to the second node N2 (each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS) up to a voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth), the second transistor T2 turns off. At this time, the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS hold the voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth), and the first node N1 and each electrode electrically connected to the first node N1 hold the voltage RDATA(n) (RDATA(n)). Also, as described above, the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are supplied with and hold the initialization voltage VINI. Therefore, the difference between the voltage held by the second electrode 694 of the capacitor element CS and the voltage held by the first electrode 692 of the capacitor element CS (the potential difference between the electrodes of the capacitor element CS) becomes the voltage VDDEL + threshold voltage Vth + initialization voltage VINI (VDDEL + Vth + VINI), and the capacitor element CS holds the data (information) of the threshold voltage Vth of the second transistor T2. As described above, the sampling period PWR of this frame is a period in which the pixel 180 (pixel circuit 181) writes the voltage corresponding to the image data to be displayed by the pixel 180 (pixel circuit 181), and is also a period (threshold correction period) in which the charge corresponding to the threshold voltage Vth of the second transistor T2 is held and the threshold of the second transistor T2 is corrected.

[0077] Next, referring to FIGS. 6 and 11, a method of driving pixel 180 (pixel circuit 181) after the sampling period PWR of the frame will be described. The period after the sampling period PWR of the frame is a period that overlaps a part of one horizontal period NthHP and one horizontal period N+2ndHP.

[0078] During the period after the sampling period PWR of the frame, the scanning signal G(n) is supplied from high (HI) to low (LO), and the third transistor T3 is in the off state. Also, the first transistor T1 and the sixth transistor T6 remain in the on state, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 remain in the off state.

[0079] At this time, the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS hold the voltage RDATA(n)+threshold voltage Vth (RDATA(n)+Vth), the first node N1 and each electrode electrically connected to the first node N1 hold the voltage RDATA(n) (RDATA(n)), and the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED hold the initialization voltage VINI.

[0080] Also, at this time, a high (HI) is supplied to the scanning signal G(n+1), the first transistor T1 is in the on state, and the voltage RDATA(n) (RDATA(n)) is supplied to the first electrode 614 and the second electrode 616 of the first transistor T1, and the first electrode 614 is at the same potential as the second electrode 616. That is, since the source electrode and the drain electrode of the first transistor T1 are at the same potential, no current flows through the first transistor T1. Also, since the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are in the off state, no current flows from the drive power supply line PVDD to the reference voltage line PVSS. Similar to the reset period PRS and the sampling period PWR, current flows from the initialization voltage line VM to the reference voltage line PVSS, and the light-emitting element OLED emits almost no light.

[0081] Next, as shown in FIG. 6, the scan signal G(n), the emission control signal EM(n), and the emission control signal EM(n+1) are supplied with low (LO), and the scan signal G(n+1) is supplied with high (HI) to low (LO). Therefore, the second transistor T2 to the fifth transistor T5 remain in the off state, the sixth transistor T6 remains in the on state, and the first transistor T1 changes from the on state to the off state. Each electrode, each node, etc. generally hold the voltage (, potential or charge) as described with reference to FIG. 11. Also, the light-emitting element OLED hardly emits light.

[0082] Next, as shown in FIG. 6, the scan signal G(n), the scan signal G(n+1), and the emission control signal EM(n+1) are supplied with low (LO), and the emission control signal EM(n) is supplied with low (LO) to high (HI). Therefore, the first transistor T1, the third transistor T3, and the fourth transistor T4 remain in the off state, the fifth transistor T5 changes from the off state to the on state, and the sixth transistor T6 changes from the on state to the off state. The second transistor T2 may be in either the on state or the off state based on the voltage relationship among the gate electrode 622, the first electrode 624, and the second electrode 626. Specifically, the voltage of the second electrode 656 and the voltage of the first electrode 654 of the fifth transistor T5 are the voltage RDATA(n) (RDATA(n)) and the initialization voltage VINI (VINI). Based on the fact that the emission control signal EM(n) is supplied with low (LO) to high (HI), when the fifth transistor T5 turns on, charge redistribution occurs, and the voltage of the second electrode 656 and the voltage of the first electrode 654 become the initialization voltage VINI (VINI). At this time, the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitive element CS become the voltage RDATA(n)+threshold voltage Vth-initialization voltage VINI (RDATA(n)+Vth-VINI). Depending on the value of the voltage RDATA(n), the second transistor T2 may be in the on state or the off state.

[0083] For example, when the second transistor T2 is turned on, current flows from the second node N2 to the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, the voltages of the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED increase. Also, a current based on the potential difference between the second electrode 684 and the first electrode 682 of the light-emitting element OLED flows through the light-emitting element OLED, and the light-emitting element OLED emits light. Note that the potential difference between the second electrode 684 and the first electrode 682 of the light-emitting element OLED may be a voltage low enough that the light-emitting element OLED hardly emits light.

[0084] Next, with reference to FIGS. 6 and 12, a driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the frame will be described. The light emission period PEM of the frame is a period during which the pixel 180 (pixel circuit 181) emits light in response to the voltage RDATA(n). The light emission period PEM of the frame is a period overlapping with one horizontal period N + 4thHP.

[0085] As shown in FIGS. 6 and 12, a low (LO) is supplied to the scanning signal G(n) and the scanning signal G(n+1), and a high (HI) is supplied to the light emission control signal EM(n) and the light emission control signal EM(n+1). The first transistor T1, the third transistor T3, and the sixth transistor T6 are in an off state. Also, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are in an on state. Based on the fact that the fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on state, a current flows from the drive power supply line PVDD to the reference voltage line PVSS. The current is, for example, a current based on the voltage RDATA(n) written in the second transistor T2 + threshold voltage Vth + voltage β(RDARA(n)+Vth+β), and the current value is, for example, the current IELA. The current IELA flows through the light emitting element OLED, and the light emitting element OLED emits light. Note that, for example, the voltage β is a positive value and is a voltage value that changes according to the voltage RDATA(n). For example, when the voltage RDATA(n) becomes high (large), the voltage β becomes high (large), and when the voltage RDATA(n) becomes low (small), the voltage β becomes low (small). For example, the voltage β is determined so that the current value flowing through the second transistor T2 according to the gate electrode 622, the first electrode 624, and the second electrode 626 is the same as the current value flowing through the light emitting element OLED.

[0086] As described above, the self-emission type display device 10 is driven, and image data corresponding to each pixel 180 (pixel circuit 181) (for example, voltage RDATA(n)+threshold voltage Vth+voltage β(RDARA(n)+Vth+β)) is supplied to each pixel 180 (pixel circuit 181), and a current corresponding to the image data (for example, current IELA) is supplied to the light emitting element OLED included in each pixel 180 (pixel circuit 181), and each light emitting element OLED emits light with a luminance corresponding to the image data. As a result, the self-emission type display device 10 can display a desired image.

[0087] For example, in the driving method of a conventional self-emitting display device different from the invention of the present application, four circuits corresponding to the control circuits (for example, a gate driver and a light emission control circuit) for driving the first transistor T1, the sixth transistor T6, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are required. Therefore, in a self-emitting display device that does not use a shift pulse similar to the invention of the present application, the frame area becomes wide (large).

[0088] On the other hand, in the self-emitting display device 10 of the present invention, the gate driver circuit 120 and the light emission control circuit 130 are each of one system, and the self-emitting display device 10 can drive each transistor included in the pixel 180 (pixel circuit 181) using a shift pulse. By using the self-emitting display device 10, the number of control circuits for driving each transistor included in the pixel 180 (pixel circuit 181) can be reduced. By using the self-emitting display device 10, a display device with a narrow frame area can be provided. Also, by using the self-emitting display device 10, since the signals supplied to the gate electrode of the fourth transistor T4 and the gate electrode of the sixth transistor T6 can be shared, the wiring structure such as the routing of the wiring connecting each transistor can be simplified compared to the configuration of a conventional self-emitting display device different from the invention of the present application. As a result, the parasitic capacitance and resistance associated with the routing of the wiring can be reduced. Therefore, the power associated with the charging of the parasitic capacitance and resistance can be reduced. Thus, by using the self-emitting display device 10, the power consumption of the display device can be suppressed compared to the configuration of a conventional self-emitting display device different from the invention of the present application.

[0089] Next, referring to FIGS. 13 and 14, an example of a driving method in which the pixel 180 (pixel circuit 181) displays black based on the initialization voltage VINI supplied from the initialization voltage line VM will be described. As described above, in the low-frequency driving, the driving other than the black period PBWR is the same as the high-frequency driving. Therefore, mainly, the driving of the pixel 180 (pixel circuit 181) in the black period PBWR will be described here. Regarding the configurations that are the same as or similar to those in FIGS. 1 to 5(A) and FIGS. 6 to 12, the description here will be omitted. Note that the horizontal axis of the timing chart is time (TIME).

[0090] The data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB are the same as those described with reference to FIG. 6 of the first embodiment, so the description here will be omitted.

[0091] The driving method of the pixel 180 (pixel circuit 181) in the light emission period PEM of the frame one before the current frame (K-1st FRAME) is the same as the driving method described with reference to FIGS. 6 and 7. Therefore, the description here will be omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED in the light emission period PEM of the frame one before the current frame (K-1st FRAME) are voltages between the voltage VDL and the voltage VDH.

[0092] Next, the driving method of the pixel 180 (pixel circuit 181) in the black period PBWR that is executed following the light emission period PEM of the frame one before the current frame (K-1st FRAME) will be described. The black period PBWR of the current frame is a period that overlaps with a part of the first horizontal period N-1st HP to a part of the first horizontal period N+3rd HP.

[0093] In the black period PBWR, the scan signal G(n), the scan signal G(n + 1), and the emission control signal EM(n) are supplied with low (LO). The first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are in the off state, and the sixth transistor T6 is in the on state. The emission control signal EM(n + 1) is supplied with high (HI) or low (LO). In any case where the fourth transistor T4 is in the on state or the off state, the second transistor T2 is in the off state, and no current flows from the drive power supply line PVDD to the reference voltage line PVSS.

[0094] Since the sixth transistor T6 is in the on state, the initialization voltage VINI is supplied from the initialization voltage line VM to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Therefore, a current IRB flows from the initialization voltage line VM to the reference voltage line PVSS. The current IRB flowing through the light emitting element OLED is a current for displaying black based on the initialization voltage VINI, and the light emitting element OLED hardly emits light. Therefore, the pixel 180 displays black. Note that in the black period PBWR, the voltage supplied to the initialization voltage line VM (the voltage supplied to the second electrode 684 of the light emitting element OLED) is not limited to the initialization voltage VINI. For example, the voltage supplied to the initialization voltage line VM may be the reference voltage VSSEL, or may be a voltage adjusted according to the electrical characteristics of the transistors in each pixel 180. The voltage supplied to the initialization voltage line VM can be adjusted as appropriate as long as the light emitting element OLED hardly emits light or does not emit light.

[0095] The driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the current frame (KthFRAME) is the same as the driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the frame one before the current frame (K - 1stFRAME). Therefore, the description here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED during the light emission period PEM of the current frame (KthFRAME) are voltages between the voltage VDL and the voltage VDH.

[0096] For example, generally, during the period for displaying black in a self-emissive display device, the emission transition speed after writing of image data (for example, the sampling period) is made the same as the emission transition speed after the period for displaying black. For example, during the period for displaying black, a voltage capable of displaying black is appropriately set on the anode electrode. As a result, in the self-emissive display device, flicker can be adjusted.

[0097] In the black period PBWR of the self-emissive display device 10 according to the first embodiment, by supplying the initialization voltage VINI from the initialization voltage line VM to the second electrode 684 (anode electrode) of the light-emitting element OLED, the self-emissive display device 10 can display black. As a result, the self-emissive display device 10 can adjust flicker.

[0098] Also, in a conventional self-emissive display device, since data for displaying black is supplied from an image data signal line to a first node N1 via a first transistor T1, the image data signal line needs to supply image data corresponding to an image and data for displaying black. The image data corresponding to the image changes according to the luminance of the light-emitting element. Therefore, in a conventional self-emissive display device, it is necessary to change the amount of change (for example, the amount of change in voltage) from the image data corresponding to the image to the data for displaying black according to the luminance of the light-emitting element. Since the image data signal line supplies the image data corresponding to the image and the data for displaying black, a change in luminance associated with the coupling between the image data signal line and the gate electrode of the second transistor T2 may become a problem depending on the amount of change in the voltage.

[0099] On the other hand, during the black period PBWR of the self-emissive display device 10, an initialization voltage VINI, which is a fixed voltage, is supplied from the initialization voltage line VM to the second electrode 684 of the light-emitting element OLED, whereby the self-emissive display device 10 can display black. That is, during the black period PBWR of the self-emissive display device 10, there is no need to supply data for displaying black from the image data signal line 321 to the first node N1 via the first transistor T1. As a result, in the self-emissive display device 10, there is no change in luminance due to the coupling between the image data signal line 321 and the gate electrode 622 of the second transistor T2. Therefore, the self-emissive display device 10 can display an image with reduced flicker compared to conventional self-emissive display devices.

[0100] Also, during the black period PBWR of the self-emissive display device 10, there is no need to supply data for displaying black from the image data signal line 321 to the first node N1 via the first transistor T1. Therefore, during the black period PBWR of the self-emissive display device 10, the first transistor T1 and the third transistor T3 can be turned off. That is, during the black period PBWR of the self-emissive display device 10, there is no need to drive the gate driver circuit 120. Therefore, for example, the control signal supplied to the gate driver circuit 120 is fixed to low (LO), the power supply voltage supplied to the gate driver circuit 120 is fixed to 0V or GND (ground, earth, etc.), and the output (scanning signal G(n), scanning signal G(n + 1), etc.) from the gate driver circuit 120 is supplied with low (LO). Therefore, by using the driving method of the self-emissive display device 10, it is possible to simplify the driving method of the display device and reduce the power consumption of the display device.

[0101] <2. Second Embodiment> Referring to FIGS. 15 to 17, the pixel circuit 182 according to the second embodiment will be described. In the pixel circuit 182, the polarities of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are opposite to those of the pixel circuit 181. Specifically, in the pixel circuit 181, the fourth transistor T4 and the fifth transistor T5 are n-channel field-effect transistors, and the sixth transistor T6 is a p-channel field-effect transistor, while in the pixel circuit 182, the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors, and the sixth transistor T6 is an n-channel field-effect transistor. The configuration other than the transistor polarities is the same as that of the self-emissive display device 10 and the pixel circuit 181. The pixel circuit 182 shown in FIGS. 15 to 17 is an example, and the pixel circuit 182 is not limited to the example shown in FIGS. 15 to 17. The description of the configuration identical or similar to that of the self-emissive display device 10 described in the first embodiment, and the configuration identical or similar to FIGS. 1 to 14 is omitted here.

[0102] Referring to FIG. 15, the outline of the pixel circuit 182 will be described. FIG. 15 is a circuit diagram showing the configuration of the pixel circuit 182.

[0103] The pixel circuit 182 is a circuit for driving the pixel 180, similar to the pixel circuit 181. As described above, the pixel circuit 182 is different from the pixel circuit 181 in that the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors, and the sixth transistor T6 is an n-channel field-effect transistor.

[0104] Referring to FIGS. 15 to 17, the driving method of the pixel 180 (pixel circuit 182) will be described. FIG. 16 is a diagram for explaining the reset period PRS, the sampling period PWR, and the emission period PEM of the driving method of the self-emissive display device 10 (pixel 180 (pixel circuit 182)). FIG. 17 is a diagram for explaining the black period PBWR of the driving method of the self-emissive display device 10 (pixel 180 (pixel circuit 182)).

[0105] In the pixel circuit 182 according to the second embodiment, since the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors, and the transistor of the sixth transistor T6 is an n-channel field-effect transistor, the emission control signal EM(n) and the emission control signal EM(n + 1) are inverted with respect to the pixel 180 (pixel circuit 181) according to the first embodiment.

[0106] The driving method of the self-emission type display device according to the second embodiment shown in FIGS. 16 and 17 is a driving method in which the HI supplied to the emission control signal EM(n) and the emission control signal EM(n + 1) in the driving method of the self-emission type display device 10 according to the first embodiment shown in FIGS. 6 and 13 is replaced with LO, and LO is replaced with HI. Since the driving methods other than the emission control signal EM(n) and the emission control signal EM(n + 1) of the driving method of the self-emission type display device according to the second embodiment are the same as the driving method of the self-emission type display device 10 according to the first embodiment, detailed description here is omitted.

[0107] Also, in the driving method of the self-emission type display device according to the second embodiment, a high (HIL) lower than high (HI) may be supplied to the emission control signal EM(n).

[0108] For example, during the light emission period PEM of the Kth FRAME, since the fifth transistor T5 is a p-channel field effect transistor, the light emission control signal EM(n) is supplied with a change from HIGH (HI) to LOW (LO). In the pixel circuit 182, since the light emission control signal EM(n) is supplied with a change from HIGH (HI) to LOW (LO), it is possible to suppress an increase in the voltage of the anode electrode associated with the coupling between the light emission control signal line 334 and the second electrode 684 (anode electrode) of the light emitting element OLED, as compared with the case where the light emission control signal EM(n) is supplied with a change from LOW (LO) to HIGH (HI). When the voltage of the anode electrode increases, a larger current flows through the light emitting element OLED than when the pixel 180 displays black, making it difficult for the pixel 180 to display black. On the other hand, in the self-emission type display device 10 (pixel 180 (pixel circuit 182)) according to the second embodiment, since an increase in the voltage of the anode electrode can be suppressed, the margin when displaying black can be increased.

[0109] Also, in the driving method of the self-emission type display device 10 (pixel 180 (pixel circuit 182)) according to the second embodiment, since the fourth transistor T4 is a p-channel field effect transistor, the high voltage of the light emission control signal EM(n) can be reduced from HIGH (HI) to HIGH (HIL) which is lower than HIGH (HI). As a result, since the voltage supplied to the gate electrode 642 of the fourth transistor T4 can be reduced, the power consumption of the self-emission type display device 10 can be reduced.

[0110] <3. Third Embodiment> Referring to FIGS. 18 to 31, an example of a manufacturing method, electrical characteristics, and a pixel circuit of a semiconductor device 40 used in an organic light-emitting display device according to the third embodiment will be described. FIGS. 18 and 19 are a cross-sectional view and a plan view showing an outline of a semiconductor device 40 used in an organic light-emitting display device according to an embodiment of the present invention. FIG. 20 is a sequence diagram showing a manufacturing method of the semiconductor device 40. FIGS. 21 to 29 are cross-sectional views showing a manufacturing method of the semiconductor device 40. FIG. 30 is a graph showing an example of electrical characteristics of the semiconductor device 40 and an example of electrical characteristics of a semiconductor device of a comparative example. FIG. 31 is a schematic diagram showing a configuration of a pixel circuit using the semiconductor device 40. Descriptions of configurations identical or similar to those in FIGS. 1 to 17 are omitted here.

[0111] In the description of the third embodiment, the direction from the substrate toward the oxide semiconductor layer is referred to as up or upward, and the direction from the oxide semiconductor layer toward the substrate is referred to as down or downward. Also, in the description of the third embodiment, for example, the substrate and the oxide semiconductor layer may be arranged so that their positions are reversed up and down. The expression "oxide semiconductor layer on the substrate" merely explains the vertical relationship between the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. The expressions "upward" or "downward" mean the stacking order in a structure in which a plurality of layers are stacked. For example, when referring to a pixel electrode above a transistor, in a plan view, the positional relationship between the transistor and the pixel electrode may be a non-overlapping positional relationship. On the other hand, when referring to a pixel electrode directly above the transistor in the vertical direction, in a plan view, it means a positional relationship in which the transistor and the pixel electrode overlap.

[0112] <3-1. Configuration of Semiconductor Device 40> As shown in FIG. 18, the semiconductor device 40 is provided above a substrate 500. The semiconductor device 40 includes a gate electrode 505, gate insulating layers 510, 520, a metal oxide layer 530, an oxide semiconductor layer 540, a gate insulating layer 550, a gate electrode 560, insulating layers 570, 580, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as a source-drain electrode 200.

[0113] The gate electrode 505 is provided on the substrate 500. The gate insulating layer 510 and the gate insulating layer 520 are provided on the substrate 500 and the gate electrode 505. The metal oxide layer 530 is provided on the gate insulating layer 520. The metal oxide layer 530 is in contact with the gate insulating layer 520. The oxide semiconductor layer 540 is provided on the metal oxide layer 530. The oxide semiconductor layer 540 is in contact with the metal oxide layer 530. Of the main surfaces of the oxide semiconductor layer 540, the surface in contact with the metal oxide layer 530 is referred to as the lower surface 542. The end of the metal oxide layer 530 and the end of the oxide semiconductor layer 540 substantially coincide.

[0114] In the third embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 530 and the substrate 500.

[0115] In the third embodiment, a configuration in which the metal oxide layer 530 is in contact with the gate insulating layer 520 and the oxide semiconductor layer 540 is in contact with the metal oxide layer 530 is illustrated, but the present invention is not limited to this configuration. Another layer may be provided between the gate insulating layer 520 and the metal oxide layer 530. Another layer may be provided between the metal oxide layer 530 and the oxide semiconductor layer 540.

[0116] In FIG. 18, the side wall of the metal oxide layer 530 and the side wall of the oxide semiconductor layer 540 are aligned in a straight line, but the present invention is not limited to this configuration. The angle of the side wall of the metal oxide layer 530 with respect to the main surface of the substrate 500 may be different from the angle of the side wall of the oxide semiconductor layer 540. The cross-sectional shape of the side wall of at least one of the metal oxide layer 530 and the oxide semiconductor layer 540 may be curved.

[0117] The gate electrode 560 faces the oxide semiconductor layer 540. The gate insulating layer 550 is provided between the oxide semiconductor layer 540 and the gate electrode 560. The gate insulating layer 550 is in contact with the oxide semiconductor layer 540. Of the main surfaces of the oxide semiconductor layer 540, the surface in contact with the gate insulating layer 550 is referred to as the upper surface 541. The surface between the upper surface 541 and the lower surface 542 is referred to as the side surface 543. The insulating layers 570 and 580 are provided over the gate insulating layer 550 and the gate electrode 560. The insulating layers 570 and 580 are provided with openings 571 and 573 that reach the oxide semiconductor layer 540. The source electrode 201 is provided inside the opening 571. The source electrode 201 is in contact with the oxide semiconductor layer 540 at the bottom of the opening 571. The drain electrode 203 is provided inside the opening 573. The drain electrode 203 is in contact with the oxide semiconductor layer 540 at the bottom of the opening 573.

[0118] The gate electrode 505 functions as a bottom gate of the semiconductor device 40 and as a light-shielding film for the oxide semiconductor layer 540. The gate insulating layer 510 functions as a barrier film that shields impurities diffusing from the substrate 500 toward the oxide semiconductor layer 540. The gate insulating layers 510 and 520 function as gate insulating layers for the bottom gate. The metal oxide layer 530 is a layer containing a metal oxide mainly composed of aluminum and functions as a gas barrier film that shields gases such as oxygen and hydrogen.

[0119] The oxide semiconductor layer 540 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is the region directly below the gate electrode 560 in the oxide semiconductor layer 540. The source region S is a region in the oxide semiconductor layer 540 that does not overlap with the gate electrode 560 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region in the oxide semiconductor layer 540 that does not overlap with the gate electrode 560 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 540 in the channel region CH has physical properties of a semiconductor. The oxide semiconductor layer 540 in the source region S and the drain region D has physical properties of a conductor.

[0120] The gate electrode 560 functions as a top gate of the semiconductor device 40 and a light-shielding film for the oxide semiconductor layer 540. The gate insulating layer 550 functions as a gate insulating layer for the top gate and has a function of releasing oxygen by heat treatment in the manufacturing process. The insulating layers 570 and 580 insulate the gate electrode 560 from the source / drain electrodes 200 and have a function of reducing the parasitic capacitance therebetween. The operation of the semiconductor device 40 is mainly controlled by the voltage supplied to the gate electrode 560. An auxiliary voltage is supplied to the gate electrode 505. However, when the gate electrode 505 is simply used as a light-shielding film, no specific voltage needs to be supplied to the gate electrode 505, and it may be floating. That is, the gate electrode 505 may simply be called a "light-shielding film".

[0121] In the third embodiment, as the semiconductor device 40, a configuration in which a dual-gate transistor having gate electrodes provided both above and below the oxide semiconductor layer is used is exemplified, but the present invention is not limited to this configuration. For example, as the semiconductor device 40, a bottom-gate transistor having a gate electrode provided only below the oxide semiconductor layer or a top-gate transistor having a gate electrode provided only above the oxide semiconductor layer may be used. The above configuration is merely an embodiment, and the present invention is not limited to the above configuration.

[0122] As shown in FIG. 19, in a plan view, the planar pattern of the metal oxide layer 530 is substantially the same as the planar pattern of the oxide semiconductor layer 540. Referring to FIGS. 18 and 19, the lower surface 542 of the oxide semiconductor layer 540 is covered by the metal oxide layer 530. In particular, in the third embodiment, the entire lower surface 542 of the oxide semiconductor layer 540 is covered by the metal oxide layer 530. In the D1 direction, the width of the gate electrode 505 is larger than the width of the gate electrode 560. The D1 direction is the direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the semiconductor device 40. Specifically, the length in the D1 direction of the region (channel region CH) where the oxide semiconductor layer 540 and the gate electrode 560 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0123] In the third embodiment, a configuration in which the entire lower surface 542 of the oxide semiconductor layer 540 is covered by the metal oxide layer 530 is illustrated, but the present invention is not limited to this configuration. For example, a part of the lower surface 542 of the oxide semiconductor layer 540 may not be in contact with the metal oxide layer 530. For example, the entire lower surface 542 of the oxide semiconductor layer 540 in the channel region CH may be covered by the metal oxide layer 530, and all or part of the lower surface 542 of the oxide semiconductor layer 540 in the source region S and the drain region D may not be covered by the metal oxide layer 530. That is, all or part of the lower surface 542 of the oxide semiconductor layer 540 in the source region S and the drain region D may not be in contact with the metal oxide layer 530. However, in the above configuration, a part of the lower surface 542 of the oxide semiconductor layer 540 in the channel region CH may not be covered by the metal oxide layer 530, and the other part of the lower surface 542 may be in contact with the metal oxide layer 530.

[0124] In the third embodiment, although an example has been illustrated in which the gate insulating layer 550 is formed over the entire surface and openings 571 and 573 are provided in the gate insulating layer 550, the present invention is not limited to this configuration. The gate insulating layer 550 may be patterned into a shape different from the shape in which the openings 571 and 573 are provided. For example, the gate insulating layer 550 may be patterned so as to expose all or part of the oxide semiconductor layer 540 in the source region S and the drain region D. That is, the gate insulating layer 550 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 540 and the insulating layer 570 may be in contact with each other in these regions.

[0125] In FIG. 19, a configuration is illustrated in which, in plan view, the source / drain electrodes 200 do not overlap the gate electrode 505 and the gate electrode 560, but the present invention is not limited to this configuration. For example, in plan view, the source / drain electrodes 200 may overlap at least one of the gate electrode 505 and the gate electrode 560. The above-described configuration is merely one embodiment, and the present invention is not limited to the above-described configuration.

[0126] <3-2. Materials of Members of Semiconductor Device 40> As the substrate 500, a rigid substrate having translucency, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 500 needs to have flexibility, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate, is used as the substrate 500. When a substrate containing a resin is used as the substrate 500, impurities may be introduced into the above-described resin in order to improve the heat resistance of the substrate 500. In particular, when the semiconductor device 40 is used in a top emission type self-luminous display device, since the substrate 500 does not need to be transparent, impurities that deteriorate the transparency of the substrate 500 may be used.

[0127] As the gate electrodes 505, gate electrodes 560, and source / drain electrodes 200, common metal materials are used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and their alloys or compounds are used. As the gate electrodes 505, gate electrodes 560, and source / drain electrodes 200, the above materials may be used in a single layer or in a stacked layer.

[0128] As the gate insulating layers 510, 520 and insulating layers 570, 580, common insulating materials are used. For example, as these insulating layers, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers are used.

[0129] As the gate insulating layer 550, an insulating layer containing oxygen among the above insulating layers is used. For example, as the gate insulating layer 550, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ) and other inorganic insulating layers are used.

[0130] As the gate insulating layer 520, an insulating layer having a function of releasing oxygen by heat treatment is used. The temperature of the heat treatment for the gate insulating layer 520 to release oxygen is, for example, 600 °C or lower, 500 °C or lower, 450 °C or lower, or 400 °C or lower. That is, the gate insulating layer 520 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 40 when a glass substrate is used as the substrate 500, for example.

[0131] As the gate insulating layer 550, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 550 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 550 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 550 is closer to the stoichiometric ratio with respect to the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layer 550 and the insulating layer 580, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 550 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 580. For example, as the gate insulating layer 550, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0132] The above SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0133] As the metal oxide layer 530 and the metal oxide layer 590 used in the manufacturing process as described later, a metal oxide mainly composed of aluminum is used. For example, as the metal oxide layer 530 (or the metal oxide layer 590), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers are used. The "metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer 530 (or the metal oxide layer 590) is 1% or more of the entire metal oxide layer 530 (or the metal oxide layer 590). The ratio of aluminum contained in the metal oxide layer 530 (or the metal oxide layer 590) may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 530. The above ratio may be a mass ratio or a weight ratio.

[0134] As the oxide semiconductor layer 540, a metal oxide having semiconductor characteristics can be used. 。

[0135] The oxide semiconductor layer 540 may be amorphous or crystalline. Further, the oxide semiconductor layer 540 may be a mixed phase of amorphous and crystal. 。Knot Crystalline oxide semiconductors are less likely to form oxygen deficiencies compared to amorphous oxide semiconductors. 。

[0136] <3-3. Problems newly recognized in the process leading to the present invention >

[0137] In the semiconductor device 40, in the heat treatment process of the manufacturing process, hydrogen is released from the layers (for example, gate insulating layers 510 and 520) provided on the substrate 500 side rather than the oxide semiconductor layer 540, and when this hydrogen reaches the oxide semiconductor layer 540, oxygen deficiency occurs in the oxide semiconductor layer 540. The occurrence of this oxygen deficiency is more prominent as the pattern size of the oxide semiconductor layer 540 is larger. In order to suppress the occurrence of such oxygen deficiency, it is necessary to suppress the reach of hydrogen to the lower surface 542 of the oxide semiconductor layer 540. The above content is the first problem.

[0138] Apart from the above problems, there is a second problem shown below. The upper surface 541 of the oxide semiconductor layer 540 is affected by the processes (for example, patterning process or etching process) after the oxide semiconductor layer 540 is formed. On the other hand, the lower surface 542 of the oxide semiconductor layer 540 (the surface on the substrate 500 side of the oxide semiconductor layer 540) is not affected by the above such influence.

[0139] Therefore, the oxygen deficiency formed on the upper surface 541 of the oxide semiconductor layer 540 is more than the oxygen deficiency formed on the lower surface 542 of the oxide semiconductor layer 540. That is, the oxygen deficiency in the oxide semiconductor layer 540 does not exist uniformly in the thickness direction of the oxide semiconductor layer 540, but exists in a non-uniform distribution in the thickness direction of the oxide semiconductor layer 540. Specifically, the oxygen deficiency in the oxide semiconductor layer 540 is less on the lower surface 542 side of the oxide semiconductor layer 540 and more on the upper surface 541 side of the oxide semiconductor layer 540.

[0140] When an oxygen supply process is uniformly performed on the oxide semiconductor layer 540 having the oxygen deficiency distribution as described above, if an amount of oxygen necessary to repair the oxygen deficiency formed on the upper surface 541 side of the oxide semiconductor layer 540 is supplied, oxygen is excessively supplied to the lower surface 542 side of the oxide semiconductor layer 540. As a result, on the lower surface 542 side, defect levels different from oxygen deficiency are formed by the excessive oxygen, and phenomena such as characteristic variations in the reliability test or a decrease in the field-effect mobility occur. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface 541 side of the oxide semiconductor layer 540 while suppressing the oxygen supply to the lower surface 542 side of the oxide semiconductor layer 540.

[0141] The above problems are problems newly recognized in the process leading to the present invention and are not problems conventionally recognized. In the conventional configuration and manufacturing method, even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer, there is a trade-off relationship between the initial characteristics and the reliability test in that characteristic variations occur in the reliability test. However, with the configuration according to the third embodiment, the above problems are solved, and good initial characteristics and reliability test results of the semiconductor device 40 can be obtained.

[0142] <3-4. Manufacturing Method of Semiconductor Device 40> The manufacturing method of the semiconductor device 40 will be described with reference to FIGS. 20 to 29. Here, an example of the manufacturing method of the semiconductor device 40 in which aluminum oxide is used as the metal oxide layers 530 and 590 will be described.

[0143] As shown in FIGS. 20 and 21, a gate electrode 505 is formed as a bottom gate on a substrate 500, and gate insulating layers 510 and 520 are formed on the gate electrode 505 ("Bottom GI / GE formation" in step S2001 of FIG. 20). As the gate insulating layer 510, for example, silicon nitride is formed. As the gate insulating layer 520, for example, silicon oxide is formed. The gate insulating layers 510 and 520 are formed by a CVD (Chemical Vapor Deposition) method. One or both of the gate insulating layers 510 and 520 may be referred to as the "first insulating layer".

[0144] By using silicon nitride as the gate insulating layer 510, the gate insulating layer 510 can block, for example, impurities diffusing from the substrate 500 side toward the oxide semiconductor layer 540. The silicon oxide used as the gate insulating layer 520 is a silicon oxide having a physical property of releasing oxygen by heat treatment.

[0145] As shown in FIGS. 20 and 22, a metal oxide layer 530 and an oxide semiconductor layer 540 are formed on the gate insulating layer 520 ("OS / AlOx film formation" in step S2002 of FIG. 20). For this process, it may be called that the gate insulating layers 510 and 520 are formed on the substrate 500 and the metal oxide layer 530 is formed on the gate insulating layers 510 and 520. Or, it may be the case that the metal oxide layer 530 is formed on the substrate 500 and the oxide semiconductor layer 540 is formed on the metal oxide layer 530. Specifically, the oxide semiconductor layer 540 is formed in contact with the metal oxide layer 530. The metal oxide layer 530 and the oxide semiconductor layer 540 are formed by a sputtering method or an atomic layer deposition method (ALD: Atomic Layer Deposition).

[0146] The thickness of the metal oxide layer 530 is, for example, 1 nm or more and 100 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 30 nm or less, or 1 nm or more and 10 nm or less. In the third embodiment, aluminum oxide is used as the metal oxide layer 530. Aluminum oxide has a high barrier property against gases. In the third embodiment, the aluminum oxide used as the metal oxide layer 530 blocks hydrogen and oxygen released from the gate insulating layer 520 and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 540.

[0147] The thickness of the oxide semiconductor layer 540 is, for example, 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. 。

[0148] Strand When the oxide semiconductor layer 540 is formed by a patterning method, the oxide semiconductor layer 540 is formed while controlling the temperature of the object to be film-formed (substrate 500 and the structure formed thereon).

[0149] When film formation is performed on the object to be film-formed by a sputtering method, ions generated in the plasma and atoms rebounded by the sputtering target collide with the object to be film-formed, so the temperature of the object to be film-formed rises with the film formation process. 。Upper In order to control the temperature of the object to be film-formed as described above, for example, film formation can be performed while cooling the object to be film-formed. For example, the object to be film-formed can be cooled from the surface opposite to the surface to be film-formed (hereinafter referred to as the "film formation temperature") so that the temperature of the surface to be film-formed (surface) of the object to be film-formed becomes 100 °C or less, 70 °C or less, 50 °C or less, or 30 °C or less. 。

[0150] As shown in FIGS. 20 and 23, a pattern of the oxide semiconductor layer 540 is formed (``OS pattern formation'' in step S2003 of FIG. 20). Although not shown, a resist mask is formed on the oxide semiconductor layer 540, and the oxide semiconductor layer 540 is etched using the resist mask. As the etching of the oxide semiconductor layer 540, wet etching may be used, or dry etching may be used. As the wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0151] After the pattern formation of the oxide semiconductor layer 540, heat treatment (OS annealing) is performed on the oxide semiconductor layer 540 (``OS annealing'' in step S2004 of FIG. 20) 。

[0152] As shown in FIGS. 20 and 24, a pattern of the metal oxide layer 530 is formed (``AlO x pattern formation'' in step S2005 of FIG. 20). The metal oxide layer 530 is etched using the oxide semiconductor layer 540 patterned in the above process as a mask. As the etching of the metal oxide layer 530, wet etching may be used, or dry etching may be used 。

[0153] As shown in FIGS. 20 and 25, a gate insulating layer 550 is formed over the oxide semiconductor layer 540 (``GI formation'' in step S2006 of FIG. 20). For example, silicon oxide is formed as the gate insulating layer 550. The gate insulating layer 550 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above as the gate insulating layer 550, the gate insulating layer 550 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 550 is, for example, 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less. After forming the gate insulating layer 550, a process of implanting oxygen into a part of the gate insulating layer 550 may be performed. The gate insulating layer 550 may be referred to as the ``second insulating layer''. A metal oxide layer 590 is formed over the gate insulating layer 550 (``AlOx film formation'' in step S2007 of FIG. 20). The metal oxide layer 590 is formed by a sputtering method. By forming the metal oxide layer 590, oxygen is implanted into the gate insulating layer 550.

[0154] The thickness of the metal oxide layer 590 is, for example, 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less. In the third embodiment, aluminum oxide is used as the metal oxide layer 590. Aluminum oxide has a high barrier property against gas. In the third embodiment, the aluminum oxide used as the metal oxide layer 590 suppresses the outward diffusion of the oxygen implanted into the gate insulating layer 550 during the film formation of the metal oxide layer 590.

[0155] For example, when the metal oxide layer 590 is formed by a sputtering method, the process gas used in sputtering remains in the film of the metal oxide layer 590. For example, when Ar is used as the sputtering process gas, Ar may remain in the film of the metal oxide layer 590. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 590.

[0156] A gate insulating layer 550 is formed on the oxide semiconductor layer 540, and a heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 540 is performed in a state where a metal oxide layer 590 is formed on the gate insulating layer 550 ("oxidation annealing" in step S2008 of FIG. 20). In other words, a heat treatment (oxidation annealing) is performed on the metal oxide layer 530 and the oxide semiconductor layer 540 patterned as described above. In the process from when the oxide semiconductor layer 540 is formed until the gate insulating layer 550 is formed on the oxide semiconductor layer 540, many oxygen deficiencies occur on the upper surface 541 and the side surface 543 of the oxide semiconductor layer 540. By the above oxidation annealing, oxygen released from the gate insulating layers 520 and 550 is supplied to the oxide semiconductor layer 540, and the oxygen deficiencies are repaired.

[0157] Due to oxidation annealing, oxygen released from the gate insulating layer 520 is blocked by the metal oxide layer 530, so it is difficult for oxygen to be supplied to the lower surface 542 of the oxide semiconductor layer 540. Oxygen released from the gate insulating layer 520 diffuses from the region where the metal oxide layer 530 is not formed to the gate insulating layer 550 provided on the gate insulating layer 520, and reaches the oxide semiconductor layer 540 through the gate insulating layer 550. As a result, oxygen released from the gate insulating layer 520 is difficult to be supplied to the lower surface 542 of the oxide semiconductor layer 540, and is mainly supplied to the side surface 543 and the upper surface 541 of the oxide semiconductor layer 540. Further, by oxidation annealing, oxygen released from the gate insulating layer 550 is supplied to the upper surface 541 and the side surface 543 of the oxide semiconductor layer 540. By the above oxidation annealing, hydrogen may be released from the gate insulating layers 510 and 520, but the hydrogen is blocked by the metal oxide layer 530.

[0158] As described above, by the oxidation annealing process, it is possible to suppress the supply of oxygen to the lower surface 542 of the oxide semiconductor layer 540 where the amount of oxygen deficiency is small, while supplying oxygen to the upper surface 541 and the side surface 543 of the oxide semiconductor layer 540 where the amount of oxygen deficiency is large.

[0159] Similarly, in the above-described oxidation annealing, oxygen implanted into the gate insulating layer 550 is blocked by the metal oxide layer 590, so that it is suppressed from being released into the atmosphere. Therefore, by the oxidation annealing, the oxygen is efficiently supplied to the oxide semiconductor layer 540, and oxygen deficiencies are repaired.

[0160] As shown in FIGS. 20 and 26, after the oxidation annealing, the metal oxide layer 590 is etched (removed) ("AlOx removal" in step S2009 of FIG. 20). As the etching of the metal oxide layer 590, wet etching may be used, or dry etching may be used. As the wet etching, for example, diluted hydrofluoric acid (DHF) is used. By the etching, the metal oxide layer 590 formed over the entire surface is removed. In other words, the removal of the metal oxide layer 590 is performed without using a mask. Further in other words, by the etching, all of the metal oxide layer 590 in the region overlapping with the oxide semiconductor layer 540 formed in a certain one pattern is removed, at least in plan view.

[0161] As shown in FIGS. 20 and 27, a gate electrode 560 is formed over the gate insulating layer 550 ("GE formation" in step S2010 of FIG. 20). The gate electrode 560 is formed by a sputtering method or an atomic layer deposition method and is patterned through a photolithography process. As described above, the gate electrode 560 is formed to be in contact with the gate insulating layer 550 exposed by the removal of the metal oxide layer 590.

[0162] With the gate electrode 560 patterned, the source region S and the drain region D of the oxide semiconductor layer 540 are made to have lower resistance (the "SD lower resistance" in step S2011 of FIG. 20). Specifically, impurities are implanted into the oxide semiconductor layer 540 through the gate insulating layer 550 from the gate electrode 560 side by ion implantation. By ion implantation, for example, argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 540. By forming oxygen vacancies in the oxide semiconductor layer 540 by ion implantation, the oxide semiconductor layer 540 has lower resistance. Since the gate electrode 560 is provided above the oxide semiconductor layer 540 that functions as the channel region CH of the semiconductor device 40, no impurities are implanted into the oxide semiconductor layer 540 of the channel region CH.

[0163] As shown in FIGS. 20 and 28, insulating layers 570 and 580 are formed as interlayer films on the gate insulating layer 550 and the gate electrode 560 (the "interlayer film formation" in step S2012 of FIG. 20). The insulating layers 570 and 580 are formed by CVD method. For example, silicon nitride is formed as the insulating layer 570, and silicon oxide is formed as the insulating layer 580. The materials used for the insulating layers 570 and 580 are not limited to the above. The thickness of the insulating layer 570 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 580 is 50 nm or more and 500 nm or less.

[0164] As shown in FIGS. 20 and 29, openings 571 and 573 are formed in the gate insulating layer 550 and the insulating layers 570 and 580 (the "contact opening" in step S2013 of FIG. 20). The oxide semiconductor layer 540 of the source region S is exposed by the opening 571. The oxide semiconductor layer 540 of the drain region D is exposed by the opening 573. By forming the source / drain electrode 200 on the oxide semiconductor layer 540 exposed by the openings 571 and 573 and on the insulating layer 580 (the "SD formation" in step S2044 of FIG. 20), the semiconductor device 40 shown in FIG. 20 is completed.

[0165] <3-5. An example of the electrical characteristics of the semiconductor device 40> With reference to FIGS. 30 and 31, mainly, an example of the electrical characteristics of the semiconductor device 40 will be described. The semiconductor device 40 is used for the channel region CH of the second transistor OT2 in the pixel circuit shown in FIG. 31. The second transistor OT2 is a transistor called a so-called driving transistor. In FIG. 30, the present application invention is described as Present Application, and the comparative example is described as Prior Art. The pixel circuit of the present application invention is the same as the pixel circuit of the comparative example, and the second transistor OT2 and the light-emitting element OLED of the present application invention correspond to the second transistor TR and the light-emitting element POLED of the comparative example. Further, the channel region CH of the second transistor OT2 of the present application invention is formed using the oxide semiconductor layer 540, while the channel region of the second transistor TR of the comparative example is formed using, for example, a low-temperature polysilicon layer (LTPS layer) or an oxide semiconductor layer having characteristics different from those of the oxide semiconductor layer 540.

[0166] Note that the pixel circuit 183 according to the third embodiment shown in FIG. 31 is a circuit in which the second transistor T2 of the pixel circuit 182 according to the second embodiment described with reference to FIG. 15 is replaced with the second transistor OT2 formed using the semiconductor device 40. The configuration and function of the pixel circuit 183 according to the third embodiment other than the second transistor OT2 are the same as those of the pixel circuit 182 according to the second embodiment described with reference to FIG. 15. Therefore, in the third embodiment, mainly, the second transistor OT2 will be described, and the description of the configuration and function other than the second transistor OT2 will be omitted. In the pixel circuit according to the third embodiment shown in FIG. 31, the channel regions of the transistors other than the second transistor OT2 (the first transistor T1, the third transistor T3 to the sixth transistor T6) are formed using, for example, a low-temperature polysilicon layer (LTPS layer).

[0167] FIG. 30 is a diagram showing the dependence of the drain current IOT2 on the drain voltage (voltage VANODE) of the second transistor OT2, and is a diagram showing the dependence of the voltage VANODE of the light-emitting element OLED and the current IDI flowing through the light-emitting element OLED. Further, FIG. 30 also shows the dependence of the drain current IOT2 on the drain voltage (voltage VANODE) of the second transistor TR, and the dependence of the voltage VANODE of the light-emitting element POLED and the current IDI flowing through the light-emitting element OLED. Also, in FIG. 30, at the boundary between the linear region and the saturated region, the source-drain voltage (for example, the potential difference (Vds) between the source electrode and the drain electrode) is the same as the value (Vgs - Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 40 from the potential difference (Vgs) between the gate electrode and the source electrode.

[0168] As shown in FIG. 30, at the operating point 50 of the invention of the present application using the semiconductor device 40 (the point where the curve of the second transistor OT2 and the curve of the light-emitting element OLED intersect), the drain voltage is smaller and the drain current is larger than the operating point 50P of the comparative example (the point where the curve of the second transistor TR and the curve of the light-emitting element POLED intersect).

[0169] That is, since the second transistor OT2 can pass the same current as the second transistor TR with a smaller gate-source voltage Vgs than the second transistor TR, the second transistor OT2 can be driven in the saturated region using a smaller source-drain voltage Vds than the second transistor TR. As a result, by using the semiconductor device 40, the pixel circuit of the invention of the present application can be driven at a lower voltage than the pixel circuit of the comparative example.

[0170] Therefore, by using the semiconductor device 40, the potential difference between the voltages supplied to the first drive power line PVDD and the reference potential line PVSS of the pixel circuit (the potential difference between the drive voltage VDDEL and the reference voltage VSSEL) can be set small. Since the self-emitting display device using the semiconductor device 40 can reduce the power supply voltage, it can achieve low power consumption.

[0171] As embodiments of the present invention, each of the above-described embodiments or a part of each embodiment can be implemented in appropriate combination as long as they do not contradict each other.

[0172] Even if there are other operational effects different from those brought about by the aspects of each of the above-described embodiments, those that are obvious from the description of this specification or can be easily predicted by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0173] 10: Self-luminous display device, 22: Display area, 24: Peripheral area, 26: Terminal area, 40: Semiconductor device, 50: Operating point, 50P: Operating point, 100: Array substrate, 110: Source driver circuit, 112: Selection circuit, 114: Input terminal, 116: Output terminal, 118: Switch, 120: Gate driver circuit, 121: Shift register, 122: Shift register, 123: Shift register, 130: Light emission control circuit, 131: Shift register, 132: Shift register, 133: Shift register, 150: Terminal section, 160: Flexible printed circuit board, 170: IC chip, 180: Pixel, 181: Pixel circuit, 182: Pixel circuit, 183: Pixel circuit, 200: Source-drain electrode, 201: Source electrode, 203: Drain electrode, 321: Image data signal line, 329: Scan signal line, 330: Scan signal line, 331: Scan signal line, 332: Scan signal line, 333: Scan signal line, 334: Light emission control signal line, 334: Light control signal line, 335: Light emission control signal line, 336: Light emission control signal line, 337: Light emission control signal line, 341: Connection wiring, 500: Substrate, 505: Gate electrode, 510: Gate insulating layer, 520: Gate insulating layer, 530: Metal oxide layer, 540: Oxide semiconductor layer, 541: Upper surface, 542: Lower surface, 543: Side surface, 550: Gate insulating layer, 560: Gate electrode, 570: Insulating layer, 571: Opening, 573: Opening, 580: Insulating layer, 590: Metal oxide layer, 612: Gate electrode, 614: First electrode, 616: Second electrode, 622: Gate electrode, 624: First electrode, 626: Second electrode, 632: Gate electrode, 634: First electrode, 636: Second electrode, 642: Gate electrode, 644: First electrode, 646: Second electrode, 652: Gate electrode, 654: First electrode, 656: Second electrode, 662: Gate electrode, 664: First electrode, 666: Second electrode, 674: First electrode, 682: First electrode, 684: Second electrode, 692: First electrode, 694: Second electrode

Claims

1. a first transistor controlled by a second control signal obtained by shifting a first control signal, the first transistor being electrically connected between an image data signal line and a first node; a second transistor electrically connected between the first node and a second node; a third transistor controlled using the first control signal and electrically connected between the second node and a gate electrode of the second transistor; a fourth transistor that is controlled by a fourth control signal obtained by shifting the third control signal and is electrically connected between a drive power supply line to which a drive voltage is supplied and the second node; a fifth transistor controlled using the third control signal and electrically connected to the first node; a light-emitting element electrically connected to a first electrode of the fifth transistor; a sixth transistor that is controlled to supply an initialization voltage to the light-emitting element and the first electrode using the third control signal, and is electrically connected to the light-emitting element and the first electrode; Self-luminous display device.

2. a control circuit that sequentially shifts and outputs the first control signal and the second control signal; a light emission control circuit that sequentially shifts and outputs the third control signal and the fourth control signal, The self-luminous display device according to claim 1 .

3. the first transistor to the fifth transistor are n-channel type field effect transistors, and the sixth transistor is a p-channel type field effect transistor; The self-luminous display device according to claim 2 .

4. The control circuit, supplying a high level to the first control signal to turn on the third transistor; supplying a low to the second control signal to turn off the first transistor; The light emission control circuit supplying a low level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying a high level to the fourth control signal to turn on the fourth transistor; the fourth transistor and the third transistor supply the drive voltage to the second node and the gate electrode; the sixth transistor supplies the initialization voltage to the light-emitting element and the first electrode; The self-luminous display device according to claim 3 .

5. The control circuit, supplying a high level to the first control signal to turn on the third transistor; supplying a high level to the second control signal to turn on the first transistor; The light emission control circuit supplying a low level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying a low level to the fourth control signal to turn off the fourth transistor; the first transistor supplies an image data signal from the image data signal line to the first node, the second node, and the gate electrode; The self-luminous display device according to claim 3 .

6. The control circuit, supplying a low level to the first control signal to turn off the third transistor; supplying a low to the second control signal to turn off the first transistor; The light emission control circuit supplying a low level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; the sixth transistor supplies an image data signal including a voltage for displaying black to the first electrode and the light-emitting element from the image data signal line; The self-luminous display device according to claim 3 .

7. the first transistor to the third transistor and the sixth transistor are n-channel type field effect transistors, and the fourth transistor and the fifth transistor are p-channel type field effect transistors. The self-luminous display device according to claim 2 .

8. The control circuit, supplying a high level to the first control signal to turn on the third transistor; supplying a low to the second control signal to turn off the first transistor; The light emission control circuit supplying a high level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying a low level to the fourth control signal to turn on the fourth transistor; the fourth transistor and the third transistor supply the drive voltage to the second node and the gate electrode; the sixth transistor supplies the initialization voltage to the light-emitting element and the first electrode; The self-luminous display device according to claim 7 .

9. The control circuit, supplying a high level to the first control signal to turn on the third transistor; supplying a high level to the second control signal to turn on the first transistor; The light emission control circuit A high level is supplied to the third control signal to turn off the fifth transistor and turn on the sixth transistor. supplying a high level to the fourth control signal to turn off the fourth transistor; the first transistor supplies an image data signal from the image data signal line to the first node, the second node, and the gate electrode; The self-luminous display device according to claim 7 .

10. The control circuit, supplying a low level to the first control signal to turn off the third transistor; supplying a low to the second control signal to turn off the first transistor; The light emission control circuit supplying a high level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; the sixth transistor supplies an image data signal including a voltage for displaying black to the first electrode and the light-emitting element from the image data signal line; The self-luminous display device according to claim 7 .

11. a channel region of each of the fourth transistor, the fifth transistor, and the sixth transistor comprises low temperature polysilicon; a channel region of the second transistor includes an oxide semiconductor; The self-luminous display device according to claim 7 .

12. A method for driving a self-luminous display device including at least a first transistor electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a third transistor electrically connected between the second node and a gate electrode of the second transistor, a fourth transistor electrically connected to the second node, a fifth transistor electrically connected to the first node, a light-emitting element electrically connected to a first electrode of the fifth transistor, and a sixth transistor electrically connected to the light-emitting element and the first electrode, sequentially shifting and outputting the first control signal and the second control signal; sequentially shifting and outputting the third control signal and the fourth control signal; controlling the third transistor using the first control signal; controlling the first transistor using the second control signal; controlling the fifth transistor and the sixth transistor using the third control signal; controlling the fourth transistor using the fourth control signal; A method for driving a self-luminous display device.

13. the first transistor to the fifth transistor are n-channel type field effect transistors, and the sixth transistor is a p-channel type field effect transistor; A method for driving the self-luminous display device according to claim 12.

14. supplying a high level to the first control signal to turn on the third transistor; supplying a low to the second control signal to turn off the first transistor; supplying a low level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying a high level to the fourth control signal to turn on the fourth transistor; supplying a drive voltage to the second node and the gate electrode via the fourth transistor and the third transistor; supplying an initialization voltage to the light-emitting element and the first electrode via the sixth transistor; A method for driving the self-luminous display device according to claim 13.

15. supplying a high level to the first control signal to turn on the third transistor; supplying a high level to the second control signal to turn on the first transistor; supplying a low level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying a low level to the fourth control signal to turn off the fourth transistor; supplying an image data signal from the image data signal line to the first node, the second node, and the gate electrode through the first transistor; A method for driving the self-luminous display device according to claim 13.

16. supplying a low level to the first control signal to turn off the third transistor; supplying a low to the second control signal to turn off the first transistor; supplying a low level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying an image data signal including a voltage for displaying black to the first electrode and the light-emitting element from the image data signal line via the first transistor; A method for driving the self-luminous display device according to claim 13.

17. the first transistor to the third transistor and the sixth transistor are n-channel type field effect transistors, and the fourth transistor and the fifth transistor are p-channel type field effect transistors. A method for driving the self-luminous display device according to claim 12.

18. supplying a high level to the first control signal to turn on the third transistor; supplying a low to the second control signal to turn off the first transistor; supplying a high level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying a low level to the fourth control signal to turn on the fourth transistor; supplying a drive voltage to the second node and the gate electrode via the fourth transistor and the third transistor; supplying an initialization voltage to the light-emitting element and the first electrode via the sixth transistor; A method for driving the self-luminous display device according to claim 17.

19. supplying a high level to the first control signal to turn on the third transistor; supplying a high level to the second control signal to turn on the first transistor; A high level is supplied to the third control signal to turn off the fifth transistor and turn on the sixth transistor. supplying a high level to the fourth control signal to turn off the fourth transistor; supplying an image data signal from the image data signal line to the first node, the second node, and the gate electrode through the first transistor; A method for driving the self-luminous display device according to claim 17.

20. supplying a low level to the first control signal to turn off the third transistor; supplying a low to the second control signal to turn off the first transistor; supplying a high level to the third control signal to turn off the fifth transistor and turn on the sixth transistor; supplying an image data signal including a voltage for displaying black to the first electrode and the light-emitting element from the image data signal line via the first transistor; A method for driving the self-luminous display device according to claim 17.

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