Voltage-type gate driving device having shunt capacitor and shunt resistor

Abstract

To provide an improved voltage-type gate driver and an improved power system.SOLUTION: In a power system 10, a shunt capacitor CGSNT and a shunt resistor RGSNT are serially connected to each other and are connected to both ends of a gate driver resistor network 18 of a voltage-type gate driver 12. The shunt capacitor and the shunt resistor separate the influence of a gate delay and a switching speed of a gate resistor RG. The shunt capacitor provides an initial high charge voltage and discharge gate current and reduces a gate delay time. The shunt resistor corrects a gate current and an effective gate resistance which affects a resultant switching speed. The shunt capacitor and the shunt resistor are determined to control a predetermined switching speed at the minimum gate delay time. When a plurality of power devices 14 are in parallel, each power device is provided with a split gate resistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 387,784, filed December 16, 2022, entitled “Voltage-Source Gate Drive Using Shunt Capacitor and Resistor that Decouples Switching Speed ​​Control and Gate Delay Time,” the entire contents of which are expressly incorporated by reference herein.

[0002] The present disclosure relates to power semiconductor devices, and more particularly to voltage type gate drive circuits for driving power semiconductor devices. [Background technology]

[0003] Power semiconductor devices are typically used in power electronic circuits to provide power conversion functions. In applications, faster switching speeds are beneficial to the operation of power semiconductor devices because they reduce switching losses associated with the devices.

[0004] Nevertheless, faster switching speeds increase electromagnetic interference and the risk of oscillations. In this regard, there is a correlation between the gate delay and switching speed of semiconductor power devices. Slower switching speeds increase switching losses and result in longer gate delays that may be undesirable from a control or protection standpoint. Faster switching speeds create challenges in complying with industry standards for electromagnetic compatibility and electromagnetic interference, causing voltage spikes, ringing, and electromagnetic interference, which makes it even more difficult to achieve electromagnetic compatibility and avoid oscillations. In addition, longer gate delays have a negative impact on the protection, parallel synchronization, and circuit operation of power electronic circuits. Another challenge in optimizing the switching speed and gate delay of power electronic circuits is the input capacitance (C) of the semiconductor power devices. ISS) is required. Semiconductor power devices have a high input capacitance (C ISS ) may have a long gate delay. Thus, depending on the design, construction, or application of the semiconductor power device, the gate delay may vary depending on the characteristics of the input capacitance (C ISS ), which will be longer and more pronounced. Therefore, an improved voltage-type gate driver is needed. Summary of the Invention

[0005] An embodiment is disclosed for controlling a semiconductor power device using an improved voltage type gate driver that decouples control of the switching speed and gate delay time of the power device. In one embodiment, a voltage type gate driver is described. The voltage type gate driver comprises a power converter including an input configured to receive a first gate signal and provide a regulated output voltage at an output node. The voltage type gate driver further comprises a gate driver resistor network having at least one gate resistor coupled between an output node of the power converter and an output terminal of the voltage type gate driver, and a shunt capacitor connected in parallel across the gate driver resistor network. In this manner, the output terminal is configured to provide a second gate signal to a gate of the semiconductor power device.

[0006] In one embodiment, the shunt capacitor has a value calculated using the following formula:

number

[0007] Here, the formula is: GSNT where V DD is the positive supply voltage, and V EE is the negative supply voltage, and C ISSis the input capacitance of the semiconductor power device, and V TH is the threshold voltage of the semiconductor power device.

[0008] In one embodiment, the voltage source gate driver further comprises a shunt resistor in series with the shunt capacitor, the shunt resistor and the shunt capacitor being connected in parallel across the gate driver resistor network. The first shunt resistor is in the range of 0Ω to 10MΩ.

[0009] In one embodiment, the gate driver resistor network has an equivalent resistance in the range of 0Ω to 10MΩ.

[0010] In another embodiment, the power converter comprises one of a voltage rectifier, a regulator, an inverter, or a converter.

[0011] In one embodiment, the voltage type gate driver further comprises a solid-state circuit breaker.

[0012] In one embodiment, the semiconductor power device comprises a half-bridge circuit topology.

[0013] In one embodiment, the semiconductor power device is a parallel transistor connected circuit topology.

[0014] In one embodiment, the semiconductor power device is a common source circuit topology.

[0015] In one embodiment, the semiconductor power device is in one of a half-bridge circuit topology, a parallel transistor connected circuit topology, or a common source circuit topology.

[0016] In one embodiment, the semiconductor power device is a metal oxide field effect transistor.

[0017] In one embodiment, the semiconductor power device is one of an insulated gate bipolar transistor (IGBT), a junction gate field effect transistor (JFET), or a high electron mobility transistor (HEMT).

[0018] In another aspect, a power system is disclosed that includes a voltage type gate driver and a semiconductor power device, the voltage type gate driver including a power converter including an input configured to receive a first gate signal and provide a regulated output voltage at an output node, a gate driver resistor network having at least one gate resistor coupled between an output node of the power converter and an output terminal of the voltage type gate driver, and a shunt capacitor connected in parallel across the gate driver resistor network, the output terminal configured to provide a second gate signal. The semiconductor power device includes a gate terminal, a drain terminal, and a source terminal, the semiconductor power device configured to receive a second gate signal at the gate terminal.

[0019] In one embodiment, the shunt capacitor has a value calculated using the following formula:

number

[0020] Here, the formula is: GSNT where V DD is the positive supply voltage, and V EE is the negative supply voltage, and C ISS is the input capacitance of the semiconductor power device, and V TH is the threshold voltage of the semiconductor power device.

[0021] In one embodiment, the power system further comprises a shunt resistor in series with the shunt capacitor, the shunt resistor and the shunt capacitor being connected in parallel across the gate driver resistor network. The first shunt resistor is in the range of 0 Ω to 10 MΩ.

[0022] In one embodiment, the gate driver resistor network has an equivalent resistance in the range of 0Ω to 10MΩ.

[0023] In another embodiment, the power converter comprises one of a voltage rectifier, a regulator, an inverter, or a converter.

[0024] In one embodiment, the semiconductor power device is a metal oxide field effect transistor.

[0025] In one embodiment, the semiconductor power device is in one of a half-bridge circuit topology, a parallel transistor connected circuit topology, or a common source circuit topology.

[0026] In one embodiment, the semiconductor power device is one of an insulated gate bipolar transistor (IGBT), a junction gate field effect transistor (JFET), or a high electron mobility transistor (HEMT).

[0027] Those skilled in the art will appreciate the scope of the present disclosure and realize other aspects thereof after reading the following detailed description in conjunction with the accompanying drawings. [Brief description of the drawings]

[0028] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0029] [Figure 1] FIG. 1 illustrates an exemplary power system having a voltage type gate driver that interfaces with a semiconductor power device.

[0030] [Diagram 2] FIG. 2 illustrates another example power system having multiple MOSFETs connected in parallel as part of a semiconductor power device.

[0031] [Figure 3A] 3A-3C illustrate example circuit topologies that may be employed in various embodiments of the present disclosure as part of the semiconductor power devices of the power system illustrated in FIG.

[0032] FIG. 3A shows an example half-bridge circuit topology.

[0033] [Figure 3B] FIG. 3B illustrates an exemplary parallel transistor connection circuit topology.

[0034] [Figure 3C] FIG. 3C illustrates an exemplary common source circuit topology.

[0035] [Figure 4A] 4A and 4B are graphs illustrating voltage and current characteristics of the semiconductor power devices of the power system shown in FIG. 1 with the shunt capacitor CGSNT and without the shunt resistor RGSNT (RGSNT=0Ω).

[0036] FIG. 4A is a graph illustrating voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 during a turn-off transition. The power system includes a shunt capacitor C GSNT and a shunt resistor R GSNT There is no (R GSNT =0Ω).

[0037] [Figure 4B] FIG. 4B is a graph illustrating voltage and current characteristics of the semiconductor power devices of the power system shown in FIG. 1 during a turn-on transition, the power system including shunt capacitor CGSNT and without shunt resistor RGSNT (RGSNT=0Ω).

[0038] [Figure 5A]5A and 5B are graphs illustrating voltage and current characteristics of semiconductor power devices (ie, discrete devices) of the power system shown in FIG. 1 having shunt capacitor CGSNT and shunt resistor RGSNT.

[0039] Figure 5A shows a shunt capacitor C GSNT and shunt resistor R GSNT 2 is a graph illustrating voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 during a turn-off transition.

[0040] [Figure 5B] FIG. 5B is a graph illustrating voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 during a turn-on transition with shunt capacitor CGSNT and shunt resistor RGSNT.

[0041] [Figure 6A] 6A and 6B are graphs illustrating voltage and current characteristics of a semiconductor power device (ie, the half bridge 30 power module) of the power system shown in FIG. 1 having a shunt capacitor CGSNT, a shunt resistor RGSNT, and a series split gate resistor RG.

[0042] Figure 6A shows a shunt capacitor C GSNT , shunt resistor R GSNT , and a series split-gate resistor R G 2 is a graph illustrating voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 during a turn-off transition.

[0043] [Figure 6B] FIG. 6B is a graph illustrating voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 having shunt capacitor CGSNT, shunt resistor RGSNT, and series split-gate resistor RG during a turn-on transition.

[0044] [Figure 7A] 7A and 7B are graphs illustrating voltage and current characteristics of the semiconductor power devices of the power system shown in FIG. 1 produced using different values ​​of the turn-on gate resistor RG-ON and the turn-off gate resistor RG-OFF.

[0045] FIG. 7A shows the results of the different values ​​(R G-ON =R G-OFF = 100Ω, R G-ON =R G-OFF = 150 Ω, and R G-ON =R G-OFF = 200 Ω) G-ON and the turn-off gate resistor R G-OFF 2 is a graph illustrating voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 during a turn-off transition generated using a

[0046] [Figure 7B] FIG. 7B is a graph showing voltage and current characteristics of the discrete semiconductor power devices of the power system shown in FIG. 1 during a turn-on transition produced using turn-on gate resistor RG-ON and turn-off gate resistor RG-OFF having different values ​​(RG-ON=RG-OFF=100Ω, RG-ON=RG-OFF=150Ω, and RG-ON=RG-OFF=200Ω).

[0047] [Figure 8A] 8A and 8B are graphs illustrating voltage and current characteristics of the semiconductor power devices of the power system shown in FIG. 1 without the shunt capacitor CGSNT and the shunt resistor RGSNT, where the discrete semiconductor power devices have electrical characteristics suitable for slow switching applications.

[0048] Figure 8A shows a shunt capacitor C GSNT and shunt resistor R GSNT2 is a graph illustrating voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 during a turn-off transition without a power supply, the semiconductor power device having electrical characteristics suitable for slow switching applications.

[0049] [Figure 8B] FIG. 8B is a graph illustrating voltage and current characteristics of the discrete semiconductor power devices of the power system shown in FIG. 1 during a turn-on transition without shunt capacitor CGSNT and shunt resistor RGSNT, where the semiconductor power devices have electrical characteristics suitable for slow switching applications.

[0050] [Figure 9A] 9A and 9B are graphs illustrating voltage and current characteristics of semiconductor power devices of the power system shown in FIG. 1 having shunt capacitor CGSNT and shunt resistor RGSNT, the semiconductor power devices having electrical characteristics suitable for slow switching applications.

[0051] Figure 9A shows a shunt capacitor C GSNT and shunt resistor R GSNT 2 is a graph illustrating voltage and current characteristics of the discrete semiconductor power devices of the power system shown in FIG. 1 during a turn-off transition having electrical characteristics suitable for slow switching applications.

[0052] [Figure 9B] FIG. 9B is a graph showing voltage and current characteristics of a semiconductor power device of the power system shown in FIG. 1 during a turn-on transition having a shunt capacitor CGSNT and a shunt resistor RGSNT, the semiconductor power device having electrical characteristics suitable for slow switching applications. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] The embodiments described below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts not specifically described herein. It is understood that these concepts and applications are within the scope of the present disclosure and the accompanying claims.

[0054] As used herein, the terms first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that there may also be intervening elements that are directly on or extending directly onto the other element. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that there may also be intervening elements that are directly on or extending directly onto the other element. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Also, when an element is referred to as being "coupled" or "bonded" to another element, it will be understood that there may be intervening elements that are directly coupled or bonded to the other element, or that there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly bonded" to another element, there are no intervening elements present.

[0056] Relative terms such as "below" or "above" or "on" or "below" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It is understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0057] The terms used herein are used only for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that as used herein, "comprises", "comprising", "includes" and / or "including" specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements and / or groups thereof.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Furthermore, it will be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and related art, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0059] The embodiments are described herein with reference to schematic diagrams of embodiments of the present disclosure. Thus, the actual dimensions of layers and elements may vary and are expected to differ from the shapes of the figures, for example, as a result of manufacturing techniques and / or tolerances. For example, a region illustrated or described as a square or rectangle may be rounded or curved in shape, and a region shown as a straight line may have some irregularities. Thus, the regions illustrated in the figures are schematic, and the shapes are not intended to illustrate the exact shape of the region of a device, nor are they intended to limit the scope of the present disclosure. Furthermore, the size of a structure or region may be exaggerated relative to other structures or regions for illustrative purposes, and thus are provided to illustrate the general structure of the subject matter, and may or may not be drawn to scale. Common elements between the figures are indicated here with common element numbers and will not be described again later.

[0060] 1 shows an exemplary power system 10 having a voltage source gate driver 12 that couples to a semiconductor power device 14. The voltage source gate driver 12 receives an input gate signal V at an input terminal 22. IN and provides a controlled and amplified drive signal at output terminal 24 that is electrically coupled to semiconductor power device 14. In this manner, voltage source gate driver 12 operates as a current buffer and signal converter, with power converter 16 and gate driver resistor network 18 connected in series between input terminal 22 and output terminal 24 of voltage source gate driver 12. To effectively control the switching speed and gate delay of semiconductor power device 14, shunt capacitor C GSNT and shunt resistor R GSNT is connected in series between the first internal node 28 and the second internal node 38. In addition, a series-connected shunt capacitor C GSNT and shunt resistor R GSNTis connected in parallel with the gate driver resistor network 18 such that a first internal node 28 connects to the output node 26 of the power converter 16 and a second internal node 38 connects to the output terminal 24 of the voltage source gate driver 12. In this manner, the shunt capacitor C GSNT and shunt resistor R GSNT may be used as part of the voltage type gate driver 12 to decouple the switching speed of the semiconductor power device 14 from the gate delay of the semiconductor power device 14 and prevent any false gate loop oscillations and / or gate loop triggering in the semiconductor power device 14, as described in more detail elsewhere herein.

[0061] The semiconductor power device 14 may be a metal-oxide-semiconductor field effect transistor (MOSFET) Q3 having an integrated body diode D3, although the scope of the present disclosure is not so limited. The semiconductor power device 14 further comprises a gate terminal G, a drain terminal D, and a source terminal S. The body diode D3 provides an internal current conduction path from the source terminal S to the drain terminal D, and blocks high voltages and high currents from the drain terminal D to the source terminal S. Additionally, the MOSFET Q3 has a gate-to-source capacitance C GS , drain-source capacitance C GS , and the gate-drain capacitance C GD where the input capacitance C ISS is the gate-source capacitance C GS and the gate-drain capacitance C GD is the sum of.

[0062] The drain terminal D and the source terminal S may be connected to the load 20 at a first load node 34 and a second load node 36, respectively. The semiconductor power devices 14 in the power system 10 may be adapted to rectify, invert, convert, or otherwise manipulate electrical energy using a voltage source gate driver, such as the voltage source gate driver 12. The source terminal S of the MOSFET Q3 of the semiconductor power device 14 is coupled to a capacitor C DDand capacitor C EE The positive supply voltage V is regulated by DD and the negative supply voltage V EE , and uses the positive power supply voltage V DD It can refer to a positive rail voltage in the ranges 5V to 30V, 10V to 20V, or 12V to 15V. The negative supply voltage V EE It can refer to a negative rail voltage that is in the range 0V to -30V, -3V to -20V, -5V to -15V, or connected to ground. Alternatively, it can refer to a negative supply voltage V EE is a positive power supply voltage V depending on whether the semiconductor power device 14 is a normally-on semiconductor power device or a normally-off semiconductor power device. DD For a normally-off semiconductor power device 14 to turn on, a positive gate-source voltage V GS Therefore, the gate-source voltage V GS When the gate-source voltage V is 0 volts, the normally-off semiconductor power device 14 is in an off state. For the normally-on semiconductor power device 14 to be turned off, a negative gate-source voltage V GS Therefore, the gate-source voltage V GS When the potential is 0 volts, the semiconductor power device 14, which is a normally-on device, is in an on state.

[0063] The voltage-type gate driver 12 operates as a current buffer and signal converter and comprises a power converter 16 and a gate driver resistor network 18 connected in series between an input terminal 22 and an output terminal 24 of the voltage-type gate driver 12. The power converter 16 may be formed by a first transistor Q1, which is an N-channel MOSFET, and a second transistor Q2, which is a P-channel MOSFET. Here, the drain terminal D Q1 is the positive supply voltage V DD and the drain terminal D of the second transistor Q2 Q2 is the negative supply voltage V EEThe source terminal S of the first transistor Q1 is connected to Q1 is the source terminal S of transistor Q2 Q2 , and is electrically coupled to the output node 26. In addition, the gate terminal G Q1 is the gate terminal G of transistor Q2. Q2 , and electrically coupled to the input terminal 22. In operation, the power converter 16 receives an input gate signal V IN and produces a regulated output voltage V at output node 26 which connects to gate driver resistor network 18. REG In alternative embodiments, power converter 16 may be one of a voltage rectifier, regulator, inverter, or converter.

[0064] The gate driver resistor network 18 is connected between the output node 26 of the voltage type gate driver 12 and the output terminal 24. The gate driver resistor network 18 includes a turn-on gate resistor R G-ON and the turn-off gate resistor R G-OFF The turn-on gate resistor R G-ON is connected to the first diode D1 and the turn-on gate resistor R G-ON Rectifies the current flowing in the first direction through the turn-off gate resistor R G-OFF is connected to the second diode D2 and the turn-off gate resistor R G-OFF The first diode D1 is connected to a turn-on gate resistor R G-ON and the turn-off gate resistor R connected to the second diode D2. G-OFF are connected in parallel as shown in Figure 1, where the turn-on gate resistor R G-ON The value of the turn-off gate resistor R G-OFFThe value of may range from 0 to 10 MΩ, 1 kΩ to 5 MΩ, or 100 kΩ to 3 MΩ. The gate driver resistor network 18 may have an equivalent resistance value in the range of 0 Ω to 10 MΩ, 1 kΩ to 5 MΩ, or 100 kΩ to 3 MΩ.

[0065] Additionally, a series split-gate resistor R G can be used to electrically couple (i.e., connect in series between) the output terminal 24 of the voltage source gate driver 12 and the gate terminal G of the semiconductor power device 14. In this manner, the gate driver resistor network 18 may include a series split-gate resistor R having a value in the range of 0 Ω to 10 MΩ, 1 kΩ to 5 MΩ, or 100 kΩ to 3 MΩ. G 1 to provide a resistively rectified current and voltage to the output terminal 24 of the voltage source gate driver 12 which is connected to the gate terminal G of the semiconductor power device 14 using a turn-on gate resistor R G-ON , turn-off gate resistor R G-OFF , and a series split-gate resistor R G The value of the input capacitance C of the semiconductor power device 14 ISS This may affect the charge and discharge current of the input capacitance C ISS is the threshold voltage V of the semiconductor power device 14 before the state of the semiconductor power device 14 changes. TH must be charged or discharged above or below the turn-on gate resistor R G-ON and the turn-off gate resistor R G-OFF As the value of R increases, the gate delay increases and the switching speed of the semiconductor power device 14 from an OFF state to an ON state or vice versa decreases. Therefore, the turn-on gate resistor R G-ON and the turn-off gate resistor R G-OFF As the value of increases, the switching losses of the semiconductor power device 14 increase during operation of the power system 10. Here, the series split-gate resistor R GThe value of the shunt capacitor C may be increased so that the power system 10 meets electromagnetic compatibility and interference industry standards while avoiding oscillations. GSNT and shunt resistor R GSNT If there is no series split-gate resistor R G Increasing the value of ΔT introduces longer gate delays and higher switching losses that are undesirable in the operation of the semiconductor power device 14.

[0066] A series connected shunt capacitor C in parallel across the gate driver resistor network 18. GSNT and shunt resistor R GSNT The introduction of the shunt capacitor C allows for the decoupling of the switching speed of the semiconductor power device 14 from the gate delay of the semiconductor power device 14. This is particularly advantageous because it allows for the switching speed of the semiconductor power device 14 to be controlled while still maintaining a reduced gate delay. GSNT is the input capacitance C of the semiconductor power device 14 that reduces the gate delay. ISS Therefore, during the turn-on and turn-off periods, the shunt capacitor C GSNT is the input capacitance C of the semiconductor power device 14 ISS The gate-source voltage V acts as a series-connected capacitive voltage divider with GS Meanwhile, the shunt resistor R GSNT serves to prevent any false gate loop oscillations and / or gate loop triggering in the semiconductor power device 14. GSNT and shunt resistor R GSNT The application of is further advantageous because it eliminates the need for an external high voltage RC snubber circuit between the drain terminal D and source terminal S of the semiconductor power device 14.

[0067] Here, the shunt capacitor C GSNTThe value of can be determined (ie, calculated) using equations (1) and (2) for the desired turn-on and turn-off performance of power semiconductor device 14.

number

[0068] Therefore, the shunt resistor R GSNT The value of the shunt resistor R may range from 0 Ω to 10 MΩ, 1 kΩ to 5 MΩ, or 100 kΩ to 3 MΩ. GSNT The shunt capacitor C is used to achieve the vibration damping function. GSNT Note that the gate drive loop does not have to be directly connected in series with the supply voltage V. Thus, as long as a sufficient resistive component is present as part of the gate drive loop, the oscillation damping function is achieved. DD or V EE , a gate current path comprising a gate driver resistor network 18 and a semiconductor power device 14 .

[0069] It is important to note that the semiconductor power device 14 shown in FIG. 1 is a MOSFET Q3, but the scope of the present disclosure is not limited thereto. The MOSFET Q3 may be either a P-type MOSFET or an N-type MOSFET. Those skilled in the art will appreciate that the semiconductor power device 14 may be one of an insulated gate bipolar transistor (IGBT), a junction gate field effect transistor (JFET), a high electron mobility transistor (HEMT), and the like. Furthermore, the semiconductor power device 14 may comprise a half-bridge circuit topology 30, a parallel transistor connected circuit topology 30', or a common source circuit topology 30", as shown and described with reference to FIGS. 3A-3C. Here, the semiconductor power device 14 may form an individual package or a power module.

[0070] FIG. 2 shows a plurality of MOSFETs Q31 to Q3 connected in parallel as part of a semiconductor power device 14′. n1 shows an example power system 10′ having a plurality of MOSFETs Q31 to Q3 n (n is the count number), each of which is connected in parallel with integrated body diodes D31 to D3 n With the exception of semiconductor power device 14' having a common drain node and a common source node (not shown for ease of illustration) of semiconductor power device 14', power system 10' shown in Figure 2 is substantially similar to power system 10 described in Figure 1. Common drain and source nodes (not shown for ease of illustration) of semiconductor power device 14' may be connected to load 20 at first load node 34 and second load node 36, respectively. Elements shown in Figure 2 previously described in connection with Figure 1 will not be described here for the sake of brevity.

[0071] As shown in Figure 2, MOSFETs Q31 to Q3 n Each of these is connected to a series split-gate resistor R G1 ~R Gn where a series split-gate resistor R G1 ~R Gn MOSFETs Q31 to Q3 n In addition, a series split-gate resistor R G1 ~R Gn By increasing the value of each of the MOSFETs Q31 to Q3 of the semiconductor power device 14′, n The switching speed of each of the two resistors is reduced. Alternatively, a series split gate resistor R G1 ~R Gn By reducing the values ​​of each of the MOSFETs Q31 to Q3 of the semiconductor power device 14′, nThe switching speed of each one of the gate driver resistors 18 is increased. In one embodiment, a current buffer (not shown here for simplicity of illustration) stage can be applied between the power converter 16 and the gate driver resistor network 18 as part of the voltage type gate driver 12. The current buffer can increase the gate current capability of the voltage type gate driver 12 in high current, high power applications. This is particularly advantageous when multiple semiconductor power devices are connected in parallel, as shown in the semiconductor power device 14'. Here, the shunt capacitor C GSNT and shunt resistor R GSNT operates in a similar manner as above, taking advantage of the increased current drive capability of the current buffer to further minimize gate delay without affecting switching speed.

[0072] 3A-3C illustrate example circuit topologies that may be applied in various embodiments of the present disclosure as part of the semiconductor power devices 14 of the power system 10 shown in FIG. 1, where a half-bridge circuit topology 30, a parallel transistor connection circuit topology 30', and a common source circuit topology 30" (hereinafter also referred to as half-bridge 30, parallel transistor connection 30, and common source circuit 30") may be integrated and applied in separate packages or power modules as part of the semiconductor power devices 14 of the power system 10 to rectify, invert, convert, or otherwise manipulate electrical energy using a voltage source gate driver 12 that provides decoupling control of switching speed and gate delays associated with the semiconductor power devices 14, as shown in FIG.

[0073] As illustrated in FIGS. 3A-3C, the half-bridge circuit topology 30, the parallel transistor connection circuit topology 30′, and the common source circuit topology 30″ each include a first transistor and a second transistor, and the first transistor and the second transistor may be one of a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a junction gate field effect transistor (JFET), a high electron mobility transistor (HEMT), and the like.

[0074] 3A illustrates an exemplary half-bridge circuit topology 30. The half-bridge circuit topology 30 (also referred to as half-bridge 30) includes a high-side power semiconductor switching device, labeled high-side, including a first MOSFET device M1, and a low-side power semiconductor switching device, labeled low-side, including a second MOSFET device M2, a power source in the form of a bulk capacitor bank DC link, and a decoupling capacitor Cd electrically coupled between a positive direct current (DC) busbar DC+ and a negative DC busbar DC-. The first MOSFET device M1 includes a first gate terminal G1, a first source terminal S1, and a first drain terminal D1, and the second MOSFET device M2 includes a second gate terminal G2, a second source terminal S2, and a second drain terminal D2. As shown, a first drain terminal D1 of a first MOSFET device M1 connects to the positive DC bus bar DC+, a second source terminal S2 of a second MOSFET device M2 connects to the negative DC bus bar DC-, and a first source terminal S1 of the first MOSFET device M1 connects to a second drain terminal D2 of a second MOSFET device M2 forming a phase node N1 to which a phase terminal T1 connects. This configuration is commonly used in a variety of topologies including, but not limited to, multi-level converters, current source inverters, solid state circuit breakers, etc.

[0075] FIG. 3B illustrates a parallel transistor connection circuit topology 30′ in which a first MOSFET device M1 and a second MOSFET device M2 are connected to form a common source node N3 and a common drain node N2. The first MOSFET device M1 includes a first gate terminal G1, a first source terminal S1, and a first drain terminal D1, and the second MOSFET device M2 includes a second gate terminal G2, a second source terminal S2, and a second drain terminal D2. As shown in FIG. 3B, the first drain terminal D1 of the first MOSFET device M1 and the second drain terminal D2 of the second MOSFET device M2 are electrically connected to form a common drain node N2 and a common drain input / output terminal T2. Similarly, the first source terminal S1 of the first MOSFET device M1 and the second source terminal S2 of the second MOSFET device M2 are electrically connected to form a common source node N3 and a common source input / output terminal T3. The parallel transistor connection circuit topology 30′ can be utilized in high power applications where individual transistors cannot carry the high current required in high power applications. For example, the semiconductor power device 14 shown in FIG. 1 may further include power MOSFETs M1, M2 connected in parallel with each other as shown in FIG. 3B. It is noted that a parallel transistor connection, for example, a parallel transistor connection circuit topology 30' shown in FIG. 3, is particularly advantageous as it further increases the power levels associated with the semiconductor power device 14 shown in FIG. 1. Here, FIG. 2 illustrates multiple transistors connected in parallel, for example, in discrete packages, as part of the semiconductor power device 14'. Here, multiple parallel-connected MOSFETs Q31-Q3 n For the entire semiconductor power device 14', a single shunt resistor R GSNT and a single shunt capacitor C GSNT However, multiple MOSFETS Q31 to Q3 n Each of the parallel MOSFETs Q31-Q3 forming part of the semiconductor power device 14' n To avoid gate oscillation between G1 ~RGn will be established.

[0076] FIG. 3C illustrates a common source circuit topology 30″. As illustrated, the common source transistor circuit topology 30″ comprises a first MOSFET M1 having a first gate terminal G1, a first source terminal S1, and a first drain terminal D1, and a second MOSFET M2 having a second gate terminal G2, a second source terminal S2, and a second drain terminal D2. In this configuration, a first source S1 of the first MOSFET device M1 and a second source S2 of the second MOSFET device M2 are electrically connected to form a common source node N4. Furthermore, a first drain D1 of the first MOSFET device M1 forms an upper input / output terminal T4, and a second drain D2 of the second MOSFET device M2 forms a lower input / output terminal T5. The upper input / output terminal T4 and the lower input / output terminal T5 are coupled between a voltage source (not shown) configured to provide a DC supply voltage and a load, forming a bidirectional switch capable of blocking current in both directions and providing an on-state voltage or an off-state voltage. This configuration provides voltage blocking capability in both directions, from the first drain terminal D1 to the second drain terminal D2, or from the second drain terminal D2 to the first drain terminal D1. The common-source circuit topology 30" is therefore particularly advantageous as it enables a variety of power conversion functions.

[0077] Figures 4A and 4B show the shunt capacitor C GSNT There is a shunt resistor R GSNT There is no (R GSNT 2 is a graph showing the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1, with a voltage type gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device. However, the shunt resistor (R GSNT ) is not connected to the shunt capacitor (C GSNT) causes oscillations during turn-off and turn-on of semiconductor power device 14, as shown in Figures 4A and 4B, respectively. Elements described in Figures 4A and 4B above in connection with Figures 1-3 will not be described here for the sake of brevity.

[0078] Here, each of Figures 4A and 4B is taken from a positive supply voltage V of 15V. DD , negative power supply voltage V of -5V EE , and the gate-source voltage (V GS -time), drain-source voltage over time (V DS -time), and the drain-source current over time (I DS The semiconductor power device 14 is a MOSFET having a rated drain-source voltage V DS , and a rated drain-source current I of 120 A DS Furthermore, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25° C. and an input capacitance C ISS , 75 Ω turn-on gate resistor R G-ON , 75 Ω turn-off gate resistor R G-OFF , 0 Ω series split-gate resistor R G , and a threshold voltage V of 5V TH Therefore, the shunt capacitor C GSNT is calculated to be 8.5 nF using equations (1) and (2) above.

[0079] FIG. 4A is a graph illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1 during a turn-off transition. The power system 10 includes a shunt capacitor C GSNT and a shunt resistor R GSNT There is no (R GSNT =0Ω). The first graph shows the gate-source voltage V GS (V GSThe second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns off. DS (I DS -time), where turn-off time (t off ) was measured to be approximately 200 ns, and the turn-off delay time ( td(off) ) was measured to be approximately 180ns, and the turn-off current speed (di / dt off ) was measured to be approximately 4A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 20 V / ns, and the voltage rise time (t r ) is measured for approximately 20 ns. A large oscillation is observed as the gate-source voltage V GS , drain-source voltage V DS , and the drain-source current I DS is related to the shunt resistor R GSNT This is due to the absence of

[0080] FIG. 4B is a graph illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1 during a turn-on transition. The power system 10 includes a shunt capacitor C GSNT and a shunt resistor R GSNT There is no (R GSNT =0Ω). The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns on. DS (I DS -time), where turn-on time (t on) was measured to be approximately 120 ns, and the turn-on delay time (t d(on) ) was measured to be approximately 80ns, and the turn-on current speed (di / dt on ) was measured to be approximately 1A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 15 V / ns, and the drain-source voltage (V DS ) fall time (t f ) is measured and lasts for about 20 ns. As shown, the large oscillation occurs at the gate-source voltage V GS , drain-source voltage V DS , and the drain-source current I DS is related to the shunt resistor R GSNT Therefore, to maintain stability, a shunt resistor (R GSNT ) can be used to prevent gate oscillation of the semiconductor power device 14.

[0081] Figures 5A and 5B show the shunt capacitor C GSNT and shunt resistor R GSNT 5A and 5B, which are graphs illustrating voltage and current characteristics of a semiconductor power device 14 (i.e., a discrete device) of the power system 10 shown in FIG. 1 having a voltage source gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device. Elements described in FIGS. 5A and 5B above in connection with FIGS. 1-3 will not be described here for the sake of brevity.

[0082] Here, each of Figures 5A and 5B is based on a positive supply voltage V of 15V. DD , negative power supply voltage V of -5V EE , and the gate-source voltage (V GS -time), drain-source voltage over time (V DS -time), and the drain-source current over time (I DSThe semiconductor power device 14 is a MOSFET having a rated drain-source voltage V DS , and a rated drain-source current I of 120 A DS Further, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25° C., a turn-on gate resistor R G-ON , 75 Ω turn-off gate resistor R G-OFF , 0 Ω series split-gate resistor R G , 8.5nF input capacitance C ISS , and a threshold voltage V of 5V TH Therefore, the shunt capacitor C GSNT is calculated to be 8.5 nF using equations (1) and (2) above. As a result, the shunt resistor R GSNT The value of R is determined to be 22 Ω. As shown, the oscillations during the turn-off and turn-on transitions are significantly reduced in Figures 5A and 5B compared to Figures 4A and 4B. This is due to the shunt resistor R being large enough to damp the oscillations. GSNT This is the result of the introduction of

[0083] Figure 5A shows a shunt capacitor C GSNT and shunt resistor R GSNT 2A-2C are graphs illustrating voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1 during a turn-off transition. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns off. DS (I DS -time), where turn-off time (t off ) was measured to be approximately 200 ns, and the turn-off delay time (t d(off)) was measured to be approximately 180ns, and the turn-off current speed (di / dt off ) was measured to be approximately 4A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 20 V / ns, and the voltage rise time (t r ) is measured to be approximately 20ns. Therefore, the shunt resistor R GSNT It has been shown that having a gyro sensor helps reduce and eliminate vibrations.

[0084] Figure 5B shows the shunt capacitor C GSNT and shunt resistor R GSNT 2A-2C are graphs illustrating voltage and current characteristics of the semiconductor power device 14 of the power system 10 of FIG. 1 during a turn-on transition. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns on. DS (I DS -time), where turn-on time (t on ) was measured to be approximately 120 ns, and the turn-on delay time (t d(on) ) was measured to be approximately 80ns, and the turn-on current speed (di / dt on ) was measured to be approximately 1A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 15 V / ns, and the drain-source voltage (V DS ) fall time (t f ) is measured to be about 20 ns.

[0085] Figures 6A and 6B show the shunt capacitor C GSNT , shunt resistor R GSNT , and a series split-gate resistor R G3A is a graph showing voltage and current characteristics of the semiconductor power device 14 (i.e., half-bridge 30 power module) of the power system 10 shown in FIG. 1 having a voltage source gate driver 12 coupled to the semiconductor power device 14, which is a half-bridge 30 power module, as shown in FIG. Elements described in FIGS. 6A and 6B above in connection with FIGS. 1-3 will not be described here for the sake of brevity.

[0086] Here, each of Figures 6A and 6B is taken from a positive power supply voltage V of 15V. DD , negative power supply voltage V of -5V EE , and the gate-source voltage (V) over time based on measurements taken with a bus voltage of 800 V used. GS -time), drain-source voltage over time (V DS -time), and the drain-source current over time (I DS The semiconductor power device 14 is a half bridge 30 having a rated drain-source voltage V DS , and a rated drain-source current I of 50 A DS Furthermore, the half-bridge power module as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 19 mΩ at 25° C., a turn-on gate resistor R G-ON , 75 Ω turn-off gate resistor R G-OFF , 0 Ω series split-gate resistor R G , 3nF input capacitance C ISS , and a threshold voltage V of 5V TH Therefore, the shunt capacitor C GSNT is calculated to be 3 nF using equations (1) and (2) above. As a result, the shunt resistor R GSNT The value of is determined to be 15 Ω. As shown, the shunt capacitor C GSNT and shunt resistor R GSNT is a series split-gate resistor R GThis mitigates the longer gate delays and higher switching losses that can be caused by the introduction of a series split-gate resistor R G may be implemented to ensure that the semiconductor power device 14 meets electromagnetic compatibility and interference industry standards while avoiding vibrations.

[0087] FIG. 6A shows the turn-off transition with shunt capacitor C GSNT , shunt resistor R GSNT , and a series split-gate resistor R G 2A-2C are graphs illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1 having a gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns off. DS (I DS -time), where turn-off time (t off ) was measured to be approximately 68ns, and the turn-off delay time (t d(off) ) was measured to be approximately 48ns, and the turn-off current speed (di / dt off ) was measured to be approximately 6A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 37.5 V / ns, and the voltage rise time (t r ) was measured to be approximately 20 ns.

[0088] FIG. 6B shows the turn-on transition with shunt capacitor C GSNT , shunt resistor R GSNT , and a series split-gate resistor R G2A-2C are graphs illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1 having a gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns on. DS (I DS -time), where turn-on time (t on ) was measured to be approximately 72ns, and the turn-on delay time (t d(on) ) was measured to be approximately 56ns, and the turn-on current speed (di / dt on ) was measured to be approximately 2A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 37.5V / ns, and the voltage drop time (t f ) was measured to be approximately 16 ns.

[0089] 7A and 7B show the turn-on gate resistor R G-ON and the turn-off gate resistor R G-OFF 7A and 7B, which are graphs illustrating voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1 generated using different values ​​of V. The power system 10 includes a voltage type gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device. Elements described in FIGS. 7A and 7B above in connection with FIGS. 1-3 are not described here for the sake of brevity.

[0090] Here, each of Figures 7A and 7B is taken from a positive power supply voltage V of 15V. DD , negative power supply voltage V of -5V EE , and the gate-source voltage (V) over time based on measurements taken with a bus voltage of 800 V used. GS -time), drain-source voltage over time (V DS-time), and the drain-source current over time (I DS The semiconductor power device 14 is a MOSFET having a rated drain-source voltage V DS , and a rated drain-source current I of 120 A DS Furthermore, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25° C. and an input capacitance C ISS , and the threshold voltage V which is 5V TH Therefore, the shunt capacitor C GSNT is calculated to be 8.5 nF using equations (1) and (2) above. As a result, the shunt resistor R GSNT The value of is determined to be 22 Ω, where V GS -Time, V DS -Time, and I DS- Three graphs are generated for each of the time periods, and each of the three graphs has a different value (R G-ON =R G-OFF = 100Ω, R G-ON =R G-OFF = 150 Ω, and R G-ON =R G-OFF = 200 Ω) G-ON and the turn-off gate resistor R G-OFF As shown, the shunt capacitor C GSNT and shunt resistor R GSNT mitigates longer gate delays.

[0091] FIG. 7A shows the turn-off transition with different values ​​(R G-ON =R G-OFF = 100Ω, R G-ON =R G-OFF = 150 Ω, and R G-ON =R G-OFF = 200 Ω) G-ON and the turn-off gate resistor R G-OFF2A-2C are graphs illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1, generated using a MOSFET. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns off. DS (I DS -time), where R G-ON =R G-OFF = Turn-on gate resistor R with a value of 100 Ω G-ON and the turn-off gate resistor R G-OFF Regarding the turn-off time (t off ) was measured to be approximately 240ns, and the turn-off delay time (t d(off) ) was measured to be approximately 200ns, and the turn-off current speed (di / dt off ) was measured to be approximately 6A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 26 V / ns, and the voltage rise time (t r ) is measured to be approximately 30 ns. Furthermore, R G-ON =R G-OFF = Turn-on gate resistor R with a value of 150 Ω G-ON and the turn-off gate resistor R G-OFF Regarding the turn-off time (t off ) was measured to be approximately 280ns, and the turn-off delay time (t d(off) ) was measured to be approximately 240ns, and the turn-off current speed (di / dt off ) was measured to be approximately 2.5A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 16V / ns, and the voltage rise time (t r ) is measured to be approximately 50 ns. Finally, R G-ON =R G-OFF = Turn-on gate resistor R with a value of 200 ΩG-ON and the turn-off gate resistor R G-OFF Regarding the turn-off time (t off ) was measured to be approximately 320ns, and the turn-off delay time (t d(off) ) was measured to be approximately 280ns, and the turn-off current speed (di / dt off ) was measured to be approximately 1.6 A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 12 V / ns, and the voltage rise time (t r ) was measured to be approximately 70 ns.

[0092] FIG. 7B shows the turn-on transition and the different values ​​(R G-ON =R G-OFF = 100Ω, R G-ON =R G-OFF = 150 Ω, and R G-ON =R G-OFF = 200 Ω) G-ON and the turn-off gate resistor R G-OFF 2A-2C are graphs illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1, generated using a MOSFET. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns on. DS (I DS -time), where R G-ON =R G-OFF = Turn-on gate resistor R with a value of 100 Ω G-ON and the turn-off gate resistor R G-OFF For turn-on time (t on ) was measured to be approximately 240ns, and the turn-on delay time (t d(on) ) was measured to be approximately 160ns, and the turn-on current speed (di / dt on) was measured to be approximately 1.5A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 15V / ns, and the voltage fall time (t f ) is measured to be approximately 40 ns. Furthermore, R G-ON =R G-OFF = Turn-on gate resistor R with a value of 150 Ω G-ON and the turn-off gate resistor R G-OFF For turn-on time (t on ) was measured to be approximately 280ns, and the turn-on delay time (t d(on) ) was measured to be approximately 200ns, and the turn-on current speed (di / dt on ) was measured to be approximately 1A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 12V / ns, and the voltage fall time (t r ) is measured to be approximately 50 ns. Finally, R G-ON =R G-OFF = Turn-on gate resistor R with a value of 200 Ω G-ON and the turn-off gate resistor R G-OFF For turn-on time (t on ) was measured to be approximately 320 ns, and the turn-on delay time (t d(on) ) was measured to be approximately 240ns, and the turn-on current speed (di / dt on ) was measured to be approximately 0.75A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 10V / ns, and the voltage drop time (t f ) was measured to be approximately 60 ns.

[0093] 8A and 8B show the shunt capacitor C GSNT and shunt resistor R GSNT8A and 8B, which are graphs illustrating voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1, without the need for a discrete semiconductor power device 14, which has electrical characteristics suitable for slow switching applications, such as a circuit breaker. The power system 10 includes a voltage type gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device and is suitable for slow switching applications, such as a solid state circuit breaker. Elements described in FIGS. 8A and 8B above in connection with FIGS. 1-3 are not described here for the sake of brevity.

[0094] Here, each of Figures 8A and 8B is taken from a positive supply voltage V of 15V. DD , negative supply voltage V of -6V EE , and the gate-source voltage (V GS -time), drain-source voltage over time (V DS -time), and the drain-source current over time (I DS The semiconductor power device 14 is a MOSFET having a rated drain-source voltage V DS , and a rated drain-source current I of 120 A DS Further, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25° C., a turn-on gate resistor R G-ON , 3kΩ turn-off gate resistor R G-OFF , 0 Ω series split-gate resistor R G , 8.5nF input capacitance C ISS , and a threshold voltage V of 5V TH has.

[0095] Figure 8A shows a shunt capacitor C GSNT and shunt resistor R GSNT2A-2C are graphs illustrating voltage and current characteristics of the semiconductor power device 14 of the power system 10 of FIG. 1 during a turn-off transition without a current source, the semiconductor power device 14 having electrical characteristics suitable for slow switching applications. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns off. DS (I DS -time), where turn-off time (t off ) was measured to be approximately 22ns, and the turn-off delay time (t d(off) ) was measured to be approximately 21 ns, and the turn-off current speed (di / dt off ) was measured to be approximately 0.09 A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 0.89 V / ns, and the voltage rise time (t r ) is measured to be approximately 1 μs.

[0096] Figure 8B shows the shunt capacitor C GSNT and shunt resistor R GSNT 2A-2C are graphs illustrating the voltage and current characteristics of the semiconductor power device 14 of the power system 10 of FIG. 1 during a turn-on transition without a gate-source current, the semiconductor power device 14 having electrical characteristics suitable for slow switching applications. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns on. DS (I DS-time), where turn-on time (t on ) was measured to be approximately 12 μs, and the turn-on delay time (t d(on) ) was measured to be approximately 11 μs, and the turn-on current speed (di / dt on ) was measured to be approximately 0.13 A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 0.93 V / ns, and the voltage drop time (t f ) is measured to be approximately 1 μs.

[0097] Figures 9A and 9B show the shunt capacitor C GSNT and shunt resistor R GSNT 9A and 9B, which are graphs illustrating voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1, the semiconductor power device 14 having electrical characteristics suitable for slow switching applications. The power system 10 includes a voltage type gate driver 12 coupled to the semiconductor power device 14, which is a discrete semiconductor device and is suitable for slow switching applications, such as a solid state circuit breaker. Elements described in FIGS. 9A and 9B above in connection with FIGS. 1-3 will not be described here for the sake of brevity.

[0098] Here, each of Figures 9A and 9B is based on a positive supply voltage V of 15V. DD , negative supply voltage V of -6V EE , and the gate-source voltage (V) over time based on measurements taken with a bus voltage of 800 V used. GS -time), drain-source voltage over time (V DS -time), and the drain-source current over time (I DS The semiconductor power device 14 is a MOSFET having a rated drain-source voltage V DS , and a rated drain-source current I of 120 A DSFurther, the MOSFET as part of the semiconductor power device 14 has a drain-source on-state resistance Rds(ON) of 9 mΩ at 25° C., a turn-on gate resistor R G-ON , 3kΩ turn-off gate resistor R G-OFF , 0 Ω series split-gate resistor R G , 8.5nF input capacitance C ISS , and a threshold voltage V of 5V TH Therefore, the shunt capacitor C GSNT is calculated to be 8.5 nF using equations (1) and (2) above. As a result, the shunt resistor R GSNT The value is determined to be 22 Ω.

[0099] Figure 9A shows a shunt capacitor C GSNT and shunt resistor R GSNT 2A-2C are graphs illustrating voltage and current characteristics of the discrete semiconductor power device 14 of the power system 10 shown in FIG. 1 during a turn-off transition having electrical characteristics suitable for slow switching applications. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns off. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns off. DS (I DS -time), where turn-off time (t off ) was measured to be approximately 3 μs, and the turn-off delay time (t d(off) ) was measured to be approximately 2 μs, and the turn-off current speed (di / dt off ) was measured to be approximately 0.05 A / ns, and the turn-off voltage speed (dv / dt off ) was measured to be approximately 0.88 V / ns, and the voltage rise time (t r ) is measured to be approximately 1 μs.

[0100] Figure 9B shows the shunt capacitor C GSNT and shunt resistor R GSNT 2A-2C are graphs illustrating voltage and current characteristics of the semiconductor power device 14 of the power system 10 shown in FIG. 1 during a turn-on transition having electrical characteristics suitable for slow switching applications. The first graph shows the gate-source voltage V GS (V GS The second graph shows the drain-source voltage V V over time when the semiconductor power device 14 turns on. DS (V DS The third graph shows the drain-source current I over time when the semiconductor power device 14 turns on. DS (I DS -time), where turn-on time (t on ) was measured to be approximately 5.5 μs, and the turn-on delay time (t d(on) ) is measured and is approximately equal to 4.5 μs, and the turn-on current speed (di / dt on ) was measured and is approximately equal to 0.07A / ns, and the turn-on voltage speed (dv / dt on ) was measured to be approximately 0.87 V / ns, and the voltage drop time (t f ) is measured to be approximately 1 μs.

[0101] Therefore, as shown, the turn-off delay time (t d(off) ) and turn-on delay time (t d(on) ) is the shunt capacitor C GSNT and shunt resistor R GSNT are significantly reduced compared to those in FIGS. 8A and 8B.

[0102] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features described herein may be combined to obtain additional advantages. Any of the various embodiments disclosed herein may be combined with one or more of the other disclosed embodiments, unless otherwise stated herein.

[0103] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A voltage-type gate driver, a power converter including an input configured to receive a first gating signal and providing a regulated output voltage at an output node; a gate driver resistor network coupled between the output node of the power converter and an output terminal of the voltage source gate driver; a shunt capacitor connected in series with a shunt resistor, the shunt capacitor and the shunt resistor being connected in parallel across the gate driver resistor network; Equipped with the output terminal is configured to provide a second gate signal to a gate of a semiconductor power device; the gate driver resistor network comprising: a turn-on resistor coupled in series with a first diode, the first diode configured to rectify a current through the turn-on resistor in a first direction toward the output terminal of the voltage source gate driver; a turn-off resistor coupled in series with a second diode configured to rectify current through the turn-off resistor in a second direction away from the output terminal of the voltage source gate driver; A voltage-type gate driver comprising:

2. The shunt capacitor is a shunt capacitor C ＧＳＮＴ having values ​​calculated using the following equation solved for [0010] In the formula, V ＤＤ is the positive power supply voltage, and V ＥＥ is the negative supply voltage, and C ＩＳＳ is the input capacitance of the semiconductor power device, and V ＴＨ 2. The voltage source gate driver of claim 1, wherein V is a threshold voltage of the semiconductor power device.

3. 2. The voltage source gate driver of claim 1, wherein the shunt resistor is in the range of 0 Ω to 10 MΩ.

4. 2. The voltage source gate driver of claim 1, wherein the gate driver resistor network has an equivalent resistance value in the range of 0 Ω to 10 MΩ.

5. The voltage source gate driver of claim 1 , wherein the power converter comprises one of a voltage rectifier, a regulator, an inverter, or a converter.

6. The voltage source gate driver of claim 1 further comprising a solid-state circuit breaker.

7. The voltage source gate driver of claim 1 , wherein the semiconductor power devices include a half-bridge circuit topology.

8. 2. The voltage source gate driver of claim 1, wherein the semiconductor power device is a parallel transistor connected circuit topology.

9. 2. The voltage source gate driver of claim 1, wherein the semiconductor power device is in a common source circuit topology.

10. 2. The voltage source gate driver of claim 1, wherein the semiconductor power device is one of a half-bridge circuit topology, a parallel transistor connection circuit topology, or a common source circuit topology.

11. 2. The voltage source gate driver of claim 1, wherein the semiconductor power device is a metal oxide field effect transistor.

12. 2. The voltage source gate driver of claim 1, wherein the semiconductor power device is one of an insulated gate bipolar transistor (IGBT), a junction gate field effect transistor (JFET), or a high electron mobility transistor (HEMT).

13. 1. A power system comprising: A voltage-type gate driver, a power converter including an input configured to receive a first gating signal and providing a regulated output voltage at an output node; a gate driver resistor network coupled between the output node of the power converter and an output terminal of the voltage source gate driver; a shunt capacitor connected in series with a shunt resistor, the shunt capacitor and the shunt resistor being connected in parallel across the gate driver resistor network; Equipped with a voltage source gate driver, the output terminal configured to provide a second gate signal; a semiconductor power device comprising a gate terminal, a drain terminal, and a source terminal, the semiconductor power device configured to receive the second gate signal at the gate terminal; Equipped with the gate driver resistor network comprising: a turn-on resistor coupled in series with a first diode, the first diode configured to rectify a current through the turn-on resistor in a first direction toward the output terminal of the voltage source gate driver; a turn-off resistor coupled in series with a second diode configured to rectify current through the turn-off resistor in a second direction away from the output terminal of the voltage source gate driver; A power system comprising:

14. The shunt capacitor is a shunt capacitor C ＧＳＮＴ having values ​​calculated using the following equation solved for [0025] In the formula, V ＤＤ is the positive power supply voltage, and V ＥＥ is the negative supply voltage, and C ＩＳＳ is the input capacitance of the semiconductor power device, and V ＴＨ 14. The power system of claim 13, wherein: V is a threshold voltage of the semiconductor power device.

15. The power system of claim 13, wherein the shunt resistor is in the range of 0 Ω to 10 MΩ.

16. 14. The power system of claim 13, wherein the gate driver resistor network has an equivalent resistance value in the range of 0 Ω to 10 MΩ.

17. 14. The power system of claim 13, wherein the power converter comprises one of a voltage rectifier, a regulator, an inverter, or a converter.

18. 14. The power system of claim 13, wherein the semiconductor power device is a metal oxide field effect transistor.

19. 14. The power system of claim 13, wherein the semiconductor power devices are in one of a half bridge circuit topology, a parallel transistor connected circuit topology, or a common source circuit topology.

20. 14. The power system of claim 13, wherein the semiconductor power device is one of an insulated gate bipolar transistor (IGBT), a junction gate field effect transistor (JFET), or a high electron mobility transistor (HEMT).

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