Memory System

Abstract

To provide a memory system capable of efficiently reading data from a nonvolatile memory.SOLUTION: A memory system includes a non-volatile memory including a plurality of dies, a controller, and a first queue, a second queue, and a command buffer provided for each die. In response to the read command to be executed being stored in the command buffer corresponding to the first die, the controller determines whether it is necessary to issue a next read command subsequent to the read command to be executed. In response to determining that the next read command needs to be issued, the controller specifies a second die in which second data subsequent to the first data requested to be read by the read command to be executed is stored, and stores the read command for reading the second data in a second queue corresponding to the second die.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE The present invention relates to a technique for controlling a non-volatile memory. [Background technology]

[0002] In recent years, memory systems equipped with non-volatile memories have become widespread. One such memory system is a solid-state drive (SSD) equipped with a NAND flash memory.

[0003] In memory systems such as SSDs, it is necessary to improve the throughput of read processing.

[0004] In addition, depending on the host, it may be required that the read target data specified in the read request issued by the host be transferred to the host in the order from the first data to the last data contained in the read target data.

[0005] In memory systems, there is a need for technology that allows data to be read efficiently from non-volatile memories. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Pat. No. 11,409,436 [Patent Document 2] U.S. Pat. No. 10,338,846 [Patent Document 3] US Patent Application Publication No. 2007 / 0005922 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a memory system and a control method that can efficiently read data from a non-volatile memory. [Means for solving the problem]

[0008] According to an embodiment, a memory system includes a non-volatile memory including a plurality of dies, a controller configured to control the plurality of dies, and a first queue, a second queue, and a command buffer provided for each of the dies. The first queue is a queue for storing a single read command associated with a read request from a host, or a first read command among a plurality of read commands associated with a read request from the host. The second queue is a queue for storing any subsequent read command among the plurality of read commands. The command buffer is a buffer for storing a read command to be executed that is fetched from a queue selected from the first queue and the second queue. In response to the read command to be executed being stored in the command buffer corresponding to a first die among the plurality of dies, the controller determines whether or not it is necessary to issue a next read command following the read command to be executed, based on whether or not the read command to be executed is a read command other than the single read command and the last read command among the plurality of read commands. In response to determining that it is necessary to issue the next read command, the controller refers to a logical-physical address conversion table to identify a second die in which second data subsequent to the first data requested to be read by the read command to be executed is stored, and a length of the second data stored in the second die. The controller generates a read command for reading the second data. The controller executes a process of transmitting the read command to be executed to the first die, and a process of storing the generated read command in the second queue corresponding to the second die. [Brief description of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Diagram 2] 1 is a block diagram showing an example of the configuration of a representative die among a plurality of dies included in a nonvolatile memory of a memory system according to an embodiment. [Diagram 3] 4 is a timing diagram illustrating a process for reading data in parallel from multiple dies of a memory system according to an embodiment. [Figure 4] 1 is a block diagram showing an example of the relationship between a host read command pool, multiple flush command queues, multiple dies, multiple channels, and a read buffer in a memory system according to an embodiment. [Diagram 5] 1 is a block diagram showing an example of the configuration of each of a plurality of flash command queues in a memory system according to an embodiment. [Figure 6] 1 is a diagram showing an example of a read process executed in a memory system according to an embodiment; [Figure 7] 1 is a diagram showing an example of a procedure of a read process executed in a memory system according to an embodiment; [Figure 8] 11 is a timing chart showing an example of the order in which read data is received at a read buffer provided in a memory system according to the embodiment, and an example of the order in which the read data is transferred from the read buffer to a host. [Figure 9] 13A and 13B are diagrams showing an example of read data held in a read buffer in a first round and an example of read data held in a read buffer in a second round. [Figure 10] 11 is a timing chart showing an example of read timing of a nonvolatile memory and an example of transfer timing from the nonvolatile memory to a read buffer. [Figure 11] 1 is a flowchart showing the procedure of a read process executed in a memory system according to an embodiment. [Figure 12]11 is a flowchart showing a procedure of a process executed when reading of a non-volatile memory is completed in a memory system according to an embodiment. [Figure 13] 11 is a flowchart showing a procedure of a process executed upon completion of data transfer to a read buffer in a memory system according to an embodiment. [Figure 14] 11 is a flowchart showing a procedure of a process executed when data transfer to a host is completed in a memory system according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described with reference to the drawings.

[0011] In the following, it is assumed that the memory system according to the embodiment is realized as a solid state drive (SSD). Fig. 1 is a block diagram showing an example of the configuration of an information processing system 1 including the memory system according to the embodiment. The information processing system 1 includes a host (host device) 2 and an SSD 3. The host 2 and the SSD 3 can be connected via a bus 7.

[0012] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile device. The host 2 accesses the SSD 3. Specifically, the host 2 issues a write command to the SSD 3, which is a command for writing data. The host 2 also issues a read command to the SSD 3, which is a command for reading data.

[0013] The SSD 3 is a storage device that can be connected to the host 2. The SSD 3 includes a non-volatile memory. The SSD 3 is capable of writing data to the internal non-volatile memory. The SSD 3 is also capable of reading data from the internal non-volatile memory.

[0014] The communication between the SSD 3 and the host 2 is performed via a bus 7. The bus 7 is a transmission path that connects the host 2 and the SSD 3. The bus 7 is, for example, a PCI express TM (PCIe TM ) bus. The PCIe bus is a full duplex transmission path. The full duplex transmission path includes both a transmission path for transmitting data and input / output (I / O) commands from the host 2 to the SSD 3, and a transmission path for transmitting data and responses from the SSD 3 to the host 2. The I / O command is a command for writing data to the nonvolatile memory or reading data from the nonvolatile memory. The I / O command is, for example, a write command or a read command. Hereinafter, a write command issued by the host 2 is also referred to as a write request or a host write command. Also, a read command issued by the host 2 is also referred to as a read request or a host read command.

[0015] An example of a logical interface standard for connecting the host 2 and the SSD 3 is NVM express. TM (NVMe TM ) standard may be used. In the NVMe standard interface, communication between the host 2 and the SSD 3 is performed using a pair of queues including at least one submission queue (SQ) and a completion queue (CQ) associated with the at least one submission queue (SQ). This pair of queues is called a submission queue / completion queue pair (SQ / CQ pair).

[0016] Next, the configuration of the host 2 will be described.

[0017] The host 2 includes a processor 21 and a memory 22. The processor 21 and the memory 22 are interconnected via an internal bus 20.

[0018] The processor 21 is, for example, a CPU. The processor 21 executes software (host software) loaded into the memory 22 from the SSD 3 or another storage device connected to the host 2. The host software includes, for example, an operating system, a file system, and an application program.

[0019] The memory 22 is, for example, a volatile memory. The memory 22 is also referred to as a main memory, a system memory, or a host memory. The memory 22 is, for example, a dynamic random access memory (DRAM). A part of the storage area of ​​the memory 22 is used as a host read buffer 221. The host read buffer 221 is a storage area to which read data read from the non-volatile memory of the SSD 3 should be transferred. The host read buffer 221 is allocated on the memory 22 by the host 2 for each host read command. The host read command includes a data pointer, which is a parameter specifying location information indicating a location in the memory 22 to which the read data should be transferred. This host read command can specify the location information to which the read data should be transferred using a physical region page (PRP) entry, a PRP list, or a scatter-gather list (SGL). For example, assume that the host read command specifies the location information using a PRP entry. In this case, the host read command includes a first PRP entry field (PRP1) and a second PRP entry field (PRP2). Each of PRP1 and PRP2 uses a PRP entry to specify a location (memory page) in memory 22 to which read data should be transferred. The PRP entry is a pointer to a memory page. The PRP entry includes a page base address of the memory page and an offset within that memory page. The page base address is an address that identifies one memory page.

[0020] Also, another part of the storage area of ​​the memory 22 is used to store SQ / CQ pairs 222. Each of the submission queues SQ included in the SQ / CQ pairs 222 is a queue used to issue an I / O command (host write command, host read command) to the SSD 3. Each of the submission queues SQ includes a plurality of slots. Each of the plurality of slots is capable of storing one I / O command. The host 2 creates the submission queues SQ in the memory 22 of the host 2. Also, the host 2 issues a submission queue create command to the SSD 3. The address indicating the storage position in the memory 22 where each of the submission queues SQ was created, the size of each of the submission queues SQ, the identifier of the completion queue CQ associated with these submission queues SQ, etc. are notified to the SSD 3 by the submission queue create command.

[0021] The completion queue CQ included in the SQ / CQ pair is a queue used to receive a completion response from the SSD 3 indicating the completion of an I / O command. The completion response includes information indicating a status indicating the success or failure of processing the completed command. The completion response is also called a command completion or a command completion notification. The completion queue CQ includes a plurality of slots. Each of the plurality of slots is capable of storing one completion response. The host 2 creates the completion queue CQ in the memory 22 of the host 2. The host 2 also issues a completion queue create command to the SSD 3. The address indicating the storage location in the memory 22 where the completion queue CQ was created, the size of this completion queue CQ, etc. are notified to the SSD 3 by the completion queue create command.

[0022] Next, the internal configuration of the SSD 3 will be described.

[0023] The SSD 3 includes a controller 4 and a non-volatile memory such as a NAND flash memory 5. The SSD 3 may further include a random access memory such as a dynamic random access memory (DRAM) 6 which is a volatile memory.

[0024] The controller 4 is a memory controller. The controller 4 is, for example, a control circuit such as a system-on-a-chip (SoC). The controller 4 is electrically connected to the NAND flash memory 5. The controller 4 processes each I / O command received from the host 2 to execute a read process for reading data from the NAND flash memory 5 and a write process for writing data to the NAND flash memory 5. For example, a Toggle interface or an Open NAND Flash Interface (ONFI) is used as a physical interface connecting the controller 4 and the NAND flash memory 5. The functions of each part of the controller 4 can be realized by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and the processor.

[0025] The NAND flash memory 5 may be a two-dimensional flash memory or a three-dimensional flash memory. The NAND flash memory 5 includes, for example, a plurality of dies. The dies are also called memory dies, flash dies, memory chips, and flash chips. Each of these dies is realized as a NAND flash memory die. Hereinafter, the dies are called flash dies. FIG. 1 shows, as an example, a case in which the NAND flash memory 5 includes 32 flash dies #0 to #31.

[0026] The DRAM 6 includes, for example, a storage area that stores a logical-to-physical address translation table (L2P table) 61. The L2P table 61 is a table that stores mapping information. The mapping information is information that indicates the mapping between each logical address and each physical address of the NAND flash memory 5 in a unit of a predetermined management size. The logical address is an address used by the host 2 to access the SSD 3. As the logical address, for example, a logical block address (LBA) is used. The physical address is an address that indicates a storage location in the NAND flash memory 5. The physical address can be expressed by, for example, a combination of a flash die address, a block address, a page address, and an offset address within the page.

[0027] Next, the internal configuration of the controller 4 will be described. The controller 4 includes, for example, a host interface (host I / F) 41, a static RAM (SRAM) 42, a CPU 43, a direct memory access controller (DMAC) 44, an error correction circuit 45, a NAND interface (NAND I / F) 46, and a DRAM interface (DRAM I / F) 47. The host interface 41, SRAM 42, CPU 43, DMAC 44, error correction circuit 45, NAND interface 46, and DRAM interface 47 are interconnected via an internal bus 40.

[0028] The host interface 41 is a communication interface circuit that executes communication with the host 2. The host interface 41 is realized by, for example, a PCIe controller. The host interface 41 also includes an arbitration mechanism. This arbitration mechanism is a mechanism that selects a submission queue SQ from which an I / O command is to be fetched from a plurality of submission queues SQ included in the SQ / CQ pair 222. The arbitration mechanism is, for example, a round robin arbitration mechanism or a weighted round robin arbitration mechanism.

[0029] The SRAM 42 is a volatile memory. The storage area of ​​the SRAM 42 is used, for example, as a working area for the CPU 43. The SRAM 42 includes, for example, a storage area for storing a host read command pool 421, a storage area for storing a flash command queue 422, and a storage area for storing a read buffer (RB) 423.

[0030] The host read command pool 421 is a storage area used to store a group of host read commands among a plurality of I / O commands issued by the host 2. Each host read command specifies a start LBA (SLBA), a data length, a data pointer, etc. The start LBA (SLBA) indicates the first LBA of one or more LBAs corresponding to the data to be read. The data length indicates the length of the data to be read, that is, the size of the data to be read. The data length may be expressed by the number of LBAs. The data pointer is location information indicating the location in the memory 22 of the host 2 to which the data to be read should be transferred.

[0031] The flash command queue 422 is an internal queue in which a group of read commands (flash read commands) for reading data from the flash memory 5 is stored. A flash command queue 422 is provided for each flash die. A flash command queue 422 corresponding to a certain flash die stores a read command (also called a flash read command) for reading data from this flash die. Details of the flash command queue 422 will be described later with reference to FIG. 3 and FIG. 4.

[0032] The read buffer (RB) 423 is a data buffer for temporarily storing read data read from the flash memory 5. The read buffer (RB) 423 is used to improve the throughput of the read process in the SSD 3. The throughput of the read process indicates the amount of read data transferred from the SSD 3 to the host 2 per unit time. The read data is data (user data) read from the flash memory 5.

[0033] The CPU 43 is a processor. The CPU 43 loads a control program (firmware) stored in the flash memory 5 or a ROM (not shown) into the SRAM 42. The CPU 43 executes the firmware to perform various processes. The firmware may be loaded into the DRAM 6.

[0034] The CPU 43, for example, as a flash translation layer (FTL), manages data stored in the flash memory 5 and manages blocks included in the flash memory 5. The management of data stored in the flash memory 5 includes, for example, management of mapping information. The CPU 42 uses the mapping information of the L2P table 61 to manage the mapping between each logical address and each physical address in units of a management size. The management size is, for example, 4 KiB.

[0035] In the flash memory 5, data can be written to a page in a block only once per program / erase cycle of the block. That is, new data cannot be directly overwritten to a memory location (physical memory location) in a block where data has already been written. Therefore, when updating data already written to a physical memory location in a block, the controller 4 writes the new data to an unwritten page (free page) in the block (or another block) and treats the previous data as invalid data. In other words, the controller 4 writes update data corresponding to a logical address to a different physical memory location, not to the physical memory location where the previous data corresponding to the logical address is stored. The controller 4 then updates the L2P table 61 to associate the logical address with a physical address indicating the different physical memory location.

[0036] The management of blocks contained in the flash memory 5 includes management of defective blocks (bad blocks) contained in the flash memory 5, wear leveling, and garbage collection (GC).

[0037] GC is an operation for increasing the number of free blocks. A free block means a block that does not contain valid data. The controller 4 manages the state of each block (free block, active block, written page, free page, amount of valid data, amount of invalid data, etc.). In the GC operation, the controller 4 selects some blocks containing a mixture of valid data and invalid data as GC source blocks. The GC source blocks are also called copy source blocks. The controller 4 copies the valid data contained in the GC source blocks to GC destination blocks (e.g., free blocks). The GC destination blocks are also called copy destination blocks. Here, valid data means data associated with a logical address. Data associated with a logical address as the latest data is valid data, and may be read by the host 2 later. Invalid data means data that is not associated with any logical address. Data that is not associated with any logical address is data that may no longer be read by the host 2. When valid data is copied from a GC source block to a GC destination block, the controller 4 updates the L2P table 61 to map each logical address of the copied valid data to a physical address of the copy destination. A block that contains only invalid data as a result of valid data being copied to another block is released as a free block. This allows the block to be reused for writing data after a data erase operation is performed on the block.

[0038] The DMAC 44 is a circuit that executes direct memory access (DMA). The DMAC 44 executes data transfer between the memory 22 of the host 2 and the SRAM 42 (or the DRAM 6). For example, in a read process, the DMAC 44 executes a process of transferring read data from the flash memory 5 to a read buffer (RB) 423 and a process of transferring read data from the read buffer (RB) 423 to the memory 22 of the host 2.

[0039] The error correction circuit 45 performs an encoding process when data is written to the flash memory 5. In the encoding process, the error correction circuit 45 adds an error correction code (ECC) as a redundant code to the data to be written to the flash memory 5. In the decoding process, the error correction circuit 45 performs a decoding process when data is read from the flash memory 5. In the decoding process, the error correction circuit 45 uses the ECC added to the data read from the flash memory 5 to perform error correction on the data.

[0040] The NAND interface 46 is a circuit that controls the NAND flash memory 5. The NAND interface 46 is electrically connected to a plurality of flash dies included in the NAND flash memory 5.

[0041] Each flash die can operate independently. Therefore, the flash die functions as a unit capable of operating in parallel. The NAND interface 46 includes, for example, NAND controllers 461-0, 461-1, ..., 461-7. The NAND controllers 461-0, 461-1, ..., 461-7 are connected to channels ch0, ch1, ..., ch7, respectively. Each of the NAND controllers 461-0, 461-1, ..., 461-7 is connected to one or more flash dies via a corresponding channel. FIG. 1 illustrates a case in which four flash dies are connected to each of channels ch0, ch1, ..., ch7. In this case, the NAND controller 461-0 is connected to flash dies #0, #8, #16, and #24 via channel ch0. The NAND controller 461-1 is connected to flash dies #1, #9, #17, and #25 via channel ch1. And, the NAND controller 461-7 is connected to the flash dies #7, #15, #23, and #31 via the channel ch7. The flash dies #0, #1, ..., #7 are treated as the bank BNK0 by the controller 4. The flash dies #8, #9, ..., #15 are treated as the bank BNK1 by the controller 4. The flash dies #16, #17, ..., #23 are treated as the bank BNK2 by the controller 4. The flash dies #24, #25, ..., #31 are treated as the bank BNK3 by the controller 4. The bank is a unit for operating multiple flash dies in parallel by interleaving operation.

[0042] In the configuration of the NAND flash memory 5 shown in FIG. 1, the controller 4 can access the flash dies #0 to #31 in parallel by using seven channels and bank interleaving operations. Therefore, the controller 4 can write or read data to a maximum of 32 flash dies in parallel (number of parallel accesses=32). Each of the flash dies #0 to #31 may have a multi-plane configuration having multiple planes. For example, if each of the flash dies #0 to #31 includes two planes, the controller 4 can write or read data to a maximum of 64 planes in parallel (number of parallel accesses=64).

[0043] The DRAM interface 47 is a circuit that controls the DRAM 6. The DRAM interface 47 stores data in the DRAM 6. In addition, the DRAM interface 47 reads the data stored in the DRAM 6.

[0044] Next, a functional configuration of the CPU 43 will be described. In addition to the components that function as an FTL, the CPU 43 includes a write processing unit 431, a read processing unit 432, a scheduler 433, and a read data transfer control unit 434. A part or all of the write processing unit 431, the read processing unit 432, the scheduler 433, and the read data transfer control unit 434 may be realized by dedicated hardware of the controller 4.

[0045] The write processing unit 431 executes write processing by processing each write request (host write command) received from the host 2. The write processing includes, for example, a process of acquiring write data associated with the host write command from the memory 22 of the host 2, a process of writing the write data to a storage location in the NAND flash memory 5, and a process of updating the L2P table 61 to map a physical address indicating the storage location where the write data has been written to a logical address specified by the host write command.

[0046] The read processing unit 432 executes a read process by processing each read request (host read command) received from the host 2. The read process includes, for example, a process of converting a logical address designated by the host read command into a physical address by referring to the L2P table 61, a process of calculating position information indicating a position on the memory 22 of the host 2 to which data should be transferred based on a data pointer designated by the host read command (also referred to as a PRP / SGL decode process), a process of reading data from a storage position in the NAND flash memory 5 indicated by the physical address, and a process of transferring the read data to a position on the memory 22 of the host 2 indicated by the calculated position information.

[0047] The read processing executed by the read processing unit 432 is roughly divided into a scheduling processing and a read data transfer processing. The scheduling processing is a processing for issuing one or more read commands to one or more flash dies for reading data from the NAND flash memory 5 based on each read request received from the host 2. Each read command for reading data from the NAND flash memory 5 may include, for example, a physical address indicating the physical memory location where the data to be read is stored, and the length of this data.

[0048] This scheduling process is executed by the scheduler 433. The read data transfer process is a process of transferring read data read from each flash die to the memory 22 (host read buffer 221) of the host 2. This read data transfer process is executed by the read data transfer control unit 434. The scheduler 433 and the read data transfer control unit 434 may be realized as components of the read processing unit 432.

[0049] The scheduler 433 performs scheduling processing so as to maximize the number of flash dies on which data read operations are performed in parallel, i.e., the number of parallel reads, in order to maximize the throughput of the read processing. The scheduler 433 also performs scheduling processing so as to transfer to the host 2 the read target data specified by a read request (host read command) received from the host 2 in the order from the first data to the last data included in the read target data.

[0050] The scheduling process uses a host read command pool 421 and a flash command queue 422 provided for each flash die.

[0051] The host read command pool 421 is used to store command management information indicating the contents of each read request (host read command). For example, one piece of command management information for one read request may be held in the host read command pool 421. The command management information may include information specified by the corresponding host read command, such as a start LBA, a data length, a data pointer, and the like.

[0052] The flash command queue 422 corresponding to one flash die includes a first queue, a second queue, and a command buffer.

[0053] The first queue is a queue for storing a single read command associated with a host read command from the host 2, or the first read command of multiple read commands associated with a host read command from the host 2. The single read command associated with a host read command is a single read command for reading the read target data specified by this host read command from one flash die. When the flash die in which the read target data is stored is, for example, flash die #m, the scheduler 433 stores the read command for reading the read target data in the first queue corresponding to flash die #m.

[0054] On the other hand, the first read command among the multiple read commands associated with the host read command is a read command for reading the first data of the read target data specified by this host read command from a certain flash die. When the size of the read target data is relatively large, the read target data may be stored across two or more flash dies. When the flash die in which the first data of the read target data is stored is, for example, flash die #m, the scheduler 433 stores the first read command among the multiple read commands associated with the host read command, that is, the read command for reading the first data of the read target data, in the first queue corresponding to flash die #m.

[0055] The second queue is a queue for storing any of the subsequent read commands among the multiple read commands associated with the host read command. Any of the subsequent read commands among the multiple read commands is any of the second and subsequent read commands among the multiple read commands. For example, when the second data among the read target data specified by a certain host read command is stored in flash die #m, the scheduler 433 stores the read command for reading the second data, that is, the second read command among the multiple read commands associated with this host read command, in the second queue corresponding to flash die #m. Also, when the third data among the read target data is stored in flash die #n, the scheduler 433 stores the read command for reading the third data, that is, the third read command among the multiple read commands associated with this host read command, in the second queue corresponding to flash die #n.

[0056] The command buffer is a buffer for storing a read command to be executed that is fetched from a queue selected from the first queue and the second queue. For example, the command buffer corresponding to the flash die #m stores a read command to be executed that is fetched from a queue selected from the first queue corresponding to the flash die #m and the second queue corresponding to the flash die #m as a read command to be sent to the flash die #m.

[0057] In response to a read command to be executed being stored in a command buffer corresponding to a certain flash die (e.g., flash die #m), scheduler 433 determines whether or not it is necessary to issue a next read command following the read command to be executed, based on whether the read command to be executed is a single read command or a read command other than the final read command among multiple read commands.

[0058] Each of the read commands stored in the first queue and the second queue may be accompanied by additional information, which includes information indicating the relationship between the corresponding host read command and this read command, and a command pointer that is a pointer to command management information of the corresponding host read command.

[0059] The information indicating the relationship between the host read command and this read command includes, for example, offset information indicating an offset from the first read command to the read command among one or more read commands associated with the host read command, and end information indicating that the read command is the last read command among one or more read commands associated with the host read command. For example, a read command represented by "CMDx Part0" or "CMDx-1" is the first read command associated with the host read command CMDx. A read command represented by "CMDx Part1" or "CMDx-2" is the second read command associated with the host read command CMDx. If this second read command is the last read command associated with the host read command CMDx, the additional information of the second read command may further include end information. A single read command associated with a certain host read command CMDx may be represented by "CMDx Part0" or "CMDx-1". Since the single read command is also the last read command, the additional information of the single read command may further include end information.

[0060] The command pointer is an address indicating the storage location in the SRAM 42 where command management information (start LBA, data length, data pointer, etc.) of the corresponding host read command is stored.

[0061] The scheduler 433 can determine whether the read command to be executed is a single read command or a read command other than the final read command among multiple read commands, based on the additional information added to the read command to be executed, or based on both the additional information and the command management information.

[0062] If the read command to be executed is a single read command, or if the read command to be executed is the last read command of multiple read commands, scheduler 433 determines that it is not necessary to issue a next read command following the read command to be executed.

[0063] On the other hand, if the read command to be executed is the first or middle read command among multiple read commands, the scheduler 433 determines that it is necessary to issue the next read command following the read command to be executed, that is, it is necessary to read the next data following the data to be read from the flash die #m by the read command to be executed.

[0064] In response to determining that it is necessary to issue the next read command, the scheduler 433 refers to the L2P table 61 to identify the die (flash die #n) in which data (second data) subsequent to the data (first data) requested to be read by the read command to be executed is stored, and the length of the second data stored in this flash die #n. Then, the scheduler 433 generates a read command for reading the second data.

[0065] After generating a read command for reading the second data, the scheduler 433 executes a process of sending the read command to be executed to the flash die #m and a process of storing the generated read command in a second queue corresponding to the flash die #n.

[0066] By the above scheduling process, when the read target data specified by one host read command is distributed among multiple flash dies, multiple read commands corresponding to the first data to the last data of the read target data, respectively, can be sent to the multiple flash dies in the order of the first read command to the last read command among the multiple read commands. As a result, the read target data can be read from the NAND flash memory 5 in the order of the first data to the last data included in the read target data.

[0067] In addition, in the above scheduling process, when a read command to be executed is stored in a command buffer corresponding to a certain flash die (e.g., flash die #m), that is, when it is determined to send a certain read command to the flash die #m via a command buffer corresponding to the flash die #m, the flash die in which the second data is stored and the length of the second data are identified. This makes it possible to execute a process of identifying the flash die in which the second data is stored and the length of the second data while a read operation corresponding to a read command preceding the read command to be executed is being executed in the flash die #m. While a read operation corresponding to a read command preceding the read command to be executed is being executed in the flash die #m, the read command to be executed cannot be sent to the flash die #m. Therefore, it is possible to efficiently identify the flash die in which the second data is stored and the length of the second data by utilizing the waiting time for the completion of the read operation corresponding to the preceding read command.

[0068] Therefore, compared to first identifying all of the flash dies in which each of the multiple data included in the read target data is stored, it is possible to quickly store the first read command for reading the first data included in the read target data in the first queue corresponding to the flash die in which the first data is stored.

[0069] Here, an example of a process for identifying a flash die on which first data is stored, the length of the first data stored in the flash die, another flash die on which second data subsequent to the first data is stored, and the length of the second data stored in the other flash die will be described. Here, it is assumed that the length of the data to be read specified by the host read command is 8 (=8LBA=32KiB), the length of the first data is 4 (=4LBA=16KiB), the length of the second data is 4 (=4LBA=16KiB), and the first data and the second data are distributed across two flash dies.

[0070] In the process of identifying the flash die on which the first data is stored, the scheduler 433, for example, obtains a physical address associated with the start LBA specified by the host read command from the L2P table 61. Then, the scheduler 433 identifies the flash die on which the first data is stored based on the obtained physical address (for example, the upper bit portion of the obtained physical address).

[0071] In the process of identifying the length of the first data stored in the identified flash die, the scheduler 433, for example, obtains a physical address associated with the start LBA+1 from the L2P table 61. If the physical address associated with the start LBA and the physical address associated with the start LBA+1 are consecutive physical addresses in the same flash die, the scheduler 433 changes the value indicating the length of the first data from 1 to 2. Then, the scheduler 433 obtains a physical address associated with the start LBA+2 from the L2P table 61. If the physical address associated with the start LBA+1 and the physical address associated with the start LBA+2 are consecutive physical addresses in the same flash die, the scheduler 433 increases the value indicating the length of the first data by 1 and changes the value indicating the length of the first data from 2 to 3. Then, the scheduler 433 obtains a physical address associated with the start LBA+3 from the L2P table 61. If the physical address associated with the start LBA+2 and the physical address associated with the start LBA+3 are consecutive physical addresses in the same flash die, the scheduler 433 increases the value indicating the length of the first data by 1 and changes the value indicating the length of the first data from 3 to 4. Then, the scheduler 433 obtains the physical address associated with the start LBA+4 from the L2P table 61. If the flash die corresponding to the physical address associated with the start LBA+4 is different from the flash die corresponding to the physical address associated with the start LBA+3, the scheduler 433 determines that the length of the first data is 4. Then, the scheduler 433 generates a read command CMD-0 for reading the first data, and stores the generated read command CMD-0 in the first queue corresponding to the flash die in which the first data is stored. This read command CMD-0 includes, for example, the physical address associated with the start LBA, the data length (=4), a command pointer, offset information, and the like. The scheduler 433 may update the command management information in the SRAM 42 so that information indicating the contents of the read command CMD-0 is added to the command management information.

[0072] In the process of identifying the flash die on which the second data is stored, the scheduler 433 may identify the start LBA+4 as the first LBA of the second data, where 4 is the data length of the first data specified by the read command CMD-0. The start LBA may be obtained by referring to the command management information using the pointer specified by the read command CMD-0.

[0073] The scheduler 433 obtains a physical address associated with the start LBA+4 from the L2P table 61. Then, the scheduler 433 identifies the flash die on which the second data is stored based on the obtained physical address (for example, the upper bit portion of the obtained physical address).

[0074] In the process of identifying the length of the second data stored in the identified flash die, the scheduler 433, for example, obtains a physical address associated with start LBA+5 from the L2P table 61. If the physical address associated with start LBA+4 and the physical address associated with start LBA+5 are consecutive physical addresses in the same flash die, the scheduler 433 changes the value indicating the length of the second data from 1 to 2. Then, the scheduler 433 obtains a physical address associated with start LBA+6 from the L2P table 61. If the physical address associated with start LBA+5 and the physical address associated with start LBA+6 are consecutive physical addresses in the same flash die, the scheduler 433 increases the value indicating the length of the second data by 1 and changes the value indicating the length of the second data from 2 to 3. Then, the scheduler 433 obtains a physical address associated with start LBA+7 from the L2P table 61. If the physical address associated with the start LBA+6 and the physical address associated with the start LBA+7 are consecutive physical addresses in the same flash die, the scheduler 433 increases the value indicating the length of the second data by 1 and changes the value indicating the length of the second data from 3 to 4. The sum of the length of the first data and the current length of the second data matches the data length indicated by the command management information. Therefore, the scheduler 433 determines that the length of the second data is 4. Then, the scheduler 433 generates a read command CMD-1 for reading the second data, and stores the generated read command CMD-1 in a second queue corresponding to the flash die in which the second data is stored. This read command CMD-1 includes, for example, a physical address associated with the start LBA+4, a data length (=4), a command pointer, offset information, and the like. The scheduler 433 may update the command management information on the SRAM 42 so that information indicating the contents of the read command CMD-1 is further added to the command management information.

[0075] The read data transfer control unit 434 executes a data transfer control process to transfer the read target data specified by the host read command received from the host 2 to the host 2 in the order from the first data to the last data contained in the read target data.

[0076] The time required for a data read operation (read time tR) may differ for each flash die. Therefore, in order to ensure that the read target data is read from the flash die in the order from the first data to the last data included in the read target data, the read data transfer control unit 434 executes the following process.

[0077] Here, it is assumed that after a read command to be executed for reading first data is sent to flash die #m, a next read command for reading second data following the first data is sent to flash die #n.

[0078] After the first data is read to the page buffer of the flash die #m, the read data transfer control unit 434 reads the first data from the page buffer of the flash die #m. That is, in the flash die #m, an operation (sensing operation) of reading the first data from the memory cell array to the page buffer is executed. When the sensing operation is completed in the flash die #m, the read data transfer control unit 434 reads the first data from the page buffer of the flash die #m.

[0079] Then, after both the reading of the first data to the page buffer of flash die #m and the reading of the second data to the page buffer of flash die #n are completed, the read data transfer control unit 434 reads the second data from the page buffer of flash die #n.

[0080] In other words, when the reading of the second data to the page buffer of the flash die #n is completed while the reading of the first data to the page buffer of the flash die #m is not completed, the read data transfer control unit 434 waits until the reading of the first data to the page buffer of the flash die #m is completed without reading the second data from the page buffer of the flash die #n. After the reading of the first data to the page buffer of the flash die #m is completed, the read data transfer control unit 434 executes the process of reading the first data to the page buffer of the flash die #m and the process of reading the second data from the page buffer of the flash die #n.

[0081] In this way, the process of rearranging the multiple data included in the read target data in the order from the first data to the last data is executed by controlling the timing of reading data from the page buffer of each flash die. As a result, even if tR differs for each flash die, the read target data can be transferred to the host 2 in the order from the first data to the last data included in the read target data.

[0082] Moreover, the read data transfer control unit 434 executes the process of allocating the read buffer 423 to each of the multiple flash dies as follows.

[0083] Here, it is assumed that after a read command to be executed for reading first data is sent to flash die #m, a next read command for reading second data following the first data is sent to flash die #n.

[0084] Upon completion of reading the first data to the page buffer of the flash die #m, the read data transfer control unit 434 allocates a first read buffer, which is a memory area in the read buffer 423, to the flash die #m and transfers the first data from the page buffer of the first die to the first read buffer.

[0085] Upon completion of reading the second data to the page buffer of the flash die #n, the read data transfer control unit 434 determines whether the first read buffer has been allocated to the flash die #m. If the first read buffer has already been allocated to the flash die #m, the read data transfer control unit 434 allocates a second read buffer, which is another storage area in the read buffer 423, to the flash die #n and transfers the second data from the page buffer of the flash die #n to the second read buffer.

[0086] This makes it possible to prevent data that cannot be transferred to the host 2 from remaining in the read buffer 423 for a long period of time, thereby minimizing the capacity of the read buffer 423 that needs to be provided in the SSD 3.

[0087] Next, the configuration of the flash die will be described. Figure 2 is a block diagram showing an example of the configuration of one representative memory die among the multiple flash dies included in the NAND flash memory 5. The other flash dies basically have the same configuration.

[0088] Here, a configuration example of flash die #0 is shown as a representative example of multiple flash dies. The other flash dies have the same configuration as flash die #0. Also, here, a case where flash die #0 has a multi-plane configuration including two planes is shown as an example.

[0089] Flash die #0 includes two planes (plane PLN0 and plane PLN1) and two peripheral circuits (peripheral circuit 51-0 and peripheral circuit 51-1) corresponding to the two planes (plane PLN0 and plane PLN1), respectively.

[0090] Each of the planes PLN0 and PLN1 includes a memory cell array. The memory cell array of each of the planes PLN0 and PLN1 includes blocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 is a unit of a data erase operation. Each of the blocks BLK0 to BLKx-1 is also referred to as an erase block, a flash block, or a memory block. Each of the blocks BLK0 to BLKx-1 includes pages P0 to Py-1. Each of the pages P0 to Py-1 is a unit of a data write operation and a data read operation. Each of the pages P0 to Py-1 includes, for example, a plurality of memory cells connected to the same word line.

[0091] Each of the peripheral circuits 51-0 and 51-1 is a circuit that controls the memory cell array of the corresponding plane. The peripheral circuit 51-0 includes a page buffer 511-0. The page buffer 511-0 is a buffer for temporarily storing data to be written to the memory cell array of the plane PLN0 or data read from the memory cell array of the plane PLN0. Similarly, the peripheral circuit 51-1 also includes a page buffer 511-1. The page buffer 511-1 is a buffer for temporarily storing data to be written to the memory cell array of the plane PLN1 or data read from the memory cell array of the plane PLN1.

[0092] The parallel read operation will now be described with reference to Figure 3, which is a timing diagram illustrating the process for reading data from multiple flash dies in parallel.

[0093] The data read operation from each flash die includes a sense operation and a data output operation (Data out). The sense operation is an operation of reading data from the memory cell array to the page buffer. The data output operation (Data out) is an operation of transferring data from the page buffer to the controller 4 via the channel ch. In each flash die, the sense operation in the plane PLN0 can be executed simultaneously with the sense operation in the plane PLN1. However, since the planes PLN0 and PLN1 of each flash die share the same channel, the data output operation of transferring data from the page buffer of the plane PLN0 to the controller 4 and the data output operation of transferring data from the page buffer of the plane PLN1 to the controller 4 cannot be executed simultaneously. Similarly, the banks BNK0 to BNK3 can operate independently of each other, but cannot transfer data simultaneously via the same channel. On the other hand, since the channels ch1 to ch7 are independent of each other as shown in FIG. 1, the data transfers via the channels ch1 to ch7 can be executed simultaneously.

[0094] For this reason, in SSD3, as shown in FIG. 3, data reading from a total of eight planes (BNK0, PLN0), (BNK0, PLN1), (BNK1, PLN0), (BNK1, PLN1), (BNK2, PLN0), (BNK2, PLN1), (BNK3, PLN0), and (BNK3, PLN1) that share channel ch0 is performed in parallel such that data transfer from these eight planes is performed in a time-division manner via channel ch0.

[0095] Similarly, data reads from a total of eight planes (BNK0, PLN0), (BNK0, PLN1), (BNK1, PLN0), (BNK1, PLN1), (BNK2, PLN0), (BNK2, PLN1), (BNK3, PLN0), and (BNK3, PLN1) that share channel ch1 are performed in parallel such that data transfers from these eight planes are performed in a time-division multiplexed manner via channel ch1.

[0096] Next, an overview of the read process will be given. Figure 4 is a block diagram showing an example of the relationship between a host read command pool, multiple flash command queues, multiple dies, multiple channels, and a read buffer.

[0097] Host read commands received from the host 2 are accumulated in a host read command pool 421. The controller 4 executes the following process for each host read command accumulated in the host read command pool 421.

[0098] The controller 4 acquires a physical address corresponding to the logical address specified by the host read command from the L2P table 61. The controller 4 identifies a flash die in which the read target data specified by the host read command is stored based on the acquired physical address. The controller 4 generates a read command for reading the read target data. Then, the controller 4 stores the generated read command in a flash command queue corresponding to the identified flash die.

[0099] The controller 4 is provided with flash command queues 422-0 to 422-31 that correspond one-to-one to the flash dies #0 to #31. For example, the flash command queue 422-0 corresponding to the flash die #0 can store multiple read commands for reading data from the flash die #0. The flash command queue 422-1 corresponding to the flash die #1 can store multiple read commands for reading data from the flash die #1. And the flash command queue 422-31 corresponding to the flash die #31 can store multiple read commands for reading data from the flash die #31.

[0100] The controller 4 transmits read commands from the flash command queues 422-0 to 422-31 to the flash dies #0 to #31, respectively. Each of the flash dies #0 to #31 executes a sense operation to read data from the memory cell array to a page buffer. The read data read from each of the flash dies #0 to #31 is transferred to the controller 4 via a corresponding channel and stored in the read buffer 423. The controller 4 transfers data corresponding to each host read command from the read buffer 423 to the host 2.

[0101] Here, a process for maximizing the number of parallel reads will be described.

[0102] When the size of data to be read specified by each host read command is relatively small, multiple read commands are issued to different flash dies based on different combinations of host read commands, which requires that these read commands be executed in parallel.

[0103] On the other hand, the size of the data to be read specified by one host read command may be relatively large. For example, if the page size is 16KiB, the maximum size of data read by one read command is 16KiB. If the number of planes per flash die is 2, the maximum size of data read by one read command is 32KiB. If the number of planes per flash die is 4, the maximum size of data read by one read command is 64KiB.

[0104] A single host read command may require large read target data, such as 2 MiB, and if such large read target data is distributed across different flash dies, multiple read commands associated with the single host read command will be generated.

[0105] For example, when the number of planes per flash die is 2, the page size is 16KiB, and the size of the data to be read specified by one host read command is 128KiB, four read commands associated with the host read command may be generated. For example, when the first 32KiB data of the 128KiB read target data is stored in flash die #0, the second 32KiB data of the 128KiB read target data is stored in flash die #1, the third 32KiB data of the 128KiB read target data is stored in flash die #2, and the fourth 32KiB data of the 128KiB read target data is stored in flash die #7, the first read command for reading the first 32KiB data is sent to flash die #0 via flash command queue 422-0. The second read command for reading the second 32KiB data is sent to flash die #1 via flash command queue 422-1. A third read command for reading the third 32 KiB of data is sent to flash die #2 via flash command queue 422-2. A fourth read command for reading the fourth 32 KiB of data is sent to flash die #7 via flash command queue 422-7.

[0106] The busy / read states vary for each flash die, and the data read time (tR) may also vary for each flash.

[0107] For this reason, if multiple read commands associated with the same host read command are simply sent to multiple flash dies, multiple pieces of data will be transferred from different flash dies to the read buffer 423 in an order different from the order in which they are sent to the host 2. This causes the size of the read buffer 423 that needs to be provided in the SSD 3 to become huge.

[0108] Therefore, in this embodiment, the controller 4 performs the following scheduling process.

[0109] The controller 4 sends a read command to the flash die if the read can be performed and immediately transferred to the host 2 .

[0110] For multiple read commands associated with one host read command, if all of the multiple read commands from the first read command to the immediately preceding read command have already been issued to the other flash dies, the next read command following the immediately preceding read command is issued to the flash die. This makes it possible to transmit the multiple read commands associated with the host read command to the different flash dies in the same order as the order in which the multiple data included in the read target data specified by this host read command should be transferred to the host 2. As a result, basically, the multiple data included in the read target data can be read from the different flash dies in the same order as the order in which this data should be transferred to the host 2.

[0111] The controller 4 prohibits read commands associated with the same host read command from being simultaneously queued in a flash command queue corresponding to the same flash die. The first read command among multiple read commands associated with the same host read command can be issued unconditionally as long as the flash die is not busy.

[0112] Furthermore, the controller 4 performs the following read data rearrangement process.

[0113] The controller 4 executes the read data sorting process by controlling the timing of transfer of read data from each flash die to the read buffer 423.

[0114] For example, assume that a first read command to read the first data included in the read target data specified by the same host read command is sent to flash die #0, a second read command to read the second data included in the read target data is sent to flash die #1, and a third read command to read the third data included in the read target data is sent to flash die #2.

[0115] After completing the reading of the first data to the page buffer of flash die #0, the controller 4 reads the first data of the read target data from the page buffer of flash die #0. In this case, after completing the reading of the first data to the page buffer of flash die #0, the controller 4 allocates a first read buffer (one storage area in the read buffer 423) to the flash die #0, and transfers the first data from the page buffer of flash die #0 to the first read buffer.

[0116] In this way, as for the top data of the read target data, once reading of that top data into the page buffer is completed, that top data can be read unconditionally from the page buffer.

[0117] Then, after both the reading of the first data to the page buffer of flash die #0 and the reading of the second data to the page buffer of flash die #1 are completed, the controller 4 reads the second data from the page buffer of flash die #1. In this case, in response to the completion of the reading of the second data from the page buffer of flash die #1, the controller 4 determines whether or not the first read buffer has been allocated to the flash die #0. If the first read buffer has already been allocated to the flash die #0, the controller 4 allocates the second read buffer (another area in the read buffer 423) to the flash die #1 and transfers the second data from the flash die #1 page buffer to the second read buffer. On the other hand, if the first read buffer has not been allocated to the flash die #0, the controller 4 allocates the second read buffer to the flash die #1 after the first read buffer has been allocated to the flash die #0.

[0118] In this way, the second data is read from the page buffer of flash die #1 on the condition that the reading of the first data to the page buffer is completed. If the reading of the second data to the page buffer of flash die #1 is completed while the reading of the first data to the page buffer of flash die #0 is not completed, the controller 4 waits until the reading of the first data to the page buffer of flash die #0 is completed without reading the second data from the page buffer of flash die #1. Then, after the reading of the first data to the page buffer of flash die #0 is completed, the controller 4 executes the process of reading the first data from the page buffer of flash die #0 and the process of reading the second data from the page buffer of flash die #1.

[0119] Then, after the first data has been read into the page buffer of flash die #0, the second data into the page buffer of flash die #1, and the third data into the page buffer of flash die #2, the controller 4 reads the third data from the page buffer of flash die #2.

[0120] If the reading of the second data to the page buffer of flash die #2 is completed while at least one of the reading of the first data to the page buffer of flash die #0 or the reading of the second data to the page buffer of flash die #1 is not completed, the controller 4 waits for the reading of the first data to the page buffer of flash die #0 and the reading of the second data to the page buffer of flash die #1 to both be completed without reading the second data from the page buffer of flash die #2.

[0121] This read data sorting process ensures that the read target data specified by the host read command is transferred to the host 2 in the order from the first data to the last data contained in the read target data, even if tR is different for each flash die.

[0122] In addition, since the read buffer is assigned to each flash die in the order from the first data to the last data, the controller 4 can start transferring data from a flash die to the read buffer as soon as the controller 4 assigns a read buffer to the flash die. In addition, as soon as the transfer of data from the flash die to the read buffer is completed, the controller 4 can start transferring data from the read buffer to the host 2.

[0123] In this way, the order of data transfer from the read buffer to the host 2 and the order of data transfer from the flash die to the read buffer match the order of allocation of the read buffer to the individual dies.

[0124] Next, the total capacity of the read buffer 423 required to be provided in the SSD 3 will be described. The total capacity of the read buffer 423 can be set so that data transfer from the flash dies of all channels to the controller 4 can be performed continuously, and data transfer to the host 2 via a bus 7 such as a PCIe bus can also be performed continuously. Here, if the read bandwidth of the entire flash memory 5 is sufficiently larger than the bandwidth per channel, the performance degradation due to the variation in tR for each flash die becomes inconspicuous. The read bandwidth of the entire flash memory 5 is expressed by the following formula.

[0125] Read Bandwidth = (1 / tR) × page size × total number of dies × planes per die Here, 1 / tR indicates the number of sense operations that can be executed per unit time. The total number of dies is the total number of flash dies provided in the SSD 3. The planes per die is the number of planes per flash die.

[0126] The bandwidth per channel is smaller than the bandwidth of a bus 7 such as a PCIe bus. When the bandwidth of the PCIe bus (PCIeBandwidth, hereinafter sometimes abbreviated as PCIeBW): bandwidth per channel (Bandwidth per channel, hereinafter sometimes abbreviated as BW / C) is, for example, 4:1, in this embodiment, at least five read buffers are provided on the SRAM 42 so that the entire bandwidth of the PCIe bus can be used to transfer read data to the host 2.

[0127] Any four of these five read buffers are used to temporarily store read data transferred in parallel from the flash memory 5 to the controller 4. In other words, the four read buffers are used as input buffers for read data. Each input buffer receives, at a slow speed, read data from the flash die that is transferred at a slow speed, and stores the received read data.

[0128] Any one of the five read buffers is used to transfer read data to the host 2 via the PCIe bus. That is, one read buffer is used as an output buffer for read data. The read data stored in the output buffer is read out from the output buffer at a high speed and transferred to the memory 22 of the host 2 via the PCIe bus.

[0129] Next, a description will be given of a configuration example of the flash command queue 422. Fig. 5 is a block diagram showing a configuration example of each of the multiple flash command queues 422 in the memory system 3 according to the embodiment.

[0130] The flash command queue 422 included in the SRAM 42 includes flash command queues 422-0 to 422-31 that correspond one-to-one to the flash dies #0 to #31, respectively. For example, the flash command queue 422-0 is used to store a group of read commands for reading data from the flash die #0. The relationships between the other flash command queues and the other flash dies are similar.

[0131] Each of the flash command queues 422-0 to 422-31 includes one leading read queue, one following read queue, and one next command buffer. Each of the leading read queue and the following read queue is, for example, a first-in, first-out (FIFO) queue having a depth of 1 or more. For example, the flash command queue 422-0 includes a leading read queue 4221-0, a following read queue 4222-0, and a next command buffer 4223-0. The flash command queue 422-1 includes a leading read queue 4221-1, a following read queue 4222-1, and a next command buffer 4223-1. And the flash command queue 422-31 includes a leading read queue 4221-31, a following read queue 4222-31, and a next command buffer 4223-31.

[0132] The leading read queues 4221-0 to 4221-31 are also referred to as first queues. For example, the leading read queue 4221-0 stores a single read command associated with a host read command among read commands for reading data stored in the flash die #0, or the first read command among multiple read commands associated with the host read command.

[0133] The following read queues 4222-0 to 4222-31 are also referred to as second queues. For example, the following read queue 4222-0 stores any of the subsequent read commands among the multiple read commands associated with the host read command among the read commands for reading data stored in the flash die #0.

[0134] The next command buffers 4223-0 to 4223-31 are also simply referred to as command buffers. For example, the next command buffer 4223-0 stores a read command to be executed that is fetched from a queue selected from the leading read queue 4221-0 and the following read queue 4222-0.

[0135] The process of sending one or more read commands associated with each host read command fetched from the host 2 to any of the flash dies #0 to #31 is controlled by the scheduler 433.

[0136] First, a host read command fetched from the submission queue (SQ) of the host 2 is stored in the host read command pool 421 .

[0137] The scheduler 433 selects one host read command from the multiple host read commands stored in the host read command pool 421. The scheduler 433 acquires from the L2P table 61 a physical address associated with the logical address specified by the selected host read command. The scheduler 433 identifies a flash die in which the read target data specified by the selected host read command is stored based on the acquired physical address. The scheduler 433 then generates a single read command associated with the host read command, or a first read command among the multiple read commands associated with the host read command. The single read command is one read command for reading the read target data specified by the host read command from one flash die. The first read command among the multiple read commands is one read command for reading the first data of the read target data specified by the host read command from one flash die.

[0138] The scheduler 433 selects a flash command queue corresponding to the identified flash die, and stores a single read command associated with the host read command, or a leading read command among multiple read commands associated with the host read command, in a leading read queue of the selected flash command queue.

[0139] When read commands are stored in both the leading read queue and the following read queue corresponding to a certain flash die, the scheduler 433 preferentially selects the following read queue over the leading read queue, fetches the read command stored in the following read queue as a read command to be executed, and stores the fetched read command to be executed in the corresponding next command buffer. By preferentially selecting the following read queue in this way, the number of host read commands that require reading from different flash dies to be executed simultaneously can be limited. In addition, once execution of multiple read commands associated with one host read command has started, it is possible to suppress the start of other host read commands that require reading from different flash dies. As a result, it is possible to read all of the multiple data included in the read target data specified by one host read command from the flash memory 5 within a certain short time, and it is possible to prevent the read buffer 423 from being monopolized for a long time by a large amount of data that cannot start being transferred to the host 2.

[0140] In addition, when the read command stored in the leading read queue is a single read command associated with one host read command, the leading read queue may be preferentially selected because the processing corresponding to the single read command is completed quickly, so even if the execution of multiple read commands associated with one host read command is started once and then the single read command is executed, the time required to complete the processing of the multiple read commands associated with one host read command is not very long.

[0141] In response to storing a read command selected from the leading read queue or the following read queue in the next command buffer, i.e., in response to deciding to send a read command to a flash die via the command buffer, the scheduler 433 determines whether it is necessary to issue a next read command following the read command to be executed stored in the next command buffer, i.e., whether it is necessary to read data following the data requested to be read by the read command to be executed.

[0142] When it is necessary to issue the next read command, the scheduler 433 generates the next read command. At this time, the scheduler 433 refers to the L2P table 61 to identify the flash die in which data subsequent to the data requested to be read by the read command to be executed and stored in the next command buffer is stored, and the length of this subsequent data stored in the identified flash die.

[0143] Then, the scheduler 433 executes a process of sending the read command to be executed that is stored in the next command buffer to the flash die, and a process of storing the next read command following the read command to be executed in a following read queue corresponding to the identified flash die.

[0144] For example, if the flash die storing data subsequent to the data requested to be read by the read command to be executed stored in the next command buffer 4223-0 corresponding to the flash die #0 is the flash die #1, the scheduler 433 identifies the flash die #1 storing the subsequent data and the length of the subsequent data stored in the flash die #1 at the stage of the next command buffer 4223-0 corresponding to the flash die #0. Then, the scheduler 433 generates a next read command for reading the subsequent data from the flash die #1. Then, the scheduler 433 executes a process of sending the read command to be executed to the flash die #0 and a process of storing the generated next read command in the following read queue 4222-1 corresponding to the flash die #1. In this case, after sending the read command to be executed to the flash die #0, the generated next read command may be stored in the following read queue 4222-1 corresponding to the flash die #1. Alternatively, the generated next read command may be stored in the following read queue 4222-1 corresponding to flash die #1, and then the read command to be executed may be sent to flash die #0. In the process of storing the generated next read command in the following read queue 4222-1 corresponding to flash die #1, for example, the scheduler 433 may first prepare the generated next read command in the next command buffer 4223-0 corresponding to flash die #0, and then transfer the generated next read command from the next command buffer 4223-0 to the following read queue 4222-1 corresponding to flash die #1.

[0145] When a read command is stored in the following read queue 4222-1, the scheduler 433 selects the following read queue 4222-1 and stores the read command stored in the following read queue 4222-1 in the next command buffer 4223-1 as a read command to be executed. In this case as well, the scheduler 433 determines whether or not it is necessary to issue the next read command following the read command to be executed stored in the next command buffer 4223-1.

[0146] When it is necessary to issue the next read command following the read command to be executed stored in the next command buffer 4223-1, the scheduler 433 generates the next read command. At this time, the scheduler 433 refers to the L2P table 61 to identify the flash die in which data following the data requested to be read by the read command to be executed stored in the next command buffer 4223-1 is stored, and the length of the following data stored in this identified flash die.

[0147] Then, the scheduler 433 executes a process of sending the read command to be executed that is stored in the next command buffer to flash die #1, and a process of storing the subsequent next read command in the following read queue corresponding to the identified flash die.

[0148] For example, if the flash die storing data subsequent to the data requested to be read by the read command to be executed stored in the next command buffer 4223-1 is the flash die #31, the scheduler 433 identifies the flash die #31 storing the subsequent data and the length of the subsequent data stored in the flash die #31 at the stage of the next command buffer 4223-1 corresponding to the flash die #1. The scheduler 433 generates a next read command for reading the subsequent data from the flash die #31. The scheduler 433 then executes a process of sending the read command to be executed to the flash die #1 and a process of storing the generated next read command in the following read queue 4222-31 corresponding to the flash die #31. In this case, after sending the read command to be executed to the flash die #1, the generated next read command may be stored in the following read queue 4222-31 corresponding to the flash die #31. Alternatively, the generated next read command may be stored in the following read queue 4222-31 corresponding to the flash die #31, and then the read command to be executed may be sent to the flash die #1. In the process of storing the generated next read command in the following read queue 4222-31 corresponding to the flash die #31, for example, the scheduler 433 may first prepare the generated next read command in the next command buffer 4223-1 corresponding to the flash die #1, and then transfer the generated next read command from the next command buffer 4223-1 to the following read queue 4222-31 corresponding to the flash die #31.

[0149] The read command stored in a certain next command buffer is sent to the flash die corresponding to the next command buffer after the state of the flash die corresponding to the next command buffer transitions from a busy state to a ready state. The flash die executes a sense operation to read data from the memory cell array to the page buffer based on the received read command.

[0150] When the data read into the page buffer of a certain flash die is the first data of the read target data corresponding to the host read command, the read data transfer control unit 434 transfers this data to the read buffer 423 in response to the data being read into the page buffer. When the data read into the page buffer of a certain flash die is data other than the first data of the read target data corresponding to the host read command, the read data transfer control unit 434 starts a process of transferring the data read into the page buffer of this flash die to the read buffer 423 after completing the reading of the data preceding this data into the page buffer.

[0151] Then, the read data transfer control unit 434 reads the data from the read buffer 423, and transfers the read data to the host 2 via the PCIe bus.

[0152] Next, a read process will be described. Fig. 6 is a diagram showing an example of a read process executed in a memory system according to an embodiment. Fig. 6 shows an example in which the read target data specified by a host read command is distributed among three flash dies.

[0153] The host read command received from the host 2 is stored in the host read command pool 421. Here, it is assumed that the stored host read command specifies LBA0 as the start LBA and 10 as the data length (data size). Data length=1 indicates that the size of the data to be read corresponds to 10 LBAs. The page size is, for example, 16KiB, and the size corresponding to one LBA is, for example, 4KiB. Each page includes four 4KiB areas corresponding to the four offsets 0 to 3.

[0154] First, the scheduler 433 refers to the L2P table 61 to identify the flash die in which the first data of the read target data specified by the host read command is stored and the length (size) of the first data stored in this flash die.

[0155] Here, as shown in Figure 6, it is assumed that 16KiB data (D1 to D4) corresponding to LBA0 to LBA3 is stored in page P0 of block BLK0 of flash die #i, 16KiB data (D5 to D8) corresponding to LBA4 to LBA7 is stored in page P0 of block BLK100 of flash die #j, and 8KiB data (D9 to D10) corresponding to LBA8 to LBA9 is stored in page P0 of block BLK200 of flash die #k.

[0156] In this case, since the four physical addresses corresponding to the four LBAs (LBA0 to 3) obtained from the L2P table 61 are four consecutive physical addresses in the flash die #i, the scheduler 433 specifies the flash die #i as the flash die in which the leading data of the data to be read is stored. Furthermore, the scheduler 433 specifies the length corresponding to the four LBAs (=16 KiB) as the length of the leading data stored in the flash die #i. The scheduler 433 generates a read command CMD0-1 for reading 16 KiB data (D1 to D3) from page P0 of block BLK0 of the flash die #i, and stores the read command CMD0-1 in the leading read queue 4221-i corresponding to the flash die #i. Here, if no read command is stored in the following read queue 4222-i, the scheduler 433 selects the leading read queue 4221-i and stores the read command CMD0-1 stored in the leading read queue 4221-i in the next command buffer 4223-i.

[0157] In response to the read command CMD0-1 being stored in the next command buffer 4223-i, the scheduler 433 determines whether or not it is necessary to issue the next read command following the read command CMD0-1. This determination may be performed, for example, based on the additional information added to this read command CMD0-1.

[0158] The read command CMD0-1 is the first read command among the multiple read commands associated with one host read command, and is not the last read command among the multiple read commands. Therefore, the scheduler 433 determines that it is necessary to issue the next read command following the read command CMD0-1.

[0159] In response to determining that it is necessary to issue the next read command, the scheduler 433 refers to the L2P table 61 to identify the flash die in which the second data following the first data is stored and the length of the second data stored in this flash die. Since the four physical addresses corresponding to the four LBAs (LBA4 to 77) acquired from the L2P table 61 are four consecutive physical addresses in the flash die #j, the scheduler 433 identifies the flash die #j as the flash die in which the second data is stored. In addition, the scheduler 433 identifies the length corresponding to the four LBAs (=16 KiB) as the length of the second data stored in the flash die #j. The scheduler 433 generates a read command CMD0-2 for reading 16 KiB data (D5 to D7) from page P0 of block BLK100 of the flash die #j.

[0160] Then, the scheduler 433 executes a process of sending the read command CMD0-1 to the flash die #i, and a process of storing the read command CMD0-2 in the following read queue 4222-j corresponding to the flash die #j.

[0161] When the read command CMD0-2 is stored in the following read queue 4222-j, the scheduler 433 selects the following read queue 4222-j in preference to the leading read queue 4221-j, thereby storing the read command CMD0-2 in the next command buffer 4223-j corresponding to the flash die #j.

[0162] In response to the read command CMD0-2 being stored in the next command buffer 4223-j, the scheduler 433 determines whether or not it is necessary to issue the next read command following the read command CMD0-2. This determination may be performed, for example, based on the additional information added to this read command CMD0-2.

[0163] The read command CMD0-2 is the second read command among the multiple read commands associated with one host read command, and is not the last read command among the multiple read commands. Therefore, the scheduler 433 determines that it is necessary to issue the next read command following the read command CMD0-2.

[0164] In response to determining that it is necessary to issue the next read command, the scheduler 433 refers to the L2P table 61 to identify the flash die in which the third data following the second data is stored and the length of the third data stored in this flash die. Since the two physical addresses corresponding to the two LBAs (LBA8-9) acquired from the L2P table 61 are two consecutive physical addresses in the flash die #k, the scheduler 433 identifies the flash die #k as the flash die in which the third data is stored. In addition, the scheduler 433 identifies the length corresponding to the two LBAs (=8KiB) as the length of the third data stored in the flash die #k. The scheduler 433 generates a read command CMD0-3 for reading 8KiB data (D9-D10) from page P0 of block BLK200 of the flash die #k.

[0165] Then, the scheduler 433 executes a process of sending the read command CMD0-2 to the flash die #j and a process of storing the read command CMD0-3 in the following read queue 4222-k corresponding to the flash die #k.

[0166] When the read command CMD0-3 is stored in the following read queue 4222-k, the scheduler 433 selects the following read queue 4222-k in preference to the leading read queue 4221-k, thereby storing the read command CMD0-3 in the next command buffer 4223-k corresponding to the flash die #k.

[0167] In response to the read command CMD0-3 being stored in the next command buffer 4223-k, the scheduler 433 determines whether or not it is necessary to issue the next read command following the read command CMD0-3. This determination may be performed, for example, based on the additional information added to the read command CMD0-3.

[0168] The read command CMD0-3 is the last read command among a plurality of read commands associated with one host read command, and therefore the scheduler 433 determines that it is not necessary to issue the next read command following the read command CMD0-3.

[0169] The scheduler 433 executes the process of sending the read commands CMD0-3 to the flash die #k.

[0170] Through the above processing, three read commands CMD-1, CMD-2, and CMD-3 corresponding to the read target data of the host read command are sent to the flash dies #i, #j, and #k, respectively, in the order of CMD-1, CMD-2, and CMD-3.

[0171] Next, the timing of executing PRP / SGL decoding will be described. Fig. 7 is a diagram showing an example of the procedure of a read process executed in the memory system according to the embodiment.

[0172] First, the controller 4 fetches a host read command from the submission queue SQ of the host 2 by command fetch processing (step S1). The controller 4 stores the host read command fetched in S1 in the host read command pool 421.

[0173] The controller 4 refers to the L2P table 61 to generate a first read command (flash read command) associated with the host read command (step S2). The controller 4 refers to the L2P table 61 to obtain a physical address indicating a storage location where the first data included in the read target data specified by the host read command is stored. Based on the obtained physical address, the controller 4 generates the first read command. In this case, the controller 4 obtains a physical address associated with the start LBA specified by the host read command from the L2P table 61, and identifies the flash die where the first data is stored based on the obtained physical address. The controller 4 stores the generated read command in the flash command queue 422 corresponding to the identified flash die.

[0174] The controller 4 executes PRP / SGL decoding to calculate an address indicating a storage location in the host read buffer 221 of the host 2 to which data corresponding to the read command stored in the flash command queue 422 should be transferred (step S3).

[0175] If it is necessary to issue a read command following the generated read command, the controller 4 repeats the process of step S2 and the process of step S3 until the last read command associated with the host read command is generated.

[0176] The controller 4 issues the generated read command to the specified flash die (step S4). The flash die that receives the read command executes a sense operation to read data from a page including a storage location indicated by a physical address specified by the read command to the page buffer 511.

[0177] After the data has been read out to the page buffer 511, the controller 4 allocates the read buffer RB to the identified flash die (step S5). The read buffer RB allocated to the identified flash die is one storage area in the read buffer 423.

[0178] The controller 4 transfers the data stored in the page buffer 511 to the read buffer RB allocated in S5 (step S6).

[0179] Then, the controller 4 transfers data from the read buffer RB to a storage area on the host read buffer 221 based on the address acquired in S3 (step S7). In S7, data having the length specified in step S2 is transferred from the read buffer RB to a storage area on the host read buffer 221.

[0180] Thus, in this embodiment, when it is necessary to generate multiple read commands associated with a host read command, the process of identifying the multiple flash dies to be read is not performed all at once, but is performed in a time-division manner so that the multiple flash dies to be read are identified sequentially in the order from the first data to the last data included in the read-target data.

[0181] 7, in this embodiment, the process of step S3 for calculating multiple addresses in the host read buffer 221 of the host 2 to which multiple data included in the read target data should be transferred is also executed in a time-division manner rather than calculating multiple addresses at once. Therefore, compared to the case where multiple addresses are calculated at once, it is possible to reduce the amount of PRP / SGL decoded results that need to be stored simultaneously, that is, the number of calculated addresses. This makes it possible to reduce the amount of memory resources that need to be prepared in the SSD 3 for storing the PRP / SGL decoded results.

[0182] Next, a description will be given of the order in which read data is received by the read buffer 423 and the order in which the read data is transferred from the read buffer 423 to the host read buffer 221. Fig. 8 is a timing chart showing an example of the order in which read data is received by the read buffer provided in the memory system according to the embodiment and an example of the order in which the read data is transferred from the read buffer to the host.

[0183] The horizontal axis of FIG. 8 indicates time. The upper part of FIG. 8 shows data received by the read buffer 423 and the time required for the data reception process. The lower part of FIG. 8 shows data transferred from the read buffer 423 to the host 2 and the time required for the data transfer process. Here, the ratio of the bandwidth of the PCIe bus (PCIeBW) to the bandwidth per channel (BW / C) is 4:1, and five read buffers RB#1 to RB#5 are provided on the SRAM 42. Any four of the five read buffers RB#1 to RB#5 are simultaneously used for the process of receiving read data read from the flash die via the channel. Any one of the five read buffers RB#1 to RB#5 is used to transfer the read data stored in that read buffer to the host 2 via the PCIe bus.

[0184] First, at time T1, reception processing of the read data corresponding to the read command CMD0 Part0 is started. The read data corresponding to the read command CMD0 Part0 is the first data among the data to be read specified by the host read command CMD0. The read data corresponding to the read command CMD0 Part0 is read from the page buffer of the flash die to which the read command CMD0 Part0 is issued. Then, the read data corresponding to the read command CMD0 Part0 is transferred from the page buffer to the read buffer RB#1 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#1. The reception processing of the read data corresponding to the read command CMD0 Part0 is executed from time T1 to time T5.

[0185] Next, at time T2, a receiving process for the read data corresponding to the read command CMD1 Part0 is started. The read data corresponding to the read command CMD1 Part0 is the first data among the data to be read specified by the host read command CMD1. The read data corresponding to the read command CMD1 Part0 is read from the page buffer of the flash die to which the read command CMD1 Part0 is issued. The read data corresponding to the read command CMD1 Part0 is transferred from the page buffer to the read buffer RB#2 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#2. The receiving process for the read data corresponding to the read command CMD1 Part0 is executed from time T2 to time T6.

[0186] Next, at time T3, a receiving process for the read data corresponding to the read command CMD0 Part1 is started. The read data corresponding to the read command CMD0 Part1 is the second data among the data to be read specified by the host read command CMD0. The read data corresponding to the read command CMD0 Part1 is read from the page buffer of the flash die to which the read command CMD0 Part1 is issued. The read data corresponding to the read command CMD0 Part1 is transferred from the page buffer to the read buffer RB#3 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#3. The receiving process for the read data corresponding to the read command CMD0 Part1 is executed from time T3 to time T7.

[0187] Next, at time T4, a receiving process for the read data corresponding to the read command CMD0 Part2 is started. The read data corresponding to the read command CMD0 Part2 is the third data among the read target data specified by the host read command CMD0. The read data corresponding to the read command CMD0 Part2 is read from the page buffer of the flash die to which the read command CMD0 Part2 is issued. The read data corresponding to the read command CMD0 Part2 is transferred from the page buffer to the read buffer RB#4 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#4. The receiving process for the read data corresponding to the read command CMD0 Part2 is executed from time T4 to time T8.

[0188] Next, at time T5, the reception process of the read data corresponding to the read command CMD0 Part 0 is completed. In response to this, a transfer process is started to transfer the read data corresponding to the read command CMD0 Part 0 stored in the read buffer RB#1 to the host 2. The transfer process of the read data corresponding to the read command CMD0 Part 0 is executed from time T5 to time T6 at a speed four times faster than the reception process speed.

[0189] Also, at time T5, the reception process for the read data corresponding to the read command CMD2 Part0 is started. The read data corresponding to the read command CMD2 Part0 is the first data among the data to be read specified by the host read command CMD2. The read data corresponding to the read command CMD2 Part0 is read from the page buffer of the flash die to which the read command CMD2 Part0 is issued. This flash die is, for example, a flash die connected to the same channel as the flash die to which the read command CMD0 Part0 is issued. The read data corresponding to the read command CMD2 Part0 is transferred from the page buffer to the read buffer RB#5 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#5. The reception process for the read data corresponding to the read command CMD2 Part0 is executed from time T5 to time T9.

[0190] Next, at time T6, the reception process of the read data corresponding to the read command CMD1 Part0 is completed, and the transfer process of transferring the read data corresponding to the read command CMD0 Part0 to the host 2 is also completed. In response to this, the transfer process of transferring the read data corresponding to the read command CMD1 Part0 stored in the read buffer RB#2 to the host 2 is started. The transfer process of the read data corresponding to the read command CMD1 Part0 is executed from time T6 to time T7 at a speed four times faster than the reception process speed. Also, since the transfer process of transferring the read data corresponding to the read command CMD0 Part0 to the host 2 is completed at time T6, the read buffer RB#1 becomes available for the reception process of new read data.

[0191] Then, at time T6, the reception process for the read data corresponding to the read command CMD0 Part3 is started. The read data corresponding to the read command CMD0 Part3 is the fourth data among the read target data specified by the host read command CMD0. The read data corresponding to the read command CMD0 Part3 is read from the page buffer of the flash die to which the read command CMD0 Part3 is issued. This flash die is, for example, a flash die connected to the same channel as the flash die to which the read command CMD1 Part0 is issued. The read data corresponding to the read command CMD0 Part3 is transferred from the page buffer to the read buffer RB#1 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#1. The reception process for the read data corresponding to the read command CMD0 Part3 is executed from time T6 to time T10.

[0192] Next, at time T7, the reception process corresponding to the read command CMD1 Part1 is completed, and the transfer process of the read data corresponding to the read command CMD1 Part0 is also completed. In response to this, a transfer process is started to transfer the read data corresponding to the read command CMD0 Part1 stored in the read buffer RB#3 to the host 2. The transfer process of the read data corresponding to the read command CMD0 Part1 is executed from time T7 to time T8 at a speed four times faster than the reception process speed. In addition, since the transfer process of the read data corresponding to the read command CMD1 Part0 is completed, the read buffer RB#2 becomes available for the reception process of new read data.

[0193] Then, at time T7, the reception process of the read data corresponding to the read command CMD2 Part1 is started. The read data corresponding to the read command CMD2 Part1 is the second data among the read target data specified by the host read command CMD2. The read data corresponding to the read command CMD2 Part1 is read from the page buffer of the flash die to which the read command CMD2 Part1 is issued. This flash die is, for example, a flash die connected to the same channel as the flash die to which the read command CMD0 Part1 is issued. The read data corresponding to the read command CMD2 Part1 is transferred from the page buffer to the read buffer RB#2 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#2. The reception process of the read data corresponding to the read command CMD2 Part1 is executed from time T7 to time T11.

[0194] Next, at time T8, the reception process of the read data corresponding to the read command CMD0 Part2 is completed, and the transfer process of transferring the read data corresponding to the read command CMD0 Part1 to the host 2 is also completed. In response to this, the transfer process of transferring the read data corresponding to the read command CMD0 Part2 stored in the read buffer RB#4 to the host 2 is started. The transfer process of the read data corresponding to the read command CMD0 Part2 is executed from time T8 to time T9 at a speed four times faster than the reception process speed. In addition, since the transfer process of the read data corresponding to the read command CMD0 Part1 is completed, the read buffer RB#3 becomes available for the reception process of new read data.

[0195] Then, at time T8, the reception process for the read data corresponding to the read command CMD0 Part4 is started. The read data corresponding to the read command CMD0 Part4 is the fifth data among the read target data specified by the host read command CMD0. The read data corresponding to the read command CMD0 Part4 is read from the page buffer of the flash die to which the read command CMD0 Part4 is issued. This flash die is, for example, a flash die connected to the same channel as the flash die to which the read command CMD0 Part2 is issued. The read data corresponding to the read command CMD0 Part4 is transferred from the page buffer to the read buffer RB#2 at a slow speed corresponding to the bandwidth per channel (BW / C), and is stored in the read buffer RB#2. The reception process for the data of the read command CMD0 Part4 is executed from time T8 to time T12.

[0196] Next, the data stored in each storage area of ​​the read buffer will be described. Fig. 9 is a diagram showing an example of read data held in the read buffer in the first round and an example of read data held in the read buffer in the second round.

[0197] As explained between time T1 and time T6 in Figure 8, in the first round, read data corresponding to read command CMD0 Part 0 is stored in read buffer RB#1, read data corresponding to read command CMD1 Part 0 is stored in read buffer RB#2, read data corresponding to read command CMD0 Part 1 is stored in read buffer RB#3, read data corresponding to read command CMD0 Part 2 is stored in read buffer RB#4, and read data corresponding to read command CMD2 Part 0 is stored in read buffer RB#5.

[0198] Next, in response to completion of the transfer process of transferring read data corresponding to the read command CMD0 Part0 stored in the first round to the host 2, data corresponding to the read command CMD0 Part3 is stored in the read buffer RB#1 as data for the second round. Then, in response to completion of the transfer process of transferring read data corresponding to the read command CMD1 Part0 stored in the first round to the host 2, read data corresponding to the read command CMD2 Part1 is stored in the read buffer RB#2 as data for the second round. In response to completion of the transfer process of transferring read data corresponding to the read command CMD0 Part1 stored in the first round to the host 2, read data corresponding to the read command CMD0 Part4 is stored in the read buffer RB#3 as data for the second round.

[0199] Next, the timing of the read process of the flash memory will be described with reference to Fig. 10, which is a timing chart showing an example of the read timing of the flash memory and an example of the transfer timing from the flash memory to the read buffer.

[0200] The horizontal axis of Fig. 10 indicates time. The upper part of Fig. 10 indicates the timing at which the flash die executes a read operation based on each read command. The lower part of Fig. 10 indicates the timing at which data corresponding to each read command is transferred from the flash die to the read buffer 423.

[0201] When the ratio between the bandwidth of the PCIe bus (PCIeBW) and the bandwidth per channel (BW / C) is 4:1, in order to improve the throughput of the read process, it is preferable to transfer read data corresponding to four read commands in parallel from the flash memory 5 to the read buffer 423 as shown in the lower part of Fig. 10. When the time tR required for the read operation (sense operation) in the flash die is longer than the time required for the transfer operation to the read buffer 423, the throughput of the read process can be improved by executing read operations based on multiple read commands in parallel.

[0202] In the case shown in FIG. 10, read operations based on a maximum of seven read commands are executed in parallel.

[0203] The procedure of the read process will now be described with reference to a flowchart shown in Fig. 11, which is a flow chart showing the procedure of the read process executed in the memory system according to the embodiment.

[0204] First, the controller 4 receives a host read command from the host 2 (step S11). The received host read command is stored in the host read command pool 421.

[0205] The controller 4 refers to the L2P table 61 to identify the flash die in which the first data of the read target data of the host read command received in S11 is stored and the size (length) of the data stored in the identified flash die (step S12).

[0206] The controller 4 generates a read command for reading the leading data, and stores the generated read command in the leading read queue corresponding to the flash die identified in S12 (step S13).

[0207] The controller 4 determines to transmit the read command stored in the leading read queue in S13 to the flash die identified in S12 (step S14). In this case, the read command determined to be transmitted to the flash die is stored in the next command buffer as a read command to be executed.

[0208] The controller 4 judges whether or not it is necessary to read data following the first data corresponding to the read command determined to be sent to the flash die in S14, that is, whether or not it is necessary to issue a next read command following the read command to be executed (step S15). This judgment is made based on whether or not the read command to be executed is a read command other than the single read command associated with the host read command and the last read command of the multiple read commands associated with the host read command.

[0209] If it is not necessary to read subsequent data, i.e., if it is not necessary to issue the next read command (No in S15), the controller 4 sends the read command determined in S14 (the read command to be executed) to the flash die (step S16), and terminates the read process.

[0210] If it is necessary to read subsequent data, that is, if it is necessary to issue the next read command (Yes in S15), the controller 4 refers to the L2P table 61 at the stage of the next command buffer where the read command determined in S14 (the read command to be executed) is, and identifies the flash die in which the subsequent data is stored and the size (length) of the subsequent data stored in this flash die (step S17). The subsequent data is data following the data requested to be read by the read command to be executed. In step S17, the controller 4 generates the next read command for reading the subsequent data from the flash die identified in step S17.

[0211] The controller 4 executes a process of sending the read command (the read command to be executed) determined in S14 and stored in the next command buffer to the flash die identified in S12, and a process of storing the generated next read command in a following read queue corresponding to the flash die identified in S17 (step S18).

[0212] The controller 4 selects the following read queue corresponding to the flash die identified in S17 with priority over the leading read queue corresponding to the flash die identified in S17. Therefore, the controller 4 determines to transmit the next read command stored in the following read queue in S18 to the flash die identified in S17 (step S19). The read command determined to be transmitted to the flash die is stored in the next command buffer corresponding to the flash die identified in S17 as a read command to be executed.

[0213] The controller 4 determines whether or not it is necessary to read data subsequent to the data corresponding to the read command decided to be sent in S19, that is, whether or not it is necessary to issue the next read command subsequent to the read command to be executed stored in the next command buffer corresponding to the flash die identified in S17 (step S20).

[0214] If it is not necessary to read subsequent data, i.e., if it is not necessary to issue the next read command (No in step S20), the controller 4 sends the read command determined in S19 (the read command to be executed) to the flash die identified in S17 (step S21), and terminates the read process.

[0215] If it is necessary to read subsequent data, that is, if it is necessary to issue the next read command (Yes in S20), the controller 4 executes the processes from S17 onwards again. At this time, the "read command determined in S14" in the previous explanation corresponds to the "read command determined in S19".

[0216] In this way, when a read command is stored in a next command buffer corresponding to a flash die #m as a read command to be executed, the controller 4 judges whether or not it is necessary to issue a next read command following the read command to be executed. Then, in response to judging that it is necessary to issue a next read command, the controller 4 identifies the flash die #n in which data following the data requested to be read by the read command to be executed is stored, and the length of the following data stored in this flash die #n. Then, the controller 4 executes a process of generating a next read command for reading the following data, transmitting the read command to be executed to the flash die #m, and storing the generated next read command in a following read queue corresponding to the flash die #n.

[0217] Next, a process executed when reading from the non-volatile memory is completed will be described with reference to a flowchart of FIG 12, which shows the procedure of the process executed when reading from the non-volatile memory is completed in the memory system according to the embodiment.

[0218] First, in response to completion of reading data to the page buffer 511 of a certain flash die (start), the controller 4 judges whether the data read to the page buffer 511 corresponds to the next read order (step S31). For example, assume that a first read command for reading the first data of the read target data specified by a certain host read command and a second read command for reading data subsequent to the first data are transmitted to different flash dies in the order of the first read command and the second read command. In this case, if the reading of the data corresponding to the first read command to the page buffer 511 is not completed, the data corresponding to the next read order is the data corresponding to the first read command. If the reading of the data corresponding to the first read command to the page buffer 511 is already completed, the data corresponding to the next read order is the data corresponding to the second read command.

[0219] If the data read to the page buffer 511 is not data corresponding to the next read order (No in S31), the data read to the page buffer 511 does not satisfy the readable condition. Therefore, the controller 4 maintains the data in the page buffer 511 (step S32) and ends this process. In other words, the controller 4 ends this process without reading data from the page buffer 511.

[0220] If the data read into the page buffer 511 is data corresponding to the next read order (Yes in S31), the data read into the page buffer 511 satisfies the readable condition. Therefore, the controller 4 allocates a read buffer (one storage area in the read buffer 423) to this flash die (step S33).

[0221] The controller 4 reads data from the page buffer 511 and transfers the read data to the read buffer allocated in S33 (step S34). The data corresponding to the next read order is changed to the next data following the data transferred to the read buffer in S34.

[0222] The controller 4 determines whether or not the reading of subsequent data into the page buffer 511 has been completed in a certain flash die (step S35).

[0223] If the reading of the subsequent data into the page buffer 511 is complete (Yes in S35), the controller 4 executes the processes from S31 onwards again.

[0224] If reading of the subsequent data into the page buffer 511 is not complete (No in S35), the controller 4 ends this process.

[0225] Next, a process executed when data transfer to the read buffer is completed will be described with reference to a flowchart of FIG 13. The process executed when data transfer to the read buffer is completed in the memory system according to the embodiment.

[0226] When the transfer of data to a certain read buffer is completed (started), the controller 4 marks this read buffer as the completion of the data transfer (step S41).

[0227] The controller 4 judges whether or not other data is being transferred to the host 2 (step S42).

[0228] If no other data is being transferred to the host 2 (No in S42), the controller 4 starts the process of transferring the data that has been transferred to the read buffer to the memory 22 of the host 2 (step S43).

[0229] If other data is being transferred to the host 2 (Yes in S42), the controller 4 skips the procedure of S43.

[0230] Then, the controller 4 transfers data maintained in the page buffer in a certain flash die (data maintained in the page buffer in S32 of FIG. 12) to the read buffer assigned to this flash die (step S44), and ends this process. This is because, at the time when step S44 is executed, the data maintained in the page buffer in S32 of FIG. 12 satisfies the readable condition. In other words, if the data that has been read into the page buffer of a certain flash die is not data corresponding to the next read order, the controller 4 does not read this data from the page buffer of this flash die, but waits until the reading of other data is completed and the readable condition of this data is satisfied. Then, after the readable condition of this data is satisfied, the controller 4 assigns a read buffer to this flash die, and transfers the data stored in the page buffer of this flash die to the read buffer.

[0231] Next, a process executed when data transfer to the host is completed will be described with reference to a flowchart shown in FIG 14. The process executed when data transfer to the host is completed in the memory system according to the embodiment.

[0232] In response to the completion (start) of the data transfer from the read buffer to the memory 22 of the host 2, the controller 4 releases the read buffer (one storage area in the read buffer 423) in which the data transferred to the memory 22 of the host 2 was stored (step S51). The released read buffer becomes available for storing new data.

[0233] The controller 4 judges whether there is no data remaining to be transferred to the host 2 (step S52). If there is no data remaining to be transferred to the host 2, the data remaining to be transferred to the host 2 does not remain in the read buffer 423.

[0234] Therefore, if there is no data that has not been transferred to the host 2 (Yes in S52), the controller 4 ends this process.

[0235] If there is data that has not been transferred to the host 2 (No in S52), the controller 4 transfers the untransferred data to the host 2 (step S53), and ends this process.

[0236] As described above, according to the embodiment, when the read target data specified by the host read command is distributed among a plurality of flash dies, the controller 4 can transmit a plurality of read commands corresponding to the first data to the last data of the read target data, respectively, to a plurality of different dies in the order of the first read command to the last read command among the plurality of read commands. As a result, the read target data can be read from the flash memory 5 in the order of the first data to the last data included in the read target data. Therefore, the read target data specified by the host read command can be transferred to the host 2 in the order of the first data to the last data included in the read target data without providing a large-capacity read buffer.

[0237] Furthermore, in response to a read command to be executed being stored in a next command buffer corresponding to a certain flash die (e.g., flash die #m), that is, in response to a decision to transmit a certain read command to the flash die #m via a command buffer corresponding to the flash die #m, the controller 4 identifies the flash die in which data subsequent to the data requested to be read by the read command to be executed is stored and the length of the subsequent data stored in the flash die. This makes it possible to execute a process of identifying the flash die in which the subsequent data is stored and the length of the subsequent data while a read operation corresponding to a read command preceding the read command to be executed is being executed in the flash die #m.

[0238] In addition, since the order of data transferred from each flash die to the read buffer 423 is controlled, there is no need to rearrange the data on the read buffer 423 to the order in which the data is transferred to the host 2. This makes it possible to reduce the time required for rearrangement and the resources of the read buffer 423.

[0239] Thus, the controller 4 can efficiently read data from the flash die.

[0240] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0241] 1...information processing system, 2...host, 3...SSD, 4...controller, 5...NAND flash memory, 6...DRAM, 7...bus, 20...internal bus, 21...processor, 22...memory, 40...internal bus, 41...host interface, 42...SRAM, 43...CPU, 44...DMAC, 45...error correction circuit, 46...NAND interface, 47...DRAM interface, 61...L2P table, 431...write processing unit, 432...read processing unit, 433...scheduler, 434...read data transfer control unit.

Claims

1. A non-volatile memory; a controller electrically connected to the non-volatile memory and configured to receive a plurality of requests from a host, including at least a first request and a second request, and to generate, for each of the plurality of requests, one or more commands to be issued to the non-volatile memory, the one or more commands for transferring one or more data requested by the request; The controller further configured to schedule issuance of the first command and the second command such that, when both a first command and a second command are available to be issued to the non-volatile memory, the second command is issued to the non-volatile memory before the first command is issued to the non-volatile memory; the first command is one of the one or more commands generated in response to the first request, and is for transferring first data that is to be transferred first among the one or more data requested by the first request; the second command is one of the one or more commands generated in response to the second request, and is for transferring second data that is not data to be transferred first among the one or more data requested by the second request; Memory system.

2. The method of claim 1, wherein each of the plurality of requests specifies a starting logical address; the first data includes data associated with a first starting logical address specified as the starting logical address by the first request; the second data does not include data associated with a second starting logical address specified as the starting logical address by the second request; 10. The memory system of claim 1.

3. The plurality of requests further includes a third request; The controller if both the second command and the third command are ready to be issued to the non-volatile memory, scheduling issuance of the second command and the third command such that the third command is issued to the non-volatile memory before the second command is issued to the non-volatile memory; the third command is a single command generated in response to the third request, for transferring third data, which is a single piece of data requested by the third request; 10. The memory system of claim 1.

4. The controller generating a fourth command that is another one of the one or more commands for the second request, the fourth command being for transferring fourth data that is to be transferred before the second data among the one or more data requested by the second request; and further configured to issue the fourth command to the non-volatile memory before the second command.

10. The memory system of claim 1.

5. Further comprising a read buffer, the non-volatile memory includes a plurality of dies, the plurality of dies including at least a first die and a second die; each of the one or more commands is a read command; The controller when the fourth data stored in the first die is not in a state where it can be transferred from the first die to the read buffer and the second data stored in the second die is in a state where it can be transferred from the second die to the read buffer, waiting until the fourth data is in a state where it can be transferred from the first die to the read buffer without transferring the second data from the second die to the read buffer; When the fourth data is ready to be transferred from the first die to the read buffer, the fourth data is transferred from the first die to the read buffer, and the second data is transferred from the second die to the read buffer.

5. The memory system of claim 4.

6. The method of claim 1, wherein each of the plurality of dies includes a memory cell array and a page buffer; the fourth data is in a state where it can be transferred from the first die to the read buffer when the fourth data is read from the memory cell array of the first die and stored in the page buffer of the first die; the second data is ready to be transferred from the second die to the read buffer when the second data is read from the memory cell array of the second die and stored in the page buffer of the second die; 6. The memory system of claim 5.

7. The plurality of dies further includes a third die; The controller generating a fifth command that is another one of the one or more commands for the second request, the fifth command being for transferring fifth data that is to be transferred after the second data among the one or more data requested by the second request; issuing the fifth command to the nonvolatile memory after the second command; when the second data stored in the second die is not in a state where it can be transferred from the second die to the read buffer and the fifth data stored in the third die is in a state where it can be transferred from the third die to the read buffer, waiting until the second data is in a state where it can be transferred from the second die to the read buffer without transferring the fifth data from the third die to the read buffer; When the second data is ready to be transferred from the second die to the read buffer, the second data is transferred from the second die to the read buffer, and the fifth data is transferred from the third die to the read buffer.

6. The memory system of claim 5.

8. Further comprising a read buffer, the non-volatile memory includes a plurality of dies, the plurality of dies including at least a first die and a second die; each of the one or more commands is a read command; The controller and when the second data stored in the first die is not in a state where it can be transferred from the first die to the read buffer and the first data stored in the second die is in a state where it can be transferred from the second die to the read buffer, the first data is transferred from the second die to the read buffer without waiting for the second data to be in a state where it can be transferred from the first die to the read buffer.

10. The memory system of claim 1.

9. Further comprising a first command queue and a second command queue; The controller retrieving commands from the second command queue with priority over retrieving commands from the first command queue; storing the first command in the first command queue in response to determining that the first command is a command for transferring the first data that is to be transferred first among the one or more data requested by the first request; storing the second command in the second command queue in response to determining that the second command is a command for transferring the second data that is not to be transferred first among the one or more data requested by the second request; further configured to issue the second command from the second command queue to the non-volatile memory, and issue the first command from the first command queue to the non-volatile memory.

10. The memory system of claim 1.

10. Further comprising a command buffer, The controller removing the second command from the second command queue; storing the second command in the command buffer; determining whether to generate another one of the one or more commands for the second request based on a size of data requested by the second command; generating the other one of the one or more commands for the second request; storing the other one of the one or more commands for the second request in the second command queue; and further configured to issue the second command from the command buffer to the non-volatile memory.

10. The memory system of claim 9.

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